TWI734287B - Display device and display panel - Google Patents

Abstract

A display device and a display panel are provided. The display device includes the display panel, and the displayincludes a selection circuit and a lightening circuit. The selection circuit includes a selection transistor, and the lightening circuit includes a bypass transistor and a light emitting component. The selection transistor is selectively conducted according to a voltage level of the gate control line. The bypass transistor is electrically connected to the branch terminal, the discharge selection line, and a data line. The bypass transistor is selectively conducted according to a voltage level of the discharge selection line. The light emitting component is electrically connected to the branch terminal and the data line. During a light emitting duration, the selection transistor is conducted, and the bypass transistor is inconducted. Meanwhile, a data current flows from the supply voltage to the data line, through the selection transistor, the branch terminal, and the light emitting component. The luminance of the light emitting component is determined by the data current.

Description

Display device and display panel

The present invention relates to a display device and a display panel, and more particularly to a display device and a display panel that can avoid the ghost phenomenon.

Please refer to Figure 1, which is a schematic diagram of a conventional LED display device. The LED display device 10 includes an LED display panel 11, a timing controller 13, a column controller 15 and a row controller 17. It is assumed that the LED display panel 11 includes a plurality of sub-pixel circuits SP(1,1)-SP(M,N) arranged in M rows and N columns. Both M and N are positive integers. If the LED display device 10 is a monochrome display, M is a positive integer. If the LED display device 10 is a color display, M is a multiple of 3. In addition, the row controller 17 further includes a shift register 12, an ON/OFF register/latch 14, and M switches sw1, sw2, swM, and so on.

First, the timing controller 13 generates timing control signals to the column controller 15 and the row controller 17. Next, the column controller 15 generates N gate control signals GC[1]~GC[N] according to the timing control signal, which are respectively used to select the sub-pixel circuits SP(1,1)~SP(M,N ). In addition, the row controller 17 generates M data voltages according to the timing control signal, and respectively supplies the sub-pixel circuits SP(1,1)~SP(M,N) arranged in M rows. For the convenience of description, this article uses the same symbol to represent both the signal line and the signal line The transmitted signal. For example, GC[1] simultaneously represents the gate control line electrically connected to the sub-pixels SP(1,1)~SP(M,1) in the first column and the sub-pixel SP(1, 1)~SP(M,1) gate control signal.

In Figure 1, each sub-pixel circuit SP(1,1)-SP(M,N) includes a light-emitting element (for example, a light-emitting diode LED). The anode of the light emitting diode LED is electrically connected to a gate control line GC[1]~GC[N], and its cathode is electrically connected to a data line S[1]~S[M]. Since there is a voltage difference between the gate control line GC[1]~GC[N] and the data line S[1]~S[M], there is a parasitic capacitance Cp between the two poles of each light-emitting diode LED. For example, in the sub-pixel circuit SP(1,1), it includes a light-emitting diode LED and is located between the gate control line GC[1] and the data line S[1]~S[M]S[1] The parasitic capacitance Cp. Similarly, the sub-pixel circuit SP(M, N) includes a light emitting diode LED and a parasitic capacitance Cp formed between the gate control signal GC[N] and the data line S[M].

Next, taking the sub-pixel SP(m,n) located in the mth row and the nth column as an example, it is explained that the conventional LED display panel 11 may cause ghosting due to the existence of the parasitic capacitance Cp. The sub-pixel circuit SP(m,n) is electrically connected to the data line S[m] and the gate control line GC[n]. Among them, m is less than or equal to M, n is less than or equal to N, and both m and n are positive integers.

Please refer to FIG. 2, which is a schematic diagram of selecting the sub-pixel circuits SP(1,n)~SP(M,n) in the nth column by changing the level of the gate control signal GC[n]. When the gate control signal GC[n] switches from a low level (L) to a high level (H) at time ta, it means that the timing controller 13 selects the sub-pixel circuits SP(1,n)~SP( M, n) emit light. When the gate control signal GC[n] switches from a high level (H) to a low level (L) at time tb, it means that the timing controller 13 does not select the sub-pixel circuit SP(1,n) in the nth column~ SP(M,n).

Please refer to FIG. 3A, which is a schematic diagram of the current flowing through the sub-pixel circuit SP(m,n) when the timing controller selects the sub-pixel circuit SP(m,n) in the conventional LED display panel to emit light. Please refer to Figure 2 and Figure 3A at the same time. At time ta, when the timing controller 13 selects the sub-pixel circuit SP(m,n) to emit light, the gate control signal GC[n] switches from a low level (L) to a high level (H). At this time, the data current ip flows from the gate control line GC[n] through the light emitting diode LED to the data line S[m]. The light emitting diode LED is turned on and emits light due to the flow of the data current ip, and the size of the data current ip is determined by a current source. The details of how to use the current source to control the brightness of the sub-pixel circuit SP(m,n) will not be described in detail in this article. During the period from time ta to time tb, the parasitic capacitance Cp located in the sub-pixel circuit SP(m,n) is also charged due to the voltage difference between the gate control line GC[n] and the data line S[m] .

Please refer to FIG. 3B, which is a schematic diagram of the current flow of the sub-pixel circuit SP(m,n) in the conventional LED display panel when it is not selected by the timing controller to emit light. Please refer to Figure 2 and Figure 3B at the same time. When the timing controller 13 does not select the sub-pixel circuit SP(m,n), the gate control signal GC[n] switches from the high level (H) to the low level (L) at the time tb. Under ideal conditions, the light-emitting diode LED at this time will stop emitting light because the anode gate control signal GC[n] is at a low level (L). However, because the parasitic capacitance Cp previously accumulated charge during the period from the time ta to the time tb, a discharge current id will be generated from the parasitic capacitance Cp after the time tb. After the discharge current id flows out from the parasitic capacitance Cp, it first flows through the light emitting diode LED, and then flows to the data line S[m]. Therefore, even though the timing controller 13 does not select the sub-pixel circuit SP(m,n) after the time tb, the sub-pixel circuit SP(m,n) still emits light due to the flow of the discharge current id.

Since the amount of charge accumulated by the parasitic capacitance Cp from time ta to time tb is limited, the light emitted by the light emitting diode LED after time tb is relatively weaker than the light emitted from time ta to time tb. Such a sub-pixel circuit SP (m, n) is not actually selected by the timing controller 13, but the light-emitting diode LED in the sub-pixel circuit SP (m, n) is still derived from the discharge of the parasitic capacitance Cp The phenomenon of the discharge current id and then the light will have an impact on the visual effect of the user when viewing the display screen. This kind of unexpected LED light emission is called ghosting phenomenon. The ghosting phenomenon is a problem that LED display panel manufacturers want to solve.

The invention relates to a display device and a display panel capable of avoiding ghosting phenomenon. In the sub-pixel circuit of the display panel, a selection circuit and a light-emitting circuit are provided. The light-emitting circuit includes bypass transistors and light-emitting elements connected in parallel with each other. When the light-emitting element in the sub-pixel circuit is selected by the timing controller, the bypass transistor is disconnected. Conversely, when the light-emitting element in the sub-pixel circuit is not selected, the bypass transistor will be turned on, so that the light-emitting element does not emit light because the voltage across it is less than the forward voltage Vf.

According to one aspect of the present invention, a display device including a display panel is provided. The display panel includes a first selection circuit and a first light-emitting circuit. The first selection circuit includes a first selection transistor, and the first light-emitting circuit includes a first bypass transistor and a first light-emitting element. The first selection transistor is electrically connected to the supply voltage, the first gate control line and the first branch node. The first selection transistor is selectively turned on according to the level of the first gate control line. The first bypass transistor is electrically connected to the first branch node, the first discharge selection line and the first data line. The first bypass transistor is selected according to the first discharge Select the level of the line to selectively turn on. The first light-emitting element is electrically connected to the first branch node and the first data line. During the first light-emitting period, the first selection transistor is turned on, and the first bypass transistor is turned off. At this time, the first data current flows from the first supply voltage through the first selection transistor, the first branch node and the first light-emitting element to the first data line. Wherein, the brightness of the first light-emitting element is determined according to the first data current.

According to another aspect of the present invention, a display panel is provided. The display panel includes: a first selection circuit and a first light-emitting circuit. The first selection circuit includes a first selection transistor, and the first light-emitting circuit includes a first bypass transistor and a first light-emitting element. The first selection transistor is electrically connected to the supply voltage, the first gate control line and the first branch node. The first selection transistor is selectively turned on according to the level of the first gate control line. The first bypass transistor is electrically connected to the first branch node, the first discharge selection line and the first data line. The first bypass transistor is selectively turned on according to the level of the first discharge selection line. The first light-emitting element is electrically connected to the first branch node and the first data line. During the first light-emitting period, the first selection transistor is turned on, and the first bypass transistor is turned off. At this time, the first data current flows from the first supply voltage through the first selection transistor, the first branch node and the first light-emitting element to the first data line. Wherein, the brightness of the first light-emitting element is determined according to the first data current.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows:

10: LED display device

13: Timing controller

15: Column controller

11: LED display panel

17: Row controller

14: Latch

12: shift register

V _LED : Light-emitting diode voltage

GC[1], GC[2], GC[N], GC[n], GCr[n], GCg[n], GCb[n], GCr[1], GCg[1], GCb[1], GCr[2], GCg[2], GCb[2], GCr[3], GCg[3], GCb[3]: gate control line (signal)

S[1], S[2], S[M], Sr[x], Sg[x], Sb[x], Sr[1], Sg[1], Sb[1], Sr[2], Sg[2], Sb[2], S[3], S[4], S[5], S[6]: data signal

LED, LEDr, LEDg, LEDb: light-emitting diode

SP(1,1), SP(2,1), SP(M,1), SP(1,2), SP(2,2), SP(M,2)), SP(1,N), SP(2,N), SP(M,N), SP(m,n): sub-pixel circuit

sw1, sw2, swM, sw[1], sw[2], sw[3], sw[4], sw[5], sw[6], swG1, swG2: switch

Cp: Parasitic capacitance

ta, tb, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, tc, td: time point

ip, ispr, ispg, ispb: data current

id, idg, idb, idr: discharge current

Vdd[n], Vdd[1], Vdd[2], Vdd[3]: supply voltage

DS[n], DSr[n], DSg[n], DSb[n], DSr[1], DSg[1], DSb[1], DSr[2], DSg[2], DSb[2], DSr[3], DSg[3], DSb[3]: discharge selection line (signal)

selTFT: select transistor

bpTFT, bpTFTr, bpTFTg, bpTFTb: bypass transistor

Nbr, Nbrr, Nbrg, Nbrb: branch nodes

Vbr: branch voltage

LC: Light-emitting circuit

SC, SC[1], SC[2], SC[3]: select circuit

P(x,n), P(1,1), P(2,1), P(1,2), P(2,2), P(1,3), P(2,3): pixels Circuit

SCr: Red selection circuit

SCg: Green selection circuit

SCb: Blue selection circuit

LCr: red light-emitting circuit

LCg: Green light-emitting circuit

LCb: blue light-emitting circuit

Tp: During pixel display

Tspr, Tspg, Tspb: Sub-pixel emission period

Senr[1], Seng[1], Senb[1], Senr[2], Seng[2], Senb[2], SenG1, SenG2: data line (signal)

Isrc[1], Isrc[2], Isrc[3], Isrc[4], Isrc[5], Isrc[6], IsrcG1, IsrcG2: current source

Tr[1], Tr[2], Tr[3]: during column light emission

22, 32, 39: GOA

21, 37: Micro drive circuit

31: display panel

33: TFT array

35: LED array

Figure 1 is a schematic diagram of a conventional LED display device.

Fig. 2 is a schematic diagram of selecting the sub-pixel circuits SP(1,n)~SP(M,n) in the nth column by changing the level of the gate control signal GC[n].

FIG. 3A is a schematic diagram of the current flow when the sub-pixel circuit SP(m,n) in the conventional LED display panel is selected by the timing controller to emit light.

FIG. 3B is a schematic diagram of the current flow of the sub-pixel circuit SP(m,n) in the conventional LED display panel when it is not selected by the timing controller to emit light.

FIG. 4A is a schematic diagram of an embodiment of the sub-pixel circuit SP(m,n) of the present disclosure.

Fig. 4B is a schematic diagram of changing the level of the gate control signal GC[n] as a schematic diagram of selecting whether the sub-pixel circuit SP(m,n) in Fig. 4A emits light.

FIG. 5A is a schematic diagram of the current flow when the sub-pixel circuit SP(m,n) is selected by the timing controller to emit light.

Figure 5B, which is a schematic diagram of the current flow when the sub-pixel circuit SP(m,n) is not selected by the timing controller to emit light

Fig. 6A is a schematic diagram of the structure of Fig. 4A used in the color pixel circuit.

Fig. 6B is a waveform diagram of control signals related to the pixel circuit of Fig. 6A.

FIG. 7A is a schematic diagram of combining the sub-pixel circuits of the foregoing embodiments into an LED display panel.

Fig. 7B is a waveform diagram of control signals related to the pixel circuit of Fig. 7A.

Fig. 8 is a schematic diagram based on the LED display panel shown in Fig. 6 further equipped with a demultiplexer control.

Figure 9 is a waveform diagram for controlling the LED display panel shown in Figure 8.

Figures 10A and 10B are schematic diagrams of using the LED display panel of this case with a micro-drive circuit.

FIG. 11 is a schematic diagram of another embodiment of the LED display panel according to the present disclosure.

Fig. 12 is a schematic diagram of the first type of pixel circuit P(x, n) in the LED display panel shown in Fig. 11.

Figure 13 is a schematic diagram of changing the level of the gate control signal GC[n] as a schematic diagram for selecting whether the pixel circuit P(x,n) in Figure 12 emits light.

Figures 14A, 14B, 14C, and 14D are schematic diagrams of the operation of the pixel circuit P(x, n) in Figure 14 in response to the control and selection of the timing controller and the related current flow.

Figure 15 is a schematic diagram of the second type of pixel circuit P(x,n) (where x=2~M/3, and n=1~N) in the LED display panel shown in Figure 11.

Figure 16 changes the level of the gate control signal GC[n] as the pixel circuit P(x,n) of Figure 13 (where x=2~M/3, and n=1~N) Schematic diagram of whether it is luminous or not.

Figures 17A, 17B, 17C, and 17D are schematic diagrams of the operation of the pixel circuit P(x, n) in Figure 15 in response to the control and selection of the timing controller and the related current flow.

Figure 18 is a waveform diagram for controlling the LED display panel shown in Figure 11.

As mentioned above, due to the existence of the parasitic capacitance Cp, the conventional LED display panel produces a ghosting phenomenon and affects the user's visual experience. To this end, the embodiments of the present disclosure provide LED sub-pixel circuits that are different from conventional technologies. LED adopting embodiment of the present invention The sub-pixel circuit can avoid the ghosting phenomenon caused by the existence of the parasitic capacitance Cp. Although the following description focuses on color LED display panels, the present invention can also be applied to monochromatic LED display panels. In addition, other display panels that do not use light-emitting diode LEDs as light-emitting elements can also improve the ghosting phenomenon in a similar manner.

Please refer to FIG. 4A, which is a schematic diagram of an embodiment of the sub-pixel circuit SP(m,n) according to the present disclosure. The sub-pixel circuit SP(m,n) is electrically connected to the column supply voltage Vdd[n] of the nth column, the gate control line GC[n], the discharge selection line DS[n] and the data line S[m] ]. Among them, the column supply voltage Vdd[n] is always maintained at a high voltage (for example, the light-emitting diode voltage V _LED with a voltage of 6 volts).

The sub-pixel circuit SP (m, n) includes a selection circuit (SC for short) and a lightening circuit (LC for short). The selection circuit SC includes a selection transistor selTFT, and the light-emitting circuit LC includes a bypass transistor bpTFT and a light-emitting diode LED connected in parallel with each other. For the convenience of explanation, in this article, it is assumed that the selected transistor selTFT and the bypass transistor bpTFT are both P-type thin film transistors, but in actual applications, the selected transistor selTFT and the bypass transistor bpTFT may both be N-type thin film transistors. Or, one of the selTFT and the bypass transistor bpTFT is selected as a P-type thin film transistor, and the other is an N-type thin film transistor. Among them, there may be a parasitic capacitance Cp between the gate and drain of the selective transistor selTFT.

The source of the selection transistor selTFT is electrically connected to the column supply voltage Vdd[n], the gate receives the gate control signal GC[nc], and the drain is electrically connected to the branch node Nbr. For ease of description, this article defines the voltage of the branch node Nbr as the branch voltage Vbr. In the light-emitting circuit, the light-emitting diode LED and the bypass transistor bpTFT are connected in parallel with each other. Among them, luminous The anode of the diode LED and the source of the bypass transistor bpTFT are electrically connected to the branch node Nbr. The cathode of the light emitting diode LED and the drain of the bypass transistor bpTFT are electrically connected to the data line S[m]. The gate of the bypass transistor bpTFT receives the discharge selection signal DS[n].

Please refer to FIG. 4B, which changes the level of the gate control signal GC[n] as a schematic diagram of selecting whether the sub-pixel circuit SP(m,n) in FIG. 4A emits light. At time ta, the gate control signal GC[n] is converted from a high level (H) to a low level (L), and the discharge selection signal DS[n] is converted from a low level (L) to a high level (H). At time tb, the gate control signal GC[n] is converted from a low level (L) to a high level (H), and the discharge selection signal DS[n] is converted from a high level (H) to a low level (L). For example, the voltage value of the high level (H) of the gate control signal GC[n] and the discharge selection signal DS[n] can be 8 volts, and the low level of the gate control signal GC[n] and the discharge selection signal DS[n] The voltage value of the standard (L) can be -10 volts).

If the selected transistor selTFT and the bypass transistor bpTFT are the same type of transistors (for example, the same P-type or the same N-type), the position of the gate control signal GC[n] and the discharge selection signal DS[n] Quasi-maintain the reverse. Or, if the transistor selTFT and the bypass transistor bpTFT are selected as different types of transistors (for example, the transistor selTFT is selected as P type and the bypass transistor bpTFT is selected as N type, or the transistor selTFT is selected as N type and The bypass transistor bpTFT is P-type), the gate control signal GC[n] and the discharge selection signal DS[n] maintain the same direction.

It is assumed here that the gate control signal GC[n] and the discharge selection signal DS[n] are provided by the column controller. In addition, the change of the branch voltage Vbr depends on the influence of the change of the gate control signal GC[n] and the discharge selection signal DS[n] on the selection circuit and the light-emitting circuit. About branches How the voltage Vbr changes in response to changes in the gate control signal GC[n] and the discharge selection signal DS[n] will be described in Figs. 5A and 5B.

Please refer to FIG. 5A, which is a schematic diagram of the current flow when the sub-pixel circuit SP(m,n) is selected by the timing controller to emit light. This diagram corresponds to the period from time ta to time tb in Figure 4B, so please refer to Figure 4B and Figure 5A at the same time. Since the gate control signal GC[n] is at a low level (L) from time ta to time tb, the selection transistor selTFT will be turned on from time ta to time tb. Therefore, the source of the selective transistor selTFT will receive the light-emitting diode voltage V _{LED to} conduct to the branch node Nbr. Therefore, the branch voltage Vbr is at a high level (H) from the time point ta to the time point tb.

Incidentally, the anode of the light-emitting diode LED is also at a high level (H) because it is connected to the branch node Nbr. Therefore, the light-emitting diode LED emits light during the period from time ta to time tb. On the other hand, the bypass transistor bpTFT remains closed (disconnected) because the gate receives the high-level (H) discharge selection signal DS[nc]. Accordingly, when the sub-pixel circuit SP(m,n) is selected and emits light, the light-emitting diode LED can normally emit light, and the setting of the bypass transistor bpTFT does not affect the light-emitting of the light-emitting diode LED.

Please refer to FIG. 5B, which is a schematic diagram of the current flow when the sub-pixel circuit SP(m,n) is not selected by the timing controller to emit light. This pattern corresponds to the tb time point in Fig. 4B, so please refer to Fig. 4B and Fig. 5B at the same time.

Since the gate control signal GC[n] is at a high level (H) after the tb time point, the selection transistor selTFT will be turned off. Although the selection transistor selTFT is disconnected, the branch voltage Vbr cannot receive the light-emitting diode voltage V _LED from the column supply voltage Vdd[n] through the selection transistor selTFT, but the branch voltage Vbr will still receive from Cp at the time point ta and The charge stored between tb time points. Therefore, the branch voltage Vbr does not drop to the low level (L) immediately at the tb time point, but drops to the low level after a period of decreasing.

After the tb time point, the discharge selection signal DS[nc] switches from a high level (H) to a low level (L). At this time, the bypass transistor bpTFT is turned on because the gate receives the low-level (L) discharge selection signal DS[n]. At this time, the charge transferred from the parasitic capacitor Cp to the branch node Nbr will cause the discharge current id to flow through the bypass transistor bpTFT first, and then to the data line S[m] due to the conduction of the bypass transistor bpTFT. Due to the conduction of the bypass transistor bpTFT, the voltage across the light emitting diode LED is less than its forward voltage (Vf). Incidentally, no current will flow through the light-emitting diode LED at this time. Accordingly, it can be ensured that the light-emitting diode LED that is not selected does not emit light. Therefore, the LED display panel adopting this pixel structure does not produce ghost images.

According to the concept of the present invention, the LED display panel includes a plurality of sub-pixel circuits SP(m, n) as shown in FIG. 4A, which are controlled with the waveform in FIG. 4B. Among them, the light-emitting diode LED in the sub-pixel circuit can be a single color or different colors. In a color LED display panel, the pixel circuit may include a red subpixel circuit, a green subpixel circuit, and a blue subpixel circuit.

Please refer to FIG. 6A, which is a schematic diagram of the color pixel circuit adopting the structure of FIG. 4A. In this figure, the pixel circuit P(x, n) includes: a red sub-pixel circuit, a green sub-pixel circuit, and a blue sub-pixel circuit. The red sub-pixel circuit includes a red selection circuit SCr and a red light-emitting circuit LCr; the green sub-pixel circuit includes a green selection circuit SCg and a green light-emitting circuit LCg; the blue sub-pixel circuit includes a blue selection circuit SCb and a blue light-emitting circuit LCb.

In the red sub-pixel circuit, the red selection circuit SCr is electrically connected to the column supply voltage Vdd[n], the gate control line GCr[n] and the branch node Nbrr. In addition, red glow The circuit LCr is electrically connected to the branch node Nbrr, the discharge selection line DSr[n] and the data line Sr[x]. In the green sub-pixel circuit, the green selection circuit SCg is electrically connected to the column supply voltage Vdd[n], the gate control line GCg[n] and the branch node Nbrg. In addition, the green light-emitting circuit LCg is electrically connected to the branch node Nbrg, the discharge selection line DSg[n], and the data line Sg[x]. In the blue sub-pixel circuit, the blue selection circuit SCb is electrically connected to the column supply voltage Vdd[n], the gate control line GCb[n] and the branch node Nbrb. In addition, the blue light-emitting circuit LCb is electrically connected to the branch node Nbrb, the discharge selection line DSb[n], and the data line Sb[x].

It can be seen from Figure 6A that the circuit architectures of the sub-pixel circuits of different colors are similar. The difference lies in the color of the light-emitting diode LED contained in the sub-pixel circuit and the corresponding gate control signal GC[n] And discharge selection signal DS[n]. Table 1 summarizes the comparison of the sub-pixel circuits in Figure 6A.

Please refer to Fig. 6B, which is a waveform diagram of control signals related to the pixel circuit of Fig. 6A. The waveforms of this figure from top to bottom are: column supply voltage Vdd[n], gate control signal GCr[n] connected to the red sub-pixel, gate control signal GCg[n] connected to the green sub-pixel, The gate control signal]GCb[n] connected to the blue sub-pixel, the discharge selection signal DSr[n] connected to the red sub-pixel, the discharge selection signal DSg[n] connected to the green sub-pixel, and the blue sub-pixel Connected discharge selection signal DSb[n]. The time t1 to the time t4 is the pixel display period Tp corresponding to the pixel circuit P(x, n).

During the period from time t1 to time t2, the gate control signal GCr[n] is at a low level, and the discharge selection signal DSr[n] is at a high level. At this time, the state of the red sub-pixel circuit is shown in Figure 5A. That is, the light emitting diode LEDr emits light, and the bypass transistor bpTFTr is turned off. On the other hand, since the gate control signals GCg[n] and GCb[n] are at high levels, the discharge selection signals DSg[n] and DS[n] are at low levels. During the period from time t1 to time t2, the states of the green sub-pixel circuit and the blue sub-pixel circuit are as shown in FIG. 5B. That is, in the green sub-pixel, the discharge current id will flow through the bypass transistor bpTFTg, so that the voltage across the light emitting diode LEDg is less than its forward voltage Vf; and, in the blue sub-pixel circuit, the discharge current id will be Flowing through the transistor bpTFTb makes the voltage across the light emitting diode LEDb smaller than its forward voltage Vf. Therefore, since no current flows through the light-emitting diode LEDg in the green sub-pixel and the light-emitting diode LEDb in the blue sub-pixel, the light-emitting diodes LEDg and LEDb do not flow from time t1 to time t2. Will shine. Here, the period from time t1 to time t2 is defined as the sub-pixel light-emitting period Tspr corresponding to the red sub-pixel circuit.

Similarly, during the period from time t2 to time t3, the green sub-pixel circuit is in the state shown in FIG. 5A, and the red sub-pixel circuit and the blue sub-pixel circuit are in the state shown in FIG. 5B. Therefore, the light-emitting diode LEDg in the green sub-pixel circuit emits light during the period from t2 to t3, while the light-emitting diode LEDr in the red sub-pixel and the light-emitting diode LEDb in the blue sub-pixel emit light during this period. It will not shine. Here, the period from time t2 to time t3 is defined as the sub-pixel light-emitting period Tspg corresponding to the green sub-pixel circuit.

During the period from time t3 to time t4, the blue sub-pixel circuit is in the state of FIG. 5A, and the red sub-pixel circuit and the green sub-pixel circuit are in the state of FIG. 5B. Therefore, the light-emitting diode LEDb in the blue sub-pixel circuit emits light during this period, while the light-emitting diode LEDr in the red sub-pixel and the light-emitting diode LEDg in the green sub-pixel will not emit light at t3. Light is emitted from time point to time t4. Here, the period from time t3 to time t4 is defined as the sub-pixel light-emitting period Tspb corresponding to the blue sub-pixel circuit.

Please refer to FIG. 7A, which is a schematic diagram of combining the sub-pixel circuits of the foregoing embodiments into an LED display panel. In this drawing, it is assumed that the display panel includes pixel circuits P(x, n) (x=1~2, n=1~3) arranged in two rows and three columns. Among them, each pixel circuit includes three sub-pixel circuits, and the structure is the same as that of FIG. 6A. Regarding the connection between the elements in each pixel and the related control lines, it will not be described in detail here, but will be presented in a tabular manner.

Please refer to Table 2, which is in Figure 7A, the red selection circuit SCr, the green selection circuit SCg, and the blue selection circuit included in the pixel circuits P(1,1) and P(2,1) in the first column SCb, a red light-emitting circuit LCr, a green light-emitting circuit LCg, a blue light-emitting circuit LCb, and a list of control signals related to these selection circuits and light-emitting circuits.

The red light-emitting circuits LCr of the pixel circuits P(1,1) and P(2,1) are all related to the gate control signal GCr[1] and the discharge selection signal DSr[1]. The difference between the red light-emitting circuits LCr of the pixel circuits P(1,1) and P(2,1) is that they are connected to different data lines S[1] and S[4]. Among them, the red light-emitting circuit LCr of the pixel circuit P(1,1) is electrically connected to the current source Isrc[1] via the data line Sr[1] and the switch sw[1], and the brightness of the light-emitting diode LEDr is determined by the current The current value of the data current provided by the source Isrc[1] is determined. On the other hand, the red light-emitting circuit LCr of the pixel circuit P(2,1) is electrically connected to the current source Isrc[4] via the data line Sr[2] and the switch sw[4], and the brightness of the light-emitting diode LEDr Determined by the current value of the data current provided by the current source Isrc[4].

The green light-emitting circuits LCg of the pixel circuits P(1,1) and P(2,1) are all related to the gate control signal GCg[1] and the discharge selection signal DSg[1], but the pixel circuit P(1,1), The green light-emitting circuit LCg of P(2,1) is connected to different data lines S[2] and S[5]. The green light-emitting circuit LCg of the pixel circuit P(1,1) is electrically connected to the current source Isrc[2] via the data line Sg[1] and the switch sw[2], and the brightness of the light-emitting diode LEDg is determined by the current source Isrc [2] The current value of the data provided is determined by the current value. On the other hand, the green light-emitting circuit LCg of the pixel circuit P(2,1) is electrically connected to the current source Isrc[5] via the data line Sg[2] and the switch sw[5], and the brightness of the light-emitting diode LEDg Determined by the current value of the data current provided by the current source Isrc[5].

The blue light-emitting circuits LCb of the pixel circuits P(1,1) and P(2,1) are all related to the gate control signal GCb[1] and the discharge selection signal DSb[1], but the pixel circuit P(1,1) , The blue light-emitting circuit LCb of P(2,1) is connected to different data lines Sb[1] and Sb[2]. The blue light-emitting circuit LCb of the pixel circuit P(1,1) is electrically connected to the current source Isrc[3] via the data line Sb[1] and the switch sw[3], and the brightness of the light-emitting diode LEDb is determined by the current source The current value of the data current provided by Isrc[3] is determined. On the other hand, the blue light-emitting circuit LCb of the pixel circuit P(2,1) is electrically connected to the current source Isrc[6] via the data line Sb[2] and the switch sw[6], and the light-emitting diode LEDb The brightness is determined by the current value of the data current provided by the current source Isrc[6].

Regarding Figure 7A, the pixel circuits P(1,2) and P(2,2) in the second column and the pixel circuits P(1,3) and P(3,3) in the third column are included Red selection circuit The related details of SCr, the green selection circuit SCg, the blue selection circuit SCb, the red light-emitting circuit LCr, the green light-emitting circuit LCg, and the blue light-emitting circuit LCb can also be derived by analogy with the foregoing description. Here is only presented in a tabular manner and will not be described in detail.

It can be seen from Figure 7A that the light-emitting circuits located in the same row are connected to the corresponding current source via the same data signal S[m]. For example, the red light-emitting circuits LCr of the pixel circuits P(1,1), P(1,2), and P(1,3) are all located in the first row, and are electrically connected to the data line S[1] at the same time. When the line enable signal Senr[1] is at a high level (H), the switch sw[1] is turned on. At this time, according to the voltage levels of the gate control signals GCr[1], GCr[2], GCr[3], it is determined to be the pixel Which of the circuits P(1,1), P(1,2), or the pixel circuit P(1,3), the red light-emitting circuit LCr will emit light. Among them, the brightness of the red light-emitting circuit LCr selected to emit light will be determined by the current value of the data current provided by the current source Isrc[1].

For example, if the gate control signal GCr[1] is at a low level (L), and the gate control signals GCr[2] and GCr[3] are both at a high level (H), the pixel circuit P(1,1) The red light-emitting circuit LCr will emit light. Or, if the gate control signal GCr[2] is at a low level (L), and the gate control signals GCr[1] and GCr[3] are both at a high level (H), the pixel circuit P(1,2) The red light-emitting circuit LCr will emit light. For another example, if the gate control signal GCr[3] is at a low level (L), and the gate control signals GCr[1] and GCr[2] are both at a high level (H), the pixel circuit P(1,3) The red light-emitting circuit LCr will emit light.

On how to use the line enable signal Seng[1] with the gate control signals GCg[1], GCg[2], GCg[3] to select the pixel circuits P(1,1), P(1,2), P(1) ,3) and control the green light-emitting circuit LCg; how to use the line enable signal Senb[1] with the gate control signal GCb[1], GCb[2], GCb[3] to select the pixel circuit P(1,1) , P(1,2), P(1,3) blue light-emitting circuit LCb and control it; how to use line enable signal Senr[2] with gate control signal GCr[1], GCr[2], GCr [3] Select and control the red light-emitting circuit LCr of pixel circuits P(2,1), P(2,2), P(2,3); how to use line enable signal Seng[2] with gate control signal GCg[1], GCg[2], GCg[3] select and control the green light-emitting circuit LCg of the pixel circuit P(2,1), P(2,2), P(2,3); how to use the behavior Can signal Senb[2] with gate control signals GCb[1], GCb[2], GCb[3] to select the blue of the pixel circuits P(2,1), P(2,2), P(2,3) The color light-emitting circuit LCb and control details are similar to the selection and control method of the red light-emitting circuit LCr of the pixel circuits P(1,1), P(1,2), P(1,3). Detailed.

Please refer to Fig. 7B, which is a waveform diagram of the control signals related to the pixel circuit of Fig. 7A. Please refer to Figure 7A and Figure 7B at the same time. The horizontal axis of Figure 7B is time.

The time t1 to the time t4 corresponds to the column light emitting period Tr[1] of the pixel circuits P(1,1) and P(2,1) of the first column. That is, during the period from time t1 to time t4, the pixel circuits P(1,2), P(2,2) located in the second column and the pixel circuits P(1,3), P(2, 2) located in the third column 3) The red light-emitting circuit LCr, the green light-emitting circuit LCg, and the blue light-emitting circuit LCb are all in the state shown in FIG. 5B and do not emit light. In addition, the period from time t1 to time t4 is further divided into three sub-pixel light emitting periods Tspr, Tspg, and Tspb. The sub-pixel light-emitting period Tspr corresponding to the red light-emitting circuit LCr is between t1 and t2; the sub-pixel light-emitting period Tspg corresponding to the green light-emitting circuit LCg is between t2 and t3; and, with blue light emission The light-emitting period Tspb of the sub-pixel corresponding to the circuit LCb is between the time t3 and the time t4.

Since the line enable signals Sen[1] and Sen[2] are also at high levels from t1 to t2, the red light-emitting circuits LCr of the pixel circuits P(1,1) and P(2,1) can be in this segment at the same time Glow during the period. That is, the light-emitting circuits that are located in the same column and have the same color can emit light at the same time. Among them, the line enable signals Senr[1] and Senr[2] will respectively turn on the switches sw[1] and sw[4]. The conduction of the switch sw[1] electrically connects the data line Sr[1] to the current source Isrc[1], and the conduction of the switch sw[4] electrically connects the data line Sr[2] to the current source Isrc[4]. Therefore, during the period from t1 to t2, the brightness of the light-emitting diode LED in the red light-emitting circuit LCr of the pixel circuits P(1,1) and P(2,1) will be determined by the current source Isrc[1] , The current value of the data current provided by Isrc[4] is determined.

During the pixel light-emitting period Tspr from t1 to t2, the gate control signals GCg[1], GCb[1], GCr[2], except for the gate control signal GCr[1] GCg[2], GCb[2], GCr[3], GCg[3], GCb[2] are all high level (H); and the discharge selection signal DSg[1] except for the discharge selection signal DSr[1] , DSb[1], DSr[2], DSg[2], DSb[2], DSr[3], DSg[3], DS3[2] are all low level (L). Accordingly, it can be ensured that only the red light-emitting circuit LCr of the pixel circuits P(1,1) and P(2,1) will emit light during the pixel light-emitting period Tspr from time t1 to time t2. First, in the pixel light-emitting period Tspr from t1 to t2, the green light-emitting circuit LCg, blue light-emitting circuit LCb of the pixel circuit P(1,1), P(2,1), and the pixel circuit P(1,2 ), P(2,2), P(1,3), P(3,3), the current in the red light-emitting circuit LCr, green light-emitting circuit LCg, and blue light-emitting circuit LCb is only left through the bypass transistor bpTFT, No current flows through the light-emitting diodes in these light-emitting circuits.

Similarly, during the pixel light-emitting period Tspg from t2 to t3, only the green light-emitting circuits LCg of the pixel circuits P(1,1) and P(2,1) emit light; and the pixels from t3 to t4 emit light During the period Tspb, only the blue light-emitting circuit LCb of the pixel circuits P(1,1) and P(2,1) emit light. Therefore, it can be ensured that only the selected light-emitting circuit will emit light during the light-emitting period of each sub-pixel Tspr, Tspg, and Tspg, so as to achieve the effect of eliminating the ghost phenomenon. The description of the other pixel circuits in FIG. 7A and the rest of the light-emitting period in FIG. 7B are similar to the foregoing description, and will not be described in detail here.

Please refer to Fig. 8, which is based on the LED display panel shown in Fig. 6, and is further controlled by a demultiplexer. The structure of the display panel in Fig. 8 is similar to that in Fig. 6. The difference between the two is the number of current sources and the number of switches in the row controller. In this figure, the pixel circuits in the same row are all connected to the same switch sw and current source Isrc. That is, for the pixel circuits P(1,1), P(1,2), P(3,1) also located in the first row, the red light-emitting circuit LCr is connected to the switch swG1 via the data line Sr[1] , Green light-emitting circuit LCg through the data The line Sg[1] is connected to the switch swG1, and the blue light-emitting circuit LCb is connected to the switch swG1 via the data line Sb[1]; ), P(2,1), the red light-emitting circuit LCr is connected to the switch swG2 via the data line Sr[2], the green light-emitting circuit LCg is connected to the switch swG2 via the data line Sg[2], and the blue light-emitting circuit LCb is connected via The data line Sb[2] is connected to the switch swG2. Among them, the switch swG1 is controlled by the horizontal enable signal SenG1, and the switch swG2 is controlled by the horizontal enable signal SenG2. When the switch swG1 is turned on due to the high-level (H) line enable signal SenG1, the data lines Sr[1], Sg[1], and Sb[1] will be electrically connected to the current source IsrcG1 at the same time; and, the switch swG2 will be electrically connected to the current source IsrcG1 at the same time. When the line enable signal SenG2 of (H) is turned on, the data lines Sr[2], Sg[2], and Sb[2] will be electrically connected to the current source IsrcG1 at the same time.

Please refer to Figure 9, which is a waveform diagram for controlling the LED display panel shown in Figure 8. Please refer to Figure 8 and Figure 9 at the same time. In Figure 9, the top-down waveforms are: column supply voltage Vdd[1], Vdd[2], Vdd[3]; used to control the pixel circuit P(1,1), The gate control signals GCr[1], GCg[1], GCb[1] of the red selection circuit SCr, the green selection circuit SCg, and the blue selection circuit SCb of P(2,1); used to control the second column The gate control signals GCr[2], GCg[2], GCb[2] of the pixel circuit P(1,2), P(2,2) of the red selection circuit SCr, the green selection circuit SCg, and the blue selection circuit SCb ]; Used to control the gate control signal GCr of the red selection circuit SCr, the green selection circuit SCg, and the blue selection circuit SCb of the pixel circuits P(1,3) and P(2,3) located in the third column[3] , GCg[3], GCb[3]; used to control the red light-emitting circuit LCr, green light-emitting circuit LCg, and blue light-emitting circuit LCb of the pixel circuits P(1,1) and P(2,1) located in the first column The discharge selection signals DSr[1], DSg[1], DSb[1]; used to control the red light-emitting circuit LCr and green light-emitting of the pixel circuits P(1,2) and P(2,2) located in the second column The discharge selection signals DSr[2], DSg[2], DSb[2] of the circuit LCg and the blue light-emitting circuit LCb; used to control the bit The discharge selection signals DSr[3], DSg[3], the red light-emitting circuit LCr, the green light-emitting circuit LCg, and the blue light-emitting circuit LCb of the pixel circuits P(1,3) and P(2,3) in the third column DSb[3]; the row enable signal SenG1 of the switch swG1 connected to the pixel circuit located in the first row; and the row enable signal SenG2 of the switch swG2 connected to the pixel circuit located in the second row.

The horizontal axis in Figure 9 is time, and t1 to t10 are also marked. Since the architectures in Figure 6 and Figure 8 are similar, there are some similar waveforms in Figures 9 and 7. For example: column supply voltages Vdd[1], Vdd[2], Vdd[3]; gate control lines GCr[1 respectively connected to the red selection circuit SCr, green selection circuit SCg, and blue selection circuit SCb of the first column ], GCg[1], GCb[1]; the gate control lines GCr[2], GCg[2], GCb respectively connected to the red selection circuit SCr, the green selection circuit SCg, and the blue selection circuit SCb in the second column [2]; The gate control lines GCr[3], GCg[3], GCb[3] connected to the selection circuit red SCr, green selection circuit SCg, and blue selection circuit SCb of the third column respectively; and the first column The discharge selection lines DSr[1], DSg[1], DSb[1] connected to the red light-emitting circuit LCr, the green light-emitting circuit LCg, and the blue light-emitting circuit LCb respectively; and the red light-emitting circuit LCr and the green light-emitting circuit in the second column LCg and blue light-emitting circuit LCb are respectively connected to discharge selection lines DSr[2], DSg[2], DSb[2]; respectively connected to the red light-emitting circuit LCr, green light-emitting circuit LCg, and blue light-emitting circuit LCb in the third column The change modes of the discharge selection lines DSr[3], DSg[3], DSb[3] are all similar.

On the other hand, the difference between the waveforms shown in Fig. 9 and Fig. 7 is the waveforms of the line enable signals SenG1 and SenG2. In Figure 7, the sub-pixels of each row are independent of each other, so six parallel row enable signals Senr[1], Seng[1], Senb[1], Senr[2], Seng[2], Senb are used. [2]. In Figure 9, each row enable signal SenG corresponds to the sub-pixels belonging to three rows at the same time.

The row enable signal SenG1 is at a high level (H) at time t1 and t2, so that the data current flows from the column supply voltage Vdd[1] and then flows through the red selection circuit SCr of the pixel circuit P(1,1). After connecting with the red light-emitting circuit LCr, it flows to the current source IsrcG1 through the data line Sr[1] and the switch swG1. The row enable signal SenG1 is at a high level (H) from t2 to t3, so that the data current flows from the column supply voltage Vdd[1] and then flows through the red selection circuit of the pixel circuit P(1,1). After SCr and the red light-emitting circuit LCr, they then flow to the current source IsrcG1 via the data line Sg[1] and the switch swG1. The row enable signal SenG1 is at a high level (H) from t3 to t4, so that the data current flows from the column supply voltage Vdd[1] and then flows through the blue selection of the pixel circuit P(1,1). After the circuit SCb and the blue light-emitting circuit LCb, they flow to the current source IsrcG1 via the data line Sb[1] and the switch swG1.

The row enable signal SenG2 is at a high level (H) at time t1 and t2, so that the data current flows from the column supply voltage Vdd[1] and then flows through the red selection circuit SCr of the pixel circuit P(2,1). After connecting with the red light-emitting circuit LCr, it then flows to the current source IsrcG2 through the data line Sr[2] and the switch swG2. The row enable signal SenG2 is at a high level (H) from t2 to t3, so that the data current flows from the column supply voltage Vdd[2], and then flows through the red selection circuit of the pixel circuit P(2,1). After SCr and the red light-emitting circuit LCr, they flow to the current source IsrcG2 via the data line Sg[2] and the switch swG1. The row enable signal SenG2 is at a high level (H) from t3 to t4, so that after the data current flows from the column supply voltage Vdd[1], it first flows through the blue selection of the pixel circuit P(2,1) After the circuit SCb and the blue light-emitting circuit LCb, they flow to the current source IsrcG2 via the data line Sb[2] and the switch swG2.

As mentioned above, the horizontal enable signals SenG1 and SenG2 are maintained at the high level (H) from the time t1 to the time t4. Among them, the line enable signal SenG1 is used to enable the light-emitting element LCr of the pixel circuit P(1,1) to be raised according to the current source IsrcG1 during the period from t1 to t2. The green light-emitting circuit LCg of the pixel circuit P(1,1) emits light according to the data current provided by the current source IsrcG1 during the period from t2 to t3; and, the pixel circuit P(1,1) The blue light-emitting circuit LCb of) emits light according to the data current provided by the current source IsrcG1 during the period from time t3 to time t4. In addition, the line enable signal SenG2 is used to make the light-emitting element LCr of the pixel circuit P(2,1) emit light according to the data current provided by the current source IsrcG2 during the period from time t1 to time t2; to make the pixel circuit P(2,1) The green light-emitting circuit LCg emits light according to the data current provided by the current source IsrcG2 during the period from t2 to t3; and the blue light-emitting circuit LCb of the pixel circuit P(2,1) is made to emit light during the period from t3 to t4 The current source IsrcG2 provides the data current and emits light.

Similarly, the row enable signals SenG1 and SenG2 must be maintained at the high level (H) during the column light-emitting period Tr[2] from t4 to t7. The row enable signal SenG1 is maintained at a high level (H) during the column light-emitting period Tr[2], so that the red light-emitting circuit LCr, the green light-emitting circuit LCg, and the blue light-emitting circuit LCb of the pixel circuit P(1,2) are respectively at t4 From time to t5, from t5 to t6, and from t6 to t7, the current source IsrcG1 is turned on; the row enable signal SenG2 is maintained at a high level (H) during the column light-emitting period Tr[3], which enables the pixel circuit P The red light-emitting circuit LCr, green light-emitting circuit LCg, and blue light-emitting circuit LCb of (2, 2) are respectively conducted with the current source IsrcG2 during the periods from t4 to t5, t5 to t6, and t6 to t7.

In addition, the row enable signals SenG1 and SenG2 must also be maintained at a high level (H) during the column light-emitting period Tr[3] at time t7 and t10. The row enable signal SenG1 is maintained at a high level during the column light-emitting period Tr[3], so that the red light-emitting circuit LCr, the green light-emitting circuit LCg, and the blue light-emitting circuit LCb of the pixel circuit P(1,3) can be respectively from t7 to t8 At time, from t8 to t9, and from t9 to t10, the current source IsrcG1 is turned on; the row enable signal SenG2 is maintained at the high level (H) during the column light-emitting period Tr[3], so that the pixel circuit P(2, 3) The red light-emitting circuit LCr, the green light-emitting circuit LCg, and the blue light-emitting circuit LCb are respectively conducted with the current source IsrcG2 during the periods from t7 to t8, t8 to t9, and t9 to t10.

According to the foregoing description, in Figure 9, the line enable signals SenG1 and SenG2 need to be maintained at a high level (H) from time t1 to time t10. This is because in Figure 8, the switch swG1 is connected to the data lines Sr[1], Sg[1], Sb[1] at the same time, and the switch swG2 is connected to the data lines Sr[2], Sg[2], Sb[ 2] Connected sake.

Please refer to Figures 10A and 10B, which are schematic diagrams of using the LED display panel in this case with a micro-drive circuit. Since thin film transistors can be used as the selective transistor selTFT and bypass transistor bpTFT in this case, the LED display panel designed in this case can be used with the gate driver on array (GOA) and micro-drive circuit. Architecture use. In Figure 10A, it is assumed that the row controller is the micro-drive circuit 21, and the column controller uses the GOA 22.

In FIG. 10B, it is assumed that the display device includes a plurality of display panels 31. Each display panel 31 includes a TFT array 33, an LED array 35, a micro-drive circuit 37 and an internal GOA 39. In addition, the display device also provides an external GOA 32, which is shared by multiple display panels 31. It can be seen from FIG. 10B that the LED display panel adopting this architecture can be further arranged in an array in a modular manner. Therefore, this architecture is quite suitable for controlling medium and large LED display panels.

Please refer to FIG. 11, which is a schematic diagram of another embodiment of an LED display panel according to the present disclosure. In this figure, the structure of the display panel is roughly similar to that of Fig. 6. The difference between the two is that, in Figure 6, each sub-pixel SP (m, n) contains a selection Selection circuit SC and a light-emitting circuit LC. On the other hand, in Fig. 11, the sub-pixels located in the same column share the same selection circuit SC[n] (n=1, 2, 3). Accordingly, in Figure 11, the red light-emitting circuit LCr, green light-emitting circuit LCg, and blue light-emitting circuit LCb located in the same column will share the same one and be connected to the column supply voltage Vdd[n](n=1,2,3) The choice of transistor selTFT. To simplify the description, the components in each column of Figure 11 and the control signals related to these components are summarized in a table.

Please refer to Table 4, which is in Figure 11, the internal components included in the pixel circuits P(1,1) and P(2,1) in the first column, and the control signals related to these internal components List.

Please refer to Table 5, which is in Figure 11, the internal components included in the pixel circuits P(1,1) and P(2,2) in the second column, and the control signals related to these internal components List.

Please refer to Table 6, which is in Figure 11, the internal components included in the pixel circuits P(1,3) and P(2,3) in the third column and the control signals related to these internal components List.

For ease of description, this article divides the pixels in Figure 11 into two categories. The first category is the pixel circuits connected to the column supply voltage Vdd[n] (for example, pixel circuits P(1,1), P(1,2)). , P(1,3)), the second category is pixel circuits that are not connected to the column supply voltage Vdd[n] (for example, pixel circuits P(2,1), P(2,2), P(2,3) )). Please also note that in practical applications, it is not necessary to limit the connection to the column supply voltage Vdd[n] on the pixel side of the first row. That is, one row of pixel circuits can be optionally connected (for example, x=5) to be connected to the column supply voltage Vdd[n]; or Alternatively, the column supply voltage Vdd[n] is connected to pixel circuits in different rows in different columns (for example, pixel circuits with x=7 in the first column and x=3 in the second column are selected). In short, among multiple pixel circuits in the same column, one pixel circuit needs to be connected to the column supply voltage Vdd[n], and the remaining pixel circuits do not need to be connected to the column supply voltage Vdd[n].

For ease of description, this article defines a pixel circuit connected to the column supply voltage Vdd[n] as a composite pixel circuit; and defines a pixel circuit not connected to the column supply voltage Vdd[n] as a controlled pixel circuit. Next, use Figures 12, 13, 14A, 14B, 14C, and 14D to illustrate the internal structure and operation of the composite pixel circuit; and use Figures 15, 16, 17A, 17B, and 17D to illustrate the controlled pixel circuit The internal structure of the company and how it operates.

Please refer to FIG. 12, which is a schematic diagram of the internal structure of the composite pixel circuit P(x, n) in the LED display panel shown in FIG. 11. In Figure 11, the controlled pixel circuit includes: pixel circuits P(1,1), P(1,2), P(1,3). Since in Figure 11, it is assumed that the composite pixel circuits are all located in the first row, it is represented by P(x,n) (x=1, and n=1~N).

The composite pixel circuit P(x, n) (where x=1) includes a selection circuit SC, a red light-emitting circuit LCr, a green light-emitting circuit LCg, and a blue light-emitting circuit LCb. Among them, the selection circuit SC includes a selection transistor selTFT. The source of the selection transistor selTFT is electrically connected to the column supply voltage Vdd[n], the gate receives the gate control signal GC[n], and the drain is electrically connected to the branch node Nbr. The red light-emitting circuit LCr further includes a light-emitting diode LEDr and a bypass transistor bpTFTr. The anode of the light emitting diode LEDr is electrically connected to the branch node Nbr, and the cathode is electrically connected to the data line Sr[1]. In addition, the source of the bypass transistor bpTFTr is electrically connected to the branch node Nbr, the gate receives the discharge selection signal DSr[n], and the drain is electrically connected to the data line Sr[1]. The light-emitting circuit LCg further includes a light-emitting diode LEDg and a bypass transistor bpTFTg. The anode of the light emitting diode LEDg is electrically connected to the branch node Nbr, and the cathode is electrically connected to the data line Sg[x]. In addition, the source of the bypass transistor bpTFTg is electrically connected to the branch node Nbr, the gate receives the discharge selection signal DSg[n], and the drain is electrically connected to the data line Sg[x]. The blue light-emitting circuit LCb further includes a light-emitting diode LEDb and a bypass transistor bpTFTb. The anode of the light emitting diode LEDb is electrically connected to the branch node Nbr, and the cathode is electrically connected to the data line Sb[x]. In addition, the source of the bypass transistor bpTFTr is electrically connected to the branch node Nbr, the gate receives the discharge selection signal DSb[n], and the drain is electrically connected to the data line Sb[x].

Please refer to FIG. 13, which changes the level of the gate control signal GC[n] as a schematic diagram of selecting whether the pixel circuit P(x, n) in FIG. 12 emits light. Table 7 is a list of the control signals related to Fig. 12 that change states according to the sub-pixel circuits selected for light emission. Regarding the state of the composite pixel circuit P(x, n) in FIG. 12, how to change in response to the change of the related control signal shown in FIG. 13 will be described in FIGS. 14A, 14B, 14C, and 14D.

Please refer to Figs. 14A, 14B, 14C, and 14D, which are schematic diagrams of the operation of the pixel circuit P(x, n) in Fig. 12 in response to the control and selection of the timing controller and the related current flow.

Fig. 14A corresponds to the state of the composite pixel circuit P(x, n) in Fig. 12 before the time ta or after the time td in Fig. 13. Before the ta time point or after the td time point, the gate control signal GC[n] is at a high level (H). Therefore, the selective transistor selTFT is turned off (disconnected) because the gate receives the high level (H). Therefore, the branch voltage Vbr is at a low level (L). At the same time, the discharge selection signals DSr[n], DSg[n], DS[n] are also low level (L). Therefore, the light emitting diodes LEDr, LEDg, and LEDb in the red light emitting circuit LCr, the green light emitting circuit LCg, and the blue light emitting circuit LCb and the bypass transistors bpTFTr, bpTFTg, and bpTFTb are all disconnected. Accordingly, the light-emitting diode LEDr in the red light-emitting circuit LCr, the green light-emitting Neither the light-emitting diode LEDg in the circuit LCg nor the light-emitting diode LEDb in the blue light-emitting circuit LCb emits light.

During the period from time ta to time td, the gate control signal GC[n] is at a low level (L). Therefore, the selection transistor selTFT is turned on because the gate receives the low level (L), and the data current ip flows from the column supply voltage Vdd[n] through the selection transistor selTFT to the branch node Nbr. Therefore, the branch voltage Vbr is at a high level (H). During the period from time ta to time td, the light-emitting diode LEDr in the red light-emitting circuit LCr, the light-emitting diode LEDg in the green light-emitting circuit LCg, and the light-emitting diode LEDb in the blue light-emitting circuit LCb will be at ta respectively. The period from time tb to time tb (sub-pixel light-emitting period Tspr), the period from time tb to time tc (sub-pixel light-emitting period Tspg), and the period from time tc to time td (sub-pixel light-emitting period Tspb) alternately emit light.

FIG. 14B corresponds to the state of the sub-pixel light-emitting period Tspr from time ta to time tb in FIG. 13 from the complex pixel circuit P(x, n) in FIG. 12. During the sub-pixel light-emitting period Tspr, the discharge selection signal DSr[n] is at a high level (H), and the discharge selection signals DSg[n] and DSb[n] are at a low level (L). The high-level (H) discharge selection signal DSr[n] turns off the bypass transistor bpTFTr; the low-level (L) discharge selection signal DSg[n], DSb[n] turns on the bypass transistors bpTFTg and bpTFTb, respectively .

In the red light-emitting circuit LCr, the bypass transistor bpTFTr is disconnected, and the data current ispr flows from the branch node Nbr through the light-emitting diode LEDr to the data line Sr[x]. Therefore, the light-emitting diode LEDr emits light during the sub-pixel light-emitting period Tspr, and its brightness is determined by the current source connected to the data line Sr[x]. In the light-emitting circuit LCg, the bypass transistor bpTFTg is turned on, and the discharge current idg flows from the branch node Nbr through the bypass transistor bpTFTg to the data line Sg[x]. At this time, no current flows through the light-emitting diode LEDg, so it can be ensured that the light-emitting diode LEDg does not emit light during the light-emitting period Tspr of the sub-pixel. The same in blue In the color light emitting circuit LCb, the bypass transistor bpTFTb is turned on, and the discharge current idb flows from the branch node Nbr through the bypass transistor bpTFTb to the data line Sb[x]. At this time, no current flows through the light-emitting diode LEDb, so it can be ensured that the light-emitting diode LEDb does not emit light during the light-emitting period Tspr of the sub-pixel.

FIG. 14B corresponds to the state of the composite pixel circuit P(x, n) in FIG. 12 during the period from time ta to time tb in FIG. 13 (sub-pixel light-emitting period Tspr). During the sub-pixel light-emitting period Tspr, the discharge selection signal DSr[n] is at a high level (H), and the discharge selection signals DSg[n] and DSb[n] are at a low level (L). The high-level (H) discharge selection signal DSr[n] turns off the bypass transistor bpTFTr; the low-level (L) discharge selection signal DSg[n], DSb[n] turns on the bypass transistors bpTFTg and bpTFTb, respectively . Accordingly, the light-emitting diode LEDr in the red light-emitting circuit LCr will emit light, but the light-emitting diode LEDg in the light-emitting circuit LCg and the light-emitting diode LEDg in the light-emitting circuit LCg will not emit light.

Fig. 14C corresponds to the state of the composite pixel circuit P(x, n) in Fig. 12 from time tb to time tc in Fig. 13 (sub-pixel light-emitting period Tspg). During the sub-pixel emission period Tspg, the discharge selection signal DSg[n] is at a high level (H), and the discharge selection signals DSr[n] and DSb[n] are at a low level (L). The high level (H) discharge selection signal DSg[n] turns off the bypass transistor bpTFTg; the low level (L) discharge selection signal DSr[n], DSb[n] turns on the bypass transistors bpTFTr and bpTFTb respectively . Accordingly, the light emitting diode LEDg in the light emitting circuit LCg will emit light, while the light emitting diode LEDr in the red light emitting circuit LCr and the light emitting diode LEDb in the blue light emitting circuit LCb will not emit light.

FIG. 14D corresponds to the state of the composite pixel circuit P(x, n) in FIG. 12 during the period from time tc to time td in FIG. 13 (sub-pixel light-emitting period Tspb). During the sub-pixel emission period Tspb, the discharge selection signal DSb[n] is at a high level (H), and the discharge selection signals DSr[n] and DSg[n] are at a low level (L). The high-level (H) discharge selection signal DSb[n] makes the side The circuit transistor bpTFTb is disconnected; the low-level (L) discharge selection signals DSr[n] and DSg[n] respectively turn on the bypass transistors bpTFTr and bpTFTg. Accordingly, the light emitting diode LEDb of the blue light emitting circuit LCb will emit light, while the light emitting diode LEDr of the red light emitting circuit LCr and the light emitting diode LEDg of the light emitting circuit LCg will not emit light.

Table 8 is a list of elements in the composite pixel circuit P(x, n) in different states according to different control signals.

M/3。受控型像素電路僅包含紅色發光電路LCr、綠色發光電路LCg、藍色發光電路LCb，但不包含選擇電路SC。換言之，可以將受 控型像素電路內的紅色發光電路LCr、綠色發光電路LCg、藍色發光電路LCb視為其子像素電路。 Please refer to Figure 15, which is a schematic diagram of the controlled pixel circuit P(x,n) (where x=2~M/3, and n=1~N) in the LED display panel shown in Figure 11. In Fig. 11, it is assumed that the controlled type pixel circuit is arranged in each row except the first row. Therefore, the controlled pixel circuit includes: pixel circuits P(2,1), P(2,2), P(2,3). That is, P(x,n), where 1<x

M/3. The controlled pixel circuit only includes a red light-emitting circuit LCr, a green light-emitting circuit LCg, and a blue light-emitting circuit LCb, but does not include the selection circuit SC. In other words, the red light-emitting circuit LCr, the green light-emitting circuit LCg, and the blue light-emitting circuit LCb in the controlled pixel circuit can be regarded as its sub-pixel circuits.

The red light emitting circuit LCr includes a light emitting diode LEDr and a bypass transistor bpTFTr connected in parallel with each other. In the light-emitting circuit LCr, the anode of the light-emitting diode LEDr is electrically connected to the branch node Nbr, and the cathode is electrically connected to the data line Sr[1]. In addition, the source of the bypass transistor bpTFTr is electrically connected to the branch node Nbr, the gate receives the discharge selection signal DSr[n], and the drain is electrically connected to the data line Sr[x].

The light-emitting circuit LCg includes a light-emitting diode LEDg and a bypass transistor bpTFTg connected in parallel with each other. In the light emitting circuit LCg, the anode of the light emitting diode LEDg is electrically connected to the branch node Nbg, and the cathode is electrically connected to the data line Sg[x]. In addition, the source of the bypass transistor bpTFTg is electrically connected to the branch node Nbr, the gate receives the discharge selection signal DSg[n], and the drain is electrically connected to the data line Sg[x].

The blue light-emitting circuit LCb includes a light-emitting diode LEDb and a bypass transistor bpTFTb connected in parallel with each other. In the blue light-emitting circuit LCb, the anode of the light-emitting diode LEDb is electrically connected to the branch node Nbr, and the cathode is electrically connected to the data line Sb[x]. In addition, the source of the bypass transistor bpTFTb is electrically connected to the branch node Nbr, the gate receives the discharge selection signal DSb[n], and the drain is electrically connected to the data line Sb[x].

Please refer to Figure 16, which is to change the level of the gate control signal GC[n] to select the pixel circuit P(x,n) in Figure 13 (where x=2~M/3, and n=1~ N) Schematic diagram of whether to emit light or not. Please refer to Table 9, Figure 15 and Figure 16 at the same time.

Please refer to Figures 17A, 17B, 17C, and 17D, which are schematic diagrams of the operation of the pixel circuit P(x, n) in Figure 15 in response to the control and selection of the timing controller and the related current flow.

Fig. 17A corresponds to the state of the controlled pixel circuit P(x,n) (x=2~M/3) in Fig. 15 before the time ta or after the time td in Fig. 16. Before the ta time point or after the td time point, the branch voltage Vbr is at a low level (L). At the same time, the discharge selection signals DSr[n], DSg[n], DSb[n] are also low level (L). Therefore, the light-emitting diodes LEDr, LEDg, and LEDb in the red light-emitting circuit LCr, green light-emitting circuit LCg, and blue light-emitting circuit LCb do not emit light, and the bypass transistors bpTFTr, bpTFTg, and bpTFTb are all off.

During the period from time ta to time td, the branch voltage Vbr is at a high level (H). During this period, the light-emitting diode LEDr of the red light-emitting circuit LCr and the green light-emitting circuit LCg The light-emitting diode LEDg in the internal light-emitting diode LEDg and the light-emitting diode LEDb in the blue light-emitting circuit LCb will be in the period from the time ta to the time tb (sub-pixel emission period Tspr), and the period from the time tb to the time tc (sub-pixel emission period). Tspg), and emit light alternately from time tc to time td (sub-pixel light-emitting period Tspb).

Fig. 17B corresponds to the state of the controlled pixel circuit P(x,n) (x=2~M/3) in Fig. 15 from the time ta to the time tb in Fig. 16 (the sub-pixel light-emitting period Tspr). During the sub-pixel light-emitting period Tspr, the discharge selection signal DSr[n] is at a high level (H), and the discharge selection signals DSg[n] and DSb[n] are at a low level (L). The high-level (H) discharge selection signal DSr[n] turns off the bypass transistor bpTFTr; the low-level (L) discharge selection signal DSg[n], DSb[n] turns on the bypass transistors bpTFTg and bpTFTb, respectively . Accordingly, the light-emitting diode LEDr in the red light-emitting circuit LCr will emit light, but the light-emitting diode LEDg in the light-emitting circuit LCg and the light-emitting diode LEDg in the light-emitting circuit LCg will not emit light.

Fig. 17C corresponds to the state of the controlled pixel circuit P(x,n) (x=2~M/3) in Fig. 15 from time tb to time tc in Fig. 16 (sub-pixel light-emitting period Tspg). During the sub-pixel emission period Tspg, the discharge selection signal DSg[n] is at a high level (H), and the discharge selection signals DSr[n] and DSb[n] are at a low level (L). The high level (H) discharge selection signal DSg[n] turns off the bypass transistor bpTFTg; the low level (L) discharge selection signal DSr[n], DSb[n] turns on the bypass transistors bpTFTr and bpTFTb respectively . Accordingly, the light emitting diode LEDg in the light emitting circuit LCg will emit light, while the light emitting diode LEDr in the red light emitting circuit LCr and the light emitting diode LEDb in the blue light emitting circuit LCb will not emit light.

Fig. 17D corresponds to the state of the controlled pixel circuit P(x,n) (x=2~M/3) in Fig. 15 from time tc to time td in Fig. 16 (sub-pixel light-emitting period Tspb). During the sub-pixel emission period Tspb, the discharge selection signal DSb[n] is at a high level (H), and the discharge selection signals DSr[n] and DSg[n] are at a low level (L). High level (H) discharge selection The signal DSb[n] turns off the bypass transistor bpTFTb; the low-level (L) discharge selection signals DSr[n] and DSg[n] turn on the bypass transistors bpTFTr and bpTFTg respectively. Accordingly, the light emitting diode LEDb in the blue light emitting circuit LCb will emit light, while the light emitting diode LEDr in the red light emitting circuit LCr and the light emitting diode LEDg in the light emitting circuit LCg will not emit light.

Table 10 is a list of elements in the controlled pixel circuit P(x,n) (x=2~M/3) that are in different states according to different control signals.

Please refer to Figure 18, which is a waveform diagram for controlling the LED display panel shown in Figure 11. Please refer to Figure 11 and Figure 18 at the same time. The horizontal axis in Figure 18 is time, and time t1 to time t10 are used to represent different time points. From t1 to t4 corresponds to the pixel display period of pixel circuits P(1,1) and P(2,1); from t4 to t7 corresponds to the pixel circuits P(2,1) and P(2,2) Pixel display period; t7 to t10 corresponds to the pixel display period of the pixel circuits P(1,3) and P(2,3).

Because the column supply voltages Vdd[1], Vdd[2], Vdd[3] are directly connected to the light-emitting diode voltage V _LED , the column supply voltages Vdd[1], Vdd[2], Vdd[3] are Does not change due to different time points. Regarding how each pixel circuit presents different states in response to related control signals, it is similar to Figures 14A to 14D and 17A to 17D, respectively. Below, Table 11 summarizes the states of each pixel circuit in different periods.

According to the foregoing description, the embodiment of this case changes the design of the light-emitting circuit LC. The light-emitting circuit LC includes a light-emitting diode LED and a bypass transistor bpTFT. When the light-emitting circuit LC is selected to emit light, the data current isp flows through the light-emitting diode LED; when the light-emitting circuit LC is not selected, the discharge current id will flow through the bypass transistor bpTFT. In addition, depending on the embodiment, a corresponding selection circuit SC may be provided for each light-emitting circuit LC. Alternatively, the light-emitting circuits LC in the same column can share one selection circuit SC[n]. Among them, the selection transistor selTFT in the selection circuit SC is controlled by the gate control signal GC, and the bypass transistor bpTFT in the light-emitting circuit LC is controlled by the discharge selection signal DS. In addition, the level between the gate control signal GC and the discharge selection signal DS remains reversed.

When the LED display panel adopts the aforementioned structure, because the light-emitting circuit is equipped with both the light-emitting diode LED and the bypass transistor bpTFT, the bypass transistor bpTFT can make the light-emitting diode when the light-emitting diode LED is not selected. The voltage difference between the two ends of the bulk LED is maintained to be less than the forward voltage Vf. Therefore, therefore, the light-emitting circuit LC will only emit light when it is indeed selected to emit light, thereby avoiding ghosting.

In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

Vdd[n]: supply voltage

V _LED : Light-emitting diode voltage

GC[n]: Gate control line (signal)

DS[n]: Discharge selection line (signal)

selTFT: select transistor

Cp: Parasitic capacitance

Nbr: branch node

Vbr: branch voltage

bpTFT: Bypass transistor

LED: light emitting diode

S[m]: data line

SP(m,n): Sub-pixel circuit

LC: Light-emitting circuit

SC: select circuit

Claims (21)

A display device, including: a display panel, including: a first selection circuit, including: a first selection transistor, electrically connected to a first supply voltage, a first gate control line, and a first branch node , Which is selectively turned on according to the level of the first gate control line; and a first light-emitting circuit, including: a first bypass transistor, electrically connected to the first branch node, and a first discharge selection Line and a first data line, which are selectively turned on according to the level of the first discharge selection line; and a first light-emitting element, connected in parallel with the first bypass transistor and electrically connected to the first branch node And the first data line, wherein, during a first light-emitting period, the first selection transistor is on, the first bypass transistor is off, and a first data current flows from the first supply voltage To the first data line through the first selection transistor, the first branch node and the first light-emitting element, the brightness of the first light-emitting element is determined according to the first data current. The display device according to claim 1, wherein the light-emitting element is a light-emitting diode, wherein the anode of the light-emitting diode is electrically connected to the first branch node, and the light-emitting diode The cathode is electrically connected to the first data line. The display device described in item 1 of the scope of patent application, wherein the selective transistor and the bypass transistor are both P-type thin film transistors, or the selective transistor and the bypass transistor are both N-type thin film transistors . As for the display device described in claim 1, wherein one of the selection transistor and the bypass transistor is a P-type thin film transistor, and the other of the selection transistor and the bypass transistor One is an N-type thin film transistor. According to the display device described in claim 1, wherein the display panel further includes: a second selection circuit, including: a second selection transistor, electrically connected to the first supply voltage and a second gate control Line, and a second branch node, which is selectively turned on according to the level of the second gate control line; and, a second light-emitting circuit includes: a second bypass transistor electrically connected to the first Two branch nodes, a second discharge selection line, and a second data line, which are selectively turned on according to the level of the second discharge selection line; and a second light-emitting element, electrically connected to the second branch node and The second data line, wherein, during a second light-emitting period, the first selection transistor and the second bypass transistor are both disconnected, and the first bypass transistor and the second selection transistor are both disconnected Turned on, and a second data current flows from the first supply voltage through the second selection transistor, the second branch node and the second light-emitting element to the second data line, wherein the brightness of the second light-emitting element It is determined based on the second data current. The display device according to claim 5, wherein the second selection transistor is turned off during the first light-emitting period, and the second bypass transistor is turned on during the first light-emitting period, and one of the first discharges Current flows through the first bypass transistor during the second light-emitting period, and a second discharge current flows through the second bypass transistor during the first light-emitting period. The display device according to claim 5, which further includes: a row of controllers, including: a first current source that provides the first data current during the first light-emitting period; and, a first switch , Electrically connected between the first current source and the first data line, which is turned on during the first light-emitting period under the control of a first enable signal, so that the first data current is turned on during the first light-emitting period Flow through the first data line. According to the display device described in claim 7, wherein the row controller further includes: a second current source, which provides the second data current during the second light-emitting period; and a second switch, electric Connected between the second current source and the second data line, which is turned on during the second light-emitting period under the control of a second enable signal, so that the second data current flows through the second light-emitting period The second data line. The display device according to claim 7, wherein the first current source provides the second data current during the second light-emitting period, and the row controller further includes: a third switch electrically connected to the The first current source and the second data line are turned on during the second light-emitting period under the control of a third enable signal, so that the first data current flows through the second light-emitting period during the second light-emitting period. Data line. According to the display device described in claim 5, the display panel further includes: a third selection circuit, including: a third selection transistor, electrically connected to the first supply voltage and a third gate control Line, and a third branch node, which is selectively turned on according to the level of the third gate control line; and a third light-emitting circuit, including: a third bypass transistor electrically connected to the third Branch node, a third discharge selection line, and a third data line, which are selectively turned on according to the level of the third discharge selection line; and a third light-emitting element is electrically connected to the third branch node and the third data line The third data line, wherein, during a third light-emitting period, the first selection transistor, the second selection transistor, and the third bypass transistor are all disconnected, the first bypass transistor, the second The two bypass transistors and the third selection transistor are both turned on, and a third data current flows from the first supply voltage through the third selection transistor, the third branch node and the third light-emitting element to The third data line, The brightness of the third light-emitting element is determined according to the third data current. As for the display device described in claim 10, the third selection transistor is turned off during the first light-emitting period and the second light-emitting period, and the third bypass transistor is turned off during the first light-emitting period. Both the period and the second light-emitting period are on. The display device according to claim 10, wherein the display panel further includes: a fourth selection circuit, including: a fourth selection transistor, electrically connected to a second supply voltage and a fourth gate control Line, and a fourth branch node, which is selectively turned on according to the level of the fourth gate control line; and a fourth light-emitting circuit, including: a fourth bypass transistor, electrically connected to the fourth Branch nodes, a fourth discharge selection line, and the first data line, which are selectively turned on according to the level of the fourth discharge selection line; and a fourth light-emitting element, electrically connected to the fourth branch node and the first data line The first data line, wherein, during a fourth light-emitting period, the first selection transistor, the second selection transistor, the third selection transistor, and the fourth bypass transistor are all disconnected, and the first The bypass transistor, the second bypass transistor, the third bypass transistor, and the fourth selection transistor are all conductive, and a fourth data current flows from the second supply voltage through the fourth selection A transistor, the fourth branch node and the fourth light-emitting element to the first data line, The brightness of the fourth light-emitting element is determined according to the fourth data current. As for the display device described in claim 12, wherein the fourth selective transistor system is disconnected during the first light-emitting period, the second light-emitting period, and the third light-emitting period, and the fourth bypass transistor The system is turned on during the first light-emitting period, the second light-emitting period, and the third light-emitting period. The display device according to claim 12, wherein the first light-emitting element and the fourth light-emitting element each have a first color, the second light-emitting element has a second color, and the third light-emitting element has A third color. The display device according to claim 10, wherein the display panel further includes: a fifth selection circuit, including: a fifth selection transistor, electrically connected to the first supply voltage and the first gate control Line, and a fifth branch node, which is selectively turned on according to the level of the first gate control line; and a fifth light-emitting circuit, including: a fifth bypass transistor, electrically connected to the fifth Branch nodes, the first discharge selection line, and the first data line are selectively turned on according to the level of the first discharge selection line; and a fifth light-emitting element is electrically connected to the fourth branch node and the first data line The first data line, wherein, during the first light-emitting period, the fifth selection transistor is on, the fifth bypass transistor is off, and a fifth data current flows from the first supply voltage through the The fifth selection transistor, the fifth branch node and the fifth light-emitting element to the fifth data line, wherein the brightness of the fifth light-emitting element is determined according to the fifth data current. The display device described in claim 1, wherein the display panel further includes: a sixth light-emitting circuit, including: a sixth bypass transistor, electrically connected to the first branch node, and a sixth discharge option Line and the sixth data line, which are selectively turned on according to the level of the sixth discharge selection line; and a sixth light-emitting element, electrically connected to the first branch node and a sixth data line, wherein During a fifth light-emitting period, the first selection transistor and the first bypass transistor are both on, the sixth bypass transistor is off, and a sixth data current flows from the first supply voltage The first selection transistor, the first branch node, and the sixth light-emitting element to the sixth data line, wherein the brightness of the sixth light-emitting element is determined according to the sixth data current. As for the display device described in claim 16, wherein the sixth bypass transistor system is turned on during the first light-emitting period. In the display device described in item 16 of the scope of patent application, a seventh light-emitting circuit includes: a seventh bypass transistor electrically connected to the first branch node, a seventh discharge selection line, and a seventh data Line, which is selectively turned on according to the level of the seventh discharge selection line; and A seventh light-emitting element electrically connected to the first branch node and the seventh data line, wherein, during a sixth light-emitting period, the first selection transistor is turned on and the seventh bypass transistor is turned off, And a seventh data current flows from the first supply voltage through the first selection transistor, the first branch node and the seventh light-emitting element to the seventh data line, wherein the brightness of the seventh light-emitting element is based on The seventh data current is determined. According to the display device described in item 18 of the scope of patent application, the seventh bypass transistor is turned on during the first light-emitting period and the fifth light-emitting period. According to the display device described in claim 18, the first light-emitting element has a first color, the sixth light-emitting element has a second color, and the seventh light-emitting element has a third color. A display panel, including: a first selection circuit, including: a first selection transistor, electrically connected to a first supply voltage, a first gate control line, and a first branch node, which is based on the A gate control line is selectively turned on; and a first light-emitting circuit including: a first bypass transistor electrically connected to the first branch node, a first discharge selection line, and a first data Line, which is selectively turned on according to the level of the first discharge selection line; and a first light-emitting element, connected in parallel with the first bypass transistor and electrically connected to the first branch node and the first data line , Wherein, during a first light-emitting period, the first selection transistor is turned on, the first bypass transistor is turned off, and a first data current flows through the first data line to make the first light-emitting element During the first light-emitting period, the brightness of the first light-emitting element is determined according to the first data current.

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