TWI732831B - Semiconductor component, in particular power transistor - Google Patents

Abstract

A semiconductor component (1), in particular a power transistor, is described, having a substrate, an active semiconductor region which has at least one source region (8) and at least one drain region (10), and having a source pad (2) convering a first part of the substrate and having a drain pad (4) covering a second part of the substrate, wherein an essentially horizontally extending structured metallization plane (30) is arranged between the source pad (2) and the at least one source region (8), and between the drain pad (4) and the at least one drain region (10), respectively, the source pad (2) and the drain pad (4) being connected to the metallization plane (30) by means of essentially vertically extending metallizations (51, 52), and the metallization plane (30) being connected to the source region (8) and to the drain region (10) by means of essentially vertically extending metallizations (53, 54). The metallization plane (30) may cover at least 50%, at least 70% or ar least 90% of the area of the active semiconductor region, in order to permit a low overall resistance.

Description

Semiconductor components, especially power transistors

The present invention relates to a semiconductor component, preferably a power transistor, especially a gallium nitride power transistor.

An important parameter used to evaluate the characteristics of semiconductor components is the overall resistance in the on state. For a transistor or MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the aforementioned resistance is usually referred to as R _DSon . Part of the aforementioned resistance is formed by the metallization of the source and drain. In the present invention, it is intended to achieve a resistance that makes the aforementioned resistance as low as possible.

It is known from the prior art that semiconductor components, especially power transistors, are formed by a plurality of layers. In this case, the active semiconductor region is usually formed in the substrate and horizontally extending pads are vertically arranged thereon to serve as source and drain electrodes. Generally, there are multiple source and drain regions in the semiconductor component, which have a thin and long shape. The pads as source and drain usually cover both the multiple source and drain regions. In order to allow current to flow from the drain region to the drain pad, for example, vertical extension metallization is introduced as a connection between the active semiconductor region and the pads. Through these vertical connections, the current can flow out of the drain region and into the drain pad and from the source pad into the source region, respectively. In this case, in particular, a pad is flat or substantially ohmic contact, by which the semiconductor component can be externally connected catch.

Due to design reasons, the source pad and the drain pad cannot respectively cover the entire active semiconductor region, and a part of the current must be transferred laterally through the semiconductor component to reach the corresponding pad. In this case, the lateral current transfer occurs until it reaches a position covered by the corresponding source pad or drain pad. Therefore, current occurs via the vertical connection between the active semiconductor region and the corresponding pad. In this case, the lateral current transfer can occur in the active semiconductor region or in the ohmic contacts of the source and drain regions, which contacts usually occur simultaneously with the corresponding source or drain regions.

One problem with this design relates to the relatively high resistance that will result in the lateral current transfer, which adversely contributes to the overall resistance of the semiconductor component.

The present invention provides a semiconductor component, particularly a power transistor, which has a substrate, an active semiconductor region including at least one source region and at least one drain region, and a first portion having a source pad to cover the substrate And has a drain pad to cover the second part of the substrate, wherein a structured metallization plane extending substantially horizontally is disposed between the source pad and the at least one source region and in the drain pad, respectively. Between the electrode pad and the at least one drain region, the source pad is connected to at least a first portion of the metallization plane by at least one first substantially vertically extending metallization, and the drain pad is connected by Is connected to at least a second portion of the metallization plane by at least one second substantially vertically extending metallization, and the at least first portion of the metallization plane is connected to the at least one metallization plane by a third substantially vertically extending metallization. A source region, and the at least a second portion of the metallization plane is connected to the at least one drain region by a fourth substantially vertically extending metallization. "Substantially vertical" connection in the present invention It is particularly intended to refer to connections having an angle greater than 45 degrees relative to the horizontal, preferably greater than 75 degrees. Particularly preferably, the connection extends exactly vertically. The term "substantially level" is also intended to be interpreted as a similar meaning.

Advantages of the invention

The semiconductor component according to the present invention has the advantage that low and uniform resistance can be achieved. At the same time, a semiconductor component with a high current-carrying capacity greater than 50A can be produced. In the present invention, the metallization plane is meant to represent not only a geometrical plane but a spatial configuration, which is composed of conductive materials, such as metal. The metallization plane is particularly a metal layer, which is thinner than the entire semiconductor device. The metallization plane is two-dimensionally structured and is characterized by being able to specify the location or area where the material exists from the viewing direction perpendicular to the plane. In particular, the metallization plane has a substantially uniform thickness, that is, it is substantially a two-dimensional configuration.

The metallized plane is insulated by two dielectric intermediate layers, so that the electrical connection between the individual planes is only at the vertical metallization. A particular advantage of the present invention is that none of the source regions and the drain regions has the possibility of current travels for a long distance without passing to the metal plane located thereon. The resistance increased by this effect is thus effectively avoided.

In a preferred embodiment, the metallization plane has a structure such that at least 50% of the area of the active semiconductor region, preferably at least 70% of the area of the active semiconductor region, and particularly preferably At least 90% of the area of the active semiconductor region is covered by the metallization plane. The larger the area covered by the metallization plane, the greater the lateral current transfer that can be obtained on the average cross-section. This improves the aforementioned resistance reduction.

Advantageously, the at least one source region and the at least one drain region can be constructed as a plurality of parallel strips. This results in a simple structured layout that can be integrated into existing manufacturing processes without major modifications.

In the present invention, the metallization plane may have a plurality of strips, which have at least the width of the strips of the source and drain regions, and the width of the strips of the source and drain regions at least Three times or at least five times the width. This measurement also ensures that a large enough cross-section is available for lateral current transfer. The orientation of the plurality of strips of the metallization plane and the orientation of the source and drain pads are at an angle of 30 degrees to 150 degrees, particularly from 80 degrees to 100 degrees, and in special cases 90 degrees. The current can then be distributed particularly effectively in the semiconductor component.

In a refined embodiment of the present invention, the metalized plane includes a plurality of long strips constructed as a trapezoid. In this case, the narrow side of the trapezoid may be at a position where there is a direct connection point, and the direct connection point may be through the first or second vertical connection between the trapezoids and the contact pads. The trapezoids are part of the metallization plane. The advantage of this embodiment is that there is a reduced overall resistance, and the reduced overall resistance is due to the larger metal volume buried area of the metallization plane.

In another embodiment, it is advantageous that the metallization plane has a grid-like or mesh-like structure. The periodicity may be at least twice the separation from the drain region to the source region, and may fall in the range between 10 μm and 1 mm, for example. One of the pads may encapsulate the other pad annularly. In other words, the source pad completely encapsulates the drain pad, and vice versa. The advantage of this embodiment is the concentric arrangement of the source pad and the drain pad. In this geometric description, the source and drain potentials can be interchanged without functional loss.

In the refined embodiment of the present invention, the semiconductor component includes the metallization in the intermediate layer, which is constructed in the same way as the metallization plane and also realizes the current distribution function but is arranged below the metallization plane Or above. Therefore, the current distribution for the source region/the source pad and the drain region/the drain pad can be optimized without affecting each other, because the path of the source current and the drain current can be seen in the plan view It can even be crossed.

The metal plane may also have at least two regions placed at different potentials, and the at least two regions are structured to be joined to each other in a tooth-like or battlement-like manner. In this method, it is possible to reduce the overall resistance due to the more compact structure of the additional metal plane.

The advantageous refined embodiments of the present invention are classified in the appendix and are described in this specification.

1: Semiconductor components

2: liner/source liner

4: Pad/Drain pad

6: gap

8: Source area

10: Drain area

10.1: Drain area

10.2: Drain area

12: Gate area

30: metalized plane

32: long bar/source long bar

34: Long bar/Dip pole long bar

51: vertical connection / first vertical connection

52: vertical connection / second vertical connection

53: vertical connection / third vertical connection

54: vertical connection/fourth vertical connection

100: Semiconductor components

102: liner/source liner

104: Pad/Drain pad

106: source region

108: Drain area

110: Gate area

112: The first vertical connection

114: second vertical connection

Exemplary embodiments of the present invention will be outlined in more detail with the aid of the accompanying drawings and the description below.

1 shows a plan view and a cross-sectional view of a semiconductor component according to the prior art; FIG. 2 shows a plan view according to a first exemplary embodiment of the present invention; FIG. 3 shows a plan view according to a second exemplary embodiment of the present invention; FIG. 4 Shows a plan view of a third exemplary embodiment according to the present invention; FIG. 5 shows a plan view of a fourth exemplary embodiment according to the present invention; FIG. 6 shows a plan view of a fifth exemplary embodiment according to the present invention; An enlarged view of the details of the exemplary embodiment shown in 6.

Fig. 1 shows a conventional semiconductor component in the prior art. The semiconductor component The plan view of 100 is shown in the upper part of the figure. The source pad 102 and the drain pad 104 can be seen, they respectively extend horizontally from right to left and form the uppermost layer of the semiconductor component 100. In this case, the semiconductor component 100 may be externally connected, thereby being incorporated into a circuit. It can be further seen that the source region 106 and the drain region 108 extend in a direction perpendicular to the extension direction of the pads 102 and 104, respectively. The source region 106 and the drain region 108 are part of the active semiconductor region and respectively provide ohmic contacts on the surface. The gate region 110 is also represented in the same manner (not discussed further).

The source region 106 is connected to the source pad 102 by a first vertical connection 112. The same as the connection method of the source region 106, the drain region 108 is connected to the drain pad 104 by a second vertical connection 114.

This example shows the layout used to produce gallium nitride power transistors (GaN transistors). The upper area of Figure 1 shows a plan view of the mask plane. These represent the lateral dimensions of various metals and dielectrics. In the area defined by the source region 106, current is applied to the semiconductor. In this case, the current represents the flow of electrons. These areas contain ohmic contacts, which are connected to the source pad 102 by the first vertical connection 112. In the area defined by the drain region 108, current (ie, the flow of electrons) leaves the semiconductor. These areas also contain ohmic contacts, which are connected to the drain pad 104 via the second vertical connection 114.

The gate region 110 represents a metal or semiconductor gate electrode, which is used to control the transistor. These are not further considered within the scope of the present invention. Here, the first vertical connections 112 and the second vertical connections 114 are metal through holes, which are buried in a layer of insulating material.

The transistor can be formed by the source pad 102, the drain pad 104 and the gate pad Pad (not shown) while being connected to peripherals.

The source region 106 and the drain region 108 are generally configured to be thin, for example, a strip with a width from 0.2 μm to 10 μm, for example, a length from 0.1 mm to 10 mm and usually occupies the length of the entire wafer, with the same interval, for example, from 5 μm. To 30μm, and alternate configuration, so that the current travels the same distance through the semiconductor at each position of the wafer.

In the example shown in the prior art, the orientation of the contact pads (ie, the source pad 102 and the drain pad 104) relative to the source region 106 and the drain region 108 has been selected to be 90 degrees. In order to provide a sufficient area for the connection of peripheral devices, the dimensions of these contact pads are about (0.1mm-10mm)×(0.1mm-10mm).

The problem is that the applied or extracted current must sometimes travel a long distance between the active semiconductor region and the corresponding pads 102 and 104. For example, the electrons in the center of FIG. 1 flowing through the channel between the source region 106 and the drain region 108 must first flow into the part of the semiconductor component in the lower region of the figure in order to be able to pass through the drain pad 104 Leave the semiconductor component. The resistance to these currents significantly contributes to the overall resistance of the semiconductor component 100. In addition, this effect will also cause the non-uniformity of the resistance of the semiconductor component 100.

A cross-sectional view of the semiconductor component 100 can be seen in the lowermost area of FIG. 1. The source region 106, the drain region 108, the gate region 110 and the second vertical connection 114 can also be seen. The last one connects the drain region 108 to the drain pad 104.

Fig. 2 shows a plan view of the first exemplary embodiment of the present invention. Unless a teaching to the contrary is mentioned, the same elements in the semiconductor component described in FIG. 1 as in the embodiment in FIG. 2 can be applied to FIG. 2. In particular, the pads, source and drain mentioned in the previous section The dimensions of the pole area... etc. and the design of the vertical connection can be adopted from it in the embodiment of FIG. 2.

In the same manner as in FIG. 1, the source region 8 and the drain region 10 can be seen, which are formed as parallel strips and arranged in a common plane. It can also be seen that the gate region 12 is located beside the source region 8. The source pad 2 is indicated in the left part of the figure, and the drain pad 4 is indicated in the right part of the figure. The two pads 2, 4 are configured to rotate 90 degrees compared to the corresponding pads in FIG. 1, and the pads in FIG. 2 extend from top to bottom instead of extending from right to left. Therefore, the pads 2 and 4 extend parallel to the source region 8 and the drain region 10. Furthermore, the area of the pads 2 and 4 is doubled and covers most of the area of the semiconductor component 1. In essence, the dimensions of the pads 2 and 4 correspond to those known in the prior art.

The metallization plane 30 is indicated as extending at a right angle with respect to the source region 8 and the gate region 12. The metallization plane is composed of a plurality of long strips 32 and 34, which are shown to be parallel in this embodiment and cover the main part of the surface of the substrate. In the metallization plane 30, the individual strips 32, 34 are connected to the other strips 32, 34 without conductivity. Each strip 32, 34 is assigned to and is conductively connected to one of the source region 8 and the drain region 10. Therefore, the strip 32 is connected to the source region 8 by the third vertical connection 53, and the strip 34 is connected to the drain region 10 by the fourth vertical connection 54. The metallization plane 30 is thus at least partially connected to both the source region 8 and the drain region 10 and to the source pad 2 and the drain pad 4. Each separate section (that is, one of the individual strips 32, 34 shown in this embodiment) is connected to the source region 8 and the source pad 2, while the other sections are all connected to the source region 8 and the source pad 2. It is connected to the drain region 10 and the drain pad 4. These strips 32 are therefore called The source region or source strip of the metallization plane 30 is long, and the strips 34 are called the drain region or drain strip of the metallization plane 30.

The source strips 32 and the drain strips 34 extend longitudinally across the width of the chip (0.1mm-10mm). The width of the strips can vary between approximately 5 μm and 1 mm along the length of the wafer. The interval between the strips may be, for example, about 5 μm to 30 μm. However, it is also possible that the smaller interval is in the range of about 1 μm, for example. The effect achieved by the configuration of the vertical connections 51, 52, 53, 54 is that the two adjacent strips 32, 34 have different potentials (source and drain). In the example, the terms "length" and "width" in the wafer can be arbitrarily selected and interchangeable with each other. The "length" and "width" may also be referred to as "first side" and "second side".

In these regions, the source strips 32 and the source region 8 and the third vertical connection 53 are configured to allow current to flow between the source regions 8 and the source strips 32 . In the same way, the fourth vertical connection 54 is arranged between the drain strips 34 and the drain regions 10.

Electrical connections between the metallization plane 30 and the source pad 2 and between the drain pad 4 are provided in a similar manner. Likewise, the corresponding overlapping area is used to place the vertical connections 51, 52. Therefore, the first vertical connection 51 is arranged in a region where the source pad 2 and the source strip 32 overlap each other. The second vertical connection 52 is arranged in the area where the drain pad 4 and the drain strip 34 overlap.

The vertical connections 51, 52, 53, 54 can be simply metallized, and they are encapsulated by a thin insulating layer. In this embodiment, the vertical connections respectively have a square cross-section (or a circular cross-section), and can be equally spaced in the corresponding area. According to the overlap area Geometric shapes, linear configurations may be suitable, such as the first and second vertical connections 51, 52 in this embodiment or the third and fourth vertical connections 53, 52 in the embodiment of a two-dimensional checkered configuration. 54.

Some strips 32 of the metallization plane 30 are connected to the source pad 2 by the first vertical connections 51. The other strips 34 of the metalized plane 30 are connected to the drain pad 4 by the second vertical connections 52.

Fig. 3 shows a plan view of a second exemplary embodiment of the present invention. In essence, the structure of the semiconductor member 1 corresponds to the structure shown in FIG. 2. Therefore, the individual components have the same component symbols as those in FIG. 2, respectively. The substantial difference lies in the structure of the metallized plane 30. The source strips 32 and drain strips 34 are not formed in a rectangular shape as shown in FIG. 2, but are trapezoidal in shape. In other words, the strips 32 and 34 do not have a fixed width but gradually become narrower toward the sides, which are the strips respectively connected to the source pad 2 through the first vertical connections 51 Or connected to the side of the drain pad 4 through the second vertical connections 52.

The ratio of the lengths of the mutually parallel sides of these trapezoids is approximately 2 to 1. Other ratio ranges of approximately 10:1 to 1:1 are also possible, such as 1:1, 5:1, or 10:1. For example, the long side of the source strip 32 is disposed under the drain pad 4. The long side is approximately twice as long as the side parallel to the side, and the side defines the boundary of the long strip on the opposite side and is disposed under the source pad 2. Because of this configuration, there is a particularly low resistance, since the metallization plane 30 is connected to the active semiconductor region in the region of the metallization plane 30, that is, to the source region 8 or respectively. The drain area 10. This advantage is due to the relatively high resistance formed in this area in the conventional semiconductor component.

In the opposite area, the strips 32, 34 are connected to the pads 2, 4, although the width of these strips is reduced compared with the width of the rectangular strip in FIG. 2 and has a slightly higher resistance, the overall resistance of the strips 32 and 34 designed as ladder type is relatively high. Compared to the rectangular bar, it is reduced.

Fig. 4 shows a plan view of a third exemplary embodiment of the present invention. The exemplary embodiment shown in the figure substantially corresponds to the exemplary embodiment shown in FIG. 3. The same component symbols also refer to components with the same name. Compared with the exemplary embodiment shown in FIG. 3, the source pad 2 and the drain pad 4 as well as the source strip 32 and the drain strip 34 in this embodiment are rotated by 90 degrees. The source strips 32 and the drain strips 34 therefore extend parallel to the source regions 8 and the drain regions 10, and the pads 2, 4 are opposite to the source regions 8 and drain regions. The area 10 extends at a right angle. The source regions 8 and the drain regions 10 are respectively connected to the source strips 32 and the drain lengths with their entire lengths equidistantly by third and fourth vertical connections 53, 54 respectively. Article 34.

Fig. 5 shows a plan view of a fourth exemplary embodiment of the present invention. It can be seen from the figure that the drain pad 4 is arranged in the center and is completely enclosed by the source pad 2. In the illustrated embodiment, the metallization plane 30 occupies the main area of the semiconductor component 1 and has only a small number of gaps 6, that is, there is no material in it between the drain pad 4 and the active semiconductor region. The metallization plane 30, especially the source region 8, is under the drain pad 4. The source pad 2 is entirely located outside the active semiconductor region, that is, does not cover the active semiconductor region. Alternatively, the active semiconductor region may be connected under the source pad 2.

The drain regions 10 are connected to the drain pad 4 by the second vertical connection 52 and the fourth vertical connection 54. In the exemplary embodiment shown, the second vertical connections 52 and the fourth vertical connections 54 are directly arranged on each other. The second vertical connections 52 have a larger cross section than the fourth vertical connections 54. The function is not important, but it can provide advantages in manufacturing technology, because the third and fourth vertical connections 53, 54 can be used in the same way as the first and second vertical connections 51, 52. constitute.

The first vertical connections 51 connecting the metallization plane 30 to the source pad 2 are arranged annularly around the semiconductor component 1. As shown in this exemplary embodiment, the first vertical connections are equidistantly arranged in two parallel rows, although they can also be arranged in other patterns.

Fig. 6 shows a plan view of a fifth exemplary embodiment of the present invention. Similarly, the drain pad 4 is arranged in the center and is completely enclosed by the source pad 2. Compared with the exemplary embodiment shown in FIG. 5, the source pad 2 covers a part of the active semiconductor region. The metallization plane is divided into two parts called a source part 36 and a drain part 38. The source portion 36 roughly has a "double T structure": at the top and bottom in the figure, it extends to the edge of the semiconductor member 1, and at the left edge and at the right edge, the source portion is set to retract to At about a quarter of the width of the semiconductor member 1 so that the source portion 36 covers about half of the width of the semiconductor member 1. In the regions where the source portion 36 is not extended on the left and right sides of the figure, the drain portion 38 is arranged.

In the boundary area between the source portion 36 and the drain portion 38, they are "meshing" with each other. In other words, both the source portion 36 and the drain portion 38 have a battlement structure, and the battlements of one part of the metallization plane are formed in a manner corresponding to the battlements of the other part of the metallization plane. And join in it. However, in this embodiment, a small horizontal spacing is maintained in each case, so that no electrical contact occurs in the source portion 36 And the drain part 38 between. Instead of this battlement structure, it is also conceivable to use a zigzag shape. Of course, in all the exemplary embodiments presented, all the metallized parts contacting the source pad 2 are electrically insulated from the drain pad 4.

The two central drain regions 10.1 and 10.2 in the figure are connected to the drain pad 4 by a second vertical connection 52 (see FIG. 7) and a fourth vertical connection 54 (see FIG. 7). On the other hand, other drain regions 10 are also connected to the metallization plane, here in the form of drain portions 38 as described in other exemplary embodiments via the fourth vertical connection 54 (see FIG. 7 ) And connected to the metallization plane.

FIG. 7 shows an enlarged detail view of the semiconductor component 1 according to FIG. 6. The engagement of the source portion 36 and the drain portion 38 of the metallization plane and the boundary between the source pad 2 and the drain pad 4 can be particularly clearly seen here.

All the disclosed structures can be repeated multiple times on the entire semiconductor component as required, and therefore can be regarded as individual units. Similarly, without departing from the scope of the present invention, the geometric positions of the element with the source function and the element with the drain function can be interchanged. In this way, only the current direction is reversed. It is also possible that in the unit cell shown, there are more individual elements, such as more parallel source and drain regions. For clarity, only a relatively small number of structures are shown separately in the accompanying drawings.

1‧‧‧Semiconductor components

2‧‧‧Liner/Source Liner

4‧‧‧Pad/Dip pad

8‧‧‧Source area

10‧‧‧Dip pole area

12‧‧‧Gate area

30‧‧‧Metalized plane

32‧‧‧Strip/Source Strip

34‧‧‧Long strip/Dip pole strip

51‧‧‧Vertical connection/First vertical connection

52‧‧‧Vertical connection/Second vertical connection

53‧‧‧Vertical connection/Third vertical connection

54‧‧‧Vertical connection/fourth vertical connection

Claims (9)

A semiconductor component (1), especially a power transistor, which has a substrate, an active semiconductor region including at least one source region (8) and at least one drain region (10), and a source pad (2) to cover The first part of the substrate has a drain liner (4) to cover the second part of the substrate, wherein i. structured metallization planes (30) extending substantially horizontally are respectively arranged on the source liner Between the pad (2) and the at least one source region (8) and between the drain pad (4) and the at least one drain region (10); ii. the source pad (2) borrows Is connected to at least a first portion of the metallization plane (30) by at least one first substantially vertically extending metallization (51), and the drain pad (4) is connected to at least a first portion of the metallization plane (30) by at least one second substantially vertically extending The metallization (52) is connected to at least the second part of the metallization plane (30); iii. The at least the first part of the metallization plane (30) is formed by a third substantially vertically extending metallization (53) Is connected to the at least one source region (8), and the at least second part of the metallization plane (30) is connected to the at least one drain region ( 10), wherein the metallization plane (30) is composed of a plurality of strips on the same plane. The semiconductor component (1) described in the first item of the patent application, wherein the metallization plane (30) has a structure such that at least 50% of the area of the active semiconductor region is covered by the metallization plane (30) . The semiconductor component (1) described in item 1 or 2 of the scope of the patent application, wherein the at least one source region (8) and the at least one drain region (10) are constructed as a plurality of elongated regions aligned parallel to each other The plurality of strips have at least the width of the plurality of strips of the source and drain regions (8, 10). The semiconductor component (1) described in item 1 or 2 of the scope of patent application, wherein the metallization plane (30) includes a plurality of long strips (32, 34) constructed as trapezoids. The semiconductor component (1) described in item 4 of the scope of patent application, wherein the orientation of the plurality of strips (32, 34) of the metallization plane (30) and the source and drain pads (2, 4) ) Is oriented at an angle of 30 degrees to 150 degrees. According to the semiconductor component (1) described in item 1 or 2 of the scope of patent application, the metallized plane (30) has a grid-like or mesh-like structure. The semiconductor component (1) described in item 1 or 2 of the scope of patent application, wherein the source pad (2) encapsulates the drain pad (4) in a ring or box shape, or is the drain pad The pad (4) encloses the source pad (2) in a ring or box shape. The semiconductor component (1) described in item 1 or 2 of the scope of the patent application, wherein the semiconductor component (1) has additional metallization in the intermediate layer, and the additional metallization constitutes the metallization plane (30 ) Is constructed in the same way, the additional metallization realizes the current distribution function and is arranged below or above the metallization plane (30). The semiconductor component (1) described in item 1 or 2 of the scope of patent application, wherein the metallization plane (30) has at least two regions (36, 38) of different potentials in a common plane, and the at least two regions Are structured to engage with each other in a toothed or battlemented manner.

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