DE102016203906A1 - Semiconductor component, in particular power transistor - Google Patents

Abstract

A semiconductor component (1), in particular a power transistor, is described, having a substrate, an active semiconductor region which has at least one source region (8) and at least one drain region (10), and a source pad (2) covering a first part of the substrate. and a drain pad (4) covering a second part of the substrate, wherein a substantially horizontally extending pattern is arranged between the source pad (2) or the drain pad (4) and the at least one source region (8) or the at least one drain region (10) Metallization level (30) is arranged, wherein the source pad (2) and the drain pad (4) by means of substantially vertically extending metallizations (51, 52) is connected to the metallization (30), and wherein the metallization (30) by means in Substantially vertically extending metallizations (53, 54) to the source region (8) and to the drain region (10) n is. The metallization level (30) can cover at least 50%, at least 70%, or at least 90% of the area of the active semiconductor region in order to allow a low total resistance.

Description

The present invention relates to a semiconductor device, preferably a power transistor, in particular a gallium nitride power transistor.

State of the art

An important parameter for evaluating the performance of semiconductor devices is the total on-state resistance. For transistors or MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), this resistance is usually referred to as R _DSon . Part of this resistance is formed by the metallization of the source and drain. It is desirable to achieve the lowest possible resistance.

It is known from the prior art to construct a semiconductor component, in particular a power transistor, in a multilayered manner. It is customary to form the active semiconductor region in a substrate and to arrange vertically above it horizontally extending pads for source and drain. Often, there are a plurality of source and drain regions in a semiconductor device which are in the form of thin strips. The source and drain pads then regularly cover a plurality of both source and drain regions. In order to allow a current to flow, for example, from a drain region to the drain pad, vertically extending metallizations are inserted as connections between the active semiconductor region and the pads. Through these vertical connections, the current can thus flow from the drain region or into the source region and into the drain pad or from the source pad. A pad is in particular a flat, essentially ohmic contact with which the semiconductor component can be externally connected.

Since the source pad and the drain pad can not cover the entire active semiconductor region by design, it is necessary that a part of the current is transported laterally through the semiconductor device in order to reach the corresponding pad. Lateral current transport then takes place until a position is reached which is covered by the corresponding source pad or drain pad. There then takes place a current flow through the vertical connections between the active semiconductor region and the corresponding pad. The lateral current transport can take place here within the active semiconductor region or in the ohmic contacts of the source and drain regions which usually coincide with the respective source or drain regions.

The problem with this construction is the resulting relatively high lateral current transfer resistances, which disadvantageously contribute to the overall resistance of the semiconductor device.

Disclosure of the invention

According to the invention, a semiconductor component, in particular a power transistor, is provided with a substrate, an active semiconductor region having at least one source region and at least one drain region, and with a source pad covering a first part of the substrate and with a second part covering the substrate Drainpad, wherein between the source pad or the drain pad and the at least one source region or the at least one drain region, a substantially horizontally extending structured metallization is arranged, wherein the source pad by means of at least a first substantially vertically extending metallization with at least a first part of the metallization connected and the drain pad is connected by means of at least a second substantially vertically extending metallization with at least a second part of the metallization, and wherein d at least a first part of the metallization plane is connected to the at least one source region by means of a third substantially vertically extending metallization, and wherein the at least one second part of the metallization plane is connected to the at least one drain region by means of a fourth substantially vertically extending metallization. By "substantially vertical" connections are meant in particular compounds which form an angle of more than 45 °, preferably of more than 75 °, to the horizontal. Particularly preferably, the compounds are exactly vertical. The term "essentially horizontal" is to be understood analogously.

Advantages of the invention

The semiconductor device according to the invention has the advantage that a low and homogeneous total resistance is achieved. At the same time, semiconductor devices with a high current carrying capacity of more than 50 A can be produced. In this case, a metallization level is understood to mean, in particular, not merely a geometric plane but a spatial structure which consists of electrically conductive material, for example of a metal. In particular, this is a thin layer of metal, which is structured in two dimensions in comparison to the entire semiconductor component, and by specifying the locations or regions at which they are perpendicular to one direction Considered level material is present, can be characterized. In particular, the metallization has an approximately homogeneous thickness, so is essentially a two-dimensional structure.

The metallization level is isolated by two dielectric interlayers, so that only at the vertical metallizations electrical connections between the individual levels are present. A particular advantage of the invention is that there are no regions of the source regions and the drain regions in which the current travels a long distance, without having an alternative possibility to an overlying metal plane. An increase of the resistance by such an effect is thereby effectively avoided.

In a preferred embodiment, the metallization level has a structure such that at least 50% of the area of the active semiconductor area, preferably at least 70% of the area of the active semiconductor area, and more preferably at least 90% of the area of the active semiconductor area, is covered by the metallization level. The larger the fraction of the area covered by the metallization level, the larger the average cross-section available for lateral power transports. This improves the mentioned reduction of the

See resistance

Advantageously, the at least one source region and the at least one drain region can be designed as strips parallel to one another. This results in a simply structured layout that can be incorporated into existing processes without major changes.

In this case, the metallization level can have strips which have at least the simple, at least three times or at least five times the width of the strips of the source and drain regions. This measure also ensures that a sufficiently large cross-section is available for lateral current transport. The orientation of the strips of the metallization plane can form an angle to the orientation of the source and drain pads of 30 ° to 150 °, in particular from 80 ° to 100 ° and in a special case of 90 °. The current can then be distributed particularly effectively in the semiconductor component.

In a development of the invention, the metallization plane has trapezoidal stripes. In this case, the narrow end of the trapezoid can be located at the places where a direct connection between the trapezoids, which are part of the metallization, and the contact pads by means of the first or second vertical connections is possible. An advantage of this embodiment is a reduced total resistance by a larger metal volume of the buried regions of the metallization.

In an alternative embodiment, it is advantageously provided that the metallization level has a grid or net-like structure. The periodicity may be at least about twice the distance of the source regions from the drain regions and, for example, in the range between 10 .mu.m and 1 mm. It can then enclose one of the pads ring the other pad. In other words, the source pad completely encloses the drain pad, or vice versa. An advantage of this embodiment is a concentric arrangement of source pad and drain pad. In the described geometry, source and drain potentials can be reversed without loss of functionality.

In one development of the invention, the semiconductor component comprises a metallization in an intermediate layer, which has a similar structure to the metallization level and also fulfills a current-distributing function, but is arranged below or above the metallization level. It thus becomes possible to optimize the current distribution for the source regions / source pad and for the drain regions / drain pad independently of one another, since the paths of the source current and the drain current can also cross over one another in plan view.

It is also possible for the metallization plane to have at least two regions lying at different potential, which are structured in such a way that they mesh with one another like a tooth or crenellation. In this way, a reduction of the total resistance can be achieved by a more compact construction of the additional metallization level.

Advantageous developments of the invention are specified in the subclaims and described in the description.

drawings

Embodiments of the invention will be explained in more detail with reference to the drawings and the description below. Show it:

1 1 is a schematic plan view and a cross section through a semiconductor device according to the prior art,

2 a schematic plan view of a first embodiment of the invention,

3 a schematic plan view of a second embodiment of the invention,

4 a schematic plan view of a third embodiment of the invention,

5 a schematic plan view of a fourth embodiment of the invention,

6 a schematic plan view of a fifth embodiment of the invention, and

7 an enlarged section of the in 6 shown embodiment.

Embodiments of the invention

1 shows a semiconductor device, as is known in the prior art. In the upper part of the figure is a schematic plan view of the semiconductor device 100 shown. You can see the sourcepad 102 and the drainpad 104 each extending horizontally from right to left and the uppermost layer of the semiconductor device 100 form. Here, the semiconductor device 100 contacted externally and thus integrated into a circuit. Furthermore, they are each perpendicular to the extension direction of the pads 102 . 104 extending source areas 106 and drainage areas 108 to recognize. The source areas 106 and drainage areas 108 are part of the active semiconductor region and each provided on its surface with ohmic contacts. Also marked are the gate areas not discussed here 110 ,

The source areas 108 become through first vertical connections 112 with the sourcepad 102 connected. The drain areas 110 are analogous to the source regions 108 through second vertical connections 114 with the drainpad 104 connected.

The example shown is the layout for producing a gallium nitride power transistor (GaN transistor). 1 shows in the upper area the plan view of the mask levels. These represent the lateral dimensions of the various metals and dielectrics. The source areas 106 define the areas in which the current is impressed into the semiconductor. Under the current in this case, the electron flow is understood. These areas contain ohmic contacts that have first vertical connections 112 with the sourcepad 102 are connected. The drain areas 108 define the areas in which the current, in turn the flow of electrons, leaves the semiconductor. These also contain ohmic contacts, which have second vertical connections 114 with the drainpad 104 are connected.

The gate areas 110 represent the metallic or semiconductive gate electrodes used to control the transistor. These are not considered further in the context of the present invention. At the first vertical connections 112 and the second vertical connections 114 These are through contacts made of metal, which are embedded in a layer of insulating material.

By means of the sourcepads 102 and the drainpads 104 As well as the gate pad, not shown, the transistor can be connected to the periphery.

The source and drain regions 106 . 108 are usually arranged in, for example, 0.1 mm to 10 mm long and often the entire chip length, thin, for example, 0.2 .mu.m to 10 .mu.m wide strips alternately at equal intervals, for example 5 .mu.m to 30 .mu.m, so that the current flow through the semiconductor covers the same distance at each position of the wafer.

In the example shown in the prior art, an orientation of the contact pads, so the source pads 102 and the drainpads 104 , 90 ° to source areas 106 and the drain areas 108 selected. To provide sufficient area for peripheral connection, the contact pads have dimensions of about (0.1mm-10mm) × (0.1mm-10mm).

The problem is that the current to be impressed or the current to be extracted partially covers long distances between the active semiconductor region and the corresponding pad 102 . 104 The electrons must be covered, for example, in the central area of the 1 through the channel between source area 106 and drainage area 108 flow, must now flow only in the part of the semiconductor device shown in the figure in the lower part to the device through the drain pad 104 to be able to leave. The resistance for these currents can make a significant contribution to the overall resistance of the component 100 Afford. In addition, this effect also leads to an inhomogenization of the resistance of the component 100 ,

At the bottom of the 1 is a cross section through the semiconductor device 100 to see. In turn, the source areas can be seen 106 , the drain areas 108 , the gate areas 110 as well as the first vertical connections 114 , These connect the drain areas 108 with the drainpad 104 ,

2 shows a schematic plan view of a first embodiment of the invention. Unless otherwise stated, the elements of the 2 described Embodiment the same as for the in 1 apply described semiconductor device. In particular, the mentioned dimensions of the pads, source and drain regions, etc. as well as the construction of the vertical connections can be adopted.

Similar to in 1 are source areas 8th and drainage areas 10 to recognize, which are designed as parallel strips and are arranged in a common plane. Also visible are those adjacent to the source regions 8th lying gate areas 12 , In the left part of the figure is the Sourcepad 2 drawn in the right part of the figure is the drain pad 4 to see. The two pads 2 . 4 are out compared to the corresponding pads 1 rotated 90 ° and run in the figure from top to bottom instead of from right to left the pads 2 . 4 thus run parallel to the source regions 8th and to the drainage areas 10 , In addition, the pads are 2 . 4 enlarged in area and cover a large part of the surface of the semiconductor device 1 , In essence, the dimensions of the pads match 2 . 4 those known from the prior art.

As at right angles to the source areas 8th and the gate areas 10 running is the metallization level 30 located. The metallization level consists of several parallel strips in the case shown 32 . 34 that cover most of the substrate surface. The individual stripes 32 . 34 are within the metallization level 30 each non-conductive with the other strips 32 . 34 connected. Every strip 32 . 34 is either the source areas 8th or the drainage areas 10 assigned and electrically connected to these. Such are the stripes 32 by means of the third vertical connections 53 with the source areas 8th connected, and the stripes 34 are by means of the fourth vertical connections 54 with the drainage areas 10 connected. The metallization level 30 is thus at least partially with both the source regions 8th as well as with the drainage areas 10 as well as the sourcepad 2 and the drainpad 4 connected. In each case separate sections, in the case shown in each case one of the strips 32 . 34 , is both with the source area 8th as well as with the sourcepad 2 whereas other sections connect both to the drain region 10 as well as with the drainpad 4 are connected. You can get the stripes 32 thus as source sections of the metallization level 30 or as a source strip and the stripes 34 analogous to drain sections of the metallization plane 30 or denote drainpipe.

The source stripes 32 and the drains 34 extend lengthwise across the width of the chip (0.1mm-10mm). Their width along the chip length can vary between approx. 5 μm and 1 mm. Their distance can be, for example, about 5 microns to 30 microns. But there are also smaller distances in the range of 1 micron possible. By the arrangement of the vertical connections 51 . 52 . 53 and 54 is achieved that two adjacent stripes 32 . 34 have different potential (source and drain). The terms "length" and "width" of the chip are chosen arbitrarily and interchangeable. Man could call "length" and "width" also "first page" and "second page".

In the areas where the source stripes 32 and the source areas 8th overlap, are third vertical links 53 arranged to allow a current flow between the source regions 8th and the source strip 32 to enable. Analogous to this are between the drain strips 34 and the drainage areas 10 fourth vertical connections 54 arranged.

In a similar way, the electrical connection between the metallization level 30 and the sourcepad 2 as well as the drainpad 4 realized. Again, the appropriate overlap area for placement of vertical connections 51 . 52 used. So are in the area where the sourcepad 2 and the source stripes 32 overlap each other, first vertical connections 51 arranged. In the area where the drainpad 4 and the drains 34 overlap, are second vertical links 52 arranged.

The vertical connections 51 . 52 . 53 and 54 may be simple metallizations enclosed by a thin insulating layer. They can, as in the illustrated embodiment, each have a square cross-section (alternatively also circular) and be distributed equidistantly over the corresponding surface. Depending on the geometric shape of the overlap surface may be a linear arrangement as in the first and second vertical connections 51 . 52 or a two-dimensional grid arrangement as in the third and fourth vertical connections 53 . 54 to offer.

Some stripes 32 the metallization level 30 are with the sourcepad 2 by means of the first vertical connections 51 connected. The other stripes 34 the metallization level are by means of the second vertical connections 52 with the drainpad 4 connected.

3 shows a schematic plan view of a second embodiment of the invention. In essence, the structure of the semiconductor device corresponds 1 the in 2 shown. Accordingly, the individual elements are each denoted by the same reference numerals as in FIG 2 Mistake. The main difference lies in the Structuring of the metallization level 30 , The source stripes 32 and drainpipe 34 are not rectangular as in 2 but trapezoidal. In other words, the stripes show 32 . 34 do not have a constant width but are directed to the side where they reach by means of the first vertical links 51 or by means of the second vertical connections 52 with the sourcepad 2 or with the drainpad 4 are connected, narrower.

The lengths of the mutually parallel sides of the trapeze have a ratio of about 2 to 1. Other ratios in the range between 10 to 1 and 1 to 1 are also possible, for example, 1: 1, 5: 1 or 10: 1. For example, so is the long side of the source strip 32 the one below the drainpads 4 is arranged. This page is about twice as long as the parallel side that bounds the strip opposite and the one below the source pad 2 is arranged. Such a configuration results in the area in which the metallization level 30 with the active semiconductor region, in other words with the source region 8th or the drainage area 10 is connected, a particularly small resistance through the metallization 30 , This is advantageous, since in these areas a relatively large resistance arises in conventional semiconductor components.

In the opposite area where the stripes 32 . 34 with the pads 2 . 4 are connected, results from the opposite rectangular strip as in 2 Although the width of the strip is slightly lower, the overall resistance is due to the design with trapezoidal stripes 32 . 34 but reduced to rectangular strips.

4 shows a schematic plan view of a third embodiment of the invention. The embodiment shown substantially corresponds to the embodiment of 3 , Like reference numerals indicate elements of the same name. Opposite the in 3 However, the embodiment shown are Sourcepad 2 and drainpad 4 as well as the source stripes 32 and the drains 34 turned by 90 degrees. The source stripes 32 and the drains 34 thus run parallel to the source regions 8th and the drain areas 10 whereas the pads 2 . 4 perpendicular to the source regions 8th and the drain areas 10 run. The source areas 8th and the drain areas 10 are each equidistant over their full length by means of third and fourth vertical connections 53 . 54 with the source stripes 32 or the drainage strip 34 connected.

5 shows a schematic plan view of a fourth embodiment of the invention. You can see the drain pad 4 , which is centrally located and from the sourcepad 2 is completely enclosed. The metallization level 30 takes in the embodiment shown, the majority of the surface of the semiconductor device 2 and only points below the drainpads 4 some gaps 6 on, so where none to the metallization level 30 belonging material between the drainpad 4 and the active semiconductor region, in particular the source regions 8th , is available. The sourcepad 2 lies completely outside the active semiconductor region, so does not cover it. Alternatively, the active semiconductor region may also be below the source pad 2 be continued.

By means of second vertical connections 52 and fourth vertical links 54 are the drain areas 10 with the drainpad 4 connected. In the embodiment shown, the second vertical connections 52 and the fourth vertical links 54 arranged directly above one another. The second vertical connections 52 have a larger cross-section than the fourth vertical links 54 , This is not important for the functionality, but can offer production advantages, since thus the third and fourth vertical connections 53 . 54 as well as the first and second vertical connections 51 . 52 are designed similar.

Surrounding the semiconductor device 1 are the first vertical connections 51 arranged the metallization level 30 with the sourcepad 2 connect. They are arranged equidistantly in two parallel rows in the embodiment shown, but can also be arranged in other patterns.

6 shows a schematic plan view of a fifth embodiment of the invention. Again, the drainpad 4 centrally located and accessed by the sourcepad 2 enclosed. The sourcepad 2 thus, unlike in 5 shown embodiment again a part of the active semiconductor region. The metallization level is divided in two into a source 36 and a drain portion 38 , The source part 36 has roughly a "double-T-structure": In the figure above and below it extends to the edge of the semiconductor device 1 , on the right edge and on the left edge of the source portion is about one quarter of the width of the semiconductor device 1 withdrawn, so that the source part 36 here about half the width of the semiconductor device 2 covers. In the areas right and left in the figure, in which the source part 36 not extending is the drain portion 38 arranged.

In the border area between source part 36 and drainage share 38 they are "interlocked" with each other. In other words, both source share 36 as well as drainage share 36 a crenellated structure, wherein the battlements of one part of the metallization are formed corresponding to the battlements of the other part of the metallization and engage in this. However, in each case a small horizontal distance is maintained so that there is no electrical contact between the source component 36 and drainage share 38 comes. Instead of a crenellated embodiment, for example, a sawtooth-like shape is conceivable. Of course, as in all illustrated embodiments, all the metallization components associated with the source pad 2 in contact, electrically from the drain pad 4 isolated.

The middle two drainage areas in the figure 10.1 and 10.2 are by means of the second vertical connections 52 (please refer 7 ) and the fourth vertical connections 54 (please refer 7 ) with the drain pad 4 connected. The other drainage areas 10 are on the other hand, over the fourth vertical connections 54 (please refer 7 ) as in the other embodiments also with the metallization, here in the form of the drain section 38 , connected.

7 shows an enlarged section of the semiconductor device 1 according to 6 , It is particularly good here the teeth of the source part 36 with the drainage portion 38 the metallization level as well as the boundaries of the sourcepads 2 and the drainpads 4 to recognize.

All structures described can be repeated as often as desired over the entire semiconductor component and thus be regarded as unit cells. It is also possible to exchange the respective geometric positions of the elements with source functionality with the elements with drain functionality, without deviating from the idea of the invention. It is thereby reversed only the current direction. Also, more individual elements, for example, more parallel source and drain regions than shown may be present in the unit cells. For the sake of clarity, only a relatively small number of structures are shown in the figures.

Claims (10)

Semiconductor device ( 1 ), in particular power transistor, having a substrate, an active semiconductor region, which has at least one source region ( 8th ) and at least one drain region ( 10 ) and with a source pad covering a first part of the substrate ( 2 ) and with a drain pad covering a second part of the substrate ( 4 ), characterized in that i. between the sourcepad ( 2 ) or the drainpad ( 4 ) and the at least one source region ( 8th ) or the at least one drain region ( 10 ) has a substantially horizontally extending structured metallization plane ( 30 ), wherein ii. the sourcepad ( 2 ) by means of at least one first substantially vertically extending metallization ( 51 ) with at least a first part of the metallization plane ( 30 ) and the drainpad ( 4 ) by means of at least one second substantially vertically extending metallization ( 52 ) with at least a second part of the metallization level ( 30 ), and wherein iii. the at least one first part of the metallization level ( 30 ) by means of a third substantially vertically extending metallization ( 53 ) with the at least one source region ( 8th ) and wherein the at least one second part of the metallization level ( 30 ) by means of a fourth substantially vertically extending metallization ( 54 ) with the at least one drain region ( 10 ) connected is. Semiconductor device ( 1 ) according to claim 1, wherein the metallization plane ( 30 ) has a structure such that at least 50% of the area of the active semiconductor region, preferably at least 70% of the area of the active semiconductor region and more preferably at least 90% of the area of the active semiconductor region of the metallization plane ( 30 ) are covered. Semiconductor device ( 1 ) according to claim 1 or 2, wherein the at least one source region ( 8th ) and the at least one drain region ( 10 ) are designed as mutually parallel aligned strips which at least the simple width of the strips of the source and drain regions ( 8th . 10 ) exhibit. Semiconductor device ( 1 ) according to any one of the preceding claims, wherein the metallization level ( 30 ) trapezoidal stripes ( 32 . 34 ) having. Semiconductor device ( 1 ) according to one of claims 3 to 4, wherein the orientation of the strips ( 32 . 34 ) of the metallization level ( 30 ) an angle to the orientation of the source and drainpads ( 2 . 4 ) forms an angle of 30 ° to 150 °, in particular of 90 °. Semiconductor device ( 1 ) according to any one of the preceding claims, wherein the metallization level ( 30 ) has a grid or net-like structure. Semiconductor device ( 1 ) according to any one of the preceding claims, wherein either the source pad ( 2 ) the drainpad ( 4 ) or the drainpad ( 4 ) the sourcepad ( 2 ) encloses annular or box-shaped. Semiconductor device ( 1 ) according to one of the preceding claims, wherein the semiconductor component ( 1 ) another metallization in one Intermediate layer, which to the metallization ( 30 ) is constructed similarly, wherein the further metallization fulfills a current-distributing function and below or above the metallization ( 30 ) is arranged. Semiconductor device ( 1 ) according to any one of the preceding claims, wherein the metallization level ( 30 ) at least two areas lying in a common plane at different potential ( 36 . 38 ), which are structured so that they mesh with each other like a tooth or crenelated. Control device for a vehicle, comprising at least one semiconductor component ( 1 ) according to any one of the preceding claims.

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