TWI732221B - Power-on reset circuit and electronic device using it - Google Patents

Abstract

A power-on reset circuit has: a resistor and a capacitor, connected in series between a DC voltage and a reference ground, and providing a first output signal at a connection point of the resistor and the capacitor; a digital conversion circuit, The first output signal is used to perform a digital conversion operation to generate a reset signal; a potential detection circuit is used to generate a switching signal according to the potential of the DC voltage, and the potential detection circuit At the first potential, the switching signal is made to assume a high potential, when the DC voltage is higher than a second potential, the switching signal is made to assume a low potential, and the second potential is greater than or equal to the first potential; and The switch element has a channel and a control terminal, the channel is coupled between the connection point and the reference ground, and the control terminal is coupled with the switch signal.

Description

Power-on reset circuit and electronic device using it

The invention relates to a power-on reset circuit, in particular to a power-on reset circuit that can ensure the consistency of the power-on reset signal under the condition of repeated fast power-on and power-off.

During the reset process of general electronic devices, most of their registers are reset by an external HWRESET signal, and some of the registers are reset by an internal POR (power on reset) signal. . However, in the process of repeated power-on and power-off, the POR signal may become invalid.

Please refer to FIG. 1, which shows a circuit diagram of an internal power-on reset circuit of a conventional electronic device. As shown in FIG. 1, the internal power-on reset circuit has a resistor 11, a capacitor 12, an inverter 13 and an inverter 14.

The resistor 11 and the capacitor 12 are connected in series between the DC voltage V _PP and a reference ground, and provide a first output signal V _{A at} the connection point of the resistor 11 and the capacitor 12.

The inverter 13 and the inverter 14 are used to _{perform a digital conversion operation on the first output signal V A} to generate a reset signal POR.

However, when the conventional electronic device is repeatedly powered on and off quickly, the reset signal POR is likely to be invalid. Please refer to FIG. 2, which is a working waveform diagram of the internal power-on reset circuit of FIG. 1 when the conventional electronic device is repeatedly powered on and off quickly. As shown in FIG. 2, the conventional electronic device is powered off _{at t 1 and powered on at t 2 immediately after the DC voltage V PP} drops to zero potential. Because the resistor 11 and the capacitor 12 provide a delay effect, the first output signal V _A is still maintained at a high logic potential when the DC voltage V _PP drops to a zero potential, so that the reset signal POR fails to change from a high potential to a low potential. Therefore, the reset signal POR cannot _{generate a rising edge after t 2} to reset part of the registers.

In order to solve the above-mentioned problems, a novel power-on reset circuit is urgently needed in the art.

The main purpose of the present invention is to provide a power-on reset circuit, which can ensure the consistency of a power-on reset signal when a user repeats quick power-on and power-off operations on an electronic device by a potential detection circuit .

To achieve the aforementioned purpose, a power-on reset circuit is proposed, which has:

A resistor and a capacitor are connected in series between the DC voltage and a reference ground, and provide a first output signal at a connection point of the resistor and the capacitor;

A digital conversion circuit for performing a digital conversion operation on the first output signal to generate a reset signal;

A potential detection circuit is used to generate a switching signal according to the potential of the DC voltage. When the DC voltage is lower than a first potential, the potential detection circuit makes the switching signal present a high potential. When it is higher than a second potential, the switch signal will be at a low potential, and the second potential is greater than or equal to the first potential; and

A switch element has a channel and a control terminal, the channel is coupled between the connection point and the reference ground, and the control terminal is coupled with the switch signal.

In one embodiment, the digital conversion circuit is formed by connecting two inverters in series.

In one embodiment, the switching element is an NMOS transistor. The NMOS transistor has a drain, a gate, and a source. The drain and the source are both ends of the channel, and the gate Department of the control terminal.

To achieve the foregoing objective, the present invention further provides an electronic device having a power-on reset circuit and a processor. The power-on reset circuit is used to generate a reset signal to reset the electronic device when the electronic device is powered on. At least one register in the processor is set, characterized in that the power-on reset circuit has:

A resistor and a capacitor are connected in series between the DC voltage and a reference ground, and provide a first output signal at a connection point of the resistor and the capacitor;

A digital conversion circuit for performing a digital conversion operation on the first output signal to generate the reset signal;

A potential detection circuit is used to generate a switching signal according to the potential of the DC voltage. When the DC voltage is lower than a first potential, the potential detection circuit makes the switching signal present a high potential. When it is higher than a second potential, the switch signal will be at a low potential, and the second potential is greater than or equal to the first potential; and

A switch element has a channel and a control terminal, the channel is coupled between the connection point and the reference ground, and the control terminal is coupled with the switch signal.

In one embodiment, the digital conversion circuit is formed by connecting two inverters in series.

In one embodiment, the switching element is an NMOS transistor. The NMOS transistor has a drain, a gate, and a source. The drain and the source are both ends of the channel, and the gate Department of the control terminal.

In possible embodiments, the electronic device can be a smart phone or a portable computer.

In order to enable your reviewer to further understand the structure, features and purpose of the present invention, drawings and detailed descriptions of preferred specific embodiments are attached as follows.

Please refer to FIG. 3, which shows a circuit diagram of an embodiment of the electrical reset circuit on the electronic device of the present invention. As shown in FIG. 3, a power-on reset circuit 100 has a resistor 110, a capacitor 120, an inverter 130, an inverter 140, a potential detection circuit 150, and an NMOS transistor 160.

The resistor 110 and the capacitor 120 are connected in series between the DC voltage V _PP and a reference ground, and provide a first output signal V _{A at} the connection point A of the resistor 110 and the capacitor 120.

The inverter 130 and the inverter 140 are connected in series to form a digital conversion circuit to _{perform a digital conversion operation on the first output signal V A} to generate a reset signal POR.

The potential detection circuit 150 is used to _{generate a switch signal SW according to the potential of the DC voltage V PP} . The potential detection circuit 150 makes the switch signal SW present a high potential when the _{DC voltage V PP is lower than a first potential.} When the DC voltage V _{PP is} higher than a second potential, the switch signal SW will be at a low potential, and the second potential is greater than or equal to the first potential.

The NMOS transistor 160 has a drain, a gate, and a source for realizing a switching element. The drain and the source are two ends of a channel of the switching element, and the gate is the switching element A control terminal, the channel is coupled between the connection point A and the reference ground, and the control terminal is coupled with the switch signal SW.

Please refer to FIG. 4, which is a working waveform diagram of the electrical reset circuit in FIG. 3 when the electronic device is repeatedly powered on and off. As shown in Fig. 4, the electronic device is powered off _{at t 1 and powered on at t 2 immediately after the DC voltage V PP} drops to zero potential. When the DC voltage V _PP drops below V ₁ , the reset signal POR will change from high to low; and when the DC voltage V _PP rises from zero to higher than V ₂ , the reset signal POR will change from low. It becomes a high potential, so that the reset signal POR _{can generate a rising edge after t 2} to reset part of the registers.

Based on the above description, the present invention further provides an electronic device. Please refer to FIG. 5, which shows a block diagram of an embodiment of the electronic device of the present invention. As shown in FIG. 5, an electronic device 200 has a power-on reset circuit 210 and a processor 220, where the power-on reset circuit 210 is implemented by the power-on reset circuit 100 on the electronic device 200. At least one register in the processor 220 is reset when it is powered on.

In possible embodiments, the electronic device 200 can be a smart phone or a portable computer.

With the technical solutions disclosed above, the power-on reset circuit of the present invention can ensure the consistency of a power-on reset signal when the user repeatedly performs quick power-on and power-off operations on an electronic device.

The disclosure in this case is a preferred embodiment, and any partial changes or modifications that are derived from the technical ideas of the case and can be easily inferred by those who are familiar with the art will not deviate from the scope of the patent right of the case.

To sum up, no matter the purpose, means or effect of this case, it is shown that it is very different from the conventional technology, and its first invention is suitable for practicality, and it does meet the patent requirements of the invention. I implore the examiner to check it out and grant the patent as soon as possible. Society is for the best prayer.

11: Resistance

12: Capacitance

13: inverter

14: inverter

100: Power-on reset circuit

110: resistance

120: Capacitance

130: inverter

140: inverter

150: Potential detection circuit

160: NMOS transistor

200: electronic device

210: Power-on reset circuit

220: processor

FIG. 1 is a circuit diagram of an internal power-on reset circuit of a conventional electronic device. FIG. 2 is a working waveform diagram of the internal power-on reset circuit of FIG. 1 when the conventional electronic device is repeatedly powered on and off quickly. 3 is a circuit diagram of an embodiment of the electrical reset circuit on the electronic device of the present invention. FIG. 4 is a working waveform diagram of the electrical reset circuit of FIG. 3 when the electronic device is repeatedly powered on and off quickly. FIG. 5 is a block diagram of an embodiment of the electronic device of the present invention.

100: Power-on reset circuit

110: resistance

120: Capacitance

130: inverter

140: inverter

150: Potential detection circuit

160: NMOS transistor

Claims (7)

A power-on reset circuit, which has: a resistor and a capacitor, which are connected in series between a DC voltage and a reference ground, and provide a first output signal at a connection point of the resistor and the capacitor; a digital conversion The circuit is used to perform a digital conversion operation on the first output signal to generate a reset signal; a potential detection circuit is used to generate a switching signal according to the potential of the DC voltage, wherein the potential detection circuit is in the When the DC voltage is lower than a first potential, the switching signal will be at a high potential. When the DC voltage is higher than a second potential, the switching signal will be at a low potential, and the second potential is greater than or equal to the first potential. Potential; and a switching element having a connection terminal, a channel and a control terminal, wherein the connection terminal is coupled between the connection point and the digital conversion circuit, and the channel is coupled to the connection terminal via the connection terminal Between the connection point and the reference ground, and the control terminal is coupled to the switch signal. For example, the power-on reset circuit described in the first item of the scope of patent application, wherein the digital conversion circuit is formed by two inverters connected in series. As described in the first item of the scope of patent application, the upper electrical reset circuit, wherein the switching element is an NMOS transistor, the NMOS transistor has a drain, a gate and a source, the drain and the source Are the two ends of the channel, and the gate and the drain are the control end and the connection end, respectively. An electronic device having a power-on reset circuit and a processor. The power-on reset circuit is used to generate a reset signal to reset at least one register in the processor when the electronic device is powered on, It is characterized in that the power-on reset circuit has: a resistor and a capacitor, which are connected in series between the DC voltage and a reference ground, and provide a first output signal at a connection point of the resistor and the capacitor; A digital conversion circuit for performing a digital conversion operation on the first output signal to generate the reset signal; a potential detection circuit for generating a switching signal according to the potential of the DC voltage, wherein the potential detection circuit When the DC voltage is lower than a first potential, the switching signal will be at a high potential. When the DC voltage is higher than a second potential, the switching signal will be at a low potential, and the second potential is greater than or equal to the first potential; and a switching element having a connection terminal, a channel and a control terminal, Wherein, the connection terminal is coupled between the connection point and the digital conversion circuit, the channel is coupled between the connection point and the reference ground via the connection terminal, and the control terminal is coupled to the switch signal Pick up. In the electronic device described in item 4 of the scope of patent application, the digital conversion circuit is formed by connecting two inverters in series. The electronic device described in claim 4, wherein the switching element is an NMOS transistor, the NMOS transistor has a drain, a gate and a source, and the drain and the source are the channel The gate and the drain are the control terminal and the connection terminal respectively. For example, the electronic device described in item 4 of the scope of patent application is a smart phone or a portable computer.

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