TWI728267B - Process control method for semiconductor manufacturing - Google Patents

Abstract

A process control method for semiconductor manufacturing is disclosed. First, a substrate having a dielectric layer thereon is provided. A patterning process is performed to form at least a trench in the dielectric layer, wherein a main surface of the dielectric layer comprises a trench pattern defined by the trench. A conductive material is formed on the dielectric layer and completely fills the trench. Subsequently, a polishing process is performed to remove the conductive material outside the trench and a portion of the dielectric layer until a first surface of the dielectric layer comprising a first circuit pattern defined by the conductive material remained in the trench is obtained. Afterward, an inline critical dimension measurement step is performed to obtain a dimension of the first circuit pattern. The dimension of the first circuit pattern is then used to determine whether the patterning process needs to be adjusted.

Description

Semiconductor manufacturing process control method

The present invention relates to a semiconductor process control method, in particular to a semiconductor process control method for controlling the size and sidewall profile of trenches used to form circuit structures.

As the size of semiconductor devices shrinks, the adjustment of key dimensions has a significant impact on device performance and yield. Generally speaking, for semiconductor structures formed by filling trenches, for example, the key dimensions of metal electrical connection structures formed by filling trenches formed in a dielectric layer, the production control is mostly to form conductive materials to fill the trenches. The ditch is measured online, and the size of the metal electrical connection structure is indirectly obtained according to the ditch size for control. Subsequently, after forming a conductive material to fill the trench, a polishing process is used to remove the excess conductive material outside the trench, and at the same time, the dielectric layer is polished to a predetermined thickness to produce a metal electrical connection structure. However, in the process of forming trenches, due to material properties or process load effects, the trenches may have sidewall profiles that are not perpendicular to the substrate surface, such as expanded, recessed, or cup-shaped sidewall profiles. In this case, there are often errors between the size of the trench obtained by the aforementioned online measurement and the size of the metal electrical connection structure in the final semiconductor device, and the tendency of the size deviation cannot be correctly reflected. On the other hand, although it is possible to cut the wafer and prepare a sample showing the cross-sectional structure of the metal electrical connection structure, and then use electron microscopy techniques such as TEM or SEM to measure the actual size and sidewall profile of the metal electrical connection structure. The method not only consumes wafer and sample preparation time, but also fails to provide statistically significant within wafer uniformity data to feed back to the production line to determine whether the process needs to be adjusted. Therefore, it is necessary to provide an improved semiconductor process control method that can effectively control The key dimensions of the metal electrical connection structure filled in the trench.

The main purpose of the present invention is to provide a semiconductor manufacturing process control method. Specifically, after grinding and removing the excess conductive material outside the trench, the circuit pattern exposed on the surface is measured on-line, so as to obtain a semiconductor device closer to the final existence. The size of the line structure in the. According to the size, it is evaluated whether it is necessary to adjust the patterning process for forming the trench, so that the size of the trench can be controlled more accurately, and the size of the circuit structure can be more accurately controlled.

To achieve the above objective, an embodiment of the present invention provides a semiconductor manufacturing process control method, which includes the following steps. First, a substrate is provided, and a dielectric layer is located on the substrate. Then, a patterning process is performed to form at least one trench in the dielectric layer, and the trench forms a trench pattern on a main surface of the dielectric layer. After forming a conductive material to completely fill the trench, a first polishing process is performed to remove the conductive material outside the trench and remove part of the dielectric layer until a first surface of the dielectric layer is exposed. A surface includes a first circuit pattern composed of the remaining conductive material. Subsequently, an online measurement is performed on the first circuit pattern to obtain a first circuit pattern size, and according to the first circuit pattern size, it is evaluated whether the patterning process needs to be adjusted.

To achieve the above objective, another embodiment of the present invention provides a semiconductor manufacturing process control method, which includes the following steps. First, a wafer is provided, which includes a plurality of non-overlapping wafer areas, and a dielectric layer is located on the wafer and covers each of the wafer areas. Then, a patterning process is performed to form at least one trench in the dielectric layer of each of the chip regions, and the trenches of each of the chip regions respectively form a trench pattern on a surface of the dielectric layer. Then, a conductive material is formed to completely fill the trenches of each of the chip regions, and a first polishing process is performed to remove the conductive material outside the trenches of each of the chip regions and remove part of the dielectric layer. Until a first surface of the dielectric layer is exposed, the first surface includes a plurality of first circuit patterns formed by the conductive material filled in the trenches of each of the chip regions. After that, perform an online measurement on the first circuit patterns to obtain a plurality of first circuit pattern sizes and a first circuit pattern size wafer map, and evaluate whether the first circuit pattern size wafer map needs to be adjusted. Patterning process.

As mentioned above, the present invention can not only control the size of the trench more accurately, but also more accurately control the size of the circuit structure. It is also possible to obtain and compare the circuit dimensions of multiple different grinding stages by measuring the semiconductor components online at different grinding stages. It is possible to infer the accommodating circuit structure without the need to scrap wafers and save the time for preparation of profile samples. Whether the ditch has an ideal sidewall profile is immediately fed back to the steps of forming the ditch to effectively control the size and sidewall profile of the ditch. In addition, online measurement can also be used to quickly obtain a size wafer map closer to the final size of the circuit structure of the semiconductor device and more statistically significant within wafer uniformity data.

102: Step

104: Step

106: step

108: Step

110: Step

112: Step

114: step

116: step

118: Steps

110a: Step

112a: Step

100: flow chart

200: flow chart

300: flow chart

A-A': Tangent

P1: Patterning process

S, S0, S1, S2: spacing

210: Base

220: Dielectric layer

222: Etch stop layer

226: first dielectric layer

226: second dielectric layer

228: third dielectric layer

229: Hard Mask Layer

220': main surface

220a: first surface

220b: second surface

220c: third surface

230: ditch

230a: Ditch pattern

230b: sidewall profile

240: conductive material

P2: The first grinding process

P3: The second grinding process

T, T1, T2, T3: thickness

W, W0, W1, W2: width

250: conductive material

250a: the first line pattern

250b: second line pattern

250c: third line pattern

In order to make the above and other objectives, features, advantages and embodiments of the present invention more obvious and understandable, the detailed description of the accompanying drawings is as follows: FIG. 1 is a flowchart of a semiconductor process control method 100 according to the first embodiment of the present invention.

FIGS. 2 to 5 are schematic diagrams of the semiconductor device 10 in different process stages of the semiconductor process control method 100 of the first embodiment, wherein the upper part is a top view, and the lower part is a schematic cross-sectional view along the AA' line in the top view .

FIG. 6 is a flowchart of a semiconductor process control method 200 according to the second embodiment of the present invention.

Figures 7 to 10 show the semiconductor device 10 in the second embodiment of the semiconductor process control method 200 Schematic diagrams of different process stages, where the upper part is a top view, and the lower part is a schematic cross-sectional view along the A-A' tangent line in the top view.

FIG. 11 is a flowchart of a semiconductor process control method 300 according to the third embodiment of the present invention.

FIG. 12 is a schematic diagram of a wafer 400 used in the semiconductor process control method 300 of the third embodiment.

FIG. 13 illustrates a size wafer map 500 obtained by the semiconductor process control method 300 of the third embodiment.

FIG. 14 illustrates a test wafer diagram 600 obtained by the semiconductor process control method 300 of the third embodiment.

Please refer to Figure 1 to Figure 5. FIG. 1 is a flowchart of a semiconductor process control method 100 according to the first embodiment of the present invention. FIGS. 2 to 5 are schematic diagrams of the semiconductor device 10 in different process stages of the semiconductor process control method 100 of the first embodiment, wherein the upper part is a top view, and the lower part is a schematic cross-sectional view along the AA' line in the top view . The semiconductor element 10 may be all or a part of an integrated circuit, such as a metal electrical connection structure, a capacitor structure, a resistance structure, an electronic shielding structure, a fuse, an inductor, or other semiconductor elements to which the semiconductor process control method 100 can be applied. It should be understood that, in other embodiments, other steps may be added before, during, or after the semiconductor process control method 100, and some steps in the semiconductor process control method 100 may also be substituted or omitted.

First, as shown in FIG. 1 and FIG. 2, the semiconductor process control method 100 of this embodiment includes step 102, providing a substrate 210 on which a dielectric layer 220 is included. The substrate 210 is, for example, a silicon substrate, a silicon-coated insulating substrate, a group-three-five semiconductor substrate, etc., but is not limited thereto. The substrate 210 may include fabricated semiconductor structures, such as transistors, capacitors, resistors, inductors, electrical connection structures, etc., which are not shown in order to simplify the drawings. The dielectric layer 220 can provide electrical isolation and structural support for the subsequently formed conductive structure. support. The dielectric layer 220 may include a single layer or a stacked material layer, preferably a multilayer structure, for example, it may include a hard mask layer 229, a third dielectric layer 228, a second dielectric layer 226, The first dielectric layer 224 and the etch stop layer 222. The material of the hard mask layer 229 is, for example, silicon nitride (SiN) or silicon oxynitride (SiON), the material of the third dielectric layer 228 is, for example, silicon oxynitride (SiON), and the second dielectric layer 226 is preferably low dielectric. Constant dielectric material (low-k dielectric material), such as fluorinated silica glass (FSG), carbon silicon oxide (SiCOH), spin-on glass, porous low-dielectric material Constant dielectric materials (porous low-k dielectric materials), organic polymer dielectric materials, such as benzocyclobutene (BCB-based) polymer dielectric materials, high scores based on silsesquioxanes-based Dielectric materials, etc., or combinations thereof, but not limited thereto. The material of the first dielectric layer 224 is, for example, tetra-ethyl-ortho-silicate (TEOS), which can increase the adhesion and deposition quality of the second dielectric layer 226. The material of the etch stop layer 222 is, for example, a dielectric material such as silicon nitride (SiN) or silicon carbide nitride (SiCN) that has etch selectivity with the first dielectric layer 224 and the second dielectric layer 226. The hard mask layer 229 can be used as an etching hard mask layer in the patterning process P1 of etching the dielectric layer 220 to form trenches 230 as shown in FIG. 3, or as a polishing layer in the first polishing process P2 shown in FIG. The polishing stop layer of the conductive material outside the trench.

Next, as shown in FIGS. 1 and 3, step 104 is performed to perform a patterning process P1, such as a photolithography and etching process, to define a plurality of trenches parallel to each other and closely arranged in the dielectric layer 220 230. The patterning process P1 may include first forming a photoresist layer (not shown) on the dielectric layer 220, and then transferring a predetermined pattern of the trench from a photomask to the photoresist layer through an exposure and development process, and then applying the photoresist layer to the photoresist layer. The resist layer is an etching mask to etch the dielectric layer 220, such as plasma etching, to transfer the predetermined pattern of the trench to the dielectric layer 220 to form the trench 230. It is worth noting that due to the loading effect of the patterning process P1, for example, the thickness of the patterned photoresist layer is uneven, or the etching gas has different diffusion rates at different depths of the trench when the dielectric layer 220 is etched, or due to the difference in the dielectric layer 220 The material layer has different etching rates for the etching process, which will cause the trench 230 to have a sidewall profile that is not perpendicular to the surface of the substrate, such as an outer expansion, an inner recess, or a cup shape. The sidewall profile. Especially when the second dielectric layer 226 is made of a low dielectric constant material, it will have a higher etching removal rate than the third dielectric layer 228, so that the trench 230 passes through a portion of the second dielectric layer 226 The side walls expand outward to form a side wall profile 230b that is slightly cup-shaped as shown in the lower part of FIG. 3. Please refer to the upper part of FIG. 3, the main surface 220' of the dielectric layer 220 (for example, the surface of the top hard mask layer 229) includes a plurality of trench patterns 230a defined by the trenches 230. The trench patterns 230a collectively constitute a grid-shaped trench pattern.

Next, as shown in FIGS. 1 and 4, step 108 is performed to form a conductive material 240 on the dielectric layer 220 and completely fill the trenches 230. The conductive material 240 may be formed by deposition methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), and may include a single layer Or a multi-layer structure, for example, a barrier layer and/or a liner layer (not shown) is formed to conformally cover the sidewalls and bottom surfaces of the dielectric layer 220 and the trench 230, and then on the barrier layer and/or liner layer A metal layer (not shown) is deposited to completely cover the dielectric layer 220 and fill the trench 230. The barrier layer and/or the liner layer may include materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), but is not limited thereto. The metal layer may include tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP) materials, but is not limited thereto.

Next, as shown in FIGS. 1 and 5, step 110 is performed to perform a first polishing process P2 to remove the excess conductive material 240 outside the trench 230 and remove part of the dielectric layer 220 by a thickness, such as a thickness T, The hard mask layer 229, the third dielectric layer 228 and part of the second dielectric layer 226 are completely removed until the first surface 220a of the dielectric layer 220 (that is, the surface of the second dielectric layer 226) is obtained. The first polishing process P2 may include multiple polishing stages. For example, in the first polishing stage, the hard mask layer 229 is used as a polishing stop layer to ensure that the conductive material 240 outside the trench 230 is completely removed, and then a second polishing stage is performed to remove the third The dielectric layer 228 and part of the second dielectric layer 226. As shown in the lower part of FIG. 5, the remaining conductive material 250 filled in the trench 230 becomes a circuit structure with a target thickness. Please refer to the upper part of Figure 5. At this time, the first part of the semiconductor structure 10 The surface 220a will expose the first circuit pattern 250a defined by the remaining conductive material 250 filled in the trench 230.

Please continue to refer to FIGS. 1 and 5, and then proceed to step 112 to perform an online measurement on the first circuit pattern 250a on the first surface 226a to obtain a first circuit pattern size. The size of the first circuit pattern may be the width W of the first circuit pattern 250a or the spacing S between adjacent first circuit patterns 250a. The online measurement in step 112 preferably uses a scanning electron microscope (Scanning Electron Microscope, SEM) for measurement, which scans the surface of the sample with a tiny focused electron beam, and then collects the difference between the electron beam and the surface of the sample. Signals such as secondary electrons, backscattered electrons, and characteristic X-rays are excited by the interaction between them for imaging. Because the surface morphology or material of the sample will excite signals of different strengths, a grayscale image corresponding to the pattern on the surface of the sample can be obtained, and then the size of the pattern can be obtained by measuring the grayscale image. In other words, the online measurement in step 112 is to perform electron beam scanning on the first surface 220a to obtain a grayscale image corresponding to the first circuit pattern 250a, and then measure the grayscale image to obtain the size of the first circuit pattern. It is worth noting that because the first polishing process P1 removes a part of the dielectric layer 220, the size of the first circuit pattern measured in step 112 will be the size of the trench 230 farther from the main surface 220' of the dielectric layer 220. It is also closer to the size of the circuit structure (consisting of the remaining conductive material 250) finally existing in the semiconductor element 10.

Next, referring to FIG. 1, proceed to step 114, and evaluate whether the patterning process P1 of step 104 needs to be adjusted according to the size of the first circuit pattern obtained by the on-line measurement in step 112. According to an embodiment of the present invention, the evaluation method in step 114, for example, first provides a preset range of width W or spacing S, and then determines whether the width W or spacing S of the first circuit pattern size is within the preset range. If the size of the first circuit pattern is within the preset range, there is no need to adjust the patterning process P1. If the size of the first circuit pattern is not within the preset range, the patterning process P1 needs to be adjusted, for example, adjusting the micro pattern of the patterning process P1 At least one process parameter of the shadow and etching process is, for example, the size of the patterned photoresist layer, the power of the etching process, the gas flow rate, and the gas ratio. Subsequently, the adjusted patterning process P1 can be used to form a trench 230 in the dielectric layer 220 of the other substrate 210 that can produce the first circuit pattern 250a in the predetermined range.

The present invention is characterized in that the present invention performs online measurement on the first circuit pattern 250a after the first polishing process, and then evaluates whether it is necessary to adjust the patterning process P1 for making the trench 230, compared to the conventional definition. After the trench 230 is measured, the size of the trench pattern 230a is measured to indirectly estimate the size of the circuit pattern. The method of the present invention can avoid the measurement error caused by the trench having an expanded, concave, or cup-shaped sidewall profile, and can obtain a closer to the final semiconductor The size of the circuit structure (consisting of the remaining conductive material 250) in the device 10, so that the manufacturing process can be controlled more accurately.

The following will describe different embodiments of the present invention. To simplify the description, the following description mainly focuses on the differences between the embodiments, and the similarities are not repeated. In addition, the same elements in the embodiments of the present invention are labeled with the same reference numerals to facilitate comparison between the embodiments.

Please refer to Figure 6 to Figure 10. FIG. 6 is a flowchart of a semiconductor process control method 200 according to the second embodiment of the present invention. 7 to 10 are schematic diagrams of the semiconductor device 10 in different process stages of the semiconductor process control method 200 of the second embodiment. The upper part is a top view, and the lower part is a schematic cross-sectional view taken along the line AA' in the top view. . The difference from the semiconductor process control method 100 shown in FIG. 1 is that the semiconductor process control method 200 of the second embodiment further includes inserting additional online measurements at different process stages to obtain patterns of the semiconductor structure 10 at different process stages size.

Please refer to Figure 6 and Figure 7. In the semiconductor process control method 200, after the trench 230 is formed in step 104 and before the conductive material is formed in step 108, step 106 is inserted to perform online measurement of the trench pattern 230a on the main surface 220' of the dielectric layer 220, so that a trench pattern size can be obtained. . Preferably, the on-line measurement in step 106 is also performed by a scanning electron microscope (SEM), which scans the main surface 220' with a micro-focused electron beam to obtain an image corresponding to the trench pattern 230a The grayscale image is then measured to obtain the trench pattern size, which can be the width W0 of the trench pattern 230a or the spacing S0 between adjacent trench patterns 230a. It is worth noting that the size of the trench pattern obtained by the online measurement in step 106 is roughly the size of the opening portion of the trench 230 close to the main surface 220'.

Please refer to FIGS. 6 and 8. Next, as in the first embodiment, proceed to step 108 to form a conductive material 240 to fill the trench 230, and then proceed to step 110 to remove the excess conductive material outside the trench 230 by the first polishing process P2 240 and remove part of the dielectric layer 220 until the first surface 220a exposing the first circuit pattern 250a is obtained. Next, proceed to step 112 to perform online measurement on the first surface 220a to obtain the size of the first circuit pattern. It should be noted that, unlike the first embodiment, the first polishing process P2 of this embodiment can only remove the dielectric layer with a thickness T1, which is smaller than the thickness T shown in Figure 5, for example, the hard mask is completely removed The layer 229 and part of the third dielectric layer 228 have not reached the removal amount of the second dielectric layer 226. In other words, the thickness of the conductive material 250 remaining in the trench 230 in Figure 8 will be greater than that in Figure 5. The thickness of the conductive material 250 in the trench 230. Therefore, the size of the first circuit pattern measured in step 112 of this embodiment is that the trench 230 is closer to the main surface of the dielectric layer 220 than the size of the first circuit pattern measured in step 112 of the first embodiment. 220' size.

Please refer to FIG. 6 and FIG. 9, and then proceed to step 110a, using the second polishing process P3 to further remove part of the dielectric layer 220, such as removing a thickness T2, until a second surface lower than the first surface 220a is obtained 220b. Referring to the upper part of Figure 9, the second surface 220b contains the remaining conductive material filled in the trench 230 The second circuit pattern 250b defined by the electrical material 250. Next, proceed to step 112a to perform online measurement (also using SEM) on the second circuit pattern 250b on the second surface 220b to obtain a second circuit pattern size. Similarly, the size of the second circuit pattern may be the width W2 of the second circuit pattern 250b or the spacing S2 between adjacent second circuit patterns 250b. Compared with the size of the first circuit pattern, the size of the second circuit pattern obtained at this time will be the size where the trench 230 is farther away from the main surface 220' of the dielectric layer 220.

Please refer to FIGS. 6 and 10, steps 110a and 112a can be repeated, that is, the second polishing process P3 is repeated, and then the dielectric layer 220 is removed by a thickness T3 to obtain a third surface lower than the second surface 250b 220c, including the third circuit pattern 250c defined by the conductive material 250 remaining in the trench 230, as shown in the upper part of FIG. 10, and then perform online measurement on the third circuit pattern 250c (also using SEM) to obtain a The third line pattern size may be the width W3 of the third line pattern 250c or the distance S3 between the adjacent third line patterns 250c. Compared with the second circuit pattern size, the third circuit pattern size obtained at this time will be the size of the trench 230 further away from the main surface 220' of the dielectric layer 220.

The feature of this embodiment is that, please go back to Fig. 6 and you can choose to proceed to step 114 after obtaining at least two of the trench pattern size, the first circuit pattern size, the second circuit pattern size, and the third circuit pattern size. The aforementioned difference between at least the two is to evaluate whether the patterning process P1 needs to be adjusted. For example, when the size of the trench pattern obtained in step 106 and the size of the first circuit pattern obtained in step 112 are not equal and the difference is greater than a preset range, it means that the sidewall profile of the trench 230 within the thickness T1 range may be expanded or concaved. It is necessary to adjust the patterning process P1 in step 104 so that the subsequent substrate can use the adjusted patterning process P1 to make trenches with a closer ideal vertical sidewall profile. On the other hand, it is also possible to map the removal amounts T1, T2, and T3 by plotting the trench pattern size, the first circuit pattern size, the second circuit pattern size, and the third circuit pattern size data, or even repeat more times. Grinding process and online measurement after grinding to obtain more size data corresponding to different levels and remove the amount Drawing to obtain an approximate profile of the sidewall of the trench. Compared with the conventional method of cutting the wafer to prepare a sample showing the actual cross-section of the semiconductor device 10 for measurement, the present invention can quickly obtain an approximate trench sidewall profile with reference significance for online process control, and feedback control accordingly. Patterning process P1. It should be understood that if the polishing process is performed more times and online measurement is performed, the plot of the collected line pattern size data to the removal amount can be more similar to the actual sidewall profile of the trench.

11 to 14 illustrate a semiconductor process control method 300 according to a third embodiment of the present invention. FIG. 11 is a flowchart of a semiconductor process control method 300 according to the third embodiment of the present invention. FIG. 12 is a schematic diagram of a wafer 400 used in the semiconductor process control method 300 of the third embodiment. As shown in FIG. 12, the wafer 400 may include a plurality of non-overlapping chip regions 402, and each of the chip regions 402 can be used to fabricate a semiconductor device 10. FIG. 13 shows a size wafer map 500 obtained by performing online measurement on each wafer area 402 of the wafer 400. FIG. 14 shows a test wafer diagram 600 obtained by performing a wafer test on each wafer area 402 of the wafer 400.

For the following description, please refer to the schematic diagrams of the semiconductor device 10 in different process stages shown in FIGS. 2 to 5 at the same time. First, proceed to step 102 to provide a substrate 210 including a dielectric layer 220 thereon. The substrate 210 may be the wafer 400 shown in FIG. 12, and the dielectric layer 220 completely covers each chip area 402 of the wafer 400. The material of the wafer 400 may include the material of the substrate 210 described above, which will not be repeated here. The dielectric layer 220 may include a single layer or a stacked material layer, preferably a multilayer structure. As shown in FIG. 2, it may include a hard mask layer 229, a third dielectric layer 228, and a third dielectric layer 228 in sequence from top to bottom. The second dielectric layer 226, the first dielectric layer 224 and the etch stop layer 222.

Next, proceed to step 104, using a patterning process P1 to form a plurality of trenches 230 in the dielectric layer 220 of each chip area 402, and the trenches 230 are formed on the surface 220' of the dielectric layer 220 of each chip area 402. A plurality of trench patterns 230a are formed. Next, proceed to step 108 to form a conductive material 240 to completely cover the dielectric layer 220 of each wafer area 402 and fill the trenches 230. Afterwards, proceed to step 110 to perform the first polishing process P2 to remove the excess conductive material 240 outside the trench 230 and remove part of the dielectric layer 220 until the first surface 220' of the dielectric layer 220 is obtained, including the filling in each chip The remaining conductive material 250 in the trench 230 of the region 402 forms a plurality of first circuit patterns 250a. Next, proceed to step 112 to perform online measurement on the first circuit patterns 250a to obtain a plurality of first circuit pattern sizes to obtain a first circuit pattern size wafer map 500, as shown in FIG. 13. Next, proceed to step 114 to evaluate whether the patterning process P1 needs to be adjusted according to the wafer map 500 of the first circuit pattern size. The evaluation method in step 114 is, for example, to determine whether the within wafer uniformity of the first circuit pattern size wafer pattern 500 is within a predetermined range. If not, the patterning process P1 must be adjusted so that another wafer 400 can use the adjusted patterning process P1 to form trenches 230 in its dielectric layer 220 to produce a first circuit that meets the preset range Pattern 250a.

The feature of this embodiment is that after the line measurement in step 112, step 116 is followed by the subsequent manufacturing process of the semiconductor device 10 to form a completed semiconductor device 10 in each wafer area 402. Next, proceed to step 118 to perform a wafer test on each wafer area 402, such as an acceptability test (WAT), a voltage-ramping stress test (VRDB), or a dielectric layer collapse test (time- dependent dielectric breakdown, TDDB), etc., are not limited to this. The wafer test in step 118 may each include multiple test items, and each test item can obtain a corresponding test wafer map. Then, the first circuit pattern size wafer image obtained in step 112 is compared with the test wafer images obtained in step 118 to associate the first circuit pattern size to a test item. For example, please refer to FIG. 13, which is a first circuit pattern size wafer map 500, which includes an area 502 whose size deviates from a preset value. Please refer to FIG. 14, which is a test wafer diagram 600 for testing the breakdown (TDDB) of the dielectric layer 220 between the conductive material 250 in the adjacent trenches 230 of the semiconductor device 10, which contains the chips marked as failures. District 602, Its position corresponds to the area 502 of the first circuit pattern size wafer map 500, so it can be determined that the first circuit pattern size is related to the test item in Fig. 14. In this way, when the semiconductor device 10 is subsequently fabricated on another wafer, the test result of the test item on the wafer can be predicted according to the first circuit size wafer map obtained by the other wafer in step 112. Conversely, it is also possible to determine whether the size of the first circuit is abnormal according to the test wafer map of the test item of the wafer, so as to adjust the patterning process P1.

It should be understood that the semiconductor process control method 300 shown in FIG. 11 may include step 106 in the semiconductor process control method 200 of FIG. 6 to perform online measurement on the trench pattern 230a of each wafer area 402 to obtain a plurality of trenches. The pattern size is further obtained by obtaining a trench pattern size wafer map, and then according to the difference between the first circuit pattern size wafer map and the trench pattern size wafer map, it is evaluated whether the patterning process P1 of step 104 needs to be adjusted. In addition, the semiconductor process control method 300 may also include steps 110a and 112a in the semiconductor process control method 200 of FIG. 6, to perform the second polishing process P2 and subsequent online measurements on the wafer 400 to obtain a plurality of second The circuit pattern size is further obtained a second circuit pattern size wafer map, and then according to the difference between the first circuit pattern size wafer map and the second circuit pattern size wafer map, it is evaluated whether the patterning process P1 of step 104 needs to be adjusted .

In summary, the semiconductor manufacturing process control method of the present invention removes the excess conductive material outside the trench by grinding, and then measures the circuit pattern exposed on the surface of the semiconductor device and defined by the conductive material remaining in the trench. Compared with conventional techniques that measure the size of the trench after etching the trench, the method of the present invention can obtain a size closer to the final circuit structure in the semiconductor device. In addition, by online measurement of semiconductor components in different grinding stages to obtain and compare the circuit dimensions of multiple different grinding stages, it is possible to infer that it is used for forming without scrapping wafers and saving time for preparation of profile samples. Whether the trench of the circuit structure has an ideal sidewall profile. In addition, online measurement can quickly obtain the size of the circuit structure closer to the final semiconductor device and more statistical The meaningful size wafer map can be fed back to the patterning process of forming trenches in real time to improve the within wafer uniformity of subsequent wafers (within wafer uniformity).

The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: Semiconductor process control method

102: Step

104: Step

108: Step

110: Step

112: Step

114: step

Claims (18)

A semiconductor manufacturing process control method includes: providing a substrate on which a dielectric layer is located; performing a patterning process to form at least one trench in the dielectric layer, and the trench is formed on a surface of the dielectric layer A trench pattern; forming a conductive material to completely fill the trench; performing a first polishing process to completely remove the conductive material outside the trench and remove part of the dielectric layer until one of the dielectric layers is exposed A surface, the first surface includes a first circuit pattern formed by the conductive material filled in the trench; after the first grinding process, an online measurement is performed on the first circuit pattern to obtain a first circuit The pattern size, wherein the online measurement uses a scanning electron microscope; and according to the first circuit pattern size, it is evaluated whether the patterning process needs to be adjusted. For the semiconductor manufacturing process control method described in claim 1, wherein the step of evaluating whether the manufacturing process needs to be adjusted according to the size of the first circuit pattern includes: judging whether the size of the first circuit pattern is within a preset range; If the size of the first circuit pattern is not within the preset range, the patterning process is adjusted; and the trench is formed in the dielectric layer of the other substrate by using the adjusted patterning process. The semiconductor manufacturing process control method described in claim 1 further includes: performing a second polishing process on the first surface, and further removing part of the dielectric layer until a second surface of the dielectric layer is exposed , The second surface includes a second circuit pattern formed by the conductive material filled in the trench; after the second grinding process, another online measurement is performed on the second circuit pattern to obtain a second wire Circuit pattern size; and comparing the difference between the size of the first circuit pattern and the size of the second circuit pattern with a preset range to evaluate whether the patterning process needs to be adjusted. For example, in the semiconductor manufacturing process control method described in item 3 of the scope of patent application, when the difference between the size of the first circuit pattern and the size of the second circuit pattern is greater than the preset range, the patterning process is adjusted and the adjusted The patterning process forms the trench in the dielectric layer of the other substrate. For the semiconductor process control method described in item 3 of the scope of patent application, when the difference between the size of the first circuit pattern and the size of the second circuit pattern is within the preset range, the patterning process does not need to be adjusted. The semiconductor manufacturing process control method as described in claim 1 further includes: performing another online measurement on the trench pattern to obtain a trench pattern size; and comparing the size of the first circuit pattern and the difference between the trench pattern size And a preset range to evaluate whether the patterning process needs to be adjusted. For example, in the semiconductor manufacturing process control method described in item 6 of the scope of patent application, when the difference between the size of the circuit pattern and the size of the trench pattern is greater than the preset range, the patterning process is adjusted and the adjusted patterning process is used The trench is formed in the dielectric layer of the other substrate. For example, the semiconductor manufacturing process control method described in item 6 of the scope of patent application, wherein when the difference between the size of the first circuit pattern and the size of the trench pattern is within the preset range, the patterning does not need to be adjusted Process. The semiconductor manufacturing process control method described in claim 1, wherein: the patterning process forms a plurality of the trenches parallel to each other and closely arranged in the dielectric layer, and the trenches are on the surface of the dielectric layer Forming a grid-shaped trench pattern; and after the first polishing process, the conductive material filled in the trenches forms a grid-shaped first circuit pattern on the first surface. According to the semiconductor manufacturing process control method described in claim 9, wherein the size of the first circuit pattern is a width or a pitch of the grid-shaped first circuit pattern. The semiconductor process control method described in claim 9 further includes: performing another online measurement on the grid trench pattern to obtain a trench pattern size, the trench pattern size being a width of the grid trench pattern Or a pitch; and according to the difference between the size of the first circuit pattern and the size of the trench pattern, it is evaluated whether the patterning process needs to be adjusted. A semiconductor manufacturing process control method includes: providing a wafer including a plurality of non-overlapping wafer regions, a dielectric layer on the wafer and covering each of the wafer regions; performing a patterning process in each of the wafer regions At least one trench is formed in the dielectric layer, and the trenches of each of the chip regions respectively form a trench pattern on a surface of the dielectric layer; forming a conductive material to completely fill the trenches of each of the chip regions; performing a second A polishing process to completely remove the conductive material outside the trench of each wafer area and move it Remove part of the dielectric layer until a first surface of the dielectric layer is exposed, the first surface including a plurality of first circuit patterns formed by the conductive material filled in the trenches of each of the chip regions; After a grinding process, perform an online measurement on the first circuit patterns to obtain a plurality of first circuit pattern sizes and a first circuit pattern size wafer map, wherein the online measurement uses a scanning electron microscope; And to evaluate whether the patterning process needs to be adjusted according to the wafer map of the first circuit pattern size. According to the semiconductor process control method described in claim 12, the step of evaluating whether the patterning process needs to be adjusted according to the first circuit pattern size wafer map includes: determining the first circuit pattern size wafer map Whether the in-circle uniformity is within a preset range; if the in-wafer uniformity of the first circuit pattern size wafer map is not within the preset range, adjust at least one process parameter of the patterning process; and use adjustment After the patterning process, the trench is formed in the dielectric layer of another wafer. As described in item 12 of the scope of patent application, the semiconductor manufacturing process control method further includes: performing a wafer test on each wafer area to obtain a plurality of test wafer images; and comparing the size of the first circuit pattern with the wafer image The test wafer images are associated with the size of the first circuit pattern to a test item. The semiconductor process control method described in claim 12, wherein: the patterning process forms a plurality of the trenches that are parallel and closely arranged in the dielectric layer of each of the chip regions, and the trenches of each of the chip regions are closely arranged. The surface of the dielectric layer respectively includes a grid-shaped trench pattern formed by the trenches; and after the first polishing process, the first surface of the dielectric layer of each of the chip regions includes a filling A grid-shaped first circuit pattern is formed by the conductive material in the trench structures. According to the semiconductor process control method described in claim 15, wherein the size of the first circuit pattern of each of the wafer regions is a width or a pitch of the grid-shaped first circuit pattern. The semiconductor process control method described in claim 12 further includes: performing another online measurement on the trench pattern of each chip area to obtain a plurality of trench pattern sizes and a trench pattern size wafer map; and According to the difference between the first circuit pattern size wafer map and the trench pattern size wafer map, it is evaluated whether the patterning process needs to be adjusted. The semiconductor manufacturing process control method described in claim 12, further comprising: performing a second polishing process on the first surface, and further removing part of the dielectric layer until a second surface of the dielectric layer is exposed , The second surface includes a plurality of second circuit patterns formed by the conductive material filled in the trenches of each of the chip regions; another online measurement is performed on the second circuit patterns of each of the chip regions to obtain more A second circuit pattern size and a second circuit pattern size wafer map; and according to the difference between the first circuit pattern size wafer map and the second circuit pattern size wafer map, assess whether the patterning process needs to be adjusted .

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