CN110416106B - OCD test pattern structure and manufacturing method thereof - Google Patents
OCD test pattern structure and manufacturing method thereof Download PDFInfo
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- CN110416106B CN110416106B CN201910697715.XA CN201910697715A CN110416106B CN 110416106 B CN110416106 B CN 110416106B CN 201910697715 A CN201910697715 A CN 201910697715A CN 110416106 B CN110416106 B CN 110416106B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
Abstract
The invention discloses an OCD test pattern structure, which is formed on a semiconductor substrate outside a device forming region. The semiconductor device comprises a plurality of device process layers, and the OCD test pattern structure corresponds to the tested device process layer in the device process layers and is used for simulating the pattern structure of the tested device process layer. The OCD test pattern structure adopts a stack structure formed by overlapping a plurality of test process layers, and each test process layer corresponds to the process condition of each corresponding device process layer one by one and has a pattern structure in the corresponding device process layer. The invention also discloses a manufacturing method of the OCD test pattern structure. The method can overcome the influence of the graph load effect on the OCD measurement precision and improve the OCD measurement precision.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to an Optical Critical Dimension (OCD) test pattern structure. The invention also relates to a manufacturing method of the OCD test pattern structure.
Background
The OCD measurement is to project light onto the pattern structure to be tested, and then measure the light spectrum of the reflected light to measure the dimension or profile of the pattern structure to be tested. In the manufacturing of semiconductor integrated circuits, the OCD measurement can be adopted to realize good online monitoring on the sizes of all process layers. Semiconductor integrated circuits are usually formed on a wafer composed of a semiconductor substrate such as a silicon substrate, and as the process technology shrinks, i.e., the device process structure shrinks in proportion, the size of each device process layer becomes more and more complicated and the measurement accuracy also becomes worse after the device process structure shrinks. In the existing process of process nodes below 28nm, a copper process is usually adopted in a back-end-of-line (BEOL), the copper process needs a damascene process, an interlayer film is formed first, then a trench or a through hole is formed in the interlayer film, then copper is filled in the trench or the through hole, the copper filled in the trench forms a connecting line of a front metal layer, and the copper filled in the through hole is used as a connecting structure between an upper front metal layer and a lower front metal layer.
In the existing method, when the size of each process layer of a semiconductor device in a semiconductor integrated circuit needs to be monitored by OCD measurement, a corresponding OCD test pattern structure needs to be manufactured on a semiconductor substrate. The existing OCD test pattern structure adopts a single-layer structure with the same process conditions as the process layer of a tested device. However, with the development of the technology, the device process structures will be scaled down, and after the size of the device process structures is reduced, the film morphology corresponding to each device process layer will be affected by the behavior between different pattern structures, i.e. the film morphology has a loading effect, i.e. a pattern loading effect (pattern loading), related to the pattern structures. In the existing method, the OCD test pattern structure adopting a single-layer structure cannot reflect the pattern load effect, so that the OCD measurement accuracy is poor or even inaccurate.
FIG. 1 is a schematic diagram of a conventional OCD test pattern structure; as shown in fig. 1, the conventional OCD test pattern structure adopts a single-layer structure, that is, a pattern structure is formed only in the same process layer as the process layer of the device under test; the conventional OCD test pattern structure shown in FIG. 1 is a trench 105 formed in an interlayer film 101, the interlayer film 101 usually employs a low-K dielectric layer, the material of the low-K dielectric layer includes BD or BD II, BD is a dielectric material composed of C, H, O, Si, etc., and the K value is 2.5-3.3. BD ii is an improved version of BD.
The low-K dielectric layer of the interlayer film 101 is typically formed on the surface of a nitrogen-doped silicon carbide (NDC) layer 3, and the bottom surface of the NDC layer 3 covers the surface of the bottom corresponding interlayer film or front metal layer 102.
The trench 105 is formed by using a metal hard mask layer 104, and in fig. 1, the metal hard mask layer 104 is formed by stacking a Ti layer 104a, TiN104b, and an oxide layer 104 c.
In the structure shown in fig. 1, the bottom of the trench 105 has no pattern structure; in the device forming region, the bottom of the corresponding pattern of the tested device process layer is provided with patterns of other device process layers, so that the pattern of the tested device process layer can be influenced by the patterns of the other device process layers at the bottom to generate a pattern load effect, and the conventional OCD test pattern structure shown in FIG. 1 cannot reflect the influence of the pattern load effect on the OCD test pattern structure, so that the pattern size or the outline of the tested device process layer cannot be truly reflected, and the OCD test precision is reduced.
Disclosure of Invention
The technical problem to be solved by the invention is to provide an OCD test pattern structure, which can overcome the influence of pattern load effect on OCD measurement precision and improve the OCD measurement precision.
In order to solve the above technical problems, the present invention provides an OCD test pattern structure having a device formation region on a semiconductor substrate, a semiconductor device being formed in the device formation region, the OCD test pattern structure being formed on the semiconductor substrate outside the device formation region.
The semiconductor device comprises a plurality of device process layers, and the OCD test pattern structure corresponds to a tested device process layer in the device process layers and is used for simulating the pattern structure of the tested device process layer.
The OCD test pattern structure adopts a stack structure formed by overlapping a plurality of test process layers, the topmost test process layer corresponds to the tested device process layer and has the same process conditions, and the process conditions of the slave test process layers below the topmost test process layer correspond to the process conditions of the device process layers below the tested device process layer one by one and have corresponding pattern structures in the device process layers; the stack structure enables the testing process layer at the topmost layer of the OCD testing pattern structure to reflect the influence of the patterns of the device process layers below the device process layer to be tested on the patterns of the device process layer to be tested, so that the measuring precision is improved.
In a further improvement, the semiconductor substrate is a silicon substrate.
In a further improvement, the semiconductor device comprises a plurality of front metal layers formed on the surface of the semiconductor substrate, and the front metal layers of the upper layer and the lower layer are connected through a through hole and isolated through an interlayer film.
In a further improvement, the semiconductor device adopts a process node below 28 nm.
The further improvement is that the front metal layer is made of copper material.
In a further improvement, the front metal layer is formed by adopting a Damascus process.
In a further refinement, the device under test process layer includes trenches or vias formed in the corresponding interlayer film prior to formation of the corresponding front side metal layer.
In a further improvement, the OCD test pattern structure is used to detect the size of the trench or via corresponding to the process layer of the device under test by using OCD measurement.
In order to solve the above technical problem, the manufacturing method of the OCD test pattern structure provided by the present invention comprises the following steps:
step one, arranging a forming region of the OCD test pattern structure outside a device forming region on a semiconductor substrate.
And secondly, the semiconductor device comprises a plurality of device process layers, the OCD test pattern structure corresponds to the tested device process layer in the device process layers and is used for simulating the pattern structure of the tested device process layer, and the test process layer at the topmost layer of the OCD test pattern structure is designed according to the tested device process layer.
And step three, forming the semiconductor device by adopting a multi-step device process, forming a test process layer with the same process condition as the device process layer in a forming area of the OCD test pattern structure when forming the tested device process layer and each device process layer below the tested device process layer, and forming the OCD test pattern structure by a stacked structure formed by overlapping the test process layers.
In a further improvement, the semiconductor substrate is a silicon substrate.
In a further improvement, the semiconductor device comprises a plurality of front metal layers formed on the surface of the semiconductor substrate, and the front metal layers of the upper layer and the lower layer are connected through holes and isolated through interlayer films.
In a further improvement, the semiconductor device adopts a process node below 28 nm.
The further improvement is that the front metal layer is made of copper; the front metal layer is formed by adopting a Damascus process.
In a further refinement, the device under test process layer includes trenches or vias formed in the corresponding interlayer film prior to formation of the corresponding front side metal layer.
In a further improvement, the OCD test pattern structure is formed and then OCD measurement is used to detect the size of the trench or via corresponding to the device under test process layer.
The OCD test pattern structure adopts a stack structure formed by overlapping a plurality of test process layers, and the process conditions of each test process layer are the same as those of the device process layers of the corresponding layers, so that the test process layer at the topmost layer of the OCD test pattern structure can reflect the influence of the patterns of each device process layer below the tested device process layer on the patterns of the tested device process layer, the influence of the pattern load effect on the OCD measurement precision can be overcome, and the OCD measurement precision is improved; especially after the device process structure is reduced in equal proportion, the invention can improve the problem of inaccurate measurement caused by process shrinkage and further improve the measurement precision.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a schematic diagram of a conventional OCD test pattern structure;
fig. 2A-2D are schematic cross-sectional views of different positions of an OCD test pattern structure according to an embodiment of the invention.
Detailed Description
Fig. 2A to 2D are schematic cross-sectional views of different positions of an OCD test pattern structure according to an embodiment of the present invention; wherein fig. 2A is a sectional view in the X-axis direction at a first position, fig. 2B is a sectional view in the Y-axis direction at a first position, fig. 2C is a sectional view in the X-axis direction at a second position, and fig. 2D is a sectional view in the Y-axis direction at a second position; in the OCD test pattern structure according to the embodiment of the present invention, a device formation region is formed on a semiconductor substrate 1, a semiconductor device is formed in the device formation region, and an OCD test pattern structure is formed on the semiconductor substrate 1 outside the device formation region.
The semiconductor device comprises a plurality of device process layers, and the OCD test pattern structure corresponds to a tested device process layer in the device process layers and is used for simulating the pattern structure of the tested device process layer.
The OCD test pattern structure adopts a stack structure formed by overlapping a plurality of test process layers, the topmost test process layer corresponds to the tested device process layer and has the same process conditions, and the process conditions of the slave test process layers below the topmost test process layer correspond to the process conditions of the device process layers below the tested device process layer one by one and have corresponding pattern structures in the device process layers; the stack structure enables the testing process layer at the topmost layer of the OCD testing pattern structure to reflect the influence of the patterns of the device process layers below the device process layer to be tested on the patterns of the device process layer to be tested, so that the measuring precision is improved.
In the embodiment of the present invention, the semiconductor substrate 1 is a silicon substrate. The semiconductor device comprises a plurality of front metal layers formed on the surface of the semiconductor substrate 1, wherein the front metal layers of the upper layer and the lower layer are connected through holes and isolated through interlayer films. In fig. 2A, four-layer interlayer films are shown, indicated by the reference numerals 2A, 2b, 2c and 2d, respectively; there are shown 3 such front side metal layers, a third front side metal layer indicated by reference numeral 6C in fig. 2B and 2D, a second front side metal layer indicated by reference numeral 6B in fig. 2C, and a first front side metal layer indicated by reference numeral 6a in fig. 2D. In the embodiment of the invention, the corresponding interlayer films in the formation region of the OCD test pattern structure and the device formation region are in the same layer structure, and the corresponding front metal layers are also the same.
In the semiconductor substrate 1 shown in fig. 2A, a device structure at the bottom of a metal interconnection layer composed of an interlayer film and a front metal layer is formed, including doped regions of a device such as a source region and a drain region of an NMOS transistor or a PMOS transistor and a polysilicon gate.
The semiconductor device adopts a process node below 28 nm. The front metal layer is made of copper materials. The front metal layer is formed by adopting a Damascus process.
In the Damascus process, an interlayer film usually adopts a low-K dielectric layer, the material of the low-K dielectric layer comprises BD or BD II, the BD is a dielectric material composed of elements such as C, H, O, Si and the like, and the K value is 2.5-3.3. BD ii is an improved version of BD.
The inter-layer film low-K dielectric layer is typically formed on the surface of a nitrogen doped silicon carbide (NDC) layer 3, and the bottom surface of the NDC layer 3 covers the surface of the corresponding bottom inter-layer film or front metal layer.
A dielectric antireflective coating (DARC) is also typically formed on the surface of the low K dielectric layer of the interlayer film.
The device under test process layer comprises trenches or vias 5 formed in the corresponding interlayer film before the formation of the corresponding front side metal layer. As shown in fig. 2A to 2D, the process layer of the device under test in the embodiment of the present invention corresponds to the trench or via 5 formed in the interlayer film 2D of the fourth layer. A fourth front metal layer is formed after the front metal layer is filled in the trench or via 5. Obviously, the top test process layer of the OCD test pattern structure in the embodiment of the present invention is the trench or via 5, the trenches or vias 5 inside and outside the device formation region are formed simultaneously, and after the trenches or vias 5 are formed, the OCD measurement is used to detect the size of the trench or via 5 corresponding to the device process layer under test.
The formation of the trench or via 5 requires the use of a metal hard mask layer 4, and in fig. 1, the metal hard mask layer 4 is formed by stacking a Ti layer 4a, TiN4b, and an oxide layer 4 c.
As shown in fig. 2A-2D, the bottom of the trench or via 5 in the embodiment of the present invention includes a pattern structure of front metal layers, as shown by the front metal layers corresponding to the marks 6a, 6b and 6 c. In an actual process, the pattern structure of each front metal layer at the bottom may affect the size of the trench or the via 5, and particularly, the effect becomes more and more obvious as the device process structure is scaled down, that is, the smaller the device process structure size is, the more serious the pattern loading effect is. The OCD test pattern structure provided by the embodiment of the invention can truly reflect the influence of each layer of pattern structure at the bottom on the size of the groove or through hole 5, thereby improving the OCD measurement precision.
The OCD test pattern structure of the embodiment of the invention adopts a stack structure formed by overlapping a plurality of test process layers, and the process conditions of each test process layer are the same as those of the device process layers of the corresponding layers, so that the test process layer at the topmost layer of the OCD test pattern structure can reflect the influence of the pattern of each device process layer below the tested device process layer on the pattern of the tested device process layer, and the embodiment of the invention can overcome the influence of the pattern load effect on the OCD measurement precision and improve the OCD measurement precision; particularly, after the process structure of the device is scaled down, the problem of inaccurate measurement caused by process shrinkage can be solved and the measurement precision is improved.
The manufacturing method of the OCD test pattern structure comprises the following steps:
step one, arranging a forming area of the OCD test pattern structure outside a device forming area on a semiconductor substrate 1.
And secondly, the semiconductor device comprises a plurality of device process layers, the OCD test pattern structure corresponds to the tested device process layer in the device process layers and is used for simulating the pattern structure of the tested device process layer, and the test process layer at the topmost layer of the OCD test pattern structure is designed according to the tested device process layer.
And step three, forming the semiconductor device by adopting a multi-step device process, forming a test process layer with the same process condition as the device process layer in a forming area of the OCD test pattern structure when forming the tested device process layer and each device process layer below the tested device process layer, and forming the OCD test pattern structure by a stacked structure formed by overlapping the test process layers.
In the method of the embodiment of the invention, the semiconductor substrate 1 is a silicon substrate.
The semiconductor device comprises a plurality of front metal layers formed on the surface of the semiconductor substrate 1, wherein the front metal layers of the upper layer and the lower layer are connected through holes and isolated through interlayer films.
The semiconductor device adopts a process node below 28 nm.
The front metal layer is made of a copper material; the front metal layer is formed by adopting a Damascus process. In the Damascus process, an interlayer film is formed, a groove is formed in an opening of the interlayer film, and then a front metal layer is filled in the groove.
The device under test process layer comprises trenches or vias 5 formed in the corresponding interlayer film before the formation of the corresponding front side metal layer.
OCD measurement is used to detect the dimensions of the trench or via 5 corresponding to the device under test process layer after the OCD test pattern structure is formed.
The present invention has been described in detail with reference to the specific examples, but these are not to be construed as limiting the invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (9)
1. An OCD test pattern structure, its characterized in that: the semiconductor device testing method comprises the steps that a device forming area is formed on a semiconductor substrate, a semiconductor device is formed in the device forming area, and an OCD testing pattern structure is formed on the semiconductor substrate outside the device forming area;
The semiconductor device comprises a plurality of device process layers, and the OCD test pattern structure corresponds to a tested device process layer in the device process layers and is used for simulating the pattern structure of the tested device process layer;
the OCD test pattern structure adopts a stack structure formed by overlapping a plurality of test process layers, the test process layer at the topmost layer corresponds to the device process layer to be tested, the process conditions are the same, the process conditions of the slave test process layers below the test process layer at the topmost layer correspond to the process conditions of the device process layers below the device process layer to be tested one by one, and the slave test process layers and the device process layers have corresponding pattern structures in the device process layer; the stack structure enables the test process layer at the topmost layer of the OCD test pattern structure to reflect the influence of the patterns of the device process layers below the device process layer to be tested on the patterns of the device process layer to be tested, so that the measurement precision is improved;
the semiconductor device comprises a plurality of front metal layers formed on the surface of the semiconductor substrate, and the front metal layers of the upper layer and the lower layer are connected through a through hole and isolated through an interlayer film;
the device under test process layer comprises trenches or vias formed in the corresponding interlayer film before the corresponding front-side metal layer is formed;
The OCD test pattern structure is used for detecting the size of the groove or the through hole corresponding to the process layer of the device to be tested by adopting OCD measurement.
2. The OCD test pattern structure of claim 1, wherein: the semiconductor substrate is a silicon substrate.
3. The OCD test pattern structure of claim 2, wherein: the semiconductor device adopts a process node below 28 nm.
4. The OCD test pattern structure of claim 3, wherein: the front metal layer is made of a copper material.
5. The OCD test pattern structure of claim 4, wherein: the front metal layer is formed by adopting a Damascus process.
6. A manufacturing method of an OCD test pattern structure is characterized by comprising the following steps:
step one, arranging a forming region of the OCD test pattern structure outside a device forming region on a semiconductor substrate;
step two, the semiconductor device comprises a plurality of device process layers, the OCD test pattern structure corresponds to a tested device process layer in the device process layers and is used for simulating the pattern structure of the tested device process layer, and the test process layer at the topmost layer of the OCD test pattern structure is designed according to the tested device process layer;
Step three, forming the semiconductor device by adopting a multi-step device process, forming a test process layer with the same process condition as that of the device process layer in a forming area of the OCD test pattern structure when forming the tested device process layer and each device process layer below the tested device process layer, and forming the OCD test pattern structure by a stacked structure formed by overlapping the test process layers;
the semiconductor device comprises a plurality of front metal layers formed on the surface of the semiconductor substrate, wherein the front metal layers of the upper layer and the lower layer are connected through a through hole and isolated through an interlayer film;
the device under test process layer comprises a trench or a via formed in the corresponding interlayer film before the formation of the corresponding front-side metal layer;
and after the OCD test pattern structure is formed, detecting the size of the groove or the through hole corresponding to the process layer of the device under test by adopting OCD measurement.
7. The method for manufacturing an OCD test pattern structure of claim 6, wherein: the semiconductor substrate is a silicon substrate.
8. The method of manufacturing an OCD test pattern structure of claim 7, wherein: the semiconductor device adopts a process node below 28 nm.
9. The method for manufacturing an OCD test pattern structure of claim 8, wherein: the front metal layer is made of a copper material; the front metal layer is formed by adopting a Damascus process.
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| KR20120120846A (en) * | 2011-04-25 | 2012-11-02 | 에스케이하이닉스 주식회사 | Method for detecting optical critical demension |
| JP2014229671A (en) * | 2013-05-20 | 2014-12-08 | ルネサスエレクトロニクス株式会社 | Method for manufacturing semiconductor device |
| CN107110638A (en) * | 2014-11-02 | 2017-08-29 | 诺威量测设备股份有限公司 | Method and system for the optical measurement in pattern structure |
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| US7678588B2 (en) * | 2008-01-22 | 2010-03-16 | United Microelectronics Corp. | Method for constructing module for optical critical dimension (OCD) and measuring method of module for optical critical dimension using the module |
| US9252060B2 (en) * | 2012-04-01 | 2016-02-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduction of OCD measurement noise by way of metal via slots |
| CN104143519B (en) * | 2014-08-01 | 2019-06-21 | 上海华力微电子有限公司 | A kind of detection method of product via etch defect |
| US9903707B2 (en) * | 2015-09-18 | 2018-02-27 | Globalfoundries Inc. | Three-dimensional scatterometry for measuring dielectric thickness |
| US10458912B2 (en) * | 2016-08-31 | 2019-10-29 | Kla-Tencor Corporation | Model based optical measurements of semiconductor structures with anisotropic dielectric permittivity |
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| KR20120120846A (en) * | 2011-04-25 | 2012-11-02 | 에스케이하이닉스 주식회사 | Method for detecting optical critical demension |
| JP2014229671A (en) * | 2013-05-20 | 2014-12-08 | ルネサスエレクトロニクス株式会社 | Method for manufacturing semiconductor device |
| CN107110638A (en) * | 2014-11-02 | 2017-08-29 | 诺威量测设备股份有限公司 | Method and system for the optical measurement in pattern structure |
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