TWI727828B - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

Provided is a semiconductor device including a dielectric layer, a first via, a second via, a first barrier layer, and a second barrier layer. The dielectric layer has a first region and a second region. The first via is disposed in the dielectric layer in the first region. The second via is disposed in the dielectric layer in the second region. The first barrier layer lines a sidewall and a bottom surface of the first via. The second barrier layer lines a sidewall and a bottom surface of the second via. The first and second barrier layers each has an upper portion and a lower portion. The upper portion has a nitrogen doping concentration greater than a nitrogen doping concentration of the lower portion. A method of manufacturing a semiconductor device is also provided.

Description

Semiconductor element and its manufacturing method

The present invention relates to a semiconductor element and its manufacturing method.

With the advancement of semiconductor technology, current integrated wafers include tens of thousands of semiconductor components. The semiconductor element may include an active element (for example, a transistor, a diode, etc.), a passive element (for example, a capacitor, a resistor, etc.), or a combination thereof. Metal-insulator-metal (MIM) structure is a common passive component, which is often integrated into the back-end-of-the-line (BEOL) metal of the integrated chip In the internal wiring, it is electrically connected with the transistor in the front-end-of-the-line (FEOL).

However, when the MIM structure is defined, the exposed via and/or barrier layer will be lost due to over-etching, thereby causing a weak point. In this case, during the subsequent BEOL heat treatment, the copper layer under the via window will produce copper volcano defects along this weak point, thereby affecting the reliability and yield of the semiconductor device.

The present invention provides a semiconductor device and a manufacturing method. The barrier strength of a barrier layer lined on the sidewall of a via is strengthened by nitriding, so as to avoid the occurrence of copper burst defects, thereby improving the reliability and quality of the device. rate.

The present invention provides a semiconductor device including: a dielectric layer, a first via window, a second via window, a first barrier layer and a second barrier layer. The dielectric layer has a first area and a second area. The first via is disposed in the dielectric layer of the first region. The second via is disposed in the dielectric layer of the second region. The first barrier layer is lined on the sidewall and the bottom surface of the first via. The second barrier layer is lined on the sidewall and bottom surface of the second via. The second barrier layer has an upper portion and a lower portion. The upper nitrogen doping concentration is greater than the lower nitrogen doping concentration.

The present invention provides a method for manufacturing a semiconductor element, which includes: forming a plurality of vias in a dielectric layer; nitriding the dielectric layer and the plurality of vias to dope nitrogen on the top of the dielectric layer The concentration is greater than the nitrogen doping concentration at the bottom of the dielectric layer; a metal-insulator-metal (MIM) stack is formed on the dielectric layer and a plurality of via windows; and the metal-insulator-metal stack is patterned to form a metal-insulator -Metal structure.

The present invention will be explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various different forms and should not be limited to the embodiments described herein. The thickness of the layers and regions in the drawing will be exaggerated for clarity. The same or similar reference numerals indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

The first embodiment of the present invention provides a manufacturing process of a semiconductor device 1 (as shown in FIG. 1I), and the detailed steps are shown in FIGS. 1A to 1I. First, referring to FIG. 1A, an initial structure is provided, which includes: a substrate 100, an isolation structure 101, a gate structure 110, 120, contact windows 115, 125, a dielectric layer 130, 132, a conductor layer 134, 136, and a dielectric layer 140, 142. Specifically, the substrate 100 includes a first region R1 and a second region R2. In some embodiments, the first region R1 is a unit cell region, and the second region R2 is a peripheral region. The first region R1 may have a plurality of memory cells arranged in a memory array. The second region R2 may have peripheral circuits.

The gate structure 110 is disposed on the substrate 100 in the first region R1. In some embodiments, the gate structure 110 includes a gate dielectric layer 112, a gate electrode 114 and a cap layer 116. The gate electrode 114 is disposed between the gate dielectric layer 112 and the cap layer 116. A pair of spacers 118 are arranged on the side walls of the gate structure 110. In addition, the gate structure 120 is disposed on the substrate 100 in the second region R2. In some embodiments, the gate structure 120 includes a gate dielectric layer 122, a gate electrode 124 and a cap layer 126. The gate electrode 124 is disposed between the gate dielectric layer 122 and the cap layer 126. A pair of spacers 128 are arranged on the side walls of the gate structure 120. In some embodiments, the spacers 118 and 128 include a single-layer structure or a multi-layer structure. In addition, the isolation structure 101 is disposed in the substrate 100 to separate the gate structures 110 and 120 and/or other transistors.

As shown in FIG. 1A, the initial structure further includes an etch stop layer 102 and a dielectric layer 104. The etch stop layer 102 conformally covers the substrate 100 and the gate structures 110 and 120. The dielectric layer 104 is disposed on the etch stop layer 102. In some embodiments, the dielectric layer 104 may be regarded as an interlayer dielectric (ILD) layer. The etch stop layer 102 and the dielectric layer 104 have different dielectric materials. For example, the material of the etch stop layer 102 includes silicon nitride, and the material of the dielectric layer 104 includes high density plasma (HDP) oxide. In some embodiments, the etch stop layer 102 may include a single-layer structure or a multi-layer structure. The contact windows 115 and 125 pass through the dielectric layer 104 and the etch stop layer 102, and are electrically connected to the doped regions (such as S/D regions) in the substrate 100 through the silicide layers 113 and 123, respectively.

The dielectric layers 130 and 132 and the conductor layers 134 and 136 are respectively disposed on the dielectric layer 104. In some embodiments, the dielectric layer 132 can be regarded as an intermetal dielectric (IMD) layer. The dielectric layer 130 can be used as an etch stop layer, and it has a different dielectric material from the dielectric layer 132. For example, the material of the dielectric layer 130 includes silicon nitride, and the material of the dielectric layer 132 includes TEOS oxide. The conductor layers 134 and 136 are embedded in the dielectric layers 130 and 132 to be electrically connected to the contact windows 115 and 125 respectively. In some embodiments, the conductor layers 134, 136 may be circuit layers. The material of the conductor layers 134 and 136 includes a metal material, such as a copper layer.

As shown in FIG. 1A, the dielectric layers 140 and 142 are disposed on the dielectric layers 130 and 132 and the conductor layers 134 and 136. In some embodiments, the lower dielectric layer 140 is used as an etch stop layer, which has a different dielectric material from the upper dielectric layer 142. For example, the material of the dielectric layer 140 includes SiCN, and the material of the dielectric layer 142 includes HDP oxide.

1B, a first opening 12 and a second opening 14 are formed in the dielectric layers 140 and 142. The first opening 12 is located in the dielectric layers 140 and 142 of the first region R1 and exposes part of the top surface of the conductive layer 134. The second opening 14 is located in the dielectric layers 140 and 142 of the second region R2 and exposes part of the top surface of the conductive layer 136.

1C, a barrier material 144 is formed to conformally cover the first opening 12 and the second opening 14 and extend to cover the top surface of the dielectric layer 142. In some embodiments, the barrier material 144 includes Ti, TiN, Ta, TaN, or a combination thereof, which can be formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD). Next, a conductive material 146 is formed on the barrier material 144. The conductive material 146 fills the first opening 12 and the second opening 14 and extends to cover the top surface of the dielectric layer 142. In some embodiments, the conductive material 146 includes a metal material (such as tungsten), which can be formed by CVD or PVD.

1D, a planarization process is performed to remove part of the conductive material 146 and part of the barrier material 144 to form a first barrier layer 154 and a first via 156 in the first opening 12, and in the second opening A second barrier layer 164 and a second via 166 are formed in 14. Specifically, the first barrier layer 154 lines the sidewalls and the bottom surface of the first via 156 to separate the first via 156 from the dielectric layers 140 and 142. Here, the so-called "lines" refers to conformal coverage. In other words, the first barrier layer 154 conformally covers the sidewall and bottom surface of the first via 156. On the other hand, the second barrier layer 164 lines the sidewall and bottom surface of the second via 166 to separate the second via 166 from the dielectric layers 140 and 142. In some embodiments, the planarization process may be a chemical mechanical polishing (CMP) process. After the planarization process, the top surface of the first barrier layer 154, the top surface of the first via 156, the top surface of the second barrier layer 164, the top surface of the second via 166, and the dielectric layer 142 The top surface can be regarded as coplanar.

1E, the first barrier layer 154, the first via 156, the second barrier layer 164, the second via 166, and the dielectric layer 142 are nitridated 16. In some embodiments, the nitriding treatment 16 includes performing a plasma nitriding process. The plasma nitriding process includes passing a nitrogen-containing gas, such as N ₂ , NH ₃ or a combination thereof. The process temperature of the plasma nitriding process may be between 300°C and 400°C, such as 350°C; the process time of the plasma nitridation process may be between 30 seconds and 300 seconds, such as 30 seconds. After the nitriding treatment 16, as shown in the enlarged view of the region 10, the dielectric layer 142 is divided into a bottom portion 142a and a top portion 142b, and the second barrier layer 164 is also divided into a bottom portion 164a and an upper portion 164b. The bottom portion 142a surrounds the lower portion 164a, and the top portion 142b surrounds the upper portion 164b. In some embodiments, the nitrogen doping concentration of the top 142 b of the dielectric layer 142 is greater than the nitrogen doping concentration of the bottom 142 a of the dielectric layer 142. The ratio (N1/N2) of the nitrogen doping concentration (N1) of the top 142b of the dielectric layer 142 to the nitrogen doping concentration (N2) of the bottom 142a of the dielectric layer 142 may be between 1 and 3. The nitrogen doping concentration of the upper portion 164b of the second barrier layer 164 is greater than the nitrogen doping concentration of the lower portion 164a of the second barrier layer 164. The ratio (N3/N4) of the nitrogen doping concentration (N3) of the upper portion 164b of the second barrier layer 164 to the lower portion 164a (N4) of the second barrier layer 164 (N3/N4) may be between 2-10. Similarly, the first barrier layer 154 is also divided into a lower part and an upper part (not shown), wherein the nitrogen doping concentration of the upper part of the first barrier layer 154 is also greater than the nitrogen doping concentration of the lower part of the first barrier layer 154. It is worth noting that the nitriding treatment 16 can strengthen the barrier strength of the upper portion 164b of the second barrier layer 164, so as to avoid weak points during subsequent patterning of the MIM stack, thereby reducing the occurrence of copper burst defects.

As shown in FIG. 2, the top 142b of the dielectric layer 142 has a height H1. In some embodiments, the height H1 may be between 5 nm and 15 nm. However, the present invention is not limited to this. In other embodiments, the height H1 can be adjusted by changing the processing time of the nitriding process 16. For example, when the processing time of the nitriding 16 increases, the height H1 will also increase. In addition, the upper portion 164b of the second barrier layer 164 has a height H2. In some embodiments, the height H2 may be between 5 nm and 15 nm. Although the height H1 and the height H2 shown in FIG. 2 are the same, the present invention is not limited thereto. In other embodiments, the height H1 may be different from the height H2. For example, the height H2 of the upper portion 164b of the second barrier layer 164 is greater than the height H1 of the top portion 142b of the dielectric layer 142. In this case, a portion of the bottom portion 142a of the dielectric layer 142 also surrounds a portion of the upper portion 164b of the second barrier layer 164.

In this embodiment, the second barrier layer 164 may have a double-layer structure, such as a Ti layer and a TiN layer. After the nitriding process 16, as shown in the enlarged view of area 20, the lower part 164a includes a Ti layer 164a1 contacting the dielectric layer 142 and a TiN layer 164a2 contacting the second via 166; and the upper part 164b includes a contact dielectric layer The Ti layer 164b1 of 142 and the TiN layer 164b2 of the second via 166 contact. The nitrogen doping concentration of the Ti layer 164b1 of the upper part 164b may be greater than the nitrogen doping concentration of the Ti layer 164a1 of the lower part 164a. From another perspective, the Ti layer 164b1 of the upper part 164b can be doped as a TiN layer, while the Ti layer 164a1 of the lower part 164a is still maintained as a Ti layer. In addition, the nitrogen doping concentration of the TiN layer 164b2 of the upper part 164b may also be greater than the nitrogen doping concentration of the TiN layer 164a2 of the lower part 164a.

1F, a metal-insulator-metal (MIM) stack 200 is formed on the dielectric layer 142, the first via 156, and the second via 166. Specifically, the MIM stack 200 includes two metal layers 202 and 206 and an insulating layer 204 sandwiched between the metal layers 202 and 206. In some embodiments, the material of the metal layers 202, 206 may include Ti, TiN, or a combination thereof. For example, the metal layers 202 and 206 may have a double-layer structure, such as a Ti layer and a TiN layer on the Ti layer.

1F and 1G, the MIM stack 200 is patterned to form the MIM structure 210 on the first region R1. The MIM structure 210 is formed on the first via 156 to be electrically connected to the first via 156. The second interlayer window 166 is exposed from the MIM structure 210. In this embodiment, in the process of patterning the MIM stack 200, in order to completely remove the MIM stack 200 on the second region R2, the dielectric layer 142, the second barrier layer 164, and the second via 166 are further The ground is etched so that the top surface 142t2 of the dielectric layer 142 in the second region R2 is lower than the top surface 142t1 of the dielectric layer 142 in the first region R1, and the top surface 166t of the second via 166 is lower than the first region R1. The top surface 156t of the via 156. It is worth noting that the nitrogen-doped second barrier layer 164 can effectively block the chlorine (Cl)-containing etchant used in the patterned MIM stack 200, thereby avoiding the loss of the second barrier layer 164. Therefore, during the subsequent BEOL heat treatment, the conductor layer 136 under the second via 166 will not produce copper burst defects along the second barrier layer 164, thereby improving the reliability and quality of the semiconductor device of the present invention. rate. In some embodiments, the top surface 164t of the second barrier layer 164 may be flush with the top surface 166t of the second via 166 and the top surface 142t2 of the dielectric layer 142 of the second region R2.

In some embodiments, the MIM structure 210 may be a memory structure, a capacitor structure, a resistance structure, or a combination thereof. The memory structure includes resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), phase change random access memory (PCRAM), ferroelectric random access memory (FeRAM) Or a combination. For example, when the MIM structure 210 is an RRAM, the insulating layer 204 is a variable resistance layer that can change its own resistance through the application of voltage. The insulating layer 204 may include a high-k dielectric material, for example, selected from TiO ₂ , NiO, HfO, HfO ₂ , ZrO, ZrO ₂ , Ta ₂ O ₅ , ZnO, WO ₃ , CoO, and Nb At least one oxide material in the group consisting of ₂ O _5.

1H, a dielectric layer 172 is formed on the MIM structure 210 and the dielectric layer 142. In some embodiments, the material of the dielectric layer 172 includes HDP oxide. Then, vias 176 and 186 are formed in the dielectric layer 172, respectively. The via 176 penetrates a portion of the dielectric layer 172 to land on the MIM structure 210. The barrier layer 174 lines the sidewalls and the bottom surface of the via 176 to separate the via 176 and the dielectric layer 172. On the other hand, the via 186 (also referred to as a third via) penetrates the dielectric layer 172 to land on the first via 156. The barrier layer 184 lines the sidewalls and the bottom surface of the via 186 to separate the via 186 from the dielectric layer 172.

Referring to FIG. 1I, dielectric layers 190 and 192 are formed on the dielectric layer 172 and the via windows 176 and 186. In some embodiments, the dielectric layer 192 can be regarded as an inter-metal dielectric (IMD) layer. The dielectric layer 190 can be used as an etch stop layer, which has a different dielectric material from the dielectric layer 192. For example, the material of the dielectric layer 190 includes silicon nitride, and the material of the dielectric layer 192 includes TEOS oxide. Next, conductor layers 194 and 196 are respectively formed in the dielectric layers 190 and 192 to complete the semiconductor device 1. The conductor layers 194 and 196 are embedded in the dielectric layers 190 and 192 to be electrically connected to the via windows 176 and 186, respectively. In some embodiments, the conductor layers 194, 196 may be circuit layers. The material of the conductor layers 194 and 196 includes a metal material, such as a copper layer.

4, the semiconductor device 2 of the second embodiment is basically similar to the semiconductor device 1 of the first embodiment. The main difference between the above two is that the MIM structure 220 of the semiconductor device 2 has curved sidewalls 220s. As shown in FIG. 4, the sidewall 220s of the MIM structure 220 tapers along the upward direction of the substrate 100. In some embodiments, the lower width and/or lower area of the MIM structure 220 may be greater than the upper width and/or upper area of the MIM structure 220.

In summary, the embodiment of the present invention strengthens the barrier strength of the barrier layer lined on the sidewall of the via by nitriding, so as to avoid weak points during subsequent patterning of the MIM stack, thereby reducing the occurrence of copper burst defects . Therefore, the embodiments of the present invention can effectively improve the reliability and yield of semiconductor devices.

1, 2: Semiconductor components 10, 20: area 12: The first opening 14: second opening 16: Nitriding treatment 100: base 101: Isolation structure 102: etch stop layer 104, 130, 132, 140, 142, 172, 190, 192: Dielectric layer 110, 120: Gate structure 112, 122: gate dielectric layer 113, 123: Silicide layer 114, 124: gate electrode 115, 125: contact window 116, 126: top cover layer 118, 128: Clearance wall 134, 136, 194, 196: conductor layer 142t1, 142t2, 156t, 164t, 166t: top surface 142a: bottom 142b: top 144: Barrier Material 146: Conductor material 154: The first barrier layer 156: First Interlayer Window 164: second barrier layer 164a: lower part 164a1: Ti layer 164a2: TiN layer 164b: upper part 164b1: Ti layer 164b2: TiN layer 166: The second interlayer window 174, 184: barrier layer 176, 186: Interlayer window 200: metal-insulator-metal (MIM) stack 202, 206: metal layer 204: Insulation layer 210, 220: MIM structure 220s: sidewall R1: Zone 1 R2: Zone 2

1A to 1I are schematic cross-sectional views of a manufacturing process of a semiconductor device according to a first embodiment of the present invention. Fig. 2 is an enlarged view of the area of Fig. 1E. Fig. 3 is an enlarged view of another embodiment of the area of Fig. 2. 4 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the invention.

1: Semiconductor components

100: base

101: Isolation structure

102: etch stop layer

104, 130, 132, 140, 142, 172, 190, 192: Dielectric layer

110, 120: Gate structure

112, 122: gate dielectric layer

113, 123: Silicide layer

114, 124: gate electrode

115, 125: contact window

116, 126: top cover layer

118, 128: Clearance wall

134, 136, 194, 196: conductor layer

154: The first barrier layer

156: First Interlayer Window

164: second barrier layer

166: The second interlayer window

174, 184: barrier layer

176, 186: Interlayer window

202, 206: metal layer

204: Insulation layer

210: MIM structure

R1: Zone 1

R2: Zone 2

Claims (13)

A semiconductor device includes: a dielectric layer having a first region and a second region; a first via window configured in the dielectric layer in the first region; a second via window configured in the dielectric layer In the dielectric layer in the second region; a first barrier layer lining the sidewall and bottom surface of the first via; and a second barrier layer lining on the second via The sidewall and the bottom surface, wherein the first barrier layer and the second barrier layer each have an upper portion and a lower portion, and the nitrogen doping concentration of the upper portion is greater than the nitrogen doping concentration of the lower portion. The semiconductor element according to claim 1, wherein the dielectric layer includes: a bottom portion surrounding the lower portion of the second barrier layer; and a top portion surrounding the upper portion of the second barrier layer, wherein The nitrogen doping concentration at the top is greater than the nitrogen doping concentration at the bottom. The semiconductor device according to claim 1, further comprising: a metal-insulator-metal (MIM) structure, which is arranged on the first via; and a third via, which is arranged on the second via on. The semiconductor device according to claim 3, wherein the top surface of the second via is lower than the top surface of the first via, and the top surface of the dielectric layer in the second region is lower On the top surface of the dielectric layer in the first region. The semiconductor device according to claim 3, wherein the top surface of the dielectric layer of the second region and the top surface of the second barrier layer are substantially coplanar. A method for manufacturing a semiconductor element includes: forming a plurality of vias in a dielectric layer; nitriding the dielectric layer and the plurality of vias, so that the top of the dielectric layer The nitrogen doping concentration is greater than the nitrogen doping concentration at the bottom of the dielectric layer; forming a metal-insulator-metal (MIM) stack on the dielectric layer and the plurality of via windows; and patterning the metal -Insulator-metal stack to form a metal-insulator-metal structure. The method for manufacturing a semiconductor device according to claim 6, wherein performing the nitriding treatment includes performing a plasma nitriding process, and the plasma nitriding process includes passing a nitrogen-containing gas, and the nitrogen-containing gas includes N ₂ , NH ₃ or a combination thereof. The method for manufacturing a semiconductor device according to claim 6, wherein the dielectric layer has a first region and a second region, the first region is a unit cell region, and the second region is a peripheral region. The method of manufacturing a semiconductor element according to claim 8, wherein forming the plurality of via windows in the dielectric layer includes: forming a first opening in the dielectric layer in the first region; A second opening is formed in the dielectric layer of the second region; a barrier material is conformally formed to cover the first opening and the second opening; a conductive material is formed on the barrier material to Fill up the first opening and the The second opening covers the top surface of the dielectric layer; and a planarization process is performed to form a first via in the first opening and a second via in the second opening , Wherein the first barrier layer is lined on the sidewall and bottom surface of the first via window, and the second barrier layer is lined on the sidewall and bottom surface of the second via window. The method for manufacturing a semiconductor device according to claim 9, wherein after the nitridation treatment, the first barrier layer and the second barrier layer each include an upper portion and a lower portion, and the dielectric layer The bottom portion surrounds the lower portion, the top portion of the dielectric layer surrounds the upper portion, and the nitrogen doping concentration of the upper portion is greater than the nitrogen doping concentration of the lower portion. The method for manufacturing a semiconductor device according to claim 9, wherein after patterning the metal-insulator-metal stack, the second via is further etched so that the top surface of the second via is low On the top surface of the first via. The method for manufacturing a semiconductor element according to claim 9, wherein after patterning the metal-insulator-metal stack, the metal-insulator-metal structure is formed on the first via, and the second The second interlayer window is exposed outside the metal-insulator-metal structure. The method for manufacturing a semiconductor device according to claim 8, wherein after patterning the metal-insulator-metal stack, the dielectric layer of the second region is further etched so that all the dielectric layer of the second region The top surface of the dielectric layer is lower than the top surface of the dielectric layer in the first region.

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