JPH11317500A - Semiconductor device having capacitive element, and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device using a ceramic thin-film capacitance, in which a multilayer metallic wiring is can be easily formed and deterioration of a capacitive element will not occur. SOLUTION: The plug of a stack structure of a via 9 and metal wirings 7 and 10 formed simultaneously with the formation of a multilayer metal wiring connects a ceramic thin-film capacitance 30 to a diffusion layer 4. Hydrogen annealing is carried out after the formation of the multilayer metal wiring and prior to the formation of the ceramic thin-film capacitance 30. Since the capacitance 30 is formed after the formation of the multilayer metal wiring, the formation of the multilayer metal wiring resulting from a capacitance difference will not be prevented. Furthermore, since it is unnecessary to make a via for a tungsten plug after formation of the capacitance, no deterioration of the capacitance takes place by chemical vapor deposition(CVD) method of tungsten. Furthermore, since the capacitance can be formed without modifying a process device in a logical circuit part, existing design parameters can be used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a capacitance element, and more particularly to a semiconductor device having a ferroelectric capacitance and a high dielectric constant capacitance and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, ferroelectric memories using ferroelectric capacitors, dynamic random access memories (DRAMs) using high dielectric constant capacitors, and the like have been actively researched and developed. These ferroelectric memory and DRAM
Has a selection transistor, and stores information using a capacitor connected to one diffusion layer of the selection transistor as a memory cell. Ferroelectric capacitor is composed of Pb
A ferroelectric thin film such as (Zr, Ti) O ₃ (hereinafter, referred to as “PZT”) is used, and nonvolatile information can be stored by polarizing the ferroelectric. On the other hand, a high dielectric constant capacitor is composed of (Ba, Sr) TiO
₃ (hereinafter, referred to as “BST”), the use of a high dielectric constant thin film makes it possible to increase the capacitance of the capacitance and to make the element finer.

In order for such a ferroelectric capacitor and a high dielectric constant capacitor to function, it is necessary to electrically connect one electrode of the capacitor to the diffusion layer of the selection transistor as described above. .

Conventionally, in a DRAM, polysilicon connected to one diffusion layer of a select transistor is used as one electrode of a capacitor, and a SiO ₂ film or a Si ₃ N ₄ film is formed on the surface of the polysilicon as a capacitor insulating film. Is generally formed as a capacitor. However, since ferroelectric thin films and high dielectric constant thin films (hereinafter referred to as “ceramic thin films”) are oxides, if they are formed directly on the surface of polysilicon, the polysilicon is oxidized. Cannot be formed.

[0005] Therefore, the 1995 symposium on
VLSI Digest of Technical
Papers (1995 Symposium on V
LSI Technology Digest of
Technical Papers) pp. Reference 123 describes a cell structure in which a capacitor upper electrode and a diffusion layer are connected by a local wiring of metal such as Al.

The International Electron Devices Meeting Technical Digest (International Electron)
devices meeting technical
digest) 1994 pp. No. 843 describes a technique for forming a PZT capacitor on a polysilicon by using a TiN barrier metal.

[0007] For the DRAM, for example, the International Electron Devices Meeting
Technical Digest (Internationa
Electron Devices Meeting
technical digest) 1994 p
p. 841 has an R formed on the polysilicon plug.
forming a SrTiO ₃ thin film on the uO ₂ / TiN lower electrode,
A technique for forming a capacitor is described.

That is, in the conventional formation of a ferroelectric memory and a DRAM, as described above, a method of forming a metal wiring after forming a capacitor has been adopted.

[0009]

However, the memory cell structure in which the capacitance is connected to the diffusion layer by a local wiring or a polysilicon plug as described above has the following problems.

The first problem is that it is difficult to form a multilayer metal wiring.

A ferroelectric memory or DRAM using a ferroelectric thin film or a high dielectric constant thin film is more highly integrated.
In order to realize a semiconductor device in which a logic circuit and such a memory are mixed, it is necessary to form a multilayer metal wiring. When forming a multilayer metal wiring, an insulating film between metal wiring layers is planarized by a chemical mechanical polishing method (CMP method) or the like.

However, due to the formation of the capacitance, the height difference between the cell array portion having the capacitance and the logic circuit portion having no capacitance becomes large, and it is difficult to connect the wiring layer by the flattening and the flattened contacts and vias. There is a problem that becomes.

Japanese Patent Application Laid-Open No. 9-92794 aims to reduce the level difference between a cell and its peripheral circuit and to form a multilayer wiring having a small wiring resistance in the peripheral circuit.
A method for manufacturing a semiconductor memory is disclosed.

In this manufacturing method, the electrode of the cell capacitor and the wiring other than the cell region are simultaneously formed. Noble metals such as Pt are usually used for electrodes of capacitors using ceramic thin films, but these noble metals are difficult to process, and
Since the wiring has high resistance, it is difficult to use it as a wiring other than the cell region.

A second problem is that the design cost for realizing a semiconductor circuit in which a logic circuit and a memory are mixed is increased.

The reason for this is that the process and device of the logic circuit must be changed due to the first problem described above, so that the existing design parameters cannot be used.

A third problem is that the electrical characteristics of the capacitor deteriorate in the process of forming the multilayer metal wiring.

In a multilayer metal wiring, a tungsten plug is usually formed in a via connecting between metal wirings, and tungsten (W) is formed by a reaction represented by the following formula.

2WF ₆ + 3SiH ₄ → 2W + 3SiH ₄ + 6H ₂ That is, tungsten (W) is formed in a very strong reducing atmosphere. Since the ceramic thin film is an oxide, when exposed to a reducing atmosphere, oxygen vacancies occur. Therefore, a decrease in resistance (as a result, an increase in leakage current),
There is a problem in that the amount of ferroelectric polarization decreases, the dielectric constant decreases, and other electrical characteristics deteriorate.

Japanese Patent Application Laid-Open No. 9-199679 proposes a structure of a semiconductor device which avoids a reducing atmosphere and allows deep contact holes to be embedded. In this semiconductor device, a plug contact made of a heat-resistant metal is formed in an opening reaching a diffusion layer of a storage circuit portion and a diffusion layer of a CMOS circuit portion, and then a ferroelectric capacitor is formed. Aluminum wiring is formed for the contact.

However, to realize such a structure of the semiconductor device, a complicated manufacturing process is required.
Although the structure of this semiconductor device can be applied to the first-layer metal wiring, a tungsten film needs to be formed in a via connecting the second-layer metal wiring and the first-layer metal wiring. Therefore, for multilayer metal wiring,
It cannot be a solution.

The fourth problem is that the threshold value (Vt) of the transistor varies and the sub-threshold characteristic deteriorates.

The plasma in plasma etching
The interface state or fixed charge generated in the gate oxide film of the MOS transistor due to damage or the like causes variation in the threshold value (Vt) of the transistor or deterioration of the subthreshold characteristic.

As a method for improving these, annealing in a hydrogen-containing atmosphere (hydrogen annealing) has been conventionally performed. However, in a semiconductor device having a capacitor using a ceramic thin film, as described in the third problem, if such annealing is performed after the capacitor is formed, the electrical characteristics of the capacitor deteriorate. Therefore, such annealing cannot be performed after the formation of the capacitor.

Therefore, for example, Japanese Patent Application Laid-Open No. Hei 7-111318
Japanese Patent Application Laid-Open Publication No. H11-163873 discloses a technique of providing a hydrogen barrier film such as Si ₃ N ₄ on a capacitor. According to this technique, by providing a hydrogen barrier film on a capacitor, diffusion of hydrogen into the capacitor is prevented, and thus deterioration of the capacitor in a reducing atmosphere is prevented.

However, in this technique, the number of steps for forming and processing the hydrogen barrier film is increased, which causes a new problem of an increase in the number of steps and an increase in manufacturing cost.

Moreover, when this technology is applied to a more highly integrated and miniaturized device, the hydrogen barrier film also needs to be made thinner. However, reducing the thickness of the hydrogen barrier film causes a problem that the hydrogen barrier property becomes insufficient.

On the other hand, with the recent increase in the scale and speed of semiconductor devices and miniaturization of elements, reduction in variations in transistor characteristics has become increasingly important.

The fifth problem is that if a metal wiring and a contact for connecting the metal wiring and the substrate are formed after the capacitor is formed as in the conventional case, the deterioration of the capacitance characteristic and the connection of the capacitor to another element are formed. This causes an increase in wiring resistance.

Usually, when a contact for connecting a metal wiring and a substrate is formed, ion implantation is performed after opening the contact in order to reduce the resistance between the metal wiring and the substrate. Therefore, after ion implantation,
It is necessary to perform a heat treatment at a temperature of about 700 ° C. or higher for ion activation.

However, if such a high-temperature heat treatment is performed after the formation of the ceramic thin film capacitor, the ceramics, the electrodes, and the wirings cause mutual reaction and mutual diffusion. Therefore, as described above, the deterioration of the capacitance characteristics and the increase of the wiring resistance occur.

As a method for solving the deterioration of the capacitor due to the high temperature heat treatment after the formation of the capacitor, Japanese Patent Laid-Open No.
No. 85187 describes a method of manufacturing a semiconductor memory device in which a capacitor is formed after forming a metal wiring. According to this manufacturing method, the contact connecting the storage electrode of the capacitor and the diffusion layer of the substrate is opened after the formation of the metal wiring, and then the capacitor is connected to the substrate by forming the storage electrode.

However, in such a structure, when the metal wiring has two or more layers, the contact hole becomes extremely deep, and it is extremely difficult to form a storage electrode of a capacitor therein. Accompanied by

Due to the above problems, a ferroelectric memory using a multilayer metal wiring structure or a ceramic thin film capacitor D
RAM has not been implemented yet.

The present invention has been made in view of the above problems in a conventional semiconductor device having a capacitor, and a ceramic thin film that can easily form a multilayer metal wiring and does not cause deterioration of the capacitor. It is an object to provide a semiconductor device using a capacitor.

Another object of the present invention is to provide a semiconductor device which can realize a chip in which a logic circuit and a memory using a ceramic thin film capacitor are mounted at low cost.

Another object of the present invention is to provide a semiconductor device using a ceramic thin film capacitor and having good transistor characteristics.

[0038]

A semiconductor device according to the present invention is formed simultaneously with the formation of a multi-layer metal wiring in a memory cell structure in which a capacitance is connected to a diffusion layer by a local wiring or a polysilicon plug or the like. A memory cell structure in which a capacitor and a diffusion layer are connected by a plug having a structure in which a via and a metal wiring are stacked is provided.

Therefore, the formation of the multilayer metal wiring is not hindered by the difference in height due to the capacitance. Further, since the capacitance can be formed without any change in the process device of the logic circuit portion, existing design parameters can be used as they are.

Specifically, claim 1 of the present invention is:
In a semiconductor device having a ceramic thin film capacitor in which a substrate, at least one layer of metal wiring, a lower electrode, a ceramic thin film, and an upper electrode are laminated in this order, the lower electrode, the ceramic thin film, and the upper electrode constituting the ceramic thin film capacitor are And a semiconductor device formed above at least one layer of metal wiring.

According to a second aspect of the present invention, at least one of the electrodes constituting the ceramic thin film capacitor is connected to the substrate via a wiring, and the wiring is formed of at least one metal wiring. It is preferable to configure so as to include.

In the case where the ceramic thin film capacitor is connected to the substrate via the wiring, the wiring may be a contact connecting the metal wiring to the substrate, a metal wiring, or the metal. It has a structure in which a via connecting the wiring and one electrode of the ceramic thin film capacitor is stacked, or a structure in which at least one metal wiring and a via are stacked between the metal wiring and one electrode of the ceramic thin film capacitor. It is preferable to configure.

Alternatively, when at least one electrode of the ceramic thin film capacitor is connected to the substrate via a wiring as described in claim 4, the wiring includes at least one metal wiring and the metal wiring. It is preferable that the contact is formed after the wiring and includes a contact connecting one of the electrode of the ceramic thin film capacitor or the metal wiring to the substrate.

Alternatively, when at least one electrode of the ceramic thin film capacitor is connected to the substrate via a wiring, the wiring is formed by directly laminating at least one contact or via. It is preferable to have a modified structure.

The above-described effects can be achieved by these specific structures described in claims 1 to 5.

As described in claim 6, it is also possible to further form at least one layer of metal wiring above the ceramic thin film capacitor.

Thus, a multi-layered metal wiring can be further formed. In particular, in multilayer metal wiring in recent large-scale LSIs, wiring in the upper layer generally has a larger wiring width and space between the wirings than the wiring in the lower layer. Therefore, even if a ceramic thin film capacitor is formed between the metal wiring layers, the resulting step does not adversely affect the formation of the upper metal wiring.

Further, it is preferable that the metal wiring formed above the ceramic thin film capacitor is used only as a plate line of a memory having at least a memory cell including the ceramic thin film capacitor.

Further, as described in claim 8,
It is preferable that one of the electrodes of the ceramic thin film capacitor is formed such that a via or a contact connecting the metal wiring or the substrate is eccentric from the center of the ceramic thin film capacitor. That is, it is preferable that the via or the contact is not formed at the center of the ceramic thin film capacitor.

With such a configuration, the area of the capacitor can be increased without increasing the cell area.

Further, as described in claim 9,
It is preferable that the contact formed on the upper portion of the ceramic thin film capacitor is arranged so as to be eccentric from the contact formed on the lower portion of the ceramic thin film capacitor.

With this configuration, the margin between the contact above the capacitor and the capacitor can be increased.

The ceramic thin film capacitor can be formed in various forms.

For example, as described in the tenth aspect, the upper electrode forming the ceramic thin film capacitor can be formed so as to be stacked with a smaller area than the lower electrode.

With this configuration, it is possible to prevent the upper electrode and the lower electrode from being short-circuited on the capacitor side wall.

Alternatively, as described in claim 11, the ceramic thin film capacitor includes a plurality of lower electrodes formed at intervals on the interlayer insulating film and an entire surface of both the interlayer insulating film and the lower electrode. It is also possible to comprise a ceramic thin film to cover and an upper electrode formed on the ceramic thin film so as to cover at least a part of the lower electrode.

According to this embodiment, since it is not necessary to process the ceramic thin film to a predetermined size, the manufacturing process can be simplified accordingly.

As described in the twelfth aspect, a diffusion barrier film can be formed between the ceramic thin film capacitor and the interlayer insulating film thereunder.

In particular, when a ceramic thin film is formed after processing the lower electrode, elements constituting the ceramic thin film may diffuse into the interlayer insulating film. Diffusion can be prevented.

According to a thirteenth aspect of the present invention, there is provided a contact for connecting a lower electrode of a ceramic thin film capacitor with a metal wiring located below the ceramic thin film capacitor, and a via formed below the metal wiring. Is preferably arranged at intervals through the metal wiring.

The metal wiring on the via may be dented depending on the process of forming the via and the metal wiring. If a contact or a via is formed on a metal wiring that is not flat as described above, good electrical connection may not be obtained. Therefore, instead of placing the contacts directly above the vias,
By forming them at a certain distance from each other, it is possible to prevent poor electrical connection.

When at least two layers of metal wiring are formed between the ceramic thin film capacitor and the substrate, the upper metal wiring may be directly connected to the substrate via a contact. It is possible.

According to such a configuration, the lower metal wiring can be used only as, for example, a bit wiring in the cell, so that the cell area can be reduced.

As described in claim 15, it is also possible to form a plate line backing wiring above the ceramic thin film capacitor.

According to such a configuration, the wiring resistance of the plate line can be reduced.

Further, as set forth in claim 16, the backing wiring of the word line can be formed by a metal wiring lower than the ceramic capacitor.

In this case, it is preferable that the backing wiring of the adjacent word line is formed by at least two layers of metal wiring.

Further, as described in claim 18, the two-layer metal wiring forming the word line backing wiring crosses at least at one position in the memory cell array, because noise can be reduced. ,preferable.

In the case where a metal wiring is formed above a ceramic thin film capacitor via an interlayer insulating film, the metal wiring is formed at the end thereof.
Through the recess formed over both the interlayer insulating film and the interlayer insulating film formed below the ceramic thin film capacitor,
It can be connected to a metal wiring or a substrate formed below the ceramic thin film capacitor.

Alternatively, as set forth in claim 20, the metal wiring is connected at an end thereof to a via formed below the ceramic thin film capacitor via a recess formed in the interlayer insulating film, The via may be connected to a metal wiring or a substrate formed below the ceramic thin film capacitor.

Alternatively, as set forth in claim 21, the metal wiring is provided at a lower end of the ceramic thin film capacitor through a concave portion formed over both the interlayer insulating film and the ceramic thin film of the ceramic thin film capacitor. Connected to a via formed below the ceramic thin film capacitor via the lower electrode, and connected to a metal wiring or a substrate formed below the ceramic thin film capacitor via the via. You may.

If connection between the metal wiring and the diffusion layer is made by any one of these three forms, it is not necessary to use tungsten CVD after the formation of the ceramic thin film capacitor, and the deterioration of the ceramic thin film capacity is reduced. Can be prevented.

When the upper electrode is used as a plate line,
As described in claim 22, the upper electrode has, at its end, a concave portion formed over both the ceramic thin film of the ceramic thin film capacitor and the interlayer insulating film formed below the ceramic thin film capacitor. And a metal wiring or a substrate formed below the ceramic thin film capacitor.

Alternatively, as described in claim 23, the upper electrode is connected to the lower electrode of the ceramic thin film capacitor at a terminal thereof through a concave portion formed in the ceramic thin film of the ceramic thin film capacitor. The lower electrode may be connected to a via formed below the ceramic thin film capacitor, and the via may be connected to a metal wiring or a substrate formed below the ceramic thin film capacitor.

As described in claim 24, the metal wiring can be mainly composed of, for example, aluminum or copper.

Further, a via or a contact for connecting one of the electrodes of the ceramic thin film capacitor to a metal wiring or a substrate can be mainly made of, for example, tungsten.

[0077] The lower electrode of the ceramic thin film capacitor may include a conductive nitride.

Further, the conductive nitride is preferably titanium nitride, tantalum nitride or tungsten nitride.

Further, as described in claim 28, the lower electrode may have a structure in which a layer containing a conductive nitride and a noble metal layer are laminated.

In this case, it is preferable that the noble metal layer is made of platinum, iridium, ruthenium, an alloy thereof, or a laminate of them.

The present invention provides a method for manufacturing a semiconductor device, comprising: a first step of forming at least one layer of metal wiring; and a second step of forming a ceramic thin film capacitor after the first step. I do.

According to the method of claim 30, the semiconductor device of claim 1 can be formed.

Further, according to this method, after forming the multilayer metal wiring, the ceramic thin film capacitor is formed.
There is no need to form a via with a tungsten plug after the formation of the ceramic thin film capacitor. Therefore, the capacity of the ceramic thin film does not deteriorate due to tungsten CVD.

Further, since the contact between the metal wiring and the substrate is also formed before the formation of the ceramic thin film capacitor, it is possible to prevent the deterioration of the ceramic thin film capacitance and the increase in wiring resistance due to activation after the contact injection. .

Further, it is preferable that the above-mentioned method includes a step of performing annealing in an atmosphere containing hydrogen.

This hydrogen annealing can reduce the deterioration of the transistor.

The temperature of the hydrogen annealing is preferably in a range of 300 degrees Celsius to 500 degrees Celsius.

If the temperature is lower than 300 degrees Celsius, the effect of improving the transistor characteristics is small, and if the temperature is higher than 500 degrees Celsius, the metal wiring may be broken.

A first step of forming at least one layer of metal wiring and a step of forming a metal wiring as a part of a wiring for connecting at least one electrode of the ceramic thin film capacitor and the substrate are provided. And a method for manufacturing a semiconductor device, comprising:

According to this method, the semiconductor device according to claim 2 can be manufactured.

The ceramic thin film capacitor can be formed by various methods.

For example, the capacitance of the ceramic thin film is defined by claim 3
4, a first step of forming a lower electrode, a second step of forming a ceramic thin film on the lower electrode, a third step of forming an upper electrode on the ceramic thin film, A fourth step of etching the lower electrode, the ceramic thin film and the upper electrode.

Alternatively, a first step of forming a lower electrode and etching the lower electrode, a second step of forming a ceramic thin film on the lower electrode, and a ceramic thin film A third step of forming a film on the upper electrode and etching the upper electrode can also be used.

In these cases, the ceramic thin film is preferably formed at a temperature of 500 degrees Celsius or less.

In a usual sol-gel method or a sputtering method, in order to obtain a good ceramic thin film, a temperature of 600 ° C.
It is necessary to form the film at a temperature higher than the temperature, but such a high temperature causes disconnection of the metal wiring and an increase in resistance. Therefore, C
By using the VD method, a film can be formed at a low temperature of 500 degrees Celsius or less.

In the case where a ceramic thin film is formed after processing the lower electrode as in the method described in claim 35, the lower electrode and the interlayer below the lower electrode are formed as described in claim 37. Preferably, the method further includes a step of forming a diffusion barrier film between the insulating film and the insulating film.

As described in claim 38, at least one layer of metal wiring may be further formed above the ceramic thin film capacitor.

As a result, a further multilayered metal wiring layer can be formed.

In this case, it is preferable that the metal wiring formed above the ceramic thin film capacitor is formed in an atmosphere having a weak reducing property.

As a result, it is possible to prevent deterioration of the capacitance of the ceramic thin film located below the metal wiring.

A semiconductor device further comprising a step of forming an interlayer insulating film on the ceramic thin film capacitor, and a step of forming a first metal wiring connected to the ceramic thin film capacitor via the interlayer insulating film. The method of manufacturing
At the end of the first metal wiring, a concave portion reaching the second metal wiring formed below the ceramic thin film capacitor extends over both the interlayer insulating film and the interlayer insulating film formed below the ceramic thin film capacitor. After formation, a method is provided that is formed in the recess.

According to this method, a semiconductor device according to claim 19 can be provided.

A semiconductor device further comprising a step of forming an interlayer insulating film on the ceramic thin film capacitor and a step of forming a first metal wiring connected to the ceramic thin film capacitor via the interlayer insulating film. The method of manufacturing
The first metal wiring is formed in the recess after forming a recess in the interlayer insulating film at the end thereof, and the first metal wiring is connected to the second metal wiring formed below the ceramic thin film. Provide a way to be connected.

According to this method, a semiconductor device according to claim 20 or 21 can be provided.

According to claim 42, the upper electrode of the ceramic thin film capacitor is formed below the ceramic thin film capacitor at both ends over the ceramic film and the interlayer insulating film formed below the ceramic thin film capacitor. A method of manufacturing a semiconductor device, wherein the method is formed in a concave portion after forming a concave portion reaching a second metal wiring.

According to this method, a semiconductor device according to claim 22 can be provided.

[0107] Claim 43 is that the upper electrode of the ceramic thin film capacitor is formed in the recess after forming a recess in the ceramic film at the end, and the upper electrode is formed of the lower electrode of the ceramic thin film capacitor and the lower electrode. A method is provided that is connected to a second metal wiring formed below the ceramic thin film capacitor through a via formed below the lower electrode.

According to this method, a semiconductor device according to claim 23 can be provided.

[0109]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a plan view showing a part of a memory cell of a ferroelectric memory or a DRAM as a first embodiment according to the present invention. FIG. 1A is a plan view of the memory cell as viewed from above before the first metal wiring is formed.
(B) is a plan view when the memory cell after the formation of the first metal wiring is viewed from above. FIG. 2 shows FIG.
It is sectional drawing along the AA of (A). FIG. 3 is a circuit diagram of the memory cell shown in FIG.

As shown in FIG. 3, the memory cell 32 includes a selection transistor 31 and a ceramic thin film capacitor 30. The gate of the selection transistor 31 is connected to the word line 33
One of the source and the drain is connected to the bit line 35.
The other is connected to a plate line 34 via a ceramic thin film capacitor 30.

As shown in FIG. 2, a MOS transistor as the selection transistor 31 shown in FIG. 3 is formed on the silicon substrate 1. On this MOS transistor, a first metal wiring 7 made of a barrier metal such as Ti and an alloy mainly containing Al or Cu is provided. It is connected to each diffusion layer 4 of the transistor.

One of the two first metal wirings 7 shown in FIG.
The other first metal wiring 7 is used as a bit line 35. On the first metal wiring 7, similarly to the first metal wiring 7, a second metal wiring 10 made of a barrier metal such as Ti and an alloy mainly containing Al or Cu is provided. The wiring 10 is electrically connected to the first metal wiring 7 via a via 9 made of a tungsten plug or the like, like the contact 6. in this way,
In the memory cell 32 according to the present embodiment, a multilayer metal wiring structure including the first metal wiring 7 and the second metal wiring 10 is formed.

On this multilayer metal wiring structure, a ceramic thin film capacitor 30 is provided. The ceramic thin film capacitor 30 is configured by laminating a lower electrode 13, a ceramic thin film 14, and an upper electrode 15 in this order.

Lower electrode 13 of ceramic thin film capacitor 30
Represents the second metal wiring 1 via the capacitor lower contact 12.
0 is connected. As a result, the connection between the ceramic thin film capacitor 30 and the selection transistor 31 in FIG. 3 is made.

The third metal wiring 18 is formed on the ceramic thin film capacitor 30 via the capacitor upper contact 17. The third metal wiring 18 corresponds to the plate line 3 in FIG.
Used as 4.

As described above, the structure below the second metal wiring 10 of the memory cell 32 in this embodiment is exactly the same as that of an LSI having no ordinary ceramic thin film capacitor. Therefore, it can be manufactured in the same manufacturing process as the LSI.

Therefore, according to the present embodiment, a ferroelectric memory or a DRAM using such a memory cell 32 is used.
An advantage is brought about that a semiconductor device in which the conventional logic circuit and the ordinary logic LSI are mounted together on a single chip can be realized at low cost by using an existing logic circuit.

The required characteristics are different between the cell transistor 31 of a memory cell used in a ferroelectric memory or a DRAM and the transistor of a normal logic circuit. Therefore, the cell transistor 31 may have a different structure from the transistor of the logic circuit. For example, since a voltage higher than the operating voltage of the memory circuit is generally applied to the word line 33, the gate film may need to be thicker than the transistors of other logic circuits. The formation of transistors having different structures on the same substrate as described above is generally performed, for example, as described in Nikkei Microdevices, March 1995, p. 55. It can be realized using a process.

FIGS. 4 to 6 show a method of manufacturing a semiconductor device having the memory cell 32 according to the present embodiment.

First, as shown in FIG.
Through the manufacturing process of the SI, MOS transistors such as a memory cell unit and a logic circuit unit are formed on the silicon substrate 1. That is, an oxide film 2 is formed on a silicon substrate 1,
An element formation region is defined by the oxide film 2, and then a gate electrode 3 and a diffusion layer 4 are formed. Further, a first interlayer insulating film 5 is formed on the silicon substrate 1. The formed first interlayer insulating film 5 is planarized by a CMP method, a reflow method, or the like.

Next, a first metal wiring 7 and a contact 6 for connecting the first metal wiring 7 and the diffusion layer 4 are formed.

These methods include forming a contact 6 with a tungsten plug or the like and then forming and processing a first metal wiring 7, and forming an interlayer insulating film 5 between the contact 6 and the first metal wiring 7. After that, there is a dual damascene method in which a metal is buried, and then the excess metal is removed to form the contact 6 and the first metal wiring 7 at the same time.

In the former case, after the contact 6 is opened by etching, contact injection and activation are performed, and T
A barrier metal such as i or TiN is deposited. After that, CV
A tungsten film is formed on the entire surface of the wafer by the D method, and then the tungsten on the surface is removed by a CMP method or an etch back to form a tungsten plug. A tungsten plug can also be formed by selective growth of tungsten.

Next, as shown in FIG. 4B, a first metal wiring 7 is formed on the contact 6. The first metal wiring 7 is composed of a barrier metal such as Ti and TiN, an alloy layer mainly composed of Al and Cu, and a composite layer composed of an antireflection film such as TiN. Is processed by etching.

Thereafter, as shown in FIG. 5C, a second interlayer insulating film 8 is formed and flattened.
A via 9 and a second metal wiring 10 are formed thereon. Via 9
The second metal wiring 10 is formed in the same manner as the contact 6 and the first metal wiring 7.

Thereafter, as shown in FIG. 5 (D), after forming the third interlayer insulating film 11, a capacitor lower contact 12 is formed on the second metal wiring 10 by a tungsten plug or the like in the same manner as the contact 6. At this time, it is desirable to remove the tungsten on the surface by the CMP method. This is because the ceramic thin film capacitor 30 to be formed later can be formed on a completely flat surface.

After that, annealing is performed in an atmosphere containing hydrogen. The annealing temperature is preferably from 300 ° C. to 500 ° C. If the temperature is lower than 300 ° C., the effect of improving the transistor characteristics is small, and if the temperature is higher than 500 ° C., the metal wirings 7 and 10 may be disconnected.

The above process is the same as a normal LSI process having no ceramic thin film capacitor. No change or addition of a special process for connecting the ceramic thin film capacitor to the diffusion layer 4 is made.

Next, the ceramic thin film capacitor 3 is formed on the third interlayer insulating film 11 so as to be connected to the capacitor lower contact 12.
0 is formed. The ceramic thin film capacitor 30 is formed by the following procedure.

First, as shown in FIG. 6E, Pt, I
A lower electrode 13 made of a noble metal such as r or Ru or a conductive oxide such as IrO ₂ or RuO ₂ is formed on the third interlayer insulating film 11 by a sputtering method or another method.

In this case, a barrier film made of TiN or the like is formed below these noble metal or conductive oxide layers in order to prevent mutual reaction and mutual diffusion of Pt and the like of the lower electrode 13 with tungsten of the capacitor lower contact 12. Is preferred.

Next, Pb (Zr,
Ti) O ₃ (PZT), (Ba, Sr) TiO ₃ (BS
A ceramic thin film 14 made of T), SrTiO ₃ (ST) or the like is formed by a CVD method or the like.

In the case of forming PZT, heating at 600 ° C. or higher is required to obtain a good PZT thin film by a usual sol-gel method or sputtering method. At such a high temperature, disconnection of the metal wiring and an increase in the resistance are caused, so that it cannot be applied to this structure. Therefore, it is desirable to form a film at a low temperature of about 500 ° C. as in the CVD method.

The PZT thin film can form a good film at a temperature of 350 ° C. to 500 ° C. by the CVD method. In addition, the ST film is made of, for example, International Electron Devices Meeting Technical Digest (International electr
on devices meeting techni
cal digest) 1994 pp. 831, 450 ° C. by the ECR-CVD method.
Can be formed.

The upper electrode 15 is formed on the ceramic thin film 14 formed by the above method by the same method as the lower electrode 13.

Thereafter, the upper electrode 15, the ceramic thin film 1
4 and the lower electrode 13 are processed by etching. Thus, the ceramic thin film capacitor 30 as shown in FIG. 6E is formed.

Further, after forming the fourth interlayer insulating film 16 on the ceramic thin film capacitor 30, the capacitor upper contact 1
7. Open 7 holes. Thereafter, as shown in FIG. 6F, the third metal wiring 18 to be the plate line 34 is formed in the same manner as the first and second metal wirings 7, 10.

The third metal wiring 18 is used only as the plate line 34, and is not used in other logic circuit portions. Therefore, in the logic circuit section, there is no change in the device by forming the memory cell array section using the ceramic thin film capacitor 30. This third
A passivation film (not shown) made of SiON or the like is formed on metal wiring 18.

The plate line 34 is usually connected to the inverter of the plate line drive circuit at the end of the cell array. Hereinafter, a method of connecting the third metal wiring 18 used as the plate line 34 to the diffusion layer 4 will be described with reference to FIGS.

FIG. 7 is a cross-sectional view showing an example of a structure for connecting the third metal wiring 18 (plate line 34) to the diffusion layer 4.

As shown in FIG. 7, the plate line contact 19 penetrates through the fourth interlayer insulating film 16 and reaches the second metal wiring 10 in the third interlayer insulating film 11. The third metal wiring 18 is directly connected to the second metal wiring 10 at the plate line contact 19, and is connected to the diffusion layer 4 via the via 9, the first metal wiring 7 and the contact 6. Such a structure can be manufactured as follows.

First, after forming the fourth interlayer insulating film 16 on the ceramic thin film capacitor 30, the plate line contact 1
9 and the capacitor upper contact 17 are opened. After that, the third metal wiring 18 is formed. In this manner, a contact with the upper electrode 15 and a contact with the second metal wiring 10 can be formed simultaneously.

FIG. 8 is a cross-sectional view showing another example of a structure for connecting the third metal wiring 18 (plate line 34) to the diffusion layer 4.

As shown in FIG. 8, a plate line contact 19 reaching the surface of the third interlayer insulating film 11 is formed in the fourth interlayer insulating film 16. The third metal wiring 18
It is connected to the second metal wiring 10 via the second via 20, and further connected to the diffusion layer 4 via the via 9, the first metal wiring 7 and the contact 6. Such a structure can be manufactured as follows.

When forming the capacitor lower contact 12, the second via 20 is formed at the same time. Then, after forming the ceramic thin film capacitor 30 and the fourth interlayer insulating film 16,
The plate line contact 19 is opened. After that, the third metal wiring 18 is formed. Thus, the upper electrode 1
5 and the second metal wiring 10 can be formed simultaneously.

The third metal wiring 1 is formed by the above two methods.
If the connection between 8 and diffusion layer 4 is formed, it is not necessary to use CVD of tungsten after forming ceramic thin film capacitor 30, and deterioration of ceramic thin film capacitor 30 does not occur.

In the present embodiment, the process of forming the ceramic thin film capacitor 30 after the formation of the multilayer metal wiring is adopted. Is not disturbed.

Further, there is no need to form a tungsten plug structure or a contact between the metal wiring and the substrate after the formation of the ceramic thin film capacitor 30. Therefore, tungsten-
The ceramic thin film capacitive element is not deteriorated by the CVD and the activation heat treatment.

Further, after forming the multilayer wiring,
Since the hydrogen annealing is performed before the formation of the ceramic thin film capacitor 30, the variation in the threshold value Vt of the transistor can be reduced, and the deterioration of the ceramic thin film capacitor does not occur.

In this embodiment, a plug wiring for connecting the ceramic thin film capacitor 30 and the selection transistor 31 is formed at the same time as the formation of the multilayer metal wiring.
Therefore, the ceramic thin film capacitor 30 and the selection transistor 3
There is no need to provide a separate plug to connect
Another advantage is that the manufacturing process can be simplified.

The first embodiment described above is an example in which the present invention is applied to a case where a ceramic thin film capacitor is formed on a two-layer metal wiring. However, the present invention is also applicable to a case where a multi-layer metal wiring is used. Can be applied. Even in such a case, the ceramic thin film capacitor can be formed after the formation of the multilayer metal wiring in the same manner as in the present embodiment.

In the first embodiment described above, the third metal wiring 18 is the uppermost metal wiring, but a multilayer metal wiring can be further formed thereon.

In recent large-scale LSIs, a multi-layered metal wiring in which a local wiring connecting adjacent elements is formed by a lower metal wiring and a so-called global wiring such as a power supply line is formed over a wide area by an upper metal wiring. The structure of is adopted. In such a case, the wiring width and the space between the wirings in the upper metal wiring are generally larger than those in the lower metal wiring. Therefore, even if a ceramic thin film capacitor is formed between the upper and lower metal wirings, the resulting step does not adversely affect the formation of the upper metal wiring.

Further, if the upper metal wiring is formed by a method such as sputtering or plating that does not create a strong reducing atmosphere, the capacity of the ceramic thin film does not deteriorate.

Next, a specific example in which the present embodiment is applied to a ferroelectric memory will be described with reference to FIGS.

First, the silicon substrate 1 was wet-oxidized.
An oxide film 2 was formed thereon. Thereafter, impurities such as boron and phosphorus were ion-implanted into the silicon substrate 1 to form n-type and p-type wells. Thereafter, the gate 3 and the diffusion layer 4 were formed as follows.

First, after a gate oxide film was formed by wet oxidation, a polysilicon film for forming the gate 3 was formed and etched. After forming a silicon oxide film on the polysilicon film, etching was performed to form a sidewall oxide film.

Next, impurities such as boron and arsenic were ion-implanted to form n-type and p-type diffusion layers 4.

Further, after a Ti film was formed thereon, it was reacted with silicon, and unreacted Ti was removed by etching, thereby forming Ti silicide on the gate 3 and the diffusion layer 4.

Through the above steps, n-type and p-type MOS transistors were formed on the silicon substrate 1 as shown in FIG.

Next, the first metal wiring layer 7 and the second metal wiring layer 10 were formed as follows.

First, as the first interlayer insulating film 5, a silicon oxide film and a silicon oxide film (B
(PSG) was formed on the silicon substrate 1 and then planarized by the CMP method.

Next, after the contact 6 was opened by etching, impurities were implanted into the n-type and p-type diffusion layers 4 and heat treatment was performed at 750 ° C. for 10 seconds.
After that, Ti and TiN were formed as barrier metals. After tungsten was formed thereon by CVD, the tungsten on the surface was removed by CMP. Thereafter, a film of AlCu was formed as the first metal wiring 7 by sputtering and processed by etching.

After a silicon oxide film was formed as a second interlayer insulating film 8 on the first metal wiring 7 by a CVD method, it was planarized by a CMP method. Via 9 is contact 6
5C, the second metal wiring 10 was formed by the same method as the first metal wiring, as shown in FIG. 5C.

Further, as shown in FIG. 5D, after the third interlayer insulating film 11 was formed, the capacitor lower contact 12 was formed in the same manner as the contact 6. Then 5% hydrogen,
Annealing was performed at a temperature of 400 ° C. for 20 minutes in an atmosphere of 95% nitrogen.

Next, a method of forming the ferroelectric capacitor 30 will be described.

First, as the lower electrode 13, a 50-nm-thick TiN film and a 100-nm-thick Pt film were formed by sputtering in this order. Pt is preferably used at a temperature of 300 ° C. or higher because the crystallinity is improved.

After that, the ferroelectric thin film 1 is formed on the lower electrode 13.
As No. 4, PZT was formed by a CVD method.

Raw materials include lead bisdipivaloyl methanate lead (Pb (DPM) ₂ ), titanium isopolopoxide (Ti
(OiPr) ₄ ), zirconium butoxide (Zr (O
tBu) ₄ ), and NO ₂ as an oxidizing agent.

These organic metal raw materials and the oxidizing agent were supplied into the reaction chamber from separate supply ports. The film formation conditions were as follows: the substrate temperature was 400 ° C., and the total pressure of the gas in the film formation chamber was 5 × 10 ⁻³ To.
rr. First, Pb (DPM) ₂ is supplied at a flow rate of 0.2 S.
CCM, Ti (OiPr) ₄ flow rate 0.25 SCCM,
NO ₂ was deposited at a flow rate of 3.0 SCCM for 40 seconds. As a result, fine core crystals of PbTiO ₃ were formed on the lower electrode 13.

Thereafter, Pb (DPM) ₂ was supplied at a flow rate of 0.25.
SCCM, Zr (OtBu) ₄ flow rate 0.225SCC
M and Ti (OiPr) ₄ were formed at a flow rate of 0.2 SCCM and NO ₂ at a flow rate of 3.0 SCCM for 600 seconds, and a film thickness of 1
A 00 nm PZT film 14 was obtained.

Thereafter, under an atmosphere of 100% oxygen, 40
Annealing was performed at a temperature of 0 ° C. for 10 minutes. By performing annealing before forming the upper electrode 15, PZ
The electrical characteristics of the T capacitance can be improved.

On the PZT film 14, as the upper electrode 15, IrO _{2 having a} thickness of 50 nm and Ir having a thickness of 100 nm were formed in this order by a sputtering method.

Thereafter, the upper electrode 15, the PZT film 14, and the lower electrode 13 were processed by etching, and further annealed at a temperature of 400 ° C. for 10 minutes in an atmosphere of 100% oxygen to obtain a PZT capacitor 30. .

When annealing is further performed after the upper electrode 15 is formed, the dependence of the electric field of the PZT capacitor 30 on the application direction is reduced, and symmetric hysteresis characteristics can be obtained.

After a silicon oxide film was formed as the fourth interlayer insulating film 16 by O ₃ TEOS-CVD, the capacitor upper contact 17 and the plate line contact 19 were opened by etching.

Next, the PZT capacitor 30 is formed by etching.
Annealing was performed at a temperature of 400 ° C. for 10 minutes in a nitrogen atmosphere in order to recover the deterioration.

As the third metal wiring 18, WSi, Ti
N, AlCu, and TiN were formed in this order by sputtering, and then processed by etching.

On this, a passivation film (not shown)
Silicon oxide film and SiO by plasma CVD
After forming the N film, a polyimide film was further formed.
Thereafter, the wiring pad portions were opened, and the electrical characteristics were evaluated. The results are shown below.

When 5000 PZT capacitors of 1 μm square were connected in parallel and their characteristics were measured, a value of 10 μC / cm ² or more was obtained as a difference between inversion and non-inversion charges, showing good ferroelectric characteristics. Was. The fatigue characteristics and retention characteristics were also good.

When the characteristics of a transistor having a gate length of 0.26 μm were evaluated, the variation of the threshold value Vt was 10% or less over the entire surface of both the p-type and n-type transistors, which was good.

Further, the resistance between the lower electrode 13 connected through the 0.4 μm square capacitance lower contact 12 and the second metal wiring 10 was measured by a contact chain, and the resistance per contact was found to be: 10 Ω or less, which was good.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 9 is a cross-sectional view of a memory cell of a ferroelectric memory or a DRAM according to the present embodiment, and FIG. 10 is a cross-sectional view of a portion where a plate line is connected to a second metal wiring at an end thereof.

In the present embodiment, unlike the first embodiment, the upper electrode 15 of the ceramic thin film capacitor 30 has a smaller area than the ceramic thin film 14 and the lower electrode 13. With the ceramic thin film capacitor 30 having such a structure, the ceramic thin film 14 and the lower electrode 1 are formed.
3, the upper electrode 15 and the lower electrode 1
3 can be prevented from short-circuiting at the capacitor side wall.

The third metal wiring 18 is connected to the lower electrode 13
And the second metal wiring 1 via the capacitor lower contact 12
0 is connected. By adopting such a structure,
The capacitor upper contact 17 and the plate line contact 19 have substantially the same depth, and it is easy to form them simultaneously. Further, since the same type of conductor can be used for the upper electrode 15 and the lower electrode 13 to which the third metal wiring 18 is connected, there is an advantage that the contact resistance for each of them can be easily controlled.

Next, a method of manufacturing the memory according to the present embodiment will be described.

The process up to the formation of the upper electrode 15 on the ceramic thin film 14 is exactly the same as in the first embodiment. After that, the upper electrode 15 is processed by etching. At this time, the plate line contact 1 shown in FIG.
In region 9, the upper electrode is removed by etching. Thereafter, a fourth interlayer insulating film 16 is formed, and further, a capacitor upper contact 17 and a plate line contact 19 are opened, and then a third metal wiring 18 is formed.

(Third Embodiment) Next, FIGS.
4, a ferroelectric memory or a DRAM according to the third embodiment of the present invention will be described. FIG. 11 is a plan view showing a memory cell of a ferroelectric memory or a DRAM according to the present embodiment. The structure below the first metal wiring is the same as the structure shown in FIG. FIG. 12 is a sectional view taken along line BB of FIG. FIG. 13 and FIG. 14 are cross-sectional views of a portion connecting the plate line to the second metal wiring at the end.

The third embodiment is similar to the first embodiment in that a ceramic thin film capacitor is electrically connected to a diffusion layer by a plug structure in which a metal wiring and a via are connected. The structure of the thin film capacitor and its manufacturing method are different from those of the first embodiment.

The ceramic thin film capacitor 3 in this embodiment
Reference numeral 0 denotes a plurality of lower electrodes 13 formed at intervals on the third interlayer insulating film 11 as shown in FIG. 12, and a ceramic thin film covering the entire surface of both the third interlayer insulating film 11 and the lower electrode 13 14 and the upper electrode 1 formed on the ceramic thin film 14 so as to cover at least a part of the lower electrode 13.
It consists of five. The upper electrode 15 also serves as the plate line 34 in FIG.

Since the ceramic thin-film capacitor 30 has such a structure, it is not necessary to form a contact with the plate line 34 on the ceramic thin-film capacitor 30, so that the structure of the ceramic thin-film capacitor is simplified and the device can be miniaturized. Can be easily performed.

By forming the lower electrode 13 in a three-dimensional shape such as a rectangular parallelepiped or a cylinder, the effective area of the ceramic thin film capacitor 30 can be increased without increasing the cell area.

Next, a method for manufacturing a memory according to the present embodiment will be described.

The manufacturing method for the structure other than the ceramic thin film capacitor 30 is the same as the method described in the first embodiment. Therefore, only the method of manufacturing the ceramic thin film capacitor 30 will be described below.

After forming the lower capacitor contact 12,
The lower electrode 13 is formed on the third interlayer insulating film 11 by a sputtering method or the like, and is processed by etching. In order to obtain a good ceramic thin film 14, the processed lower electrode 13
It is necessary to keep the surface of the substrate clean so that no etching residue remains. Therefore, it is desirable to wash the surface of the lower electrode 13 with an organic solvent or the like after the etching. On the lower electrode 13, a ceramic thin film 14, such as PZT or BST, is formed by a CVD method or the like.

As shown in FIG. 13, when the upper electrode 15 functioning as the plate line 34 is connected to the second metal wiring 10, the plate line contact 19 is opened after the formation of the ceramic thin film 14.

In FIG. 13, the plate line contact 19 penetrates through the ceramic thin film 14 and reaches the inside of the third interlayer insulating film 11, but the ceramic thin film 14
Etching may not be performed under the same conditions as the interlayer insulating film 11. In such a case, it is desirable to remove the ceramic thin film 14 around the plate line contact 19 by etching in advance.

Next, after the upper electrode 15 is formed by sputtering or the like, it is processed by etching to form the ceramic thin film capacitor 30 and the plate line 34. A passivation film (not shown) is formed thereon.

As shown in FIG. 14, the upper electrode 15 can be connected to the second metal wiring 10 via the lower electrode 13. In this case, after the ceramic thin film 14 is formed, the plate line contact 19 is opened, the upper electrode 15 is formed thereon, and then processed by etching.

In both of the above two methods, the ceramic thin film 14 needs to be etched before the upper electrode 15 is formed. However, particularly in the case of a ferroelectric memory, the interface between the electrode and the ferroelectric film greatly affects the electrical characteristics of the capacitor. Therefore, as a method of removing the resist after etching the ceramic thin film 14,
A method of peeling with an organic solvent instead of ashing is preferable because it does not damage the ceramic thin film 14.

Further, in order to easily remove the resist, it is preferable that the plate line contact 19 is also opened by wet etching.

[0202] Instead of such a method, as in the first embodiment, the upper electrode 15 via the third metal interconnection 18 is provided.
Can be connected to the second metal wiring 10.

In this embodiment, since the ceramic thin film 14 is formed after the lower electrode 13 is processed, the ceramic thin film 14 and the third interlayer insulating film 11 thereunder react with each other, or the elements constituting the ceramic thin film 14 Undesirable effects such as diffusion into the third interlayer insulating film 11 may occur. In such a case, it is preferable to provide a diffusion barrier film (not shown) on the third interlayer insulating film 11. As the diffusion barrier film, an insulating metal oxide such as TaO ₂ , TiO ₂ , or ZrO ₂ is preferable because of good adhesion to the ceramic thin film 14.

In this embodiment, the upper electrode 1
5 is used as the plate line 34, the upper electrode 15
Depending on the material, the resistance of the plate wire 34 may increase. In particular, in a ferroelectric memory, it is common to drive a plate line for writing / reading of a memory cell, so that the plate line 34 needs to have a sufficiently low resistance. In such a case, FIG.
As shown in FIG. 15B, the plate backing wiring 23 (not shown in FIG. 15B since it is directly below the plate line 34) may be used. Plate-backed wiring 23
Since the plate line 34 can be formed of a low-resistance metal, the resistance of the plate line 34 can be sufficiently reduced.

Next, a specific example in which the present embodiment is applied to a ferroelectric memory will be described with reference to FIG.

The manufacturing process prior to the formation of the ferroelectric capacitor 30 is the same as that in the example of the first embodiment.

A PZT capacitor was manufactured on the third interlayer insulating film 11 by the following method.

First, as the lower electrode 13, a thickness of 50 nm
Of TiN, 50 nm of Pt, and 50 nm of Ir were formed in this order by sputtering. After a resist was applied thereon, patterning was performed, and the lower electrode 13 was etched using Ar and Cl ₂ as reaction gases. Thereafter, the resist was removed by ashing, and further, a cleaning treatment was performed with a mixed solution of dimethyl sulfoxide and water.

On top of this, a 200 nm thick PZT thin film 1
4 was formed in the same manner as in the example of the first embodiment. However, the deposition time of PZT was 1200 seconds.

Next, after applying and patterning a resist on the PZT thin film 14, the PZT film 14 is wet-etched with hydrofluoric nitric acid to form a plate line contact 19.
Was formed.

Thereafter, the resist was stripped off using an organic solvent, and the resist was removed at a temperature of 400 ° C. in an atmosphere of 100% oxygen.
The annealing was performed for minutes.

Next, the upper electrode 15 is formed on the PZT film 14.
50 nm thick IrO ₂ and 100 nm thick I
r was formed in this order by a sputtering method.

Thereafter, 40% oxygen atmosphere is used.
Anneal at a temperature of 0 ° C. for 10 minutes to obtain a PZT capacity of 3
0 was set.

As the fourth interlayer insulating film 16, a silicon oxide film was formed by O ₃ TEOS-CVD. An SiON film was formed thereon by plasma CVD as a passivation film (not shown), and then a polyimide film was further formed. Finally, the wiring pad portion was opened.

By the above method, a cell array in which about 16,000 memory cells shown in FIG. 3 were integrated, and a ferroelectric memory including a sense amplifier, a decoder, and the like were manufactured. It has been confirmed that this ferroelectric memory operates at a power supply voltage of 2.5 V and a cycle time of 100 nsec or less.

(Fourth Embodiment) Next, a ferroelectric memory or a DRAM according to a fourth embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. FIG. 15A is a plan view of the memory cell until after the second metal wiring is formed, and FIG. 15B is a plan view omitting devices formed before the first metal wiring 7 other than the diffusion layer 4. It is. FIG.
FIG. 16 is a sectional view taken along line CC in FIG.

In this embodiment, the ceramic thin film capacitor 30
The structure of the metal wiring and the via in the plug that connects to the diffusion layer 4 is different from that of the first embodiment. That is,
In the first embodiment, the capacitor lower contact 12 is formed immediately above the via 9. However, in the present embodiment, as shown in FIG. They are arranged at regular intervals in the direction. That is, the capacitor lower contact 12 is not formed immediately above the via 9.

Depending on the process of forming the vias 9 and the second metal wirings 10, dents and the like may occur in the second metal wirings 10 on the vias 9. The capacitor lower contact 1 is formed on the uneven second metal wiring 10 having the dent.
If the second and second vias 20 are formed, good electrical connection may not be obtained. For this reason, in such a case, it is desirable to form the capacitor lower contact 12 and the like at a position separated from the via 9 by a certain distance, not directly above the via 9 as in the present embodiment.

As shown in FIG. 16, the lower capacitor contact 12 is not located at the center of the ceramic thin film capacitor 30. Further, the capacitor upper contact 17 connecting the ceramic thin film capacitor 30 and the third metal wiring 18 is not disposed immediately above the capacitor lower contact 12. By arranging the capacitor lower contact 12 and the capacitor upper contact 17 in this way, even if a dent or the like occurs on the capacitor lower contact 12, the characteristics of the ceramic thin film capacitor 30 are not adversely affected. Further, the electrical connection between the third metal wiring 18 and the upper electrode 15 is not adversely affected. Also, the cell area is not increased.

The memory according to the present embodiment can be manufactured by the same method as the memory according to the first embodiment.

(Fifth Embodiment) Next, a ferroelectric memory or a DRAM according to a fifth embodiment of the present invention will be described with reference to FIG.
18 and FIG. FIG. 17 is a plan view showing a memory cell of the ferroelectric memory or the DRAM according to the present embodiment, and shows a structure below the second contact 21. The structure above the second contact 21 is the same as the structure shown in FIG. FIG. 18 is a cross-sectional view taken along line DD of FIG.

In the present embodiment, in the plug for connecting the ceramic thin film capacitor 30 and the diffusion layer 4, the ceramic thin film capacitor 30 and the first metal wiring 7 are not connected.
The second metal wiring 10 and the diffusion layer 4 are directly connected via the second contact 21.

In the first embodiment, since the first metal wiring 7 is used for both the capacitor plug connecting the ceramic thin film capacitor 30 and the diffusion layer 4 and the bit line, the capacitor plug and the bit line are not connected to each other. It is necessary that one metal wiring 7 is separated by an interval that can be processed by etching. On the other hand, in the present embodiment, the first metal wiring 7
Is used only as the bit line 35, the capacitor plug and the bit line do not need to be separated from each other at the above-described intervals, and therefore, the cell area can be reduced.

Next, a method for manufacturing a memory according to the present embodiment will be described.

First, as in the first embodiment, the first metal wiring 7 and the second interlayer insulating film 8 are formed. However,
No contact for connecting the capacitor is formed. next,
The second contact 21 is opened by etching. Thereafter, a barrier metal such as Ti or TiN is formed.
Since the contact 21 has a particularly large aspect ratio,
It is desirable to form a film by a film forming method with good embedding property such as collimator sputtering or CVD method.

Next, a tungsten plug is formed in the same manner as when the contact 6 is formed. Second contact 2
Vias for the first and other multi-layer metal wirings can be formed simultaneously. The second metal wiring 10 is formed on the second contact 21 thus formed. The subsequent steps are the same as in the first embodiment.

(Sixth Embodiment) Next, a ferroelectric memory or a DRAM according to a sixth embodiment of the present invention will be described with reference to FIG.

The memory cell according to the present embodiment is similar to the fifth embodiment in that the plug connecting the ceramic thin film capacitor 30 and the diffusion layer 4 does not connect the ceramic thin film capacitor 30 and the first metal wiring 7. FIG. 19
2, the second metal wiring 10 is connected to the diffusion layer 4 via the via 9 and the contact 6.

In this embodiment, as in the fifth embodiment, the first metal wiring 7 is connected to the bit line 3 in the cell.
Since only 5 is used, the cell area can be reduced. In addition, unlike the fifth embodiment, the second contact 21 is not used, so that the manufacturing process can be simplified.

Next, a method for manufacturing a memory according to the present embodiment will be described.

As in the first embodiment, the first interlayer insulating film 5
Form up to. Next, the first metal wiring 7 is formed, but the first metal wiring 7 of the capacitor plug is not formed (that is, the first metal wiring 7 is not formed on the diffusion layer 4 as shown in FIG. 19).

Next, after forming the second interlayer insulating film 8 on the first interlayer insulating film 5 and the first metal wiring 7, the via 9 is opened by etching.

In a multi-layer metal wiring other than a memory cell, the second interlayer insulating film 8 is etched only up to the first metal wiring 7, but in a memory cell, it is over-etched up to the first interlayer insulating film 5.

Next, a tungsten plug is formed in the same manner as when the contact 6 is formed. The second metal wiring 10 is formed on the via 9 thus formed. The subsequent steps are the same as in the first embodiment.

(Seventh Embodiment) Next, a ferroelectric memory or a DRAM according to a seventh embodiment of the present invention will be described with reference to FIG.
23 will be described with reference to FIG. FIG. 20 is a plan view showing a memory cell of the ferroelectric memory or the DRAM in the present embodiment, and shows a structure below the first metal wiring. FIG. 21 is a sectional view taken along line EE in FIG.

In the present embodiment, the silicide wiring 22 is used as the bit line 35, and the first metal wiring 7 is used only in the plug connecting the ceramic thin film capacitor 30 and the diffusion layer 4. Therefore, as in the fifth embodiment, the cell area can be reduced.

In this embodiment, the first metal wiring 7
And the second metal wiring 10 are used as a backing wiring for the word line 33.

FIG. 22 is a circuit diagram showing the connection between the backing wiring and the word line 33. FIG. 23 is a plan view of the connection between the first metal wiring 7 and the word line 33.

The word line 33 has high resistance because it is mainly made of polysilicon. Therefore, it is common practice to lower the resistance of the word line 33 by backing a low-resistance metal wiring to the word line 33. Such a backing wiring usually uses a one-layer metal wiring. On the other hand, in the present embodiment, the word lines 33 are backed without increasing the cell area by using two layers of metal wirings as backing wirings.

Further, as shown in FIG. 22, the array connected to the word line 33 is divided into two, and the metal wiring to be lined is divided into an array having a symmetrical structure to reduce noise.

Next, a method for manufacturing a memory according to the present embodiment will be described.

First, as in the first embodiment, a transistor section is formed on a silicon substrate 1. After forming an interlayer insulating film (not shown), a contact 6 is opened,
The silicide wiring 22 is formed of WSi or the like. A first interlayer insulating film 5 is formed on this interlayer insulating film, and then a second contact 21 is opened on the diffusion layer 4. Subsequent processes are the same as in the first embodiment.

[0243]

As described above, according to the present invention,
The ceramic thin film capacitor is connected to the diffusion layer via a plug having a structure in which a via and a metal wiring formed simultaneously with the formation of the multilayer metal wiring are stacked. Therefore, a semiconductor device using a ceramic thin film capacitor that can easily form a multilayer metal wiring based on such a basic structure and does not cause deterioration of the capacitor element can be provided.

The reason is that since the ceramic thin film capacitor is formed after the formation of the multilayer metal wiring, the height difference due to the ceramic thin film capacitance does not hinder the formation of the multilayer metal wiring.

Further, since there is no need to form a contact between the metal wiring and the substrate or to form a via with a tungsten plug after the formation of the ceramic thin film capacitor, there is no deterioration of the ceramic thin film capacitance.

By performing hydrogen annealing after the formation of the multilayer metal wiring and before the formation of the ceramic thin film capacitor, the deterioration of the transistor can be reduced.

Further, according to the present invention, there is provided a semiconductor device in which a memory using a ceramic thin film capacitor and a large-scale logic circuit are mixed on the same chip at low cost. This is because the ceramic thin film capacitor can be formed without any change in the process device of the logic circuit portion, and the existing design parameters can be used.

[Brief description of the drawings]

FIGS. 1A and 1B are plan views showing a memory cell according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a circuit diagram of the memory according to the first embodiment shown in FIG. 1;

FIG. 4 is a sectional view showing the method for manufacturing the memory according to the first embodiment of the present invention.

FIG. 5 is a sectional view showing the method of manufacturing the memory according to the first embodiment of the present invention.

FIG. 6 is a sectional view showing the method of manufacturing the memory according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating an example of a structure of a terminal portion of a plate line in the memory according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view showing another example of the structure of the terminal portion of the plate line in the memory according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view of a memory according to a second embodiment of the present invention.

FIG. 10 is a cross-sectional view illustrating an example of a structure of a terminal portion of a plate line in a memory according to a second embodiment of the present invention.

FIG. 11 is a plan view showing a memory according to a third embodiment of the present invention.

FIG. 12 is a sectional view taken along line BB in FIG. 11;

FIG. 13 is a cross-sectional view illustrating an example of a structure of a terminal portion of a plate line in a memory according to a third embodiment of the present invention.

FIG. 14 is a cross-sectional view showing another example of the structure of the terminal portion of the plate line in the memory according to the third embodiment of the present invention.

FIGS. 15A and 15B are plan views showing a memory according to a fourth embodiment of the present invention.

FIG. 16 is a cross-sectional view taken along line CC of FIG.

FIG. 17 is a plan view showing a memory according to a fifth embodiment of the present invention.

18 is a sectional view taken along line DD in FIG.

FIG. 19 is a sectional view showing a memory according to a sixth embodiment of the present invention.

FIG. 20 is a plan view showing a memory according to a seventh embodiment of the present invention.

21 is a sectional view taken along line EE in FIG. 20.

FIG. 22 is a circuit block diagram of a memory according to a seventh embodiment of the present invention.

FIG. 23 is a plan view showing a connection portion between a word line of a memory according to a seventh embodiment of the present invention and a first metal wiring serving as a word line backing wiring.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Silicon oxide film 3 Gate 4 Diffusion layer 5 1st interlayer insulation film 6 Contact 7 1st metal wiring 8 2nd interlayer insulation film 9 Via 10 2nd metal wiring 11 3rd interlayer insulation film 12 Capacitance lower contact 13 Lower part Electrode 14 Ceramic thin film 15 Upper electrode 16 Fourth interlayer insulating film 17 Capacitor upper contact 18 Third metal wiring 19 Plate line contact 20 Second via 21 Second contact 22 Silicide wiring 30 Ceramic thin film capacitor 31 Selection transistor 32 Memory cell 33 Word line 34 Plate line 35 Bit line

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/8247 29/788 29/792

Claims (43)

[Claims] 1. A semiconductor device having a substrate, at least one layer of metal wiring, and a ceramic thin film capacitor, wherein the ceramic thin film capacitor is formed by stacking a lower electrode, a ceramic thin film, and an upper electrode in this order. A semiconductor thin film and an upper electrode are formed above the metal wiring. 2. The method according to claim 1, wherein at least one of the electrodes forming the ceramic thin film capacitor is connected to the substrate via a wiring, and the wiring includes at least one layer of metal wiring. Item 2. The semiconductor device according to item 1. 3. The ceramic thin film capacitor is connected to the substrate via a wiring, wherein the wiring is a contact connecting a metal wiring to the substrate, a metal wiring, and one of the metal wiring and the ceramic thin film capacitor. A structure having a structure in which vias connecting two electrodes are stacked, or a structure in which at least one metal wiring and a via are stacked between a metal wiring and one electrode of the ceramic thin film capacitor. 2. The semiconductor device according to 1. 4. At least one electrode of the ceramic thin film capacitor is connected to the substrate via a wiring, wherein the wiring is at least one layer of metal wiring and a contact formed later than the metal wiring. 4. The semiconductor device according to claim 1, wherein the semiconductor device has a structure including: a contact connecting one of the electrodes of the ceramic thin film capacitor or the metal wiring to the substrate. 5. . 5. The method according to claim 1, wherein at least one electrode of the ceramic thin film capacitor is connected to the substrate via a wiring, and the wiring has a structure in which at least one contact or via is directly laminated. 5. The semiconductor device according to any one of Items 1 to 4. 6. The semiconductor device according to claim 1, wherein at least one layer of metal wiring is further formed above the ceramic thin film capacitor. 7. The method according to claim 1, wherein the metal wiring formed above the ceramic thin film capacitor is used only as a plate line of a memory having at least a memory cell including the ceramic thin film capacitor. The semiconductor device according to claim 1. 8. The ceramic thin film capacitor according to claim 1, wherein a via or a contact connecting one of the electrodes of the ceramic thin film capacitor to the metal wiring or the substrate is eccentrically arranged from the center of the ceramic thin film capacitor. 8. The semiconductor device according to claim 7. 9. The method according to claim 1, wherein a contact formed on an upper portion of said ceramic thin film capacitor is eccentrically arranged with respect to a contact formed on a lower portion of said ceramic thin film capacitor. The semiconductor device according to claim 1. 10. The semiconductor device according to claim 1, wherein the upper electrode forming the ceramic thin film capacitor is stacked with a smaller area than the lower electrode. 11. The ceramic thin film capacitor includes: a plurality of lower electrodes formed at intervals on an interlayer insulating film; a ceramic thin film covering an entire surface of both the interlayer insulating film and the lower electrode; 10. The semiconductor device according to claim 1, comprising: an upper electrode formed on the ceramic thin film so as to cover at least a part of the semiconductor device. 11. 12. The semiconductor device according to claim 1, wherein a diffusion barrier film is formed between said ceramic thin film capacitor and an interlayer insulating film therebelow. 13. A contact for connecting a lower electrode of said ceramic thin film capacitor to a metal wiring located below said ceramic thin film capacitor, and a via formed below said metal wiring, via said metal wiring. And being arranged at an interval.
3. The semiconductor device according to claim 2. 14. At least two layers of metal wiring are formed between the ceramic thin film capacitor and the substrate, and the upper metal wiring is directly connected to the substrate via a contact. Claims 1 to 13
The semiconductor device according to claim 1. 15. The semiconductor device according to claim 1, wherein a plate line backing wiring is formed above the ceramic thin film capacitor. 16. The semiconductor device according to claim 1, wherein the backing wiring of the word line is formed by a metal wiring below the ceramic thin film capacitor. 17. The semiconductor device according to claim 16, wherein the backing wiring of the adjacent word line is formed by at least two layers of metal wiring. 18. The memory cell array according to claim 17, wherein the two-layer metal wiring forming the word line backing wiring crosses at least one position in the memory cell array.
3. The semiconductor device according to claim 1. 19. A metal wiring is formed above the ceramic thin film capacitor via an interlayer insulating film, and the metal wiring is formed at an end thereof below the interlayer insulating film and the ceramic thin film capacitor. 19. The semiconductor device according to claim 1, wherein the substrate is connected to a metal wiring or a substrate formed below the ceramic thin film capacitor via a concave portion formed over both of the interlayer insulating films. 13. The semiconductor device according to claim 1. 20. A metal wiring is formed above the ceramic thin film capacitor via an interlayer insulating film, and the metal wiring is formed at a terminal thereof through a recess formed in the interlayer insulating film. 19. The semiconductor device according to claim 1, wherein the substrate is connected to a via formed below the ceramic thin film capacitor, and is connected to the metal wiring or the substrate formed below the ceramic thin film capacitor via the via. The semiconductor device according to claim 1. 21. A metal wiring is formed above the ceramic thin film capacitor via an interlayer insulating film, and the metal wiring has both ends of the metal wiring at both ends of the interlayer insulating film and the ceramic thin film of the ceramic thin film capacitor. Is connected to a lower electrode of the ceramic thin film capacitor via a recess formed over the ceramic thin film capacitor, is connected to a via formed below the ceramic thin film capacitor via the lower electrode, and is connected to the ceramic via the via. The semiconductor device according to claim 1, wherein the semiconductor device is connected to a metal wiring formed below the thin film capacitor or the substrate. 22. An upper electrode of the ceramic thin film capacitor, at a terminal thereof, via a concave portion formed over both the ceramic thin film of the ceramic thin film capacitor and an interlayer insulating film formed below the ceramic thin film capacitor. 19. The semiconductor device according to claim 1, wherein the semiconductor device is connected to a metal wiring formed below the ceramic thin film capacitor or the substrate. 23. An upper electrode of the ceramic thin film capacitor is connected at its end to a lower electrode of the ceramic thin film capacitor through a concave portion formed in the ceramic thin film of the ceramic thin film capacitor, and is connected to the lower electrode through the lower electrode. The semiconductor device is connected to a via formed below the ceramic thin film capacitor, and is connected to a metal wiring or the substrate formed below the ceramic thin film capacitor via the via. 19. The semiconductor device according to any one of 1 to 18. 24. The method according to claim 1, wherein the metal wiring is mainly composed of aluminum or copper.
24. The semiconductor device according to claim 23. 25. The method according to claim 1, wherein a via or a contact for connecting one of the electrodes of the ceramic thin film capacitor to the metal wiring or the substrate is mainly made of tungsten. A semiconductor device according to claim 1. 26. The semiconductor device according to claim 1, wherein the lower electrode of the ceramic thin film capacitor contains a conductive nitride. 27. The semiconductor device according to claim 26, wherein said conductive nitride is titanium nitride, tantalum nitride or tungsten nitride. 28. The semiconductor device according to claim 26, wherein the lower electrode of the ceramic thin film capacitor is formed by laminating a layer containing the conductive nitride and a noble metal layer. 29. The noble metal layer is formed of platinum, iridium,
29. The semiconductor device according to claim 28, wherein the device is made of ruthenium, an alloy thereof, or a laminate thereof. 30. A method of manufacturing a semiconductor device, comprising: a first step of forming at least one layer of metal wiring; and a second step of forming a ceramic thin film capacitor after the first step. 31. A first step of forming at least one layer of metal wiring, a second step of performing annealing in an atmosphere containing hydrogen, and a third step of forming a ceramic thin film capacitor after the second step. And a method for manufacturing a semiconductor device, comprising: 32. The method according to claim 31, wherein the annealing in the second step is performed at a temperature in a range of 300 degrees Celsius to 500 degrees Celsius. 33. A first step of forming at least one layer of metal wiring, and a second step of forming a metal wiring as a part of a wiring connecting at least one electrode of the ceramic thin film capacitor and the substrate. A method for manufacturing a semiconductor device, comprising: 34. The ceramic thin film capacitor, comprising: a first step of forming a lower electrode; a second step of forming a ceramic thin film on the lower electrode; and a third step of forming an upper electrode on the ceramic thin film. 31. A process of etching the lower electrode, the ceramic thin film and the upper electrode, and a fourth process of etching the upper electrode.
34. The method of manufacturing a semiconductor device according to claim 33. 35. The ceramic thin film capacitor, comprising: a first step of forming a lower electrode and etching the lower electrode; a second step of forming a ceramic thin film on the lower electrode; 31. A third step of forming an electrode and etching the same, wherein the third step is performed.
34. The method of manufacturing a semiconductor device according to claim 33. 36. The method according to claim 34, wherein the ceramic thin film is formed at a temperature of 500 degrees Celsius or less by chemical vapor deposition. 37. The method according to claim 30, further comprising forming a diffusion barrier film between the lower electrode and an interlayer insulating film below the lower electrode. Of manufacturing a semiconductor device. 38. The method of manufacturing a semiconductor device according to claim 30, further comprising a step of further forming at least one layer of metal wiring over the ceramic thin film capacitor. 39. The method according to claim 38, wherein the metal wiring formed above the ceramic thin film capacitor is formed in an atmosphere having a weak reducing property. 40. The method according to claim 40, further comprising: forming an interlayer insulating film on the ceramic thin film capacitor; and forming a first metal wiring connected to the ceramic thin film capacitor via the interlayer insulating film. At the end, the first metal wiring extends over both the interlayer insulating film and the interlayer insulating film formed below the ceramic thin film capacitor to a second metal wiring formed below the ceramic thin film capacitor. The method of manufacturing a semiconductor device according to any one of claims 30 to 39, wherein the semiconductor device is formed in the concave portion after forming the concave portion. 41. The method according to claim 41, further comprising: forming an interlayer insulating film on the ceramic thin film capacitor; and forming a first metal wiring connected to the ceramic thin film capacitor via the interlayer insulating film. The first metal wiring is formed in the recess after forming a recess in the interlayer insulating film at the end, and the first metal wiring is formed below the ceramic thin film. 40. The method of manufacturing a semiconductor device according to claim 30, wherein the method is connected to a metal wiring. 42. An upper electrode of the ceramic thin film capacitor is formed below the ceramic thin film capacitor at both ends thereof over both the ceramic film and an interlayer insulating film formed below the ceramic thin film capacitor. 4. The semiconductor device according to claim 3, wherein the recess is formed in the recess after the recess leading to the second metal wiring is formed.
The method for manufacturing a semiconductor device according to any one of Items 0 to 39. 43. An upper electrode of the ceramic thin film capacitor is formed in the concave portion after forming a concave portion in the ceramic film at an end thereof, and the upper electrode is
31. The semiconductor device according to claim 30, wherein the lower electrode is connected to a second metal wiring formed below the ceramic thin film capacitor via a lower electrode of the ceramic thin film capacitor and a via formed below the lower electrode. 40. The method of manufacturing a semiconductor device according to claim 39.