JP2000068471A - Manufacture of semiconductor integrated circuit device and the semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of electrical connection between the lower electrode of a capacity element and the connection part of a lower layer thereof. SOLUTION: Conductor films 18a, 19a for lower electrode formation are connected through a conductor film 17a for a barrier on a plug 13 so as not to bring a capacity insulation film 20 and the plug 13 into direct contact with each other. Since such a structure in which a connection part does not come into contact with the capacity insulation film in a capacity element for information storage can be thereby realized and the problem of oxidation of a connection part thereof can be prevented, it is possible to improve the reliability of electrical connection between the lower electrode of the capacity element and the connection part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device and a technology of the semiconductor integrated circuit device, and more particularly to a method of manufacturing a semiconductor integrated circuit device having a capacitance element for storing information and to a semiconductor integrated circuit device. And effective technology.

[0002]

2. Description of the Related Art A capacitive element for information storage studied by the present inventors has a three-dimensional capacitor structure such as a so-called stacked capacitor in which an upper electrode is stacked on a surface of a lower electrode via a capacitive insulating film. And the lower electrode is
It is electrically connected to the capacitive element selecting element through a lower connecting portion. The connection portion is formed by embedding a conductive material in a connection hole formed in the thickness direction of the insulating film. In forming the pattern of the lower electrode, the lower electrode is usually formed by adjusting the relative planar position with the connection portion.

A semiconductor integrated circuit device having a capacitor for storing information is disclosed in, for example, Japanese Patent Application Laid-Open No. 6-2681.
No. 75, which has a DRAM (Dynamic Random Access Mem
mory) and its manufacturing method are disclosed.

[0004]

However, the present inventors have found that a semiconductor integrated circuit device having a capacitor for storing information has the following problems.

That is, when the lower electrode of the capacitive element is patterned, the lower electrode of the capacitive element and the lower electrode of the capacitive element are displaced because the relative planar position of the lower electrode and the connecting portion of the lower layer are shifted. This is a problem in that conduction failure occurs between the connection portion and the lower layer.

The lower electrode of the capacitive element is usually formed in a pattern in accordance with the connecting portion of the lower layer. However, since miniaturization progresses and a sufficient margin cannot be secured, the relative flatness between the lower electrode and the connecting portion is reduced. It is inevitable that a gap occurs in the connection part as a result of the displacement. Thereby, a part of the connection portion is exposed. However, if an oxide film is used as the capacitive insulating film of the capacitive element in the state where such opening has occurred, the capacitive insulating film comes into direct contact with the connection portion, and the contact between the lower electrode and the connection portion is prevented. The interface is oxidized. As a result, poor conduction between the lower electrode and the connection portion occurs.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a technique capable of improving the reliability of electrical connection between a lower electrode of a capacitive element and a connection portion thereunder.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, a method of manufacturing a semiconductor integrated circuit device according to the present invention is directed to a method of manufacturing a semiconductor integrated circuit device having a capacitor for storing information on a semiconductor substrate.
(A) depositing a first insulating film on the semiconductor substrate; and (b) forming a connection hole in the first insulating film.
(C) a step of forming a connection portion by embedding a conductive film in the connection hole; (d) a step of applying a second insulation film on the first insulation film after the formation step of the connection portion; A) a step of applying a third insulating film on the second insulating film; and (f) a step of drilling holes in the third insulating film and the second insulating film so that a part of the connection portion is exposed. (G) a step of embedding a first conductive film in the hole, and (h) a step of removing the third insulating film around the first conductive film and projecting an upper portion of the first conductive film. (I) attaching a capacitive insulating film of the information storage capacitor to the protruding surface of the first conductive film after the step of removing the third insulating film; and (j) surface of the capacitive insulating film. And forming a second conductor film for forming an upper electrode in the information storage capacitor.

The following is a brief description of an outline of the invention disclosed in the present application other than the above.

That is, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, the capacitor insulating film is formed of Ti ₂ O ₅ , (Pb,
Zr) TiO ₃ or (Ba, Sr) TiO ₃ .

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the step of embedding the first conductive film may include: (a) a step of applying the first conductive film in the third insulating film and the hole;
(B) removing the first conductive film on the third insulating film and leaving the first conductive film only in the hole.

Further, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, the first conductive film includes a conductive film for a barrier and a conductive film for forming a lower electrode formed thereon.

Further, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, the first conductive film includes a conductive film for a barrier and a conductive film for forming a lower electrode formed thereon. A step of: (a) depositing the barrier conductive film in the third insulating film and the hole;
(B) removing the barrier conductor film on the third insulating film;
Leaving a conductor film for barrier only in the hole, (c)
A step of partially removing an upper portion of the barrier conductor film in the hole and retreating an upper surface of the barrier conductor film from an upper surface height of the third insulating film; and (d) the barrier conductor film. After the retreating step, a step of depositing the conductive film for forming the lower electrode on the third insulating film and in the upper part of the hole,
(E) removing the conductive film for forming the lower electrode on the third insulating film and forming a conductive film for forming the lower electrode on the conductive film for barrier in the hole. is there.

Further, in the method for manufacturing a semiconductor integrated circuit device according to the present invention, the first conductive film includes a conductive film for a barrier and a conductive film for forming a lower electrode formed thereon. A step of: (a) depositing the barrier conductive film in the third insulating film and the hole;
(B) removing the barrier conductor film on the third insulating film;
Leaving a conductor film for barrier only in the hole, (c)
A step of partially removing an upper portion of the barrier conductor film in the hole and retreating an upper surface of the barrier conductor film from an upper surface height of the third insulating film; and (d) the barrier conductor film. After the retreating step, a step of depositing the conductive film for forming the lower electrode on the third insulating film and in the upper part of the hole,
(E) removing the conductive film for forming the lower electrode on the third insulating film, and forming a conductive film for forming the lower electrode on the conductive film for barrier in the hole; After forming a sidewall conductor film for forming a lower electrode in the information storage capacitor on the projecting side surface of the first conductor film,
Applying a capacitive insulating film of the information storage capacitor to the protruding upper surface of the conductive film and the surface of the side wall conductive film.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the step of forming the hole, a first hard mask film may be formed on the third insulating film, and then the first hard mask film may be formed in the first hard mask film. Forming an opening for forming
After depositing a second hard mask film on the first hard mask film after the formation of the opening and in the opening, the second hard mask film is etched back to form a side surface of the opening from the second hard mask film. Forming a side wall film,
Drilling the hole using the first hard mask film and the side wall film as an etching mask.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the barrier conductive film may be formed of TiN, (Ti, A
1) N, TaSiN, TiSiN or WN.

Further, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, the conductive film for forming the lower electrode may be formed of W, Pt, R
u, Ir, RuO ₂ , IrO ₃ , RuO ₂ / Ru or IrO ₂ / Ir.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. , And the repeated explanation is omitted).

(Embodiment 1) FIGS.
FIG. 2B is a cross-sectional view of a principal part during a manufacturing step of the semiconductor integrated circuit device according to the embodiment of the present invention. 1 to 29 in this specification show a memory cell region, and FIG. 1B is a cross-sectional view of a plane intersecting the cross section of FIG.

In the first embodiment, the technical idea of the present invention is applied to, for example, a dynamic random access memory (DRAM).
y) or a case where the present invention is applied to an FRAM (Ferroelectric RAM; ferroelectric memory). As shown in FIG. 1, a p-well 2 is formed in a memory cell region of a semiconductor substrate 1 made of, for example, p-type single crystal silicon. Although not particularly limited, the p-well 2 common to the memory cell region and a part of the direct peripheral circuit is surrounded by an n-type semiconductor region 3 (only the lower portion is shown in the figure) formed below and on the side thereof. It is electrically separated from the p-type semiconductor substrate 1. Thus, transmission of noise from another circuit on the semiconductor substrate 1 to the p well 2 can be suppressed, and the potential of the p well 2 can be stabilized. The semiconductor substrate 1 has an n-well in addition to the p-well 2. For example, boron (B) or boron difluoride (BF ₂ ) is introduced into the p well 2, and n
For example, phosphorus (P) or arsenic (As) is introduced into the well.

A separation section 4 is formed on the surface of the semiconductor substrate 1. The isolation portion 4 is formed by burying an isolation film 4b such as a silicon oxide film in an isolation groove 4a dug in the thickness direction of the semiconductor substrate 1, and the upper surface thereof is flattened. In the active region of the p well 2 surrounded by the isolation part 4 in the memory cell region, an n channel type MIS • FET Qs for memory cell selection is formed, and the well supply of the p well 2 in the memory cell region is performed. A p ⁺ type semiconductor region 5 is formed in the region. M for memory cell selection
The ISFET Qs has a gate oxide film 6, a gate electrode 7 formed integrally with the word line WL, a source and a drain (n-type semiconductor region 8). Gate oxide film 6
Is made of, for example, a silicon oxide film, and its thickness is, for example, about 7 to 8 nm. Although not particularly limited, after the gate oxide film 6 is formed, the semiconductor substrate 1 is subjected to a heat treatment in a nitrogen oxide (NO) or nitrous oxide (N ₂ O) atmosphere, so that the gate oxide film 6 and the semiconductor substrate 1 are formed. Nitrogen may be segregated at the interface with the substrate (oxynitriding treatment). When the thickness of the gate oxide film 6 is reduced to about 7 nm, a strain generated at the interface between the semiconductor substrate 1 and the semiconductor substrate 1 due to a difference in thermal expansion coefficient becomes apparent, and hot carriers are generated.
Since the nitrogen segregated at the interface with the semiconductor substrate 1 relaxes the distortion, the above-described oxynitriding process is performed with the extremely thin gate oxide film 6.
Reliability can be improved.

The gate electrode 7 (which is a part of the word line WL) is formed by stacking, for example, a low-resistance polycrystalline silicon film doped with phosphorus, a titanium nitride (TiN) film, and a tungsten (W) film in order from the lower layer. It is composed of three layers of conductive films, and has a sheet resistance of 2Ω / □ or less. Note that the titanium nitride film of the gate electrode 7 has a barrier function for preventing tungsten silicide or the like from being formed at the contact interface between the polysilicon film and the tungsten film when the polysilicon film and the tungsten film are brought into direct contact with each other. . The barrier function film is not limited to the titanium nitride film but can be variously changed, and may be, for example, tungsten nitride (WN).

A cap insulating film 9 made of, for example, a silicon nitride film is formed on the gate electrode 7 (word line WL). The surface of the cap insulating film 9, the gate electrode 7
An insulating film 10 made of, for example, a silicon nitride film is formed on the side surface and the main surface of the semiconductor substrate 1 so as to reflect the step of the base. An insulating film (first insulating film) 11 a made of, for example, a silicon oxide film or the like is provided on the main surface of the semiconductor substrate 1 so as to cover the insulating film 10. The upper surface of the insulating film 11a is formed by CMP (Ch
The surface is flattened by an emical mechanical polishing method. A connection hole 12a is formed in the insulating film 11a and the insulating film 10 so that the n-type semiconductor region 8 is exposed, and a plug (connecting portion) 13 made of, for example, n-type polycrystalline silicon is formed therein. Is embedded. Then, the entire surface of the insulating film 11a (including the upper surface of the plug 13).
Is formed with an insulating film (first stopper insulating film) 14a made of, for example, a silicon nitride film. Insulating film 14a
A bit line 15BL and a first-layer wiring 15L are formed on the upper surface of the substrate. Bit line 15BL and first layer wiring 15
L is made of, for example, tungsten or a tungsten alloy. The bit lines 15BL extend so as to intersect with the direction in which the word lines WL extend, and a portion extends at predetermined intervals along the direction in which the word lines WL extend. Connection hole 12b formed in insulating film 14a
Through the plug 13. The first layer wiring 15L is electrically connected to the p ⁺ type semiconductor region 5 in the well power supply region through a connection hole 12c formed in the insulating films 14a and 11a.

In the first embodiment, first, as shown in FIG. 2, on the insulating film 14a on the semiconductor substrate 1,
For example, an insulating film (second insulating film) 11 made of silicon oxide
b is deposited by a CVD method or the like, and the upper surface is
Flatten by a method or the like. Subsequently, an insulating film made of, for example, silicon nitride (an insulating film for the second stopper) is formed on the upper surface.
After depositing 14b by a CVD method or the like,
For example, an insulating film (third insulating film) 11 made of silicon oxide
c is deposited by a CVD method or the like. Thereafter, as shown in FIG. 3, holes 16 are formed in insulating films 11c, 14b, 11b by photolithography and dry etching.
Perforate. The plane dimensions of the hole 16 are smaller than the designed plane dimensions of the lower electrode, and the difference between them is equal to the film thickness of the lower electrode formed later.

In forming the holes 16, an insulating film 14a made of silicon nitride or the like is used as an etching stopper. Thereby, the uniformity of the dry etching amount (depth of the hole 16) for drilling the hole 16 can be ensured, and the hole 1
It is possible to ensure the reliability of the connection between the conductive film embedded in the hole 16 and the plug 13 without causing any problem in the formation of the plug 6. As a modified example, the hole 16 may be formed without providing the insulating film 14a. In this case, the upper portion of the insulating film 11a is slightly etched away when the hole 16 is formed. Thus, the upper portion of the plug 13 projects from the upper surface of the insulating film 11a in the hole 16, so that the contact area and the connection strength between the plug 13 and the conductive film embedded in the hole 16 can be increased. During this dry etching process,
In the etching removal of the insulating films 11b and 11a below the insulating film 14b, an etching process is performed under conditions that increase the etching selectivity between silicon oxide and silicon nitride (hereinafter, referred to as a high selective etching process).
Thus, even if the insulating film 11a is excessively etched, the insulating film 10 made of the lower silicon nitride functions as an etching stopper, so that the lower element and the like are not damaged. In addition, after FIG. 3 of this specification (FIG.
29 (except for FIG. 29), the lower part of the insulating film 11a (the insulating film 11a
(Including the lower part of).

Next, the insulating film 14a at the bottom of the hole 16 is removed by subjecting the semiconductor substrate 1 to an etching process under such conditions that the silicon nitride film is removed.
As shown in FIG. 5, a part of the upper surface of the plug 13 is exposed from the bottom of the hole 16. Subsequently, as shown in FIG. 5, after a conductive film (first conductive film) 17 is deposited on the insulating film 11c and in the hole 16, the upper portion thereof is etched back by a CMP method or the like, so that the hole 16 is formed. A conductive film (first conductive film) 17a is embedded therein. The conductor films 17, 17a
Is a film that constitutes a pillar of a capacitor for storing information and functions as a barrier metal. For example, TiN,
It consists of a single film of (Ti, Al) N, TaSiN, TiSiN, WN, or a laminated film combining these with silicide thereof. The conductor film 17 is formed, for example, by CVD.
It is formed by a method or a PVD method.

Thereafter, the upper portion of the conductor film 17a is removed by, for example, a dry etching process, and is retreated downward as shown in FIG. 6, and then a lower electrode is formed on the upper surface of the insulating film 11c and the upper surface of the conductor film 17a. A first conductive film 18 is deposited. The conductive film 18 is made of, for example, platinum (Pt), ruthenium oxide (RuO ₂ ), ruthenium (Ru), iridium oxide (IrO ₃ ), RuO ₂ and R
u or IrO ₂ and iridium (Ir)
Consisting of a material selected from a first group of tungsten or tungsten or a material selected from a second group of polycrystalline silicon. When the conductive film 18 is made of Pt, for example, CVD, PVD (Physical Vapor D)
eposition) or an electroless plating method. When the conductive film 18 is made of tungsten, it may be formed by, for example, a CVD method or a PVD method. When the conductive film 18 is made of polycrystalline silicon, it may be formed by, for example, a CVD method.

Next, the conductive film 18 is etched back by a CMP method or the like, as shown in FIG.
In the hole 16, a conductor film (first conductor film) 18a for forming a lower electrode is formed on the conductor film 17a. Subsequently, the semiconductor substrate 1 is subjected to an etching process, and the conductor films 17a,
By removing the insulating film 11c on the outer periphery of 18a, FIG.
As shown in the figure, the upper part of the conductor film 17a and the conductor film 18a
Are projected above the upper surface of the insulating film 14b. The etching process at this time may be a dry etching process or a wet etching process, but the lower insulating film 14b made of silicon nitride functions as an etching stopper.

Thereafter, as shown in FIG. 9, the insulating film 14b
A conductive film (first conductive film) 19 for forming a lower electrode is applied so as to cover the upper surface and the exposed surfaces of the conductive films 17a and 18a. The material and the forming method of the conductor film 19 are the same as those of the conductor film 18 and will not be described. Thereafter, the conductive film 19 is etched back by an anisotropic dry etching method, so that the conductive films (sidewall conductive films) 19 are formed on the protruding side surfaces of the conductive films 17a and 18a as shown in FIG.
a is formed. Thus, a lower electrode composed of the conductor films 18a and 19a is formed.

When the conductive film 19 (see FIG. 9) is etched back, the conductive film 19 on the upper surface of the conductive film 18a is etched away. Therefore, the conductor film 1
If 8a is not formed, the conductive film 17a for the barrier is exposed by the etch-back process, and the capacitive insulating film directly contacts the conductive film 17a for the barrier. The conductor film 18a is a conductor film 17a for a barrier.
Is to prevent the upper surface of the capacitor from directly contacting the capacitor insulating film.

When the lower electrode is made of polycrystalline silicon, a plurality of hemispherical crystal grains are formed on the surface of the lower electrode in order to increase the surface area of the lower electrode and increase the capacity. Structure with various irregularities (HSG; Hemisphe
rical Grain) may be used. That is, after forming the lower electrode, a hemispherical silicon film is formed on the surface of the lower electrode by a low pressure CVD method or the like.

After that, as shown in FIG. 11, a capacitive insulating film 20 and an upper electrode (second conductive film) 21 are sequentially deposited and then patterned at once to form conductive films 18a and 19a for lower electrodes. Then, an information storage capacitor C having a capacitive insulating film 20 and an upper electrode 21 is formed.
The constituent material of the capacitive insulating film 20 is such that the lower electrode material is the first material.
(For example, Pt or the like), a highly oxidizing ferroelectric material such as (Ba, Sr) TiO ₃ or (Pb, Zr) TiO ₃ is used. in this case,
It may be used as an FRAM. When the lower electrode material is tungsten, RuO _2, IrO ₂ or the like,
As the capacitance insulating film 20, for example, tantalum oxide (Ta ₂ O)
_{If 5} ) is used and the lower electrode material is polycrystalline silicon, for example, Ta ₂ O ₅ or a laminated film of silicon oxide and silicon nitride may be used as the capacitor insulating film 20. The material of the upper electrode 21 is the same as that of the conductor films 18a and 19a of the lower electrode, and the description is omitted. Also in this case, the capacitance insulating film 20
The material may be selected according to the material.

As described above, according to the first embodiment, the following effects can be obtained.

(1) Since a structure in which the plug 13 is not in contact with the capacitor insulating film 20 can be realized, for example, during the film forming process of the capacitor insulating film 20 or during crystallization annealing in these oxidizing atmospheres The problem that the plug 13 is oxidized can be prevented. For this reason, it is possible to prevent poor conduction between the lower electrode of the capacitor C for storing information and the plug 13.

(2) According to the above (1), the yield and reliability of a semiconductor integrated circuit device having a capacitor C for storing information can be improved, and high performance and
It is possible to promote cost reduction of the highly reliable semiconductor integrated circuit device.

(Embodiment 2) FIGS. 12 to 14 are cross-sectional views of essential parts during a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention.

The second embodiment is different from the above-described hole 16 (FIG. 1).
1) is described.

First, as shown in FIG. 12, after forming an insulating film 11c in the same manner as in the first embodiment, a first hard mask film 22 is formed thereon. The first hard mask film 22 is made of, for example, polycrystalline silicon, silicon nitride, or the same material as that of the barrier conductive film 17 (see FIG. 5), and is made of a material having a large etching selectivity with respect to the silicon oxide film. Is desirable.

Subsequently, by patterning the hard mask film 22 by photolithography and dry etching, as shown in FIG. 13, a first hard mask having an opening slightly larger than the formation region of the hole is formed. The pattern 22a is formed. The size of the opening is a limit size that can be patterned by exposure processing.

Thereafter, the first hard mask pattern 22
a and in the opening thereof (that is, on the insulating film 11c)
The second hard mask film is made of the same material as the first hard mask film.
After the hard mask film 23 is deposited, the hard mask film 23 is etched back by an anisotropic dry etching method or the like, thereby forming the first hard mask pattern 2.
A sidewall 23a is formed on the side surface of the opening 2a. Thereby, the insulating film 11 exposed from the hard mask
The size of the opening region on the upper surface c can be made smaller than the exposure limit, and the above-mentioned hole can be miniaturized.

Next, as shown in FIG. 14, using the first hard mask pattern 22a and the side wall 23a as an etching mask, the insulating film 11 exposed therefrom is used.
c, 14b, and 14a are removed by etching in the same manner as in the first embodiment, and a hole 16 is formed so that the upper surface of the plug 13 is exposed from the bottom. Subsequent steps are the same as in the first embodiment, and a description thereof will be omitted.

As described above, according to the second embodiment, the following effects can be obtained in addition to the effects obtained in the first embodiment.

(1) Since the plane size of the hole 16 can be made smaller than the exposure limit, the degree of integration of the memory cell can be improved, and the overall capacity of the memory can be maintained while keeping the semiconductor integrated circuit device small. Can be increased.

(Embodiment 3) FIGS. 15 and 16 are cross-sectional views of essential parts during a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention.

The third embodiment shows a modification of the manufacturing process of the semiconductor integrated circuit device of the first embodiment. FIG. 15 shows the same step as in FIG. 7 of the first embodiment. The difference here is that the insulating film 11b is made of, for example, a silicon oxide film containing no impurities, and the insulating film 11c thereover is made of a silicon oxide film containing an impurity such as phosphorus, for example. Is not interposed. By subjecting such a semiconductor substrate 1 to, for example, hydrofluoric acid vapor etching, only the insulating film 11c containing impurities such as phosphorus is selectively etched away. Thereby, as shown in FIG. 16, a structure in which the conductor films 17a and 18a protrude from the upper surface of the insulating film 11b can be formed. Subsequent steps are the same as in the first embodiment, and a description thereof will be omitted. When the holes 16 are formed, the method described in the second embodiment may be employed.

According to the third embodiment, the following effects can be obtained in addition to the effects obtained in the first embodiment.

(1) Since the number of insulating films made of silicon nitride can be reduced, the parasitic capacitance can be reduced.

(2) According to the above (1), it is possible to suppress the propagation of noise.

(3) According to the above (1), the operation speed of the semiconductor integrated circuit device can be improved.

(Embodiment 4) FIG. 17 is a sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the fourth embodiment, as shown in FIG. 17, the conductor film forming the support of the capacitor for storing information is composed of the conductor film 17a for the barrier and the conductor film for the barrier formed thereon. The conductor films 18a and 19a for forming the lower electrode are made of, for example, ruthenium oxide (RuO ₂ ).

The conductor film 17a is made of the same material as that of the first embodiment and the like.
Is in direct contact with and electrically connected to In this case, the upper surface of the conductor film 17a is deposited so as to be lower than the upper surface of the insulating film 11b. The conductor film 17b is
A conductor film having a function of absorbing diffusion of oxygen in the lower electrode, and is made of, for example, ruthenium (Ru) or Pt. The method of forming the conductive films 17a, 17b, 18a is as follows:
Since a series of processes of film formation, CMP etchback, and removal of upper etching may be performed for each of the conductor films 17a and 17b, the description is omitted. Also in the fourth embodiment, the methods of the second and third embodiments may be applied.

Also in the fourth embodiment, the same effects as in the first to third embodiments can be obtained.

(Embodiment 5) FIG. 18 is a sectional view showing a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the fifth embodiment, as shown in FIG. 18, the conductor film constituting the pillar of the capacitor for storing information is constituted by the conductor film 18a for the lower electrode. In this case, the lower part of the conductor film 18a is buried in the hole 16, and is electrically connected to the plug 13 through the barrier conductor film 17a exposed from the upper surface of the connection hole 12a at the bottom surface of the hole 16. Conductive film 1 for barrier in this case
7a is formed on the plug 13 in the connection hole 12a. Thereby, the conductor film 18a for the lower electrode and the plug 13 are prevented from directly contacting each other. The method of forming the barrier conductor film 17a is, for example, as follows. That is, first, after a conductor film for a plug is applied, the conductor film is buried in the connection hole 12a by a CMP method or the like, and the upper portion of the conductor film in the connection hole 12a is slightly etched away. After that, the barrier conductive film 17a is deposited, and the conductive film 17a is etched back by the CMP method to form the barrier conductive film 17a on the upper portion in the connection hole 12a.

The upper part of the conductor film 18a is
and protrudes above b and is a part of the lower electrode. A conductor film 19a is formed on a side surface of the conductor film 18a, and a lower electrode of the capacitor C is formed by these. Therefore, the capacitance insulating film 20 is formed of the conductive film 18a forming the support.
Is in direct contact with The constituent material of the conductive film 18a is the same as that of the first embodiment and the like, and the description is omitted. Also,
The method for forming the conductive film 18a is the same as the method for forming the conductive film 17a for a barrier constituting the support described in the first embodiment and the like, except that the conductive film 18a in the first embodiment is used.
The description is omitted because it is the same except that there is no forming step. Further, the method described in the second and third embodiments may be applied to the fifth embodiment.

Also in the fifth embodiment, the effects obtained in the first to third embodiments can be obtained.

(Embodiment 6) FIG. 19 is a sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.

The structure of a semiconductor integrated circuit device according to the sixth embodiment is substantially the same as that of the fifth embodiment, except for the lower electrode portion of the capacitor C for storing information, as shown in FIG. Is formed of a conductive oxide film 18b formed by oxidizing the surface of the conductive film 18a constituting the support. In this case, for example, Ru or Ir is used as a constituent material of the conductor film 18a.
The conductive oxide film 18b is made of, for example, RuO ₂ or IrO ₃
After removing the insulating film 11c (see FIG. 7 and the like) in the same manner as in the first embodiment, it is formed by oxidizing the projecting surface of the conductor film 18a. The other forming method is the same as that of the first embodiment, and the description is omitted. Further, the method described in the second and third embodiments may be applied to the sixth embodiment.

Also in the sixth embodiment, the effects obtained in the first to third embodiments can be obtained.

(Embodiment 7) FIG. 20 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to still another embodiment of the present invention.

As shown in FIG. 20, the structure of the semiconductor integrated circuit device according to the seventh embodiment is similar to that of the sixth embodiment except that the conductor film 18a forming the support of the capacitor C for storing information is For example, a conductor film 18c, 1 for forming a lower electrode formed of Ru or Ir and formed on an upper surface thereof.
9a is formed of, for example, RuO ₂ or IrO ₂ , but the conductor films 18c and 19a are not formed by oxidation of the conductor film 18a, but are separately formed and etched similarly to the first embodiment. It is formed by performing a process. The method for forming the conductor films 18a and 18c is the same as the method for forming the conductor films 17a and 18a in the first embodiment, and a description thereof will be omitted. Further, the method described in the second and third embodiments may be applied to the seventh embodiment.

In the seventh embodiment, the effects obtained in the first to third embodiments can be obtained.

(Embodiment 8) FIG. 21 is a cross-sectional view of a principal part of a semiconductor integrated circuit device according to still another embodiment of the present invention.

The structure of the semiconductor integrated circuit device according to the eighth embodiment is substantially the same as that of the first embodiment, except that the height of the upper surface of the barrier conductor film 17a is different as shown in FIG. The position is lower than the upper surface height position of the insulating film 11b. Conductive films 17a, 18a, 19a
Since the material and the forming method are the same as those in the first embodiment, the description is omitted. Also, the method described in the second and third embodiments may be applied to the eighth embodiment.

In the eighth embodiment, the effects obtained in the first to third embodiments can be obtained.

(Embodiment 9) FIGS. 22 to 27 are cross-sectional views of essential parts during a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the ninth embodiment, an example in which a crown type information storage capacitor is formed will be described. As shown in FIG. 22, the insulating films 11c and 14
Holes 16 are drilled in b, 11b, and 14a in the same manner as in the first embodiment. In the hole 16, a conductive film 18d for forming a lower electrode is buried. This conductor film 1
The constituent material of 8d is the conductor film 18, 1 of the first embodiment.
8a (see FIG. 7), the description thereof is omitted, but the conductor film 18d is formed so that its upper surface is higher than the upper surface of the insulating film 14b and lower than the upper surface of the insulating film 11c. Embedded.

In the ninth embodiment, first, the insulating film 11c
After an insulating film 24 made of, for example, silicon nitride or the like is deposited on the upper portion and in the hole 16 by a CVD method or the like, the insulating film 24 is etched back by a CMP method, an anisotropic dry etching method, or the like. As shown in FIG. 23, the insulating film 24 is left only in the hole 16.

Subsequently, in the same manner as in the first embodiment,
The insulating film 11c is removed by an etching method. Thereby, as shown in FIG. 24, the upper portion of the conductor film 18d and the insulating film 24 are in a state of protruding above the insulating film 14b.
Thereafter, as shown in FIG. 25, the conductive film 1 for forming the lower electrode of the capacitor is formed so as to cover the upper surface of the insulating film 14b and the exposed surfaces of the projecting insulating film 24 and the conductive film 18d.
9 is deposited, the conductive film is etched back to form a conductive film 19d on the side surfaces of the conductive film 18d and the insulating film 24.
a is formed. The constituent materials of the conductor films 19 and 19a are the same as those in the first embodiment, and the description is omitted. The conductor film 19a is formed on the conductor film 18d through the side surface of the conductor film 18d.
d is electrically connected.

After that, the insulating film 24 is removed by an etching method. At this time, since the insulating film 14b is made of the same material as the insulating film 24, the insulating film 14b is also removed. Thus, a crown-type lower electrode is formed as shown in FIG. Then, as shown in FIG.
Similarly, the capacitor insulating film 20 and the upper electrode 21 are formed to form the crown capacitor C for storing information. The method described in the second and third embodiments may be applied to the ninth embodiment. Further, the structure of the fourth and sixth embodiments may be applied to the ninth embodiment.

According to the ninth embodiment, the same effects as those of the first to fourth and sixth embodiments can be obtained.

(Embodiment 10) FIG. 28 is a sectional view showing a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.

The tenth embodiment is a modification of the ninth embodiment. As shown in FIG. 28, a conductor film 17a for a barrier is buried in a hole 16. The conductive film 17a is in contact with and electrically connected to the plug 13 at the bottom of the hole 16, and is in electrical contact with the conductive film 18d for forming a lower electrode on the upper surface. The upper surface height of the conductor film 17a is lower than the upper surface height of the insulating film 11b. The method of forming the conductor films 17a and 18d is the same as the method of forming the conductor films 17a and 18a (see FIG. 7) of the first embodiment, and thus the description is omitted. The method described in the second and third embodiments may be applied to the tenth embodiment. Further, the structure of the fourth and sixth embodiments may be applied to the tenth embodiment.

In the tenth embodiment as described above,
The same effects as in the first to fourth and sixth embodiments can be obtained.

(Embodiment 11) FIG. 29 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the eleventh embodiment, as shown in FIG. 29, hole 16 penetrates to the main surface of semiconductor substrate 1. The hole 16 in this case is formed by a high selective etching process using the insulating film 10 as an etching stopper. Therefore, the portion below the hole 16 that contacts the semiconductor substrate 1 is formed in a self-aligned manner. On the main surface of the semiconductor substrate 1 exposed from the hole 16, a silicide layer 25 such as titanium silicide is formed.
As a method for forming the silicide layer 25, for example,
After forming a Ti film in 6, a heat treatment is performed to form a silicide, and an unreacted Ti is removed.
There is a method in which a film forming process is performed while forming a silicide layer only at the bottom of a hole by a CVD (plasma enhanced CVD) method. A conductor film 17a for a barrier is buried in the hole 16. The lower portion of the barrier conductor film 17a is electrically connected to the semiconductor substrate 1 via the silicide layer 25,
The upper part is in contact with and electrically connected to the conductor films 18a and 19a for forming the lower electrode. Other structures and forming methods are the same as those in the first embodiment, and thus description thereof is omitted. Also, the method described in the second and third embodiments may be applied to the eleventh embodiment. Further, the structure of the fourth to tenth embodiments may be applied to the eleventh embodiment.

In the eleventh embodiment as well,
The same effects as in the first to tenth embodiments can be obtained.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say,

For example, in the first to eleventh embodiments, the case where the gate electrode has a polymetal structure has been described. However, the present invention is not limited to this, and various changes can be made. For example, the gate electrode is formed of a single film of a polycrystalline silicon film. A structure or a structure in which a silicide layer such as tungsten silicide is formed on a polycrystalline silicon film may be used.

In the above description, the invention made mainly by the inventor has been described in terms of the DRA which is the application field in which the invention is based.
Although the description has been given of the case where the present invention is applied to M, the present invention is not limited to this. For example, a memory-logic mixed type semiconductor in which a memory circuit and a logic circuit each including a capacitor for storing information are provided on the same semiconductor substrate It can be applied to integrated circuit devices and the like.

[0084]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, it is possible to realize a structure in which the connection portion is not in contact with the capacitive insulating film of the information storage capacitor, and to prevent the problem that the connection portion is oxidized. Therefore, it is possible to improve the reliability of the electrical connection between the lower electrode of the capacitive element and the connection portion.

(2) According to the above (1), the yield and reliability of a semiconductor integrated circuit device having a capacitor for storing information can be improved.

(3) According to the above (2), it is possible to promote cost reduction of the semiconductor integrated circuit device with high performance and high reliability.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view of a main part during a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention;
(B) is a principal part sectional view of a plane intersecting (a).

2A is a cross-sectional view of a main part of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 1, and FIG. 2B is a cross-sectional view of a main part of a plane intersecting with FIG.

3A is a cross-sectional view of a main part of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 2, and FIG. 3B is a cross-sectional view of a main part of a plane intersecting with FIG.

4A is a cross-sectional view of a main part of the semiconductor integrated circuit device in a manufacturing step following that of FIG. 3, and FIG. 4B is a cross-sectional view of a main part of a plane intersecting FIG.

5A is a cross-sectional view of a main part of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 4, and FIG. 5B is a cross-sectional view of a main part of a plane intersecting with FIG.

6A is a cross-sectional view of a main part of the semiconductor integrated circuit device in a manufacturing step following that of FIG. 5, and FIG. 6B is a cross-sectional view of a main part of a plane intersecting with FIG.

7A is a cross-sectional view of a main part of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 6, and FIG. 7B is a cross-sectional view of a main part of a plane intersecting with FIG.

8A is a cross-sectional view of a main part of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 7, and FIG. 8B is a cross-sectional view of a main part of a plane intersecting with FIG.

9A is a cross-sectional view of a main part of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 8, and FIG. 9B is a cross-sectional view of a main part of a plane intersecting with FIG.

10A is a cross-sectional view of a main part of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 9, and FIG. 10B is a cross-sectional view of a main part of a plane intersecting with FIG.

11A is a cross-sectional view of a main part of another manufacturing step of the semiconductor integrated circuit device, which is subsequent to FIG. 10; FIG.
3 is a cross-sectional view of a main part of a plane intersecting with.

FIG. 12 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention during a manufacturing step thereof;

13 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 12;

14 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 13;

FIG. 15 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention during a manufacturing step thereof;

16 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 15;

FIG. 17 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 18 is a sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 19 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 20 is a sectional view of a main part of a semiconductor integrated circuit device according to still another embodiment of the present invention.

FIG. 21 is a cross-sectional view of a principal part of a semiconductor integrated circuit device according to still another embodiment of the present invention.

FIG. 22 is an essential part cross sectional view of the semiconductor integrated circuit device of another embodiment of the present invention during a manufacturing step;

23 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 22;

24 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 23;

25 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 24;

26 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 25;

27 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 26;

FIG. 28 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 29 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention;

DESCRIPTION OF SYMBOLS 1 semiconductor substrate 2 p-well 3 n-type semiconductor region 4 separation part 4 a separation groove 4 b separation film 5 p ⁺ type semiconductor region 6 gate oxide film 7 gate electrode 8 n-type semiconductor region 9 cap insulating film DESCRIPTION OF SYMBOLS 10 Insulating film 11a Insulating film (1st insulating film) 11b Insulating film (2nd insulating film) 11c Insulating film (3rd insulating film) 12a-12c Connection hole 13 Plug (connection part) 14a Insulating film (1st stopper insulation) 14b insulating film (second stopper insulating film) 15BL bit line 15L first layer wiring 16 hole 17, 17a conductive film (first conductive film, conductive film for barrier) 18, 18a-18d conductive film (first) Conductor film, conductor film for forming lower electrode) 19 Conductor film (first conductor film, conductor film for forming lower electrode) 19a Conductor film (sidewall conductor film, conductor film for forming lower electrode) 20 Capacitive insulating film 21 Upper part Electrode (second conductive film) 22 First hard mask film 22a First hard mask pattern 23 Second hard mask film 23a Side wall (side wall film) 24 Insulating film 25 Silicide layer WL Word line Qs Memory cell selection MIS・ FET C capacitor (capacitive element)

 ────────────────────────────────────────────────── ─── Continued on the front page F term (reference) 5F083 AD22 AD62 GA30 JA02 JA06 JA14 JA15 JA32 JA35 JA36 JA38 JA39 JA40 JA43 KA01 KA05 MA05 MA06 MA17 PR03 PR05 PR21 PR22 PR39 PR40 PR46 PR56

Claims (10)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device having a capacitor for storing information on a semiconductor substrate, comprising:
(A) depositing a first insulating film on the semiconductor substrate; and (b) forming a connection hole in the first insulating film.
(C) a step of forming a connection portion by embedding a conductive film in the connection hole; (d) a step of applying a second insulation film on the first insulation film after the formation step of the connection portion; A) a step of applying a third insulating film on the second insulating film; and (f) a step of drilling holes in the third insulating film and the second insulating film so that a part of the connection portion is exposed. (G) a step of embedding a first conductive film in the hole, and (h) a step of removing the third insulating film around the first conductive film and projecting an upper portion of the first conductive film. (I) attaching a capacitive insulating film of the information storage capacitor to the protruding surface of the first conductive film after the step of removing the third insulating film; and (j) surface of the capacitive insulating film. Applying a second conductive film for forming an upper electrode in the information storage capacitance element. Method for producing a body integrated circuit device. 2. A method for manufacturing a semiconductor integrated circuit device having a capacitor for storing information on a semiconductor substrate, comprising:
(A) depositing a first insulating film on the semiconductor substrate; and (b) forming a connection hole in the first insulating film.
(C) a step of forming a connection portion by burying a conductor film in the connection hole; and (d) a second insulation film on the first insulation film after the formation step of the connection portion with a first stopper insulation film interposed therebetween. (E) depositing a third insulating film on the second insulating film; and (f) forming the third insulating film, the second insulating film, and the first stopper insulating film on the second insulating film. Drilling a hole such that a part of the connection part is exposed while using the first stopper insulating film as an etching stopper; (g) embedding a first conductor film in the hole; (h) Removing the third insulating film around the first conductive film and projecting an upper portion of the first conductive film; and (i) projecting the first conductive film after the removing step of the third insulating film. A step of applying a capacitive insulating film in the information storage capacitive element to a surface,
(J) depositing a second conductor film for forming an upper electrode in the information storage capacitor on the surface of the capacitor insulating film. 3. A method for manufacturing a semiconductor integrated circuit device having a capacitor for storing information on a semiconductor substrate, comprising:
(A) depositing a first insulating film on the semiconductor substrate; and (b) forming a connection hole in the first insulating film.
(C) a step of forming a connection portion by embedding a conductive film in the connection hole; (d) a step of applying a second insulation film on the first insulation film after the formation step of the connection portion; A) applying a third insulating film on the second insulating film via a second stopper insulating film; and (f) forming a third insulating film, a second stopper insulating film and a second insulating film on the second insulating film. Perforating a hole such that a part of the connection portion is exposed; (g) embedding a first conductor film in the hole; and (h) the third insulating film around the first conductor film. Removing the insulating film for the second stopper as an etching stopper and projecting the upper part of the first conductive film; and (i) removing the surface of the first conductive film after the step of removing the third insulating film. Depositing a capacitive insulating film in the information storage capacitive element; and (j) forming a capacitive insulating film on the surface of the capacitive insulating film. The method of manufacturing a semiconductor integrated circuit device characterized by a step of depositing a second conductive film for forming the upper electrode in the capacitor element of the serial information storage. 4. A method of manufacturing a semiconductor integrated circuit device having a capacitor for storing information on a semiconductor substrate, comprising:
(A) depositing a first insulating film on the semiconductor substrate; and (b) forming a connection hole in the first insulating film.
(C) a step of forming a connection portion by embedding a conductive film in the connection hole; (d) a step of applying a second insulation film on the first insulation film after the formation step of the connection portion; (F) applying a third insulating film made of a material having a high etching selectivity to the second insulating film on the second insulating film;
Forming a hole in the third insulating film and the second insulating film such that a part of the connection portion is exposed; (g) embedding a first conductive film in the hole; By performing an etching process in a state where the etching selectivity between the third insulating film and the second insulating film is increased, the third insulating film around the first conductive film is used as an etching stopper using the second insulating film as an etching stopper. Removing the first conductive film and projecting the upper portion of the first conductive film; and (i) forming a capacitive insulating film of the information storage capacitive element on the protruding surface of the first conductive film after the third insulating film removing process. A semiconductor integrated circuit device, comprising: attaching a second conductive film for forming an upper electrode of the capacitive element for storing information on the surface of the capacitive insulating film. Manufacturing method. 5. A method of manufacturing a semiconductor integrated circuit device having a capacitor for storing information on a semiconductor substrate, the method comprising:
(A) depositing a first insulating film on the semiconductor substrate; and (b) forming a connection hole in the first insulating film.
(C) a step of forming a connection portion by embedding a conductive film in the connection hole; (d) a step of applying a second insulation film on the first insulation film after the formation step of the connection portion; A) a step of depositing a third insulating film on the second insulating film; and (f) a step of drilling a hole in the third insulating film and the second insulating film such that a part of the connection portion is exposed. (G) embedding a first conductive film in the hole; and (h) removing the third insulating film around the first conductive film and projecting an upper portion of the first conductive film; (I) forming a side wall conductor film for forming a lower electrode in the information storage capacitor element on the projecting side surface of the first conductor film; and (j) projecting upper surface of the first conductor film and the side wall conductor film. Depositing a capacitive insulating film of the information storage capacitive element on the surface of the capacitor, and (k) forming a capacitor insulating film on the surface of the capacitive insulating film. The method of manufacturing a semiconductor integrated circuit device characterized by a step of depositing a second conductive film for forming the upper electrode in the capacitive element for information accumulation. 6. A method of manufacturing a semiconductor integrated circuit device having a capacitor for storing information on a semiconductor substrate, comprising:
(A) depositing a first insulating film on the semiconductor substrate; and (b) forming a connection hole in the first insulating film.
(C) forming a connection portion by burying a conductor film composed of a conductor film for forming a first connection portion and a conductor film for forming a second connection portion formed thereon in the connection hole; , (D)
(E) depositing a third insulating film on the second insulating film on the first insulating film after the step of forming the connection portion, and (f) applying a third insulating film on the second insulating film. Forming a hole in the third insulating film and the second insulating film such that a part of the connection portion is exposed; (g) embedding a first conductive film in the hole; and (h) forming the first conductive film in the hole. Removing the third insulating film around the conductor film and projecting an upper portion of the first conductor film;
(I) a step of applying a capacitive insulating film of the information storage capacitive element to the protruding surface of the first conductive film after the step of removing the third insulating film; and (j) a step of: Depositing a second conductor film for forming an upper electrode in the information storage capacitor. 7. A method for manufacturing a semiconductor integrated circuit device having a capacitor for storing information on a semiconductor substrate, the method comprising:
(A) depositing a first insulating film on the semiconductor substrate; and (b) forming a connection hole in the first insulating film.
(C) a step of forming a connection portion by embedding a conductive film in the connection hole; (d) a step of applying a second insulation film on the first insulation film after the formation step of the connection portion; A) a step of depositing a third insulating film on the second insulating film; and (f) a step of drilling a hole in the third insulating film and the second insulating film such that a part of the connection portion is exposed. (G) a step of embedding a first conductor film including a conductor film for a barrier and a conductor film for forming a lower electrode formed thereon on the hole, and (h) the first conductor film. Removing the third insulating film around the substrate and projecting the upper portion of the first conductive film; and (i) storing the information on the protruding surface of the first conductive film after the step of removing the third insulating film. Depositing a capacitive insulating film in the capacitive element for storage, and (j) applying the information storage capacitor on the surface of the capacitive insulating film. The method of manufacturing a semiconductor integrated circuit device characterized by a step of depositing a second conductive film for forming the upper electrode that. 8. A method of manufacturing a semiconductor integrated circuit device having a capacitor for storing information on a semiconductor substrate, comprising:
(A) depositing a first insulating film on the semiconductor substrate; and (b) forming a connection hole in the first insulating film.
(C) a step of forming a connection portion by embedding a conductive film in the connection hole; (d) a step of applying a second insulation film on the first insulation film after the formation step of the connection portion; A) a step of applying a third insulating film on the second insulating film; and (f) a step of drilling holes in the third insulating film and the second insulating film so that a part of the connection portion is exposed. (G) embedding a first conductive film in the hole and a fourth insulating film made of a material capable of increasing an etching selectivity with respect to the third insulating film on the first conductive film; Removing the third insulating film around the film and projecting the upper part of the first conductive film and the fourth insulating film; and (i) projecting the first conductive film and forming a fourth insulating film.
Forming a sidewall conductive film on a side surface of the insulating film; (j) removing the fourth insulating film after the forming the sidewall conductive film; and (k) removing the fourth insulating film after the removing the fourth insulating film. Depositing a capacitance insulating film of the information storage capacitor on the protruding surface of the first conductor film and the surface of the side wall conductor film; and (l) forming the information storage capacitor on the surface of the capacitance insulation film. Applying a second conductor film for forming an upper electrode. 9. A semiconductor integrated circuit device having a capacitor for storing information on a semiconductor substrate, wherein: (a) a first insulating film formed on the semiconductor substrate; and (b) the first insulating film.
A connection hole formed in the insulation film, (c) a connection portion formed by embedding a conductor film in the connection hole, and (d) a second insulation film formed on the first insulation film. (E) The second
A hole formed in the insulating film so that a part of the connection portion is exposed; and (f) a lower portion is embedded in the hole, and
A first conductive film having an upper portion protruding; (g) a capacitive insulating film of the information storage capacitor formed on the projecting surface of the first conductive film; and (h) a capacitive insulating film formed on a surface of the capacitive insulating film. And a second conductor film for forming an upper electrode in the information storage capacitor. 10. The semiconductor integrated circuit device according to claim 9, wherein a conductive oxide is formed on a protruding surface of said first conductive film.