TWI726867B - 半導體封裝及製造其之方法 - Google Patents

半導體封裝及製造其之方法 Download PDF

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TWI726867B
TWI726867B TW105105242A TW105105242A TWI726867B TW I726867 B TWI726867 B TW I726867B TW 105105242 A TW105105242 A TW 105105242A TW 105105242 A TW105105242 A TW 105105242A TW I726867 B TWI726867 B TW I726867B
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Taiwan
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pillar
conductive
semiconductor die
conductive pillar
cover layer
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TW105105242A
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TW201703216A (zh
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金杜黃
朴登俊
金錫文
朴俊書
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美商艾馬克科技公司
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Priority claimed from US15/049,872 external-priority patent/US9633939B2/en
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Publication of TW201703216A publication Critical patent/TW201703216A/zh
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Abstract

一種半導體封裝以及一種製造一半導體封裝之方法。作為非限制性的例子的是，此揭露內容的各種特點係提供各種的半導體封裝以及製造其之方法，其係包括一強化該半導體封裝的可靠度之覆蓋層。

Description

半導體封裝及製造其之方法
本發明關於半導體封裝及製造其之方法。
相關申請案的交互參照/納入作為參考
本申請案係參考到2015年2月23日向韓國智慧財產局申請且名稱為"用於製造半導體封裝之方法及利用其之半導體封裝"的韓國專利申請案號10-2015-0024957，主張其之優先權，並且主張其之益處，該韓國專利申請案的內容係藉此以其整體被納入在此作為參考。
本申請案係相關於2015年8月11日申請且名稱為"半導體封裝及製造其之方法"的美國專利申請案序號14/823,689，該美國專利申請案的整體內容係藉此被納入在此作為參考。
目前的半導體封裝以及用於形成半導體封裝之方法是不足的，例如其係導致過多的成本、減低的可靠度、或是過大的封裝尺寸。習知及傳統的方式的進一步限制及缺點對於具有此項技術的技能者而言，透過此種方式與如同在本申請案的其餘部分中參考圖式所闡述的本揭露內容的比較將會變成是明顯的。
此揭露內容的各種特點係提供一種半導體封裝以及一種製造一半導體封裝之方法。作為非限制性的例子的是，此揭露內容的各種特點係提供各種的半導體封裝以及製造其之方法，其係包括一強化該半導體封裝的可靠度之覆蓋層。
10‧‧‧支撐晶圓
20‧‧‧模製材料
30‧‧‧互連結構
100‧‧‧中介體
110‧‧‧矽主體
111‧‧‧介電層
120‧‧‧直通矽晶穿孔(TSV)
131‧‧‧上方的電路圖案
132‧‧‧下方的電路圖案
200A‧‧‧實施方式
200B‧‧‧例子
200C‧‧‧圖示
200D‧‧‧圖示
200E‧‧‧圖示
200F‧‧‧圖示
200G‧‧‧圖示
200H‧‧‧圖示
200I‧‧‧封裝
210‧‧‧導電的墊
220‧‧‧導電柱
300‧‧‧半導體模組
310‧‧‧半導體晶粒
320‧‧‧焊墊
330‧‧‧焊料凸塊
340‧‧‧底膠填充(材料)
400‧‧‧覆蓋層
400A、400B、400C、400D、400E、400F、400G‧‧‧圖示
400H‧‧‧封裝
1000‧‧‧方法
1107、1110、1120、1130、1140、1150、1160、1170、1180、1190‧‧‧區塊
3000‧‧‧方法
3107、3110、3120、3130、3140、3150、3160、3170、3190‧‧‧區塊
H1、H2‧‧‧高度
圖1是展示根據本揭露內容的各種特點的一種製造一半導體封裝之範例的方法之流程圖。
圖2A-2I係展示描繪根據本揭露內容的各種特點的一種範例的半導體封裝以及一種製造一半導體封裝之範例的方法的橫截面圖。
圖3係展示根據本揭露內容的各種特點的一種製造一半導體封裝之範例的方法之流程圖。
圖4A-4H係展示描繪根據本揭露內容的各種特點的一種範例的半導體封裝以及一種製造一半導體封裝之範例的方法的橫截面圖。
以下的討論係藉由提供本揭露內容的例子來呈現本揭露內容的各種特點。此種例子並非限制性的，並且因此本揭露內容的各種特點之範疇不應該是必然受限於所提供的例子之任何特定的特徵。在以下的討論中，該些措辭"例如"、"譬如"以及"範例的"並非限制性的，並且大致與"舉例且非限制性的"、"例如且非限制性的"、及類似者為同義的。
如同在此所利用的，"及/或"是表示在表列中藉由"及/或"所加入的項目中的任一個或多個。舉例而言，"x及/或y"是表示該三個元素的 集合{(x)、(y)、(x,y)}中的任一元素。換言之，"x及/或y"是表示"x及y中的一或兩者"。作為另一例子的是，"x、y及/或z"是表示該七個元素的集合{(x)、(y)、(z)、(x,y)、(x,z)、(y,z)、(x,y,z)}中的任一元素。換言之，"x、y及/或z"是表示"x、y及z中的一或多個"。
在此所用的術語只是為了描述特定例子之目的而已，因而並不欲限制本揭露內容。如同在此所用的，單數形係欲亦包含複數形，除非上下文另有清楚相反的指出。進一步將會理解到的是，當該些術語"包括"、"包含"、"具有"、與類似者用在此說明書時，其係指明所述特點、整數、步驟、操作、元件及/或構件的存在，但是並不排除一或多個其它特點、整數、步驟、操作、元件、構件及/或其之群組的存在或是添加。
將會瞭解到的是，儘管該些術語第一、第二、等等可被使用在此以描述各種的元件，但是這些元件不應該受限於這些術語。這些術語只是被用來區別一元件與另一元件而已。因此，例如在以下論述的一第一元件、一第一構件或是一第一區段可被稱為一第二元件、一第二構件或是一第二區段，而不脫離本揭露內容的教示。類似地，各種例如是"上方"、"下方"、"側邊"與類似者的空間的術語可以用一種相對的方式而被用在區別一元件與另一元件。然而，應該瞭解的是構件可以用不同的方式加以定向，例如一半導體裝置可被轉向側邊，因而其"頂"表面是水平朝向的，並且其"側"表面是垂直朝向的，而不脫離本揭露內容的教示。
本揭露內容的各種特點係提供一種半導體裝置或封裝以及一種製造其之方法，其可以減少成本、增加可靠度、且/或增加該半導體裝置的可製造性。
本揭露內容的各種特點亦提供一種半導體裝置或封裝以及一種製造其之方法，其係避免或禁止一導電柱的導電的離子擴散到一半導體晶粒中。
本揭露內容的各種特點係另外提供一種半導體裝置或封裝以及一種製造其之方法，其係避免或禁止翹曲或扭曲發生在製造期間及/或在製造之後。
本揭露內容的各種特點係提供一種製造一半導體封裝之方法，該方法係包括在一晶圓上形成一中介體(或是重新分佈結構)；在該中介體上形成至少一導電的墊以及至少一導電柱；在該中介體上設置至少一半導體晶粒並且電連接至該導電的墊；在該半導體晶粒、該柱、及/或該中介體的各種的表面上形成一覆蓋層；利用一囊封材料來囊封在該中介體上的該柱以及該半導體晶粒；並且將該柱露出到該覆蓋層以及該囊封材料的外部。
本揭露內容的各種特點亦提供一種半導體封裝，其係包括一中介體；在該中介體上的至少一導電的墊以及至少一導電柱；至少一被設置在該中介體上並且電連接至該導電的墊之半導體晶粒；一在該半導體晶粒、該柱、及/或該中介體的各種的表面上的覆蓋層；以及一囊封在該中介體上的該柱以及該半導體晶粒的囊封材料，其中該柱的一端係被露出到該覆蓋層以及該囊封材料的外部。
本揭露內容的以上及其它的特點將會在以下各種的範例實施方式的說明中加以描述、或者從該說明來看是明顯的。本揭露內容的各種特點現在將會參考所附的圖式來加以提出，使得熟習此項技術者可以輕 易地實施該各種的特點。
圖1是展示一種製造一半導體封裝之範例的方法1000的流程圖。該範例的方法1000例如可以與任何在此論述的其它方法(例如，圖3的範例的方法3000、等等)共用任何或是所有的特徵。圖2A-2I係展示描繪根據本揭露內容的各種特點的一種範例的半導體封裝以及一種製造一半導體封裝之範例的方法的橫截面圖。在圖2A-2I中展示的結構可以與在圖4A-4H中所示之類似的結構共用任何或是所有的特徵。圖2A-2I例如可以描繪在圖1的範例的方法1000的各種階段(或區塊)的一範例的半導體封裝。圖1及2A-2I現在將會一起加以論述。應注意到的是，該範例的方法1000的範例區塊的順序可以變化，而不脫離此揭露內容的範疇。
該範例的方法1000可以在區塊1107包括製備一邏輯晶圓以用於處理(例如，用於封裝)。區塊1107可包括用各種方式的任一種來製備一邏輯晶圓以用於處理，其之非限制性的方式係在此加以提出。
例如，區塊1107可包括例如從供應商交貨、從一上游製程或是在一製造地點的站、等等接收一邏輯晶圓。該邏輯晶圓例如可以包括一半導體晶圓，其係包括複數個主動的半導體晶粒。該半導體晶粒例如可以包括一處理器晶粒、記憶體晶粒、可程式化的邏輯晶粒、特殊應用積體電路晶粒、一般的邏輯晶粒、等等。
區塊1107例如可以包括在該邏輯晶圓上形成導電的互連結構。此種導電的互連結構例如可以包括導電的墊、區域、凸塊或球、導電柱或柱體、等等。該形成例如可以包括附接預先形成的互連結構至該邏輯晶圓、在該邏輯晶圓上電鍍該些互連結構、等等。
在一範例的實施方式中，該些導電的結構可包括導電柱或是柱體，其係包括銅及/或鎳，並且可包括一焊料蓋(例如，其係包括錫及/或銀)。例如，包括導電柱的導電的結構可包括：(a)一凸塊底部金屬化("UBM")結構，其係包含(i)一層藉由濺鍍所形成的鈦-鎢(TiW)(其可被稱為一"晶種層")、以及(ii)在該鈦-鎢層上的一層藉由濺鍍所形成的銅(Cu)；(b)一藉由電鍍而被形成在該UBM上的銅柱或是柱體；以及(c)一層被形成在該銅柱上的焊料、或是一層被形成在該銅柱上的鎳以及一層被形成在該鎳層上的焊料。
再者，在一範例的實施方式中，該些導電的結構可包括一種鉛及/或無鉛的晶圓凸塊(例如，Pb/Sn、無鉛的Sn、其等同物、其之合金、等等)。例如，無鉛的晶圓凸塊(或是互連結構)的形成可以至少部分是藉由：(a)形成一凸塊底部金屬化(UBM)結構，其係藉由(i)藉由濺鍍以形成一層鈦(Ti)或是鈦-鎢(TiW)、(ii)在該鈦或是鈦-鎢層上藉由濺鍍以形成一層銅(Cu)、(iii)以及在該銅層上藉由電鍍以形成一層鎳(Ni)；以及(b)在該UBM結構的鎳層上藉由電鍍以形成一種無鉛的焊料材料，其中該無鉛的焊料材料係具有一種重量1%到4%的銀(Ag)的組成物，並且該組成物重量的其餘部分是錫(Sn)。
區塊1107例如可以包括執行該邏輯晶圓的部分或整體的薄化(例如，研磨、蝕刻、等等)。再者，區塊1107例如可以包括切割該邏輯晶圓成為個別的晶粒或是晶粒組，以用於之後的附接(例如，在區塊1130)。
一般而言，區塊1107可包括製備一邏輯晶圓以用於處理(例如，用於封裝)。於是，此揭露內容的範疇不應該受限於特定類型的邏輯晶圓及/或晶粒的特徵、或是任何特定類型的邏輯晶圓及/或晶粒處理。
在區塊1110，該範例的方法1000可以包括製備一中介體晶 圓(或面板)。在一範例的實施方式中，一中介體(例如，其之一底表面)可以附接至一支撐晶圓的一表面(例如，其之一頂表面)。此種附接例如可以利用一黏著構件(未顯示)(例如，一熱脫開的黏著劑、等等)、機械式附接、真空附接、等等來加以執行。注意到的是，該支撐晶圓可包括一半導體(例如，矽、等等)晶圓、一玻璃晶圓、一金屬晶圓、等等。亦注意到的是，該支撐晶圓並不需要是圓形的，而是亦可包括一矩形(或面板)形狀。
該中介體100例如可以是(或者已經是)利用一半導體晶圓製造(FAB)過程而被形成。此種處理例如可被利用以產生細微間距的墊及/或線路，例如是具有一10微米或是更小的線路寬度及/或間距(例如，中心至中心的間隔)。
一範例的實施方式200A係被展示在圖2A，其係展示該中介體100係包括一介電層111(其在此亦可被稱為一保護層)，該介電層111係被形成在一矽主體110的頂端(或是上方)以及底部(或是下方)表面的每一個上。該介電層111例如可以包括一或多層的各種介電材料的任一種，例如是無機介電材料(例如，Si3N4、SiO2、SiON、氧化物、氮化物、等等)及/或有機介電材料(例如，聚醯亞胺(PI)、苯環丁烯(BCB)、聚苯並噁唑(PBO)、雙馬來醯亞胺三嗪(BT)、一苯酚樹脂、環氧樹脂、等等)，但是本揭露內容的範疇並不限於此。該介電層111可以利用各種製程的任一個或是多個來加以形成(例如，旋轉塗覆、噴霧塗覆、印刷、燒結、熱氧化、物理氣相沉積(PVD)、化學氣相沉積(CVD)、電漿氣相沉積、薄片疊層、等等)，但是本揭露內容的範疇並不限於此。
此外，複數個直通矽晶穿孔(TSV)120係被形成在該矽主體 110中。再者，一電連接至該些TSV 120而且被露出到該介電層111的外部(例如，透過被形成於其中的孔)之上方的電路圖案131(或導電層)係被形成在該矽主體110的一上方側上，並且一電連接至該些TSV 120而且被露出到該介電層111的外部(例如，透過被形成於其中的孔)之下方的電路圖案132(或導電層)係被形成在該矽主體110的一下方側上。該些TSV 120例如可以在該上方的電路圖案131與下方的電路圖案132之間提供導電路徑。注意到的是，該中介體100亦可包括一或多個內部的導電層。該些導電層的任一個例如可以提供電性信號相對於該中介體100垂直及/或水平的分佈。
在一範例情節中，該中介體100(或是重新分佈結構)可以與該支撐晶圓10分開地加以形成，並且接著附接至其。在另一範例情節中，該中介體100可以被直接形成(或是建立)在一晶圓上，在此情形中，該中介體100(或是重新分佈結構)已經附接至該支撐晶圓10，因而不需要進一步黏著、或者是以其它方式附接至該支撐晶圓10。此種中介體(或是重新分佈結構)及/或其之形成的各種例子係在2015年八月11日申請且名稱為"半導體封裝及製造其之方法"的美國專利申請案序號14/823,689中被提出，該美國專利申請案的整體內容係藉此被納入於此作為參考。例如，一中介體(或是重新分佈結構)可以藉由在一矽晶圓上形成一或多個介電及導電層來加以形成。在此種例子中，該中介體100可以不包括一矽主體(或是核心)。
注意到的是，區塊1110可包括從在一製造設施的一相鄰或是上游的製造站、從另一地理的位置、等等接收該中介體晶圓。該中介體晶圓例如可以是接收到已經製備的、或是額外的製備可加以執行
一般而言，區塊1110可包括製備一中介體晶圓。於是，此 揭露內容的範疇不應該受限於任何特定類型的中介體或中介體晶圓的特徵、或是受限於形成此種中介體或中介體晶圓的任何特定的方式。
在區塊1120，該範例的方法1000可以包括在該中介體上形成一或多個導電的墊及/或導電柱(或是柱體)。區塊1120可包括用各種方式的任一種來形成此種導電的墊及/或柱，其之非限制性的例子係在此加以提供。例如，該導電的墊及/或柱可以藉由濺鍍或是其它物理氣相沉積(PVD)技術、化學氣相沉積(CVD)、一般的真空沉積、電鍍、無電的電鍍、等等來加以形成。
在一範例的實施方式中，區塊1120可包括在該上方的電路圖案131的從該介電層111露出的線路上電鍍該些導電的墊及/或導電柱。為了執行此種電鍍，區塊1120例如可以包括在該中介體100的上方側上形成一晶種層。該晶種層可包括各種材料的任一種。例如，該晶種層可包括銅。同樣例如的是，該晶種層可包括一或多層的各種金屬的任一種(例如，銅、銀、金、鋁、鎢、鈦、鎳、鉬、等等)。該晶種層可以利用各種技術的任一種(例如，濺鍍或是其它物理氣相沉積(PVD)技術、化學氣相沉積(CVD)、無電的電鍍、等等)來加以形成。
區塊1120接著例如可以包括在該晶種層上形成一樣版(例如，一般是利用一光阻、各種介電材料的任一種、微影、等等)，以露出該晶種層的一其上將被電鍍該些導電的墊及/或柱的部分。區塊1120接著例如可以包括電鍍該些導電的墊及/或柱，並且移除(或是剝除)該樣版。此種樣版的形成及電鍍例如可以被執行多次。例如，該些導電柱或是其之一部分可以在與一形成該些導電的墊之電鍍製程分開的一電鍍製程中加以形成。
該些導電的墊及/或柱可包括各種特徵的任一種。該些導電的墊及/或柱例如可以包括電鍍的銅。同樣例如的是，該些導電的墊及/或柱可包括一或多層的各種材料的任一種(例如，銅、鋁、鎳、鐵、銀、金、鈦、鉻、鎢、其之組合、其之合金、等等)，但是本揭露內容的範疇並不限於此。
一例子200B係被展示在圖2B。分別電連接至該中介體100的上方的電路圖案131的一導電的墊210以及一導電柱220係被形成在該矽主體110的上表面上。如同在此所提出的，該導電的墊210可以電連接至一半導體晶粒，並且該柱220可以連接至另一電性裝置(例如，另一半導體封裝、一基板、一主機板、等等)。該導電的墊210例如可以是大致平坦的。該導電柱220例如可以大致被成形為像是在一實質垂直於該矽主體110的方向上站立的一柱體。如同在此論述的，該導電柱220可以是遠高於該導電的墊210。例如，該導電柱220可以具有一縱長的長度是至少和該導電的墊210、在該導電的墊210與一半導體晶粒之間的導電的互連結構、以及該半導體晶粒之組合的厚度一樣高的。
區塊1120可以大致包括在該中介體上形成一或多個導電的墊及/或導電柱。於是，此揭露內容的範疇不應該受限於任何特定類型的導電的墊或柱的特徵、或是受限於形成一導電的墊或柱的任何特定的方式。
在區塊1130，該範例的方法1000可以包括將一或多個半導體晶粒附接至該中介體(或是重新分佈(RD)結構)。區塊1130可包括用各種方式的任一種來將該一或多個半導體晶粒附接至該中介體，其之非限制性的例子係在此加以提供。
該半導體晶粒可包括各種類型的半導體晶粒的任一種的特 徵。例如，該半導體晶粒可包括一處理器晶粒、一記憶體晶粒、一特殊應用積體電路晶粒、一般的邏輯晶粒、一般而言的一主動式半導體構件、等等。注意到的是，被動構件亦可以在區塊1130加以附接。
區塊1130可包括用各種方式的任一種來附接該半導體晶粒(例如，如同在區塊1107所製備的)，其之非限制性的例子係在此加以提供。例如，區塊1130可包括利用質量回焊、熱壓接合(TCB)、導電的環氧樹脂、等等來附接該半導體晶粒。
圖2C係提供區塊1130的各種特點(例如，晶粒附接特點)的一範例的圖示200C。例如，該半導體晶粒310(例如，其可以是已經從一在區塊1107所製備的邏輯晶圓切割出的)係電性且機械式地附接至該中介體100。類似地，其它晶粒(例如，其可以是已經從一在區塊1107所製備的邏輯晶圓切割出的)也可以電性且機械式地附接至該中介體100。例如，如同在區塊1107所解說的，該邏輯晶圓(或是其之晶粒)可以是已經被製備有形成在其上(例如，在其之一主動側上、等等)之各種的互連結構(例如，導電的墊、區域、凸塊、球、晶圓凸塊、導電柱、等等)。此種結構的例子係在圖2C中大致被展示為在該晶粒310的底部(例如，主動)側上的焊墊320以及焊料凸塊330。該焊料凸塊330例如可以將該焊墊320以及該導電的墊210彼此機械式且電性耦接(例如，透過一回焊製程)。區塊1130例如可以包括利用各種附接製程的任一種(例如，質量回焊、熱壓接合(TCB)、導電的環氧樹脂、等等)，來將此種互連結構電性且機械式地附接至該中介體100(例如，於其上的一導電的墊210)。
在圖2C中所示的範例實施方式200C中，該柱220在該中 介體100之上的上方端的高度H1係大於該半導體晶粒310在該中介體100之上的上方側的高度H2。此種高度差例如可以避免一被形成在該半導體晶粒310上的覆蓋層在一稍後描述的囊封材料的薄化(或是導電柱露出)製程期間被移除。在一範例的實施方式中，H1係大於H2一覆蓋層(例如，如同在區塊1140所形成者)的厚度。在一範例的實施方式中，H1係大於H2超過一覆蓋層(例如，如同在區塊1140所形成者)的厚度，此例如可以在囊封(例如，在區塊1150)以及薄化(例如，在區塊1160)之後，在該半導體晶粒310的一上方側上留下模製材料或是其它介電材料的至少一部分。
儘管在圖2C的範例實施方式200C係大致被展示有該中介體100的每一封裝區域(例如，如同將會在區塊1190被單粒化為單一封裝者)的單一晶粒，但應瞭解的是任意數目的晶粒及/或被動構件都可被納入每一封裝區域中。例如，每一封裝區域可包括兩個晶粒、三個晶粒、四個晶粒、或是超過四個晶粒。
區塊1130亦可包括底膠填充(underfilling)附接至該中介體的半導體晶粒及/或其它構件。區塊1130可包括用各種方式的任一種來執行此種底膠填充，其之非限制性的例子係在此加以提供。
例如，在晶粒附接之後，區塊1130可包括利用一毛細管底膠填充來底膠填充該半導體晶粒。例如，該底膠填充可包括一種足夠黏的強化的聚合物材料，其係在一毛細管作用中流動在該附接的半導體晶粒與該中介體之間。同樣例如的是，區塊1130可包括在該晶粒於區塊1130被附接(例如，利用一熱壓接合製程)時，利用一非導電膏(NCP)及/或一非導電膜(NCF)或帶，以底膠填充該半導體晶粒。例如，此種底膠填充材料可以在附 接該半導體晶粒之前先加以沉積(例如，印刷、噴塗、等等)(例如，作為一預先施加的底膠填充)。該底膠填充可包括各種類型的材料的任一種，例如是一環氧樹脂、一熱塑性材料、一熱可固化材料、聚醯亞胺、聚氨酯、一聚合的材料、填料的環氧樹脂、一填料的熱塑性材料，一填料的熱可固化材料、填料的聚醯亞胺、填料的聚氨酯、一填料的聚合的材料、一助熔的底膠填充、以及其等同物，但是並未受限於此。
如同所有在該範例的方法1000中描繪的區塊，區塊1130可以在該方法1000的流程中的任何位置加以執行，只要在該晶粒與該中介體之間的空間是可接達的即可。該底膠填充亦可發生在該範例的方法1000的一不同的區塊處。例如，該底膠填充可以被執行作為該囊封(或是晶圓模製)區塊1150的部分(例如，利用一種模製的底膠填充)。
圖2C亦提供區塊1130的各種其它的特點，例如該底膠填充特點的一範例的圖示。該底膠填充340係被設置在該半導體晶粒310與該中介體100之間，例如是圍繞該些焊墊320、焊料凸塊330、以及導電的墊210的側表面，並且覆蓋該半導體晶粒310的下表面。注意到的是，該半導體晶粒310、焊墊320、焊料凸塊330、以及底膠填充340在此可以被稱為一半導體模組300。
儘管該底膠填充340係大致被描繪為侷限至在該晶粒310之下的區域，而且並未覆蓋該半導體晶粒310的橫向的側邊的任一個，但是該底膠填充340可以上升並且在該半導體晶粒310及/或其它構件的側邊上形成填角(fillet)。在一範例的情節中，該晶粒之橫向的側表面的至少四分之一或是至少一半可以被該底膠填充材料340所覆蓋。在另一範例情節中， 該晶粒310的整個橫向的側表面中的一或多個或是全部可以被該底膠填充材料340所覆蓋。同樣例如的是，直接在該半導體晶粒310與其它構件(未顯示)之間、及/或在其它構件(未顯示)之間的空間之一大部分可以被填入該底膠填充材料。例如，在橫向相鄰的半導體晶粒之間、在該晶粒與其它構件之間、及/或在其它構件之間的至少一半的空間或是全部空間可以被填入該底膠填充材料。在一範例的實施方式中，該底膠填充340可以覆蓋在該半導體晶粒310與一相鄰的導電柱220之間的中介體100的一整個部分。在另一範例的實施方式中，該底膠填充340可以覆蓋該整個中介體100。在此種範例實施方式中，當該中介體100稍後被單粒化(例如，在區塊1190)時，此種切割亦可以穿過該底膠填充340來切割。
在底膠填充該半導體晶粒310之後，該底膠填充340接著可加以固化。該底膠填充340例如可以保護一凸塊接合及/或其它接合，以免於可能會發生在一半導體封裝製程期間或是之後的外部衝擊(例如是機械式衝擊或腐蝕)。
一般而言，區塊1130可以包括將一或多個半導體晶粒附接至該中介體(或是RD結構)。於是，此揭露內容的範疇不應該受限於任何特定的晶粒的特徵、或是受限於任何特定的多晶粒的佈局的特徵、或是受限於附接此種晶粒的任何特定的方式的特徵、等等。再者，此揭露內容的範疇不應該受限於任何特定類型的底膠填充的特徵、或是形成此種底膠填充的任何特定的方式。
在區塊1140，該範例的方法1000可以包括在該中介體100、導電柱220、及/或半導體模組300(或是其之部分)上形成一覆蓋層。
該覆蓋層可包括各種材料的任一種。例如，該覆蓋層可包括一或多層的各種介電材料的任一種，例如是無機介電材料(例如，SiN、Si3N4、SiO2、SiON、氧化物、氮化物、等等)及/或有機介電材料(例如，一聚合物、聚醯亞胺(PI)、苯環丁烯(BCB)、聚苯並噁唑(PBO)、雙馬來醯亞胺三嗪(BT)、一苯酚樹脂、一環氧樹脂、等等)，但是本揭露內容的範疇並不限於此。注意到的是，在一其中該覆蓋層包括複數個層的實施方式中，此種層可包括不同的材料，且/或可以利用不同的個別的製程來加以執行。
該覆蓋層可以(例如，在一室或是其它裝置中)利用各種製程的任一個或是多個(例如，旋轉塗覆、噴霧塗覆、印刷、燒結、熱氧化、物理氣相沉積(PVD)、化學氣相沉積(CVD)、金屬有機化學氣相沉積(MOCVD)、原子層沉積(ALD)、低壓化學氣相沉積(LPCVD)、電漿輔助化學氣相沉積(PECVD)、電漿氣相沉積(PVD)、薄片疊層、等等)來加以形成，但是本揭露內容的範疇並不限於此。
該覆蓋層例如可以包括一均勻的(或是固定的)厚度。例如，該覆蓋層可以在被覆蓋的構件的任一個或是全部之上以及周圍包括一連續的層。例如，該覆蓋層400可包括單一連續的層。在一範例的實施方式中，該覆蓋層400係具有一平均的厚度，並且該覆蓋層400的厚度並不會變化偏離該平均的厚度超過25%(或是超過10%)。在一範例的實施方式中(例如，利用特定的沉積製程)，該覆蓋層400的厚度並不會變化偏離該平均的厚度超過2%。
該覆蓋層400例如可以是小於1微米厚的，例如是在0.1到1微米的範圍內。同樣例如的是，該覆蓋層400可以是小於10微米厚的， 例如在1到10微米的範圍內。
圖2D係提供區塊1140的各種特點(例如是形成覆蓋層的特點)的一範例的圖示200D。該範例的覆蓋層400係被形成在該舉例說明的組件200D的所有在該覆蓋層400被形成時露出的構件上。例如，該覆蓋層400係覆蓋該中介體100之露出的上表面(例如，該中介體100的上方側的未被導電的墊210、導電柱220、底膠填充340、等等所覆蓋的全部)。同樣例如的是，該覆蓋層400係覆蓋該些導電柱220的上方端以及橫向的側邊。此外，該覆蓋層400例如是覆蓋該半導體晶粒310的橫向的側邊以及上方側。再者，該覆蓋層400例如是覆蓋該底膠填充340之露出的部分(例如，橫向的側邊)。
該覆蓋層400大致是連續的，例如其係沿著在該組件200D的構件的任一個或是全部之間(例如，在相鄰的導電柱220之間、在該半導體晶粒310(或底膠填充340)與相鄰至其的導電柱220之間、等等)的中介體100的一上表面連續地延伸。在一範例的實施方式中，該覆蓋層400係被形成在一整個封裝組件的晶圓之上。如同在此所示，在單粒化(例如，在區塊1190)之後，該覆蓋層400的一橫向的側表面將會在每一個經單粒化的半導體封裝的一橫向的側邊被露出。因此，該覆蓋層400亦可以從該舉例說明的組件200D的構件的任一個連續地延伸到該經單粒化的封裝的橫向的側邊。
注意到的是，該覆蓋層400可以直接接觸該組件200D的其上被形成該覆蓋層400之構件的任一個或是全部。然而，也可以有一或多種介於中間的材料。
該覆蓋層400例如可以操作以禁止一導電柱220之導電的離子遷移及/或擴散到該半導體晶粒310中。再者，該覆蓋層400例如可以提供結構的支撐(例如，防止或禁止該半導體封裝在製造期間及/或之後的翹曲或是扭曲)。
一般而言，區塊1140可包括在該中介體100、導電柱220、及/或半導體模組300(或是其之部分)上形成一覆蓋層。於是，此揭露內容的範疇不應該受限於任何特定的覆蓋層的特徵及/或其之形成的方式。
在區塊1150，該範例的方法1000可以包括囊封該組件(或是晶圓或支撐結構)。區塊1150例如可以包括形成各種囊封材料的任一種(例如，樹脂、聚合物、聚合物複合材料(例如是具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯、或是具有一適當的填充物的聚合物)、等等)。區塊1150可包括用各種方式的任一種(例如，壓縮模製、轉移模製、液體囊封材料模製、真空疊層、膏印刷、膜輔助的模製、等等)來執行此種囊封。
例如，區塊1150可包括在晶圓層級模製該中介體100。例如，區塊1150可包括模製在該中介體100的晶圓的上方側之上、在區塊1130附接的晶粒及/或其它構件之上、在區塊1120所形成的墊、柱或是其它互連結構之上、在區塊1130所形成的底膠填充之上、在區塊1140所形成的覆蓋層之上、等等。一般而言，區塊1150可包括模製在此種構件的任一個的在該模製(或囊封)製程被執行時所露出的上表面及/或部分之上。
圖2E係提供區塊1150的各種特點(例如，模製特點)的一範例的圖示200E。例如，該模製組件200E係被展示有該模製材料20覆蓋該導電柱220、半導體晶粒310、底膠填充340、以及該中介體100的上表面。 例如，該模製材料20可以完全橫向地圍繞該柱220並且例如可以至少暫時覆蓋該導電柱220的上方端。儘管該模製材料20(其在此亦可以被稱為囊封材料)係被展示為完全地覆蓋該半導體晶粒310的橫向的側邊以及上方側，但是情形不需要是如此的。例如，區塊1150可包括利用一種膜輔助或是晶粒密封模製技術，以保持該晶粒的上方側沒有模製材料。
該模製材料20例如可以覆蓋在區塊1140所形成的覆蓋層400的所有露出的表面。例如，該模製材料20可以直接接觸該覆蓋層400。在一範例的實施方式中，該覆蓋層400亦可以直接接觸該中介體100的上方側、該導電柱220、該底膠填充340、及/或該半導體晶粒310的任一個或是全部。例如，該覆蓋層400可以將該範例的組件200E的其它構件完全地隔離，而不與該模製材料20直接接觸。
注意到的是，在該展示的例子中的模製材料20係遠厚於該覆蓋層400。例如，該模製材料20可以是比該覆蓋層400厚超過10倍、或是厚超過100倍。
一般而言，區塊1150可包括囊封該組件(或晶圓)，例如是模製封裝組件的晶圓。於是，此揭露內容的範疇不應該受限於任何特定的模製材料、結構及/或技術的特徵。
在區塊1160，該範例的方法1000可以包括薄化在區塊1150所形成的囊封材料。區塊1160可包括用各種方式的任一種來薄化該囊封材料，其之非限制性的例子係在此加以提供。例如，區塊1160可包括藉由機械式研磨或切割、雷射移除或是其它導引能量的移除製程、化學蝕刻或是其它化學移除製程、其之任意組合、等等來薄化該囊封材料。
在一範例的實施方式中，區塊1160係包括研磨在區塊1150所形成的模製材料(或是囊封材料)。區塊1160例如可以包括機械式研磨(例如，利用一鑽石研磨機、等等)該模製材料，以薄化該模製材料。此種薄化例如可以讓該晶粒及/或互連結構成為包覆成型的、或是此種薄化可以露出一或多個晶粒及/或一或多個互連結構(例如，一或多個導電柱)。
區塊1160例如可以包括研磨除了該模製材料之外的其它構件。例如，區塊1160可包括研磨在區塊1120所形成的導電柱的頂端，例如其係包含研磨掉被形成在該些導電柱的上方端上的一覆蓋層400。此種研磨例如可以在該經研磨的組件的頂端側導致一平坦的平面表面。
注意到的是，在一其中該囊封材料原先就被形成至所要的厚度之範例的實施方式中，區塊1160可被跳過。在此種範例實施方式中，若必要的話，區塊1160例如可以包括從該些導電柱的末端剝除該覆蓋層400。
圖2F係提供區塊1160的各種特點(例如，該模製研磨的特點)的一範例的圖示。該組件200F係被描繪為其中該模製材料20(例如，相對於在圖200E所描繪的模製材料20)係被薄化以露出該導電柱220的一上方的端面。注意到的是，在此範例實施方式中，在區塊1140被形成在導電柱220的上方端上的覆蓋層400係在該研磨期間被移除(例如，機械式地被移除、等等)。該導電柱220的一部分亦可以被研磨，來使得該導電柱220及/或模製材料20到達一所要的高度(或厚度)。在一範例情節中，區塊1160亦移除在該半導體晶粒310的上方側之上的模製材料20，例如是露出被形成在該晶粒310之上的導電層400。例如，區塊1160可加以執行，直到到達在該半導體晶粒310之上的覆蓋層400為止。
在圖2F所展示的範例的組件200F中，在該模製材料的移除之後或是期間，該覆蓋層400係從該導電柱220的上方端被移除，但是仍維持覆蓋該導電柱220的橫向的側邊。該覆蓋層400係覆蓋該半導體晶粒310以及底膠填充340的橫向的側邊，並且亦持續覆蓋該半導體晶粒310的上方側。在所展示的例子中，該模製材料20已經被移除到一個程度，其係從該模製材料20的上方側露出該覆蓋層400(例如，該覆蓋層400在該半導體晶粒310之上的部分、該覆蓋層400在該導電柱220的橫向的側邊上的一部分、等等)。注意到的是，在另一範例的實施方式中，除了該覆蓋層400之外，某些模製材料20可以被留下以覆蓋該晶粒310的上方側。在該展示的例子中，該導電柱220的上方端(例如，從該中介體100算起)係高於該半導體晶粒310的上方側該覆蓋層400在該晶粒310之上的厚度。同樣注意到的是，該覆蓋層400係從該導電柱220的橫向的側邊向上延伸到一高度大於該半導體晶粒310的高度。例如，該覆蓋層400係從該導電柱220的橫向的側邊向上延伸到一高度是等於或大於該覆蓋層400在該半導體晶粒310之上的上方側的高度。
一般而言，區塊1160可包括薄化在區塊1150所形成的囊封材料。於是，此揭露內容的範疇不應該受限於薄化一囊封材料(或是模製材料)的任何特定的方式的特徵。
在區塊1170，該範例的方法100可以包括移除該晶圓10(或是支撐結構)。區塊1170可包括用各種方式的任一種來移除該晶圓10，其之非限制性的例子係在此加以提供。例如，區塊1170可包括脫黏(或是分離)在區塊1110所設置的晶圓10(或是支撐結構)。區塊1170可包括用各種方式 的任一種來執行此種脫黏，其之非限制性的特點係在此被提出。
例如，在一其中該中介體100係黏附地附接至該晶圓10的範例情節中，該黏著劑可被脫開(例如，利用熱及/或力)。同樣例如的是，化學脫模劑可被利用。在另一其中該晶圓支撐件係利用一真空力而被附接的範例情節中，該真空力可被移除。注意到的是，在一涉及黏著劑或是其它物質以助於該晶圓支撐件的附接的情節中，區塊1170在該脫黏之後，可包括從該中介體100及/或從該晶圓支撐件10清除殘留物。
在另一其中該中介體100直接被建構在該晶圓10上的範例情節中，該晶圓10例如可以藉由機械式及/或化學技術來加以移除。例如，區塊1170可包括機械式研磨該晶圓10，並且亦可以利用化學蝕刻以移除該晶圓10的至少一些部份。例如，區塊1170可包括執行化學機械平坦化(CMP)(或是拋光)。
圖2F及2G係提供區塊1170的各種特點的範例的圖示200F及200G。例如，在圖2F中描繪的晶圓10係在圖2G中被移除。該下方的電路圖案132係因此在該晶圓(或是支撐件)移除製程期間被露出，以用於和如同在此論述的互連結構電性及/或機械式的連接。
一般而言，區塊1170可包括移除該晶圓(或是支撐結構)。於是，此揭露內容的範疇不應該受限於任何特定類型的晶圓支撐件的特徵、或是受限於移除一晶圓支撐件的任何特定的方式。
在區塊1180，該範例的方法1000可以包括形成互連結構。例如區塊1180可包括在該中介體(例如，該下方的電路圖案132)的藉由該支撐晶圓在區塊1170的移除而被露出的下表面(或是側邊)上形成互連結構(例 如，封裝互連結構)。區塊1180可包括用各種方式的任一種來形成該些互連結構，其之非限制性的例子係在此加以提供。
區塊1180例如可以包括在該下方的電路圖案132的藉由該支撐晶圓10的移除而被露出的部分上形成一凸塊底部金屬化(UBM)。例如，該下方的電路圖案132的墊可以透過在一介電層中之個別的孔而被露出。區塊1180例如可以包括在該下方的電路圖案132的被露出的部分上形成凸塊底部金屬化。此種UBM的形成及/或互連結構的形成的非限制性的例子係在此例如是相關於區塊1107而被提出。注意到的是，此種凸塊底部金屬化並不需要被執行。
區塊1180接著例如可以包括將導電的凸塊、或球、或柱、或是其它結構附接至該凸塊底部金屬化。其它的互連結構也可被利用，其之例子係在此被提出(例如，導電柱或柱體、焊料球、焊料凸塊、等等)。
圖2H係提供區塊1180的各種特點(例如，形成互連結構的特點)的一範例的圖示200H。例如，互連結構30(例如，導電球或凸塊、導電柱或柱體、等等)係被附接至該下方的電路圖案132及/或被形成在其上的UBM。注意到的是，儘管該些互連結構30係被描繪為小於該些互連結構320，但是此揭露內容並非限於此的。例如，該些互連結構30可以是和該些互連結構320相同的尺寸、或是大於該些互連結構320。此外，該些互連結構30可以和該些互連結構320相同類型的互連結構、或者可以是不同的類型。同樣例如的是，該些互連結構30可以利用和該些互連結構320相同類型的製程來加以形成、或是可以利用不同類型的製程來加以形成(例如，電鍍相對於落球、焊料覆蓋相對於焊料球附接、等等)。
儘管該中介體100以及互連結構30係大致在圖2H中以一種扇出配置(例如，延伸到該晶粒310的覆蓋區之外)來加以描繪，但是它們可以替代地及/或同時用一種扇入配置，例如其中該些互連結構30大致並未延伸到該晶粒310的覆蓋區之外來加以形成。
一般而言，區塊1180可包括形成互連結構。於是，此揭露內容的範疇不應該受限於任何特定的互連結構的特徵、或是受限於形成互連結構的任何特定的方式。
在區塊1190，該範例的方法1000可以包括從該晶圓組件單粒化個別的半導體封裝。再者，此種單粒化例如可以被稱為切割(例如，從該中介體100、或是其之一晶圓或面板切割)。區塊1190可包括用各種方式的任一種來單粒化該晶圓，其之非限制性的例子係在此加以提供。
在此的討論已經大致聚焦在一晶圓(或面板)的封裝之單一中介體及/或半導體封裝的處理及/或結構。此種聚焦在一晶圓的單一中介體及/或半導體封裝只是為了清楚舉例說明而已。應瞭解的是，在此論述的全部的製程步驟都可以在一整個晶圓上加以執行。例如，在圖2A-2I以及在此的其它圖所提出的圖示的每一個可以在單一晶圓上被複製數十次或是數百次。例如，在切割之前，在該些舉例說明的組件中之一組件與一晶圓的此種組件中的一相鄰的組件之間可以沒有分開。
區塊1190例如可以包括從該晶圓單粒化(例如，機械式衝壓切割、機械式鋸切割、雷射切割、軟射束切割、電漿切割、等等)該些個別的封裝。此種單粒化的最終結果例如可以是在圖2I中所示的封裝200I。例如，該單粒化可以形成該封裝200I的側表面，該些側表面係包括該封裝200I 的複數個構件的共面的側表面。例如，該模製材料20、覆蓋層400、中介體100(或是其之層的任一個或是全部)、等等的任一個或是全部的側表面可以是在該封裝200I的橫向的側邊共面的。
一般而言，區塊1190例如可包括從該晶圓組件單粒化該晶圓。於是，此揭露內容的範疇不應該受限於單粒化的任何特定的方式的特徵。
如同在此於圖1及2的討論中所論述的，區塊1160可包括薄化該囊封材料，例如是用以露出該些導電柱的頂端、用以露出在該晶粒的頂端上的一覆蓋層、用以露出該晶粒的一頂表面、等等，但是此種薄化可被跳過、或是只有部分被執行。在一範例的實施方式中，該些導電柱可以藉由移除該囊封材料的個別的部分(例如，藉由剝蝕、等等)，而從該囊封材料被露出。此種方法及/或結構的特點、以及其它方法及/或結構特點的例子現在將會參考圖3及4A-4H來加以論述。
在區塊3107，該範例的方法3000可以包括製備一邏輯晶圓以用於處理(例如，用於封裝)。區塊3107例如可以與圖1的範例的方法1000的區塊1107共用任一個或是所有的特徵。區塊3107例如可以包括用各種方式的任一種來製備該邏輯晶圓以用於處理。
在區塊3110，該範例的方法3000可以包括製備一中介體晶圓(或是面板)。區塊3110例如可以與圖1的範例的方法1000的區塊1110共用任一個或是所有的特徵。區塊3110例如可以包括用各種方式的任一種來製備一中介體晶圓。圖4A係提供區塊3110的各種特點的一範例的圖示400A。圖示400A的例子例如可以與圖2A的範例的圖示200A共用任一個 或是所有的特徵。
在區塊3120，該範例的方法3000可以包括在該中介體上形成一或多個導電的墊及/或導電柱(或是柱體)。區塊3120例如可以與圖1的範例的方法1000的區塊1120共用任一個或是所有的特徵。區塊3120例如可以包括用各種方式的任一種來製備一中介體晶圓。圖4B係提供區塊3120的各種特點的一範例的圖示400B。範例的圖示400B例如可以與圖2B的範例的圖示200B共用任一個或是所有的特徵。
在區塊3130，該範例的方法3000可以包括將一或多個半導體晶粒附接至該中介體(或是RD結構)。區塊3130例如可以與圖1的範例的方法1000的區塊1130共用任一個或是所有的特徵。區塊3130例如可以包括用各種方式的任一種來附接一或多個半導體晶粒。圖4C係提供區塊3130的各種特點的一範例的圖示400C。範例的圖示400C例如可以與圖2C的範例的圖示200C共用任一個或是所有的特徵。
在區塊3140，該範例的方法3000可以包括在該中介體100、導電柱220、及/或半導體模組300(或是其之部分)上形成一覆蓋層。區塊3140例如可以與圖1的範例的方法1000的區塊1140共用任一個或是所有的特徵。區塊3140例如可以包括用各種方式的任一種來形成一覆蓋層。圖4D係提供區塊3140的各種特點的一範例的圖示400D。範例的圖示400D例如可以與圖2D的範例的圖示200D共用任一個或是所有的特徵。
在區塊3150，該範例的方法3000可以包括囊封該組件(或是晶圓)。區塊3140例如可以與圖1的範例的方法1000的區塊1150共用任一個或是所有的特徵。區塊3150例如可以包括用各種方式的任一種來囊封該 組件(或是晶圓)。圖4E係提供區塊3150的各種特點的一範例的圖示400E。範例的圖示400E例如可以與圖2E的範例的圖示200E共用任一個或是所有的特徵。
在區塊3160，該範例的方法3000可以包括露出該些導電柱(例如，如同在區塊3120所形成者)。區塊3160例如可以與圖1的範例的方法1000的區塊1160共用任一個或是所有的特徵。區塊3160可以用各種方式的任一種來露出該些導電柱，其之非限制性的例子係在此加以提供。
例如，區塊3160可包括剝蝕(或是移除)在該些導電柱之上的模製材料，以至少露出其之一上方的端面。區塊3160例如可以包括機械式地剝蝕(或鑽孔)、雷射剝蝕(或鑽孔)、化學蝕刻(或鑽孔)、軟射束剝蝕(或鑽孔)、等等。再者，區塊3160例如可以包括從該導電柱的上方端移除該覆蓋層。
圖4F係提供區塊3160的各種特點(例如，露出導電柱的特點)的一範例的圖示400F。範例的圖示400E例如可以與圖2E的範例的圖示200E共用任一個或是所有的特徵。
如同在此論述的，例如是在圖1及2的討論中，該半導體晶粒310的上方側可以被覆蓋該覆蓋層400以及模製材料20兩者。在圖4F所描繪的範例實施方式中，該導電柱220的上方端係凹陷在該模製材料20的上方側之下。在該導電柱220的上方端之上的模製材料20(例如，和在此種上方端上的在區塊3140所形成的覆蓋層400一起)已經被移除，因此其係提供一導電的連接至該導電柱220的上方端。例如，另一半導體封裝、另一中介體、額外的重新分佈結構層、各種不同類型的互連結構的任一種、等 等可以導電地連接至該導電柱220之露出的上方端。
該導電柱220係被展示為高於該半導體晶粒310。例如，該導電柱220的上方端係高於該半導體晶粒310的上方側。然而，情形並不需要是如此的。例如，該導電柱220的上方端可以是在一低於該半導體晶粒310的上方側之高度處。同樣例如的是，該導電柱220的上方端可以是在一介於該半導體晶粒310的上方側及下方側的高度之間的高度處。在一範例的實施方式中，一被形成在該模製材料20中以露出該導電柱220的上方端的孔可以延伸至一在該半導體晶粒的上方側之下的深度處。
儘管被形成在該模製材料20中以露出該導電柱220的孔係被展示為一和該導電柱220相同的寬度(例如，其係包含在該導電柱220的橫向的側邊上的覆蓋層400的厚度)，但是情形並不需要是如此的。例如，該孔可以比該導電柱220寬，且/或比該導電柱220和該覆蓋層400的厚度的組合寬。此外，該孔例如可以只有和該導電柱220的頂端一樣寬(或是較窄的)，例如其並未露出在該導電柱220的橫向的側邊上的覆蓋層400。再者，儘管該孔係大致被描繪為具有垂直的側壁，但是情形並不需要是如此的。例如，該孔的側壁可以是傾斜的。例如，該孔可以是在上方端(例如，在該模製材料20的上方側)比在下方端(例如，在該導電柱220的上方端或是接近該上方端之處)寬的。
此外，儘管該覆蓋層400在圖4F中係被展示為覆蓋該導電柱220的整個橫向的側邊，但是情形並不需要是如此的。例如，該導電柱220的橫向的側邊的至少一上方部分(例如，以及該導電柱220的上方端)可以從該覆蓋層400而被露出。在一範例的實施方式中，被利用以露出該導 電柱220的上方端之相同的製程(或是一不同的製程)可以移除在該導電柱220的橫向的側邊的一上方部分上的覆蓋層400的一部分。
一般而言，區塊3160可包括露出該些導電柱。於是，此揭露內容的範疇不應該受限於執行此種露出的任何特定的方式的特徵。
在區塊3170，該範例的方法3000可以包括移除該晶圓10(或是支撐結構)，並且形成互連結構。區塊3170例如可以與圖1的範例的方法1000的區塊1170及1180共用任一個或是所有的特徵。區塊3170可包括用各種方式的任一種來移除該晶圓10並且形成互連結構。圖4F及4G係提供區塊3170的各種特點的範例的圖示400F及400G。例如，在圖4F中所示的晶圓10並不存在於圖4G中。此外，互連結構30係在圖4G中被形成在該中介體100的下方側上，例如其係附接至該下方的電路圖案132。
在區塊3190，該範例的方法3000可以包括從該晶圓組件單粒化個別的半導體封裝。區塊3190例如可以與圖1的範例的方法1000的區塊1190共用任一個或是所有的特徵。區塊3190例如可以包括用各種方式的任一種來單粒化該半導體封裝。圖4H係提供一可以產生自此種單粒化的範例的封裝400H。
在此的討論係包含許多舉例說明的圖，其係展示一半導體封裝組件的各種部分以及製造其之方法。為了清楚的舉例說明，此種圖並未展示每一個範例的組件的所有特點。在此所提出的範例的組件及/或方法的任一個都可以與在此所提出的其它組件及/或方法的任一個或是全部共用任一個或是所有的特徵。例如且在無限制性下，關於圖1及2所展示及論述的範例的組件及/或方法的任一個或是其之部分都可以被納入關於圖3及4 所論述的範例的組件及/或方法的任一個中。相反地，關於圖3及4所展示及論述的組件及/或方法的任一個都可以被納入關於圖1及2所展示及論述的組件及/或方法中。
總之，此揭露內容的各種特點係提供一種半導體封裝以及一種製造一半導體封裝之方法。作為非限制性的例子的是，此揭露內容的各種特點係提供各種的半導體封裝以及製造其之方法，其係包括一強化該半導體封裝的可靠度之覆蓋層。儘管先前的內容已經參考某些特點及例子來加以敘述，但是將會被熟習此項技術者理解到可以做成各種的改變，並且等同物可加以取代，而不脫離本揭露內容的範疇。此外，可以做成許多修改以將一特定的情況或材料調適至本揭露內容的教示，而不脫離其範疇。因此，所欲的是本揭露內容不受限於所揭露之特定的例子，而是本揭露內容將會包含落入所附的申請專利範圍的範疇內之所有的例子。
20‧‧‧模製材料
30‧‧‧互連結構
100‧‧‧中介體
200I‧‧‧封裝
220‧‧‧導電柱
300‧‧‧半導體模組
310‧‧‧半導體晶粒
320‧‧‧焊墊
330‧‧‧焊料凸塊
340‧‧‧底膠填充(材料)
400‧‧‧覆蓋層

Claims (12)

  1. 一種半導體封裝，其係包括：一重新分佈(RD)結構，其係包括一上方的RD側、一下方的RD側、以及一延伸在該上方的RD側與該下方的RD側之間的橫向的RD側；一導電的墊，其係在該上方的RD側上；一導電柱，其係在該上方的RD側上，該導電柱係包括一上方的柱端、一下方的柱端、以及一延伸在該上方的柱端與該下方的柱端之間的橫向的柱側邊；一半導體晶粒，其係在該上方的RD側上並且電連接至該導電的墊；一覆蓋層，其係覆蓋該半導體晶粒的至少一部分以及該導電柱的至少一部分；以及一囊封材料，其係覆蓋該覆蓋層的至少一部分、該半導體晶粒的至少一部分、以及該導電柱的至少一部分，其中：該覆蓋層係從該橫向的柱側邊向上延伸高於該半導體晶粒的一上方側的一高度，並且覆蓋該半導體晶粒的一上方側；以及該覆蓋層係在該RD結構之上，從該半導體晶粒朝向該導電柱橫向地延伸。
  2. 一種半導體封裝，其係包括：一重新分佈(RD)結構，其係包括一上方的RD側、一下方的RD側、以及一延伸在該上方的RD側與該下方的RD側之間的橫向的RD側；一導電的墊，其係在該上方的RD側上； 一導電柱，其係在該上方的RD側上，該導電柱係包括一上方的柱端、一下方的柱端、以及一延伸在該上方的柱端與該下方的柱端之間的橫向的柱側邊；一半導體晶粒，其係在該上方的RD側上並且電連接至該導電的墊；一覆蓋層，其係覆蓋該半導體晶粒的至少一部分以及該導電柱的至少一部分；以及一囊封材料，其係覆蓋該覆蓋層的至少一部分、該半導體晶粒的至少一部分、以及該導電柱的至少一部分，其中：該覆蓋層的一橫向的側邊、該RD結構的一橫向的側邊、以及該囊封材料的一橫向的側邊是共面的；以及該覆蓋層係在該RD結構之上，從該半導體晶粒朝向該導電柱橫向地延伸。
  3. 一種半導體封裝，其係包括：一重新分佈(RD)結構，其係包括一上方的RD側、一下方的RD側、以及一延伸在該上方的RD側與該下方的RD側之間的橫向的RD側；一導電的墊，其係在該上方的RD側上；一導電柱，其係在該上方的RD側上，該導電柱係包括一上方的柱端、一下方的柱端、以及一延伸在該上方的柱端與該下方的柱端之間的橫向的柱側邊；一半導體晶粒，其係在該上方的RD側上並且電連接至該導電的墊；一覆蓋層，其係覆蓋該半導體晶粒的至少一部分以及該導電柱的至少 一部分；以及一囊封材料，其係覆蓋該覆蓋層的至少一部分、該半導體晶粒的至少一部分、以及該導電柱的至少一部分，其中：該覆蓋層係在該RD結構之上，從該半導體晶粒朝向該導電柱橫向地延伸；以及該覆蓋層係在該RD結構之上，從該半導體晶粒橫向地延伸至該導電柱。
  4. 一種半導體封裝，其係包括：一重新分佈(RD)結構，其係包括一上方的RD側、一下方的RD側、以及一延伸在該上方的RD側與該下方的RD側之間的橫向的RD側；一導電的墊，其係在該上方的RD側上；一導電柱，其係在該上方的RD側上，該導電柱係包括一上方的柱端、一下方的柱端、以及一延伸在該上方的柱端與該下方的柱端之間的橫向的柱側邊；一半導體晶粒，其係在該上方的RD側上並且電連接至該導電的墊；一覆蓋層，其係覆蓋該半導體晶粒的至少一部分以及該導電柱的至少一部分；以及一囊封材料，其係覆蓋該覆蓋層的至少一部分、該半導體晶粒的至少一部分、以及該導電柱的至少一部分，其中：該覆蓋層係在該RD結構之上，從該半導體晶粒朝向該導電柱橫向 地延伸；以及該覆蓋層是介於該囊封材料與該RD結構之間，並且保持分開該囊封材料與該RD結構。
  5. 一種半導體封裝，其係包括：一重新分佈(RD)結構，其係包括一上方的RD側、一下方的RD側、以及一延伸在該上方的RD側與該下方的RD側之間的橫向的RD側；一導電的墊，其係在該上方的RD側上；一導電柱，其係在該上方的RD側上，該導電柱係包括一上方的柱端、一下方的柱端、以及一延伸在該上方的柱端與該下方的柱端之間的橫向的柱側邊；一半導體晶粒，其係在該上方的RD側上並且電連接至該導電的墊；一覆蓋層，其係覆蓋該半導體晶粒的至少一部分以及該導電柱的至少一部分；以及一囊封材料，其係覆蓋該覆蓋層的至少一部分、該半導體晶粒的至少一部分、以及該導電柱的至少一部分，其中：該覆蓋層係在該RD結構之上，從該半導體晶粒朝向該導電柱橫向地延伸；以及該覆蓋層的一連續的部分係覆蓋該橫向的柱側邊，並且延伸至該半導體封裝的一橫向的側邊。
  6. 一種半導體封裝，其係包括：一重新分佈(RD)結構，其係包括一上方的RD側、一下方的RD側、以 及一延伸在該上方的RD側與該下方的RD側之間的橫向的RD側；一導電的墊，其係在該上方的RD側上；一導電柱，其係在該上方的RD側上，該導電柱係包括一上方的柱端、一下方的柱端、以及一延伸在該上方的柱端與該下方的柱端之間的橫向的柱側邊；一半導體晶粒，其係在該上方的RD側上並且電連接至該導電的墊；一覆蓋層，其係覆蓋該半導體晶粒的至少一部分以及該導電柱的至少一部分；一囊封材料，其係覆蓋該覆蓋層的至少一部分、該半導體晶粒的至少一部分、以及該導電柱的至少一部分；以及，在該半導體晶粒與該上方的RD側之間的底膠填充材料，並且其中該覆蓋層係覆蓋該底膠填充材料的一側表面，其中該覆蓋層係在該RD結構之上，從該半導體晶粒朝向該導電柱橫向地延伸。
  7. 一種半導體封裝，其係包括：一重新分佈(RD)結構，其係包括一上方的RD側、一下方的RD側、以及一延伸在該上方的RD側與該下方的RD側之間的橫向的RD側；一導電的墊，其係在該上方的RD側上；一導電柱，其係在該上方的RD側上，該導電柱係包括一上方的柱端、一下方的柱端、以及一延伸在該上方的柱端與該下方的柱端之間的橫向的柱側邊；一半導體晶粒，其係在該上方的RD側上並且電連接至該導電的墊； 一覆蓋層，其係覆蓋該導電柱的至少一部分以及該RD結構的至少一部分；以及一囊封材料，其係覆蓋該覆蓋層的至少一部分、該半導體晶粒的至少一部分、以及該導電柱的至少一部分，其中：該覆蓋層係在該RD結構之上，從該導電柱橫向地延伸至一第二導電柱；以及該覆蓋層係在該RD結構之上，從該半導體晶粒朝向該導電柱橫向地延伸。
  8. 一種半導體封裝，其係包括：一重新分佈(RD)結構，其係包括一上方的RD側、一下方的RD側、以及一延伸在該上方的RD側與該下方的RD側之間的橫向的RD側；一導電的墊，其係在該上方的RD側上；一導電柱，其係在該上方的RD側上，該導電柱係包括一上方的柱端、一下方的柱端、以及一延伸在該上方的柱端與該下方的柱端之間的橫向的柱側邊；一半導體晶粒，其係在該上方的RD側上並且電連接至該導電的墊；一覆蓋層，其係覆蓋該導電柱的至少一部分以及該RD結構的至少一部分；以及一囊封材料，其係覆蓋該覆蓋層的至少一部分、該半導體晶粒的至少一部分、以及該導電柱的至少一部分，其中： 該覆蓋層的一連續的部分係覆蓋該橫向的柱側邊，並且延伸至該半導體封裝的一橫向的側邊；以及該覆蓋層係在該RD結構之上，從該半導體晶粒朝向該導電柱橫向地延伸。
  9. 一種半導體封裝，其係包括：一重新分佈(RD)結構，其係包括一上方的RD側、一下方的RD側、以及一延伸在該上方的RD側與該下方的RD側之間的橫向的RD側；一導電的墊，其係在該上方的RD側上；一導電柱，其係在該上方的RD側上，該導電柱係包括一上方的柱端、一下方的柱端、以及一延伸在該上方的柱端與該下方的柱端之間的橫向的柱側邊；一半導體晶粒，其係在該上方的RD側上並且電連接至該導電的墊；一覆蓋層，其係覆蓋該導電柱的至少一部分以及該RD結構的至少一部分；一囊封材料，其係覆蓋該覆蓋層的至少一部分、該半導體晶粒的至少一部分、以及該導電柱的至少一部分；以及在該半導體晶粒與該上方的RD側之間的底膠填充材料，並且其中該覆蓋層係覆蓋該底膠填充材料的一側表面，其中該覆蓋層係在該RD結構之上，從該半導體晶粒朝向該導電柱橫向地延伸。
  10. 一種半導體封裝，其係包括：一重新分佈(RD)結構，其係包括一上方的RD側、一下方的RD側、以 及一延伸在該上方的RD側與該下方的RD側之間的橫向的RD側；一導電的墊，其係在該上方的RD側上；一導電柱，其係在該上方的RD側上，該導電柱係包括一上方的柱端、一下方的柱端、以及一延伸在該上方的柱端與該下方的柱端之間的橫向的柱側邊；一半導體晶粒，其係在該上方的RD側上並且電連接至該導電的墊；一覆蓋層，其係覆蓋該半導體晶粒的至少一部分以及該RD結構的至少一部分；以及一囊封材料，其係覆蓋該覆蓋層的至少一部分、該半導體晶粒的至少一部分、以及該導電柱的至少一部分，其中該覆蓋層係在該RD結構之上，從該半導體晶粒朝向該導電柱橫向地延伸。
  11. 一種半導體封裝，其係包括：一重新分佈(RD)結構，其係包括一上方的RD側、一下方的RD側、以及一延伸在該上方的RD側與該下方的RD側之間的橫向的RD側；一導電的墊，其係在該上方的RD側上；一導電柱，其係在該上方的RD側上，該導電柱係包括一上方的柱端、一下方的柱端、以及一延伸在該上方的柱端與該下方的柱端之間的橫向的柱側邊；一半導體晶粒，其係在該上方的RD側上並且電連接至該導電的墊；一覆蓋層，其係覆蓋該半導體晶粒的至少一部分以及該RD結構的至少一部分；以及 一囊封材料，其係覆蓋該覆蓋層的至少一部分、該半導體晶粒的至少一部分、以及該導電柱的至少一部分，其中：該覆蓋層係在該RD結構之上，從該半導體晶粒朝向該導電柱橫向地延伸；以及該覆蓋層的一連續的部分係覆蓋該半導體晶粒的一橫向的側邊，並且延伸至該半導體封裝的一橫向的側邊。
  12. 一種半導體封裝，其係包括：一重新分佈(RD)結構，其係包括一上方的RD側、一下方的RD側、以及一延伸在該上方的RD側與該下方的RD側之間的橫向的RD側；一導電的墊，其係在該上方的RD側上；一導電柱，其係在該上方的RD側上，該導電柱係包括一上方的柱端、一下方的柱端、以及一延伸在該上方的柱端與該下方的柱端之間的橫向的柱側邊；一半導體晶粒，其係在該上方的RD側上並且電連接至該導電的墊；一覆蓋層，其係覆蓋該半導體晶粒的至少一部分以及該RD結構的至少一部分；以及一囊封材料，其係覆蓋該覆蓋層的至少一部分、該半導體晶粒的至少一部分、以及該導電柱的至少一部分，其中：該覆蓋層係覆蓋該半導體晶粒的一上方側以及一橫向的側邊；以及 該覆蓋層係在該RD結構之上，從該半導體晶粒朝向該導電柱橫向地延伸。
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TW200834841A (en) * 2007-01-03 2008-08-16 Advanced Chip Eng Tech Inc Package with a marking structure and method of the same
CN102324418A (zh) * 2011-08-09 2012-01-18 日月光半导体制造股份有限公司 半导体元件封装结构与其制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200834876A (en) * 2007-01-03 2008-08-16 Advanced Chip Eng Tech Inc Multi-chips package and method of forming the same
TW200834841A (en) * 2007-01-03 2008-08-16 Advanced Chip Eng Tech Inc Package with a marking structure and method of the same
CN102324418A (zh) * 2011-08-09 2012-01-18 日月光半导体制造股份有限公司 半导体元件封装结构与其制造方法

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