TWI723645B - Three dimensional memory device - Google Patents

Abstract

A three-dimensional memory device includes a plurality of conductive layers and insulating layers alternately formed to define a multi-layer stacked structure. The multi-layer stacked structure includes a stair region and an non-stair region, the stair region includes a plurality of steps, each step includes an immediately-adjacent pair of the conductive layers and insulating layers. A plurality of memory structures are located in the non-stair region, and each memory structure passes through the conductive layers and the insulating layers. A fishbone dielectric structure includes a main bone and a plurality of side bones extending from the main bone in the stair region, wherein the main bone crosses the memory structures in the non-stair region.

Description

Three-dimensional memory device

The present disclosure relates to a memory device and its manufacturing method, and more particularly to a three-dimensional memory device with high memory density and its manufacturing method.

Memory components are important data storage components in portable electronic devices, such as MP3 players, digital cameras, notebook computers, smart phones, etc. With the increase of various applications and the improvement of functions, the demand for memory components also tends to be smaller in size and larger in memory capacity. In response to this demand, current designers have turned to develop a three-dimensional memory device that includes a stack of multiple memory cells, such as a vertical-channel three-dimensional NAND flash memory device.

However, as the critical size of the device shrinks to the limit of the general memory cell technology, how to obtain a higher memory storage capacity in a smaller device size while taking into account the operational stability of the device has become a reality. Important issues facing this technical field. Therefore, there is a need to provide an advanced three-dimensional memory device and a manufacturing method thereof to solve the problems faced by the conventional technology.

An embodiment of this specification discloses a three-dimensional memory device, which includes a plurality of conductive layers and a plurality of insulating layers, which are alternately stacked with each other to form a multi-layer stack structure. The multilayer stack structure has a stepped area and a non-stepped area. The stepped area includes a plurality of steps, and each step includes the conductive layers and an adjacent pair of the insulating layers. A plurality of memory structures are located in a non-stepped area, and each memory structure passes through the conductive layers and the insulating layers. A herringbone dielectric structure includes a main stem and a plurality of side branches. The side branches extend from the main stem in a stepped area, and the main stem passes through the memory structures in a non-stepped area.

In other embodiments of this specification, the herringbone dielectric structure is a dielectric structure that does not contain conductive materials.

In other embodiments of the present specification, each side branch extends along a first-step side wall in the stepped area.

In other embodiments of the present specification, the three-dimensional memory device further includes a plurality of metal pillars connected to the steps in the stepped area, and an adjacent pair of the metal pillars is separated by one of the side branches.

In other embodiments of this specification, the three-dimensional memory device further includes a plurality of metal pillars connected to the steps in the step area, and a pair of the metal pillars is separated by a trunk.

In other embodiments of this specification, each side branch extends vertically outward from the main trunk.

In other embodiments of the present specification, the immediately adjacent pair of the side branches extend outward from two opposite sides of the main trunk.

Another embodiment of this specification discloses a three-dimensional memory element A device comprising a plurality of conductive layers and a plurality of insulating layers, which are alternately stacked to form a multi-layer stack structure, wherein the multi-layer stack structure has a step area and a non-step area. The step area includes a plurality of steps, and each step includes the conductive layers. Layer and a pair of the insulating layers immediately adjacent to each other. A plurality of memory structures are located in a non-stepped area, and each memory structure passes through the conductive layers and the insulating layers. At least one dielectric pillar is located in each of the stepped regions, and at least one of the dielectric pillars is a dielectric structure without conductive material.

In other embodiments of this specification, the three-dimensional memory device further includes a plurality of metal pillars connected to the steps in the step area, and at least one dielectric pillar is located between a pair of the metal pillars immediately adjacent to each other.

In other embodiments of this specification, the three-dimensional memory device further includes a plurality of metal pillars connected to the steps in the step area, and each metal pillar is located in the central area of each step.

In summary, the three-dimensional semiconductor memory includes dielectric pillars or herringbone dielectric structures formed in the stepped area. The dielectric pillars or herringbone dielectric structures are used as supporting structures to support the remaining insulating layer, so that the insulating layer will not collapse due to the gaps therebetween. Dielectric pillars or herringbone dielectric structures are also located between the metal pillars or metal contacts in the step area to avoid bridging in the case of overlapping and offset in the metal pillars or metal contacts.

Hereinafter, the above description will be described in detail by way of implementation, and a further explanation will be provided for the technical solution of the present invention.

In order to make the above and other objects, features, advantages and embodiments of the present invention more comprehensible, the description of the attached symbols is as follows:

107‧‧‧Insulation layer

108‧‧‧Conductive layer

109‧‧‧Insulation layer

110‧‧‧Non-step area

110a‧‧‧Memory structure

112‧‧‧Step area

112a-112d‧‧‧level

114‧‧‧Ditch

116‧‧‧Fishbone dielectric structure

116a‧‧‧trunk

116b‧‧‧Side branch

118‧‧‧Ditch

119‧‧‧Dielectric Wall

122‧‧‧Metal Column

D1‧‧‧direction

D2‧‧‧direction

H‧‧‧Height

201‧‧‧Substrate

207‧‧‧Insulation layer

208‧‧‧Conductive layer

209‧‧‧Insulation layer

210‧‧‧Non-step area

210a‧‧‧Memory structure

211‧‧‧Vertical hole

212‧‧‧Step area

212a-212d‧‧‧level

213‧‧‧Vertical hole

214‧‧‧Passivation layer

215‧‧‧Mask layer

217‧‧‧Dielectric column

218‧‧‧Ditch

219‧‧‧Dielectric Wall

220‧‧‧Common source line

222‧‧‧Metal pillar

In order to make the above and other objects, features, advantages of the present invention and The embodiments can be more obvious and easy to understand, and the description of the attached drawings is as follows:

FIGS. 1 to 6 are three-dimensional views of a method for manufacturing a semiconductor memory device in multiple steps according to an embodiment of the present disclosure; and

FIGS. 7 to 15 are three-dimensional views of a method for manufacturing a semiconductor memory device in multiple steps according to another embodiment of the present disclosure.

This specification provides a method for manufacturing a three-dimensional memory device, which can obtain a higher memory storage capacity in a smaller device size, while taking into account the operation stability of the device. In order to make the above-mentioned embodiments and other purposes, features and advantages of this specification more comprehensible, a memory device and a manufacturing method thereof are specially cited as a preferred embodiment, and will be described in detail with the accompanying drawings.

However, it must be noted that these specific implementation cases and methods are not intended to limit the present invention. The present invention can still be implemented using other features, elements, methods, and parameters. The preferred embodiments are only used to illustrate the technical features of the present invention, and not to limit the scope of the patent application of the present invention. Those with ordinary knowledge in this technical field will be able to make equivalent modifications and changes based on the description in the following specification without departing from the spirit of the present invention. In different embodiments and drawings, the same elements will be represented by the same element symbols.

Please refer to FIGS. 1 to 6, which illustrate a three-dimensional view of a semiconductor memory device manufacturing method in multiple steps according to an embodiment of the present disclosure. The semiconductor memory device forms a multilayer stack structure by alternately depositing two different insulating layers (107, 109).

In this embodiment, the two different insulating layers (107, 109) can be a silicon nitride layer and a silicon oxide layer, respectively. In other embodiments of the present invention, the two different insulating layers may be two dielectric materials, such as two dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, and silicate. In some embodiments of this specification, the two different insulating layers (107, 109) are selected from two dielectric materials, which have relatively strong and relatively weak etching resistance to the predetermined etchant. .

Referring to FIG. 2, the multi-layer stack structure undergoes an etching step to form a stepped area 112 and a non-stepped area 110. The step area 112 includes a plurality of steps (112a-112d). Each step (112a-112d) includes two different insulating layers (107, 109) which are immediately adjacent to each other.

A plurality of memory structures 110a are formed in the non-stepped region 110, and each memory structure 110a passes through a plurality of different insulating layers (107, 109) in the non-stepped region 110. From the top view, each memory structure 110a has an O-shaped, elliptical, egg-shaped or rounded rectangle circumference, but it is not limited thereto.

Each memory structure 110a includes a memory layer and a channel layer. In some embodiments of this specification, the memory layer may be a silicon oxide layer, a composite layer of a silicon nitride layer and a silicon oxide layer (that is, an ONO structure), but the structure of the memory layer is not This is a limitation. In other embodiments of this specification, the composite layer of the memory layer can also be selected from a silicon oxide-silicon nitride-silicon oxide-silicon nitride-silicon oxide (oxide-nitride-oxide -nitride-oxide (ONONO) structure, a silicon-oxide-nitride-oxide-silicon (SONOS) structure, a band gap engineering silicon-silicon oxide Compound-silicon nitride-silicon oxide-silicon (bandgap engineered silicon-oxide-nitride-oxide-silicon, BE-SONOS) structure, tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, silicon, TANOS ) Structure and a metal-high-k bandgap-engineered silicon-oxide-nitride-oxide-silicon, MA BE-SONOS ) An ethnic group formed by the structure. In this embodiment, the memory layer can be an ONO composite layer, and the channel layer can be a polysilicon layer.

The etching process is performed to form the trench 114 along the direction D1 crossing the stepped region 112 and the non-stepped region 110. The memory structure 110a traversed or divided by the trench 114 forms a semi-cylindrical three-dimensional semiconductor memory device, thereby increasing the storage density of the memory structure.

Referring to FIG. 3, a dielectric material, such as an oxide material, is formed in the trench 114 to form a herringbone dielectric structure 116. Each herringbone dielectric structure 116 includes a main stem 116a and a plurality of side branches 116b. In the step area 112, the side branch 116b extends outward from the main trunk 116a. The backbone 116a also passes through the memory structure 110a in the non-stepped area 110. The memory structure 110a passed through by the backbone 116a forms a semi-cylindrical three-dimensional semiconductor memory device, thereby increasing the storage density of the memory structure.

In some embodiments, the herringbone dielectric structure 116 is a dielectric structure without conductive material, but it is not limited thereto. In some embodiments, each side branch 116b extends along the sidewall of the corresponding step (112a-112d) of the stepped region 112, but is not limited thereto. In some embodiments, each side branch 116b is in contact with the sidewall of the corresponding step (112a-112d) of the stepped region 112, but it is not limited thereto. In some embodiments, each side branch 116b extends vertically outward from the main trunk 116a, that is, extends along the direction D2, but not limited to Here. In some embodiments, the immediately adjacent pair of the side branches 116b extend outward from two opposite sides of the main trunk 116a, but it is not limited thereto. In some embodiments, the side branch 116b extends symmetrically from the trunk 116a in the stepped region 112, but is not limited thereto. In some embodiments, the main stem 116a and the side branches 116b have substantially the same height H in the step area 112, but are not limited thereto. In some embodiments, the trunk 116a has substantially the same height H in the stepped area 112 and the non-stepped area 110, but is not limited thereto.

Referring to FIG. 4, an etching process is performed to form trenches 118 along the direction D1. The trenches 118 are between adjacent herringbone dielectric structures 116 and between adjacent rows of memory structures 110a in the non-stepped region 110. between. The trench 118 is used as a processing window for the gate replacement step. A wet etching process is performed to remove the insulating layer 109 in the multilayer stack structure until the sidewalls of the memory structure 110a are exposed. The etching speed of the etchant of the wet etching process for the insulating layer 109 is much faster than the etching speed for the insulating layer 107, so that almost all the insulating layers 109 between the insulating layers 107 are removed, so that the remaining (unetched) ) A gap is formed between the insulating layers 107. The herringbone dielectric structure 116 is used as a supporting structure to support the remaining insulating layer 107 so that the insulating layer 107 will not collapse due to the gap therebetween.

Referring to FIG. 5, a conductive material is deposited through the trench 118 to form a conductive layer 108 to fill the gaps between the remaining (unetched) insulating layers 107. Each conductive layer 108 should reach or contact the exposed sidewall of the memory structure 110a. The conductive material may include metals, such as Cu, Al, W, or metal alloys thereof. An etching process is performed to remove excess conductive material to space adjacent conductive layers 108 from each other to prevent bridging between adjacent conductive layers 108. Thereafter, a dielectric wall 119 is formed along the direction D1 by depositing a dielectric material into the trench 118, which is located in the adjacent herringbone dielectric structure 116 And between adjacent rows of memory structures 110a in the non-stepped area 110. After the gate replacement process, that is, the insulating layer 109 is replaced by the conductive layer 108, the multilayer stack structure includes alternately stacked insulating layers 107 and conductive layers 108, and each step (112a-112d) includes alternately stacked insulating layers 107 and The pair of conductive layers 108 are immediately adjacent to each other. In some embodiments, the conductive layer 108 is made of tungsten, and the insulating layer 107 is made of silicon oxide, but it is not limited thereto.

Referring to FIG. 6, a plurality of metal pillars 122 are formed to contact each step (112a-112d) of the step region 112. Each metal pillar 122 contacts the conductive layer 108 of each step (112a-112d). In some embodiments, an immediately adjacent pair of the metal pillars 122 is separated by a corresponding one of the side branches 116b. In some embodiments, the immediately adjacent pair of the metal pillars 122 are separated by the corresponding backbone 116a. In some embodiments, each metal pillar 122 is located in an area surrounded by a corresponding main trunk 116 a, two side branches 116 b, and a dielectric wall 119. Therefore, even when the adjacent metal pillars are overlapped and shifted, the adjacent trunk 116a, the two side branches 116b, and the dielectric wall make it difficult to bridge the overlapped and shifted adjacent metal pillars 122.

In Figures 2 to 6, the step area 112 is actually covered by a passivation layer. In order to clearly show the details of the step area 112, the passivation layer is omitted in the drawings. The metal pillar 122 and the herringbone dielectric structure 116 are embedded in the passivation layer.

Please refer to FIGS. 7-15, which illustrate a three-dimensional view of a semiconductor memory device manufacturing method in multiple steps according to another embodiment of the present disclosure. In Figure 7, the multilayer stack structure includes insulating layers (207, 209) alternately stacked on a substrate 201. The multilayer stack structure is etched to form stepped regions 212 and non-stepped regions 210. The step area 212 includes a plurality of steps (212a-212d). Each step (212a-212d) includes an adjacent pair of two different insulating layers (207, 209).

In this embodiment, the two different insulating layers (207, 209) can be a silicon nitride layer and a silicon oxide layer, respectively. In other embodiments of the present invention, the two different insulating layers may be two dielectric materials, such as two dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, and silicate. In some embodiments of this specification, the two different insulating layers (207, 209) are selected from two dielectric materials, which have relatively strong and relatively weak etch resistance to the predetermined etchant. .

In FIG. 8, a passivation layer 214 is deposited to cover the step area 212.

In FIG. 9, an etching process is performed to form a vertical hole 211 in the non-step area 210, and a vertical hole 213 is formed in the step area 212. In some embodiments, the vertical hole 213 is formed along the sidewall of each step (212a-212d), but it is not limited thereto.

In FIG. 10, a mask layer 215 is formed on the non-stepped area 210 to cover the vertical hole 211.

In FIG. 11, a dielectric pillar 217 is formed in the vertical hole 213, and the mask layer 215 is removed. In some embodiments, the dielectric pillar 217 is made of a dielectric material (such as an oxide) that does not contain a conductive material, but it is not limited thereto. In some embodiments, the dielectric pillar 217 is in contact with the sidewall of the corresponding step (212a-212d).

In FIG. 12, the memory structure 210a is formed in the vertical hole 211 in the non-stepped area 210. The difference between each memory structure 210a and the memory structure 210a is that the memory structure 210a is not traversed or divided by the dielectric structure, so that gate-all-around transistors are formed in the memory structure 210a. ).

Each memory structure 210a includes a memory layer and a channel Floor. In some embodiments of this specification, the memory layer may be a silicon oxide layer, a composite layer of a silicon nitride layer and a silicon oxide layer (that is, an ONO structure), but the structure of the memory layer is not This is a limitation. In other embodiments of this specification, the composite layer of the memory layer can also be selected from a silicon oxide-silicon nitride-silicon oxide-silicon nitride-silicon oxide (oxide-nitride-oxide -nitride-oxide (ONONO) structure, a silicon-oxide-nitride-oxide-silicon (SONOS) structure, a band gap engineering silicon-silicon oxide Bandgap engineered silicon-oxide-nitride-oxide-silicon (BE-SONOS) structure, tantalum nitride-alumina-alumina-silicon nitride-silicon oxide-silicon (tantalum) nitride, aluminum oxide, silicon nitride, silicon oxide, silicon, TANOS) structure and a metal-high-k bandgap-engineered silicon-silicon oxide-silicon nitride-silicon oxide-silicon (metal-high-k bandgap-engineered) Silicon-oxide-nitride-oxide-silicon (MA BE-SONOS) structure is a group. In this embodiment, the memory layer can be an ONO composite layer, and the channel layer can be a polysilicon layer.

As shown in Figure 13, trench 218 is etched to serve as a processing window for the gate replacement step. A wet etching process is performed to remove the insulating layer 209 in the multilayer stack structure until the sidewalls of the memory structure 210a are exposed. The etching rate of the etchant for the wet etching process on the insulating layer 209 is much faster than the etching rate on the insulating layer 207, so that almost all the insulating layers 209 between the insulating layers 207 are removed, so that the remaining (unetched) ) A gap is formed between the insulating layers 207. The dielectric pillar 217 serves as a supporting structure to support the remaining insulating layer 207 so that the insulating layer 207 does not collapse due to the gap therebetween.

In Figure 14, a conductive material is deposited through the trench 218 to form a conductive layer 208 to fill the gaps between the remaining (unetched) insulating layers 207. Each conductive layer 208 should reach or contact the exposed sidewalls of the memory structure 210a. The conductive material may include metals, such as Cu, Al, W, or metal alloys thereof. An etching process is performed to remove excess conductive material to space adjacent conductive layers 208 from each other to prevent bridging between adjacent conductive layers 208. Thereafter, the dielectric wall 219 is formed by depositing a dielectric material into the trench 218. After the gate replacement process, that is, the insulating layer 209 is replaced by a conductive layer 208, the multilayer stack structure includes alternately stacked insulating layers 207 and conductive layers 208, and each step (212a-212d) includes alternately stacked insulating layers 207 and conductive layers. Layer 208 is the pair immediately adjacent to each other. In some embodiments, the conductive layer 208 is made of tungsten, and the insulating layer 207 is made of silicon oxide, but it is not limited thereto.

In FIG. 15, a plurality of metal pillars 222 are formed, which contact each step (212a-212d) of the step region 212, and a common source line 220 is formed to contact the substrate 201. Each metal pillar 222 is in contact with the conductive layer 208 of each step (212a-212d). In some embodiments, each metal pillar 222 is located in the central area of each step (212a-212d), but it is not limited thereto. In some embodiments, the corresponding dielectric pillar 217 is located between the immediately adjacent pair of the metal pillars 222, but it is not limited thereto. Therefore, in the case where an overlap offset occurs in the immediately adjacent metal pillars, the immediately adjacent metal pillars 222 are not easily bridged.

According to the foregoing embodiment, the three-dimensional semiconductor memory includes a dielectric pillar or a herringbone type dielectric structure formed in the stepped region. The dielectric pillars or herringbone dielectric structures are used as supporting structures to support the remaining insulating layer, so that the insulating layer will not collapse due to the gaps therebetween. Dielectric pillars or herringbone dielectric structures are also located between the metal pillars or metal contacts in the stepped area to avoid overlapping and offset in the metal pillars or metal contacts In the case of bridging.

Although the present invention has been disclosed as above in the preferred embodiment, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

107‧‧‧Insulation layer

108‧‧‧Conductive layer

116‧‧‧Fishbone dielectric structure

116a‧‧‧trunk

119‧‧‧Dielectric Wall

D1‧‧‧direction

Claims (10)

A three-dimensional memory device, including: A plurality of conductive layers and a plurality of insulating layers are alternately stacked with each other to form a multi-layer stack structure, wherein the multi-layer stack structure has a step area and a non-step area, the step area includes a plurality of steps, and each step includes the conductive layers And a pair of the insulating layers immediately adjacent to each other; A plurality of memory structures are located in the non-stepped area, and each memory structure passes through the conductive layers and the insulating layers; and A herringbone-type dielectric structure includes a main stem and a plurality of side branches. The side branches extend outward from the main stem in the stepped area, and the main stem passes through the memory structures in the non-stepped area. In the three-dimensional memory device described in claim 1, wherein the fish-bone dielectric structure is a dielectric structure that does not contain conductive materials. In the three-dimensional memory device described in the first item of the scope of patent application, each of the side branches extends along a side wall of the first step in the stepped area. The three-dimensional memory device described in item 1 of the scope of patent application further includes a plurality of metal pillars connected to the steps in the stepped area, and a pair of the metal pillars immediately adjacent to one of the side-branched ones Separated. The three-dimensional memory device described in claim 1 further includes a plurality of metal pillars connected to the steps in the step area, and a pair of the metal pillars immediately adjacent to each other is separated by the backbone. In the three-dimensional memory device described in item 1 of the scope of patent application, each of the side branches extends vertically outward from the trunk. In the three-dimensional memory device described in claim 1, wherein a pair of the side branches immediately adjacent to each other extends outward from two opposite sides of the trunk. A three-dimensional memory device, including: A plurality of conductive layers and a plurality of insulating layers are alternately stacked with each other to form a multi-layer stack structure, wherein the multi-layer stack structure has a step area and a non-step area, the step area includes a plurality of steps, and each step includes the conductive layers And a pair of the insulating layers immediately adjacent to each other; A plurality of memory structures are located in the non-stepped area, and each memory structure passes through the conductive layers and the insulating layers; and At least one dielectric pillar is located at each step of the step area, wherein the at least one dielectric pillar is a dielectric structure without conductive material. The three-dimensional memory device described in claim 8 further includes a plurality of metal pillars connected to the steps in the step area, and the at least one dielectric pillar is located between a pair of the metal pillars immediately adjacent to each other. The three-dimensional memory device described in item 8 of the scope of patent application further includes a plurality of metal pillars connected to the steps in the step area, and each metal pillar is located in the central area of each step.

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