TWI722666B - Method of manufacturing a semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device includes forming a precursor structure including a substrate having a via hole, a liner on a sidewall of the via hole, a conductor in the via hole, a first and a second insulating layers respectively on the top and bottom surfaces, and a first and a second redistribution layers in contact with the conductor through a first hole in the first insulating layer and a second hole in the second insulating layer. A first opening and a second opening are then respectively formed in the first insulating layer and the second insulating layer to expose a portion of the liner. The liner is then etched through the first opening and the second opening to form an air gap surrounding the conductor. The first opening and the second opening are then filled to seal the air gap.

Description

Manufacturing method of semiconductor device

The present invention relates to a method of manufacturing a semiconductor device.

In 3D integration technology, two or more wafers (or chips) are bonded together using conductive pads, and then via silicon via (TSV) electrodes are formed to interconnect the first and second wafers The conductive pad. Silicon through-hole electrodes are usually made of copper or other conductive materials to provide electrical connections between conductive pads. However, the existence of TSV parasitic capacitance is the key to affecting electrical characteristics. Therefore, further improvements are needed to reduce parasitic capacitance and enhance the performance of semiconductor devices.

According to one aspect of the present invention, a method of manufacturing a semiconductor device is provided. This method includes the following operations. Form a precursor structure. The precursor structure includes a substrate, which has an upper surface, a lower surface, and a perforation through the substrate; spacers are located on the sidewalls of the perforation, the upper surface and the lower surface of the substrate; the conductor is located in the perforation; the seed layer is located on the liner Between the pad and the conductor; the first insulating layer and the second insulating layer are respectively located on the upper surface and under the lower surface of the substrate, wherein the first insulating layer and the second insulating layer respectively have a first through hole and a second The through hole exposes the conductor; and the first redistribution layer and the second redistribution layer are in contact with the conductor through the first through hole and the second through hole, respectively. Then, a first opening and a second opening are respectively formed in the first insulating layer and the second insulating layer to expose a part of the gasket. Then, the liner is etched through the first opening and the second opening to form an air gap surrounding the conductor. Then the first opening and the second opening are filled to seal the air gap.

According to some embodiments of the present invention, the conductor has a first surface, the spacer on the upper surface of the substrate has a top surface, and the first surface is flush with the top surface.

According to some embodiments of the present invention, the conductor has a diameter, the spacer on the upper surface of the substrate has a first length, and the first length is about 1/2-1/3 of the diameter.

According to some embodiments of the present invention, the first redistribution layer and the second redistribution layer jointly clamp the conductor.

According to some embodiments of the present invention, the first redistribution layer has a lateral portion extending in a first direction on the first insulating layer, and the second redistribution layer has a lateral portion extending in a second direction opposite to the first direction .

According to some embodiments of the present invention, in a top view, the first opening has a continuous pattern around the first redistribution layer located on the first through hole, and the second opening is in the second redistribution layer located under the second through hole. There is a continuous pattern around the layer.

According to some embodiments of the present invention, in a top view, the first opening includes a plurality of separated segments surrounding the first redistribution layer located on the first through hole, and the second opening includes a plurality of separated segments surrounding the first redistribution layer. The second redistribution layer under the two through holes.

According to some embodiments of the present invention, the conductor is electrically connected to the first redistribution layer and the second redistribution layer.

According to some embodiments of the present invention, the air gap separates the conductor and the substrate.

According to some embodiments of the present invention, forming the precursor structure includes: forming a groove in the semiconductor substrate from a front side of a semiconductor substrate; forming a first liner layer and a seed material layer on the semiconductor substrate and in the groove And conductors; pattern the first liner layer by a first photoresist mask; form a first insulating layer on the semiconductor substrate; form a first redistribution layer on the first insulating layer and in the first through hole; A backside of the semiconductor substrate is thinned to expose the conductors; a patterned second liner layer is formed on the backside by a second photoresist mask; a second insulating layer is formed under the substrate; and a first The double distribution layer is under the second insulating layer and in the second through hole.

10‧‧‧Method

12, 14, 16, 18‧‧‧Operation

100‧‧‧Semiconductor device

101‧‧‧Front drive structure

110‧‧‧Semiconductor substrate

110’‧‧‧Substrate

111‧‧‧Upper surface

112, 112’‧‧‧ lower surface

120‧‧‧Pad

122‧‧‧First cushion layer

124‧‧‧Second liner

130‧‧‧Seed material layer

130’‧‧‧Seed layer

132‧‧‧Conductive layer

134‧‧‧Conductor

140‧‧‧First insulation layer

150‧‧‧First Redistribution Layer

150a, 250a‧‧‧horizontal part

240‧‧‧Second insulating layer

250‧‧‧Second Redistribution Layer

AG‧‧‧Air gap

D1‧‧‧First direction

H1‧‧‧First through hole

H2‧‧‧Second through hole

H3‧‧‧Perforation

L1‧‧‧First length

OP1‧‧‧First opening

OP2‧‧‧Second opening

PR1‧‧‧First photoresist mask

PR2‧‧‧Second photoresist mask

R1‧‧‧Groove

S1‧‧‧First surface

S2‧‧‧Second surface

S122‧‧‧Top surface

W1‧‧‧diameter

When you read the accompanying drawings, you can fully understand all aspects of this disclosure from the following detailed description. It is worth noting that according to industry standard practice, various features are not drawn to scale. In fact, for clear discussion, the size of various features can be increased or decreased arbitrarily.

FIG. 1 is a flowchart of a manufacturing method of a semiconductor device according to some embodiments of the present invention.

FIG. 2 is a schematic cross-sectional view of each step of the manufacturing process of a semiconductor device according to some embodiments of the present invention.

FIG. 3 is a schematic cross-sectional view of each step of the manufacturing process of a semiconductor device according to some embodiments of the present invention.

FIG. 4 is a schematic cross-sectional view of each step of the manufacturing process of a semiconductor device according to some embodiments of the present invention.

5A and 5B are respectively a cross-sectional and top view schematic diagram of each step of the manufacturing process of a semiconductor device according to some embodiments of the present invention.

FIG. 6 is a schematic cross-sectional view of each step of the manufacturing process of a semiconductor device according to some embodiments of the present invention.

FIG. 7 is a schematic cross-sectional view illustrating various steps of the manufacturing process of a semiconductor device according to some embodiments of the present invention.

8A and 8B are respectively a cross-sectional and top view schematic diagram of each step of the manufacturing process of a semiconductor device according to some embodiments of the present invention.

FIG. 9 is a schematic cross-sectional view illustrating various steps of the manufacturing process of a semiconductor device according to some embodiments of the present invention.

FIG. 10 is a schematic cross-sectional view illustrating various steps of the manufacturing process of a semiconductor device according to some embodiments of the present invention.

FIG. 11 is a schematic cross-sectional view of each step of the manufacturing process of a semiconductor device according to some embodiments of the present invention.

FIGS. 12A to 12C are respectively a cross-sectional view and a top view schematic diagram of each step of the manufacturing process of a semiconductor device according to some embodiments of the present invention.

FIG. 13 is a schematic cross-sectional view illustrating various steps of the manufacturing process of a semiconductor device according to some embodiments of the present invention.

FIG. 14 is a schematic cross-sectional view of each step of the manufacturing process of a semiconductor device according to some embodiments of the present invention.

In order to make the description of the present disclosure more detailed and complete, the following provides an illustrative description for the implementation aspects and specific embodiments of the present disclosure, but this is not the only way to implement or use the specific embodiments of the present disclosure. The embodiments disclosed below can be combined or substituted with each other under beneficial circumstances, and other embodiments can also be added to an embodiment without further description or description. In the following description, many specific details will be described in detail so that the reader can fully understand the following embodiments. However, the embodiments of the present disclosure can be practiced without these specific details.

Although the series of actions or steps described in the disclosed method are used below, the order of the actions or steps shown should not be considered as limiting the present disclosure. For example, certain actions or steps may be performed in a different order and/or simultaneously with other steps. In addition, not all steps must be performed in order to implement the depicted embodiment of the present invention. In addition, each operation or procedure described herein may include several sub-steps or actions.

FIG. 1 is a flowchart of a manufacturing method of a semiconductor device according to some embodiments of the present invention. As shown in FIG. 1, the method 10 includes operation 14, operation 14, operation 16, and operation 18. FIGS. 2-14 are respectively schematic cross-sectional views illustrating various steps of the manufacturing process of a semiconductor device according to some embodiments of the present invention.

Referring to FIG. 1, in operation 12 of method 10, a precursor structure is formed. Figures 2-11 show detailed steps for implementing operation 12 according to some embodiments of the present disclosure.

Please refer to Figure 2, from the upper surface 111 of the semiconductor substrate 110 A groove R1 is formed in the semiconductor substrate 110. As shown in FIG. 2, the semiconductor substrate 110 has an upper surface 111 and a lower surface 112 opposite to the upper surface 111. In some embodiments, the groove R1 has inclined sidewalls, as shown in FIG. 2. In other embodiments, the groove R1 has vertical sidewalls.

In some embodiments, the semiconductor substrate 110 may be a bulk silicon substrate. Alternatively, the substrate 110 may include basic semiconductors (such as silicon or germanium with a crystal structure) or compound semiconductors, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide Or any combination thereof. The substrate 110 may also include a silicon-on-insulator (SOI) substrate. Generally speaking, an SOI substrate includes a layer with a semiconductor material (for example, silicon, germanium, silicon germanium, an insulating layer covered with silicon germanium, or any combination thereof). In some embodiments, the semiconductor substrate 110 may include one or more active elements (not shown), such as transistors.

Referring to FIG. 3, the first liner layer 122, the seed material layer 130, and the conductive layer 132 are formed on the semiconductor substrate 110 and in the groove R1. As shown in FIG. 3, the first liner layer 122, the seed material layer 130, and the conductive layer 132 are sequentially formed on the semiconductor substrate 110 conformally.

In some embodiments, the first liner layer 122 may include any suitable material, such as silicon oxide, but is not limited thereto. In some embodiments, the seed material layer 130 is composed of a single layer or multiple layers of different materials, and the material is selected from a combination including: chromium (Cr), titanium (Ti), copper (Cu), silver (Ag) ) And combinations thereof. In some embodiments, the conductive layer 132 includes a conductive material such as copper.

Please refer to FIG. 4 to perform a planarization process to form a conductor 134 in the groove R1. As shown in FIG. 4, the conductor 134 has a first surface S1, the first liner layer 122 has a top surface S122, and the first surface S1 is flush with the top surface S122. In some embodiments, the planarization process includes any suitable process, such as chemical mechanical polishing (CMP), but is not limited thereto. The conductor 134 can be used as a TSV electrode, but is not limited thereto.

Referring to FIG. 5A and FIG. 5B, the first liner layer 122 is patterned by the first photoresist mask PR1. FIG. 5B is a top view of FIG. 5A, and in order to simplify the illustration, the seed material layer 130 is not shown in FIG. 5B. As shown in FIGS. 5A and 5B, a part of the first liner layer 122 on the upper surface 111 of the semiconductor substrate 110 is etched. In some embodiments, the conductor 134 has a diameter W1, the patterned first liner layer 122 has a first length L1, and the first length L1 is approximately 1/2-1/3 of the diameter.

Please refer to FIG. 6, the first insulating layer 140 is formed on the semiconductor substrate 110. In some embodiments, the first insulating layer 140 is conformally formed on the semiconductor substrate 110 and covers the patterned first liner layer 122 and the conductor 134. The first insulating layer 140 can be deposited by any suitable process, such as: chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma assisted chemical vapor deposition (PECVD), And its combination. In some embodiments, the first insulating layer 140 includes silicon nitride, but is not limited thereto. The first insulating layer 140 may serve as an etch stop layer.

Please refer to FIG. 7, a first through hole H1 is formed in the first insulating layer 140. As shown in FIG. 7, the first through hole H1 is formed on the conductor 134 to expose the first surface S1 of the conductor 134. The first through hole H1 can be processed by photolithography and The etching process is formed.

Referring to FIGS. 8A and 8B, a first redistribution layer 150 is formed on the first insulating layer 140 and in the first through hole H1. FIG. 8B is a top view of FIG. 8A, and in order to simplify the drawing, the seed material layer 130 is not shown in FIG. 8B. As shown in FIG. 8A, the first redistribution layer 150 is filled in the first through hole H1 (shown in FIG. 7), and has a lateral portion 150a. The lateral portion 150a is located on the first insulating layer 140. A through hole H1 extends along the first direction D1. In some embodiments, the first insulating layer 140 includes silver (Ag), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), aluminum (Al), nickel (Ni), ruthenium (Ru) ), palladium (Pd), platinum (Pt), manganese (Mn), tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (AlN), tungsten silicide (WSi) , Molybdenum nitride (MoN), nickel silicide (Ni2Si), titanium silicide (TiSi2), titanium aluminide (TiAl), arsenic (As) doped polysilicon, zirconium nitride (ZrN), TaC, TaCN, TaSiN, TiAlN And/or any combination thereof.

Please refer to FIG. 9, the semiconductor substrate 110 is thinned from the back side of the semiconductor substrate 110 to expose the second surface S2 of the conductor 134. In some embodiments, a thinning process such as chemical mechanical polishing (CMP), polishing, or etching is performed to thin the semiconductor substrate 110. As shown in FIG. 9, the substrate 110' is formed after the thinning process. The lower surface 112 ′ of the substrate 110 ′ may be flush with the second surface S2 of the conductor 134.

Continuing to refer to FIG. 9, the second liner layer 124 is formed under the lower surface 112' of the substrate 110'. In some embodiments, the material and forming method of the second liner layer 124 may be substantially the same as those of the first liner layer 122, which will not be repeated here.

Referring to FIG. 10, a patterned second liner layer 124 is formed under the lower surface 112' through the second photoresist mask PR2. As shown in FIG. 10, a portion of the second liner layer 124 below the lower surface 112' of the substrate 110' is etched to form a patterned second liner layer 124. In some embodiments, the formation of the patterned second liner layer 124 is the same as the formation of the patterned first liner layer 122 shown in FIG. 5A. That is, the patterned second liner layer 124 may have a second length (not shown), which may be about 1/2-1/3 of the diameter of the conductor 134.

Please refer to FIG. 11, the second insulating layer 240 is formed under the substrate 110'. In some embodiments, the material and formation of the second insulating layer 240 are substantially the same as those of the first insulating layer 140. As shown in FIG. 11, the second through hole H2 is formed in the second insulating layer 240 to expose the second surface S2 of the conductor 134. Specifically, the second through hole H2 in the second insulating layer 240 is aligned with the first through hole H1 in the first insulating layer 140, and the conductor 134 is located therebetween.

Please continue to refer to FIG. 11, the second redistribution layer 250 is formed under the second insulating layer 240 and in the second through hole H2. Similarly, in some embodiments, the material and formation method of the second redistribution layer 250 may be substantially the same as the first redistribution layer 150. In some embodiments, the second redistribution layer 250 has a lateral portion 250a extending from the second through hole H2 in a direction opposite to the first direction D1 shown in FIG. 8A. In some embodiments, when the structure shown in FIG. 11 is turned upside down, its top view may be substantially the same as or equal to that in FIG. 8A.

As shown in FIG. 11, the precursor structure 101 is formed at this time. The precursor structure 101 includes a substrate 110', a pad 120, a conductor 134, a seed layer 130', The first insulating layer 140, the second insulating layer 240, the first redistribution layer 150, and the second redistribution layer 250. The substrate 110' has an upper surface 111, a lower surface 112', and a through hole H3 penetrating the substrate 110'. The liner 120 is located on the sidewall of the through hole H3. The spacer 120 is further located on a part of the upper surface 111 of the substrate 110' and under a part of the lower surface 112'. The conductor 134 is located in the through hole H3. The seed layer 130 ′ is between the pad 120 and the conductor 134. The first insulating layer 140 and the second insulating layer 240 are respectively located on the upper surface 111 of the substrate 110' and under the lower surface 112' of the substrate 110'. The first insulating layer 140 and the second insulating layer 240 respectively have a first through hole H1 and a second through hole H2 to expose the conductor 134. The first redistribution layer 150 and the second redistribution layer 250 are in contact with the conductor 134 through the first through hole H1 and the second through hole H2, respectively.

Next, referring to FIG. 1 and FIG. 12A to FIG. 12C, in operation 14 of method 10, a first opening OP1 and a second opening OP2 are formed in the first insulating layer 140 and the second insulating layer 240, respectively. To expose a part of the liner 120. Refer to FIG. 12B, which is a top view of FIG. 12A according to an embodiment of the present disclosure. In some embodiments, the first opening OP1 includes a plurality of separate sections surrounding the first redistribution layer 150 on the first through hole H1. For example, as shown in FIG. 12B, the first opening OP1 may be composed of three parts, and each part is adjacent to the edge of the first redistribution layer 150. Similarly, in a top view, the second opening OP2 may include a plurality of separated segments surrounding the second redistribution layer 250 located under the second through hole H2. Therefore, the arrangement of the second opening OP2 may be substantially the same as that of the first opening OP1 shown in FIG. 12B.

Please refer to Figure 12C, which is another embodiment of the present invention The top view of Figure 12A. As shown in FIG. 12C, the first opening OP1 may have a continuous pattern around the first redistribution layer 150 located on the first through hole H1. For example, the first opening OP1 may be a continuous trench adjacent to the edge of the first redistribution layer 150. Similarly, in a top view, the second opening OP2 may have a continuous pattern around the second redistribution layer 250 located under the second through hole H2. Therefore, the configuration of the second opening OP2 may be substantially the same as the first opening OP1 shown in FIG. 12C.

Next, referring to FIGS. 1 and 13, in operation 16 of method 10, the liner 120 is etched through the first opening OP1 and the second opening OP2 to form an air gap AG surrounding the conductor 134. In some embodiments, the liner 120 is etched by using an etching solution such as acid to perform etching from the first opening OP1 and the second opening OP2. Specifically, the first opening OP1 and the second opening OP2 may serve as inlets for removing the liner 120 with acid. As shown in FIG. 13, the gasket 120 shown in FIG. 12A is therefore replaced by an air gap AG. The air gap AG wraps the conductor 134 and the seed layer 130'. The conductor 134 is supported by the first redistribution layer 150 and the second redistribution layer 250 so that the conductor 134 does not fall when the pad 120 is removed.

Next, referring to FIGS. 1 and 14, in operation 18 of method 10, the first opening OP1 and the second opening OP2 are filled to seal the air gap AG. In some embodiments, the first opening OP1 and the second opening OP2 are filled with the same material as the first insulating layer 140 and the second insulating layer 240. The air gap AG can be easily closed by any suitable deposition process. As shown in FIG. 14, the semiconductor device 100 is formed at this time. The first redistribution layer 150 and the second redistribution layer 250 jointly sandwich the conductor 134. In addition, the conductor 134 is electrically connected The first redistribution layer 150 and the second redistribution layer 250 are connected. The air gap AG separates the conductor 134 and the seed layer 130' from the substrate 110'. In addition, the air gap AG electrically insulates the conductor 134 and the seed layer 130' from the substrate 110'. It should be noted that the air gap AG does not have to be filled with air, it can be filled with other types of gas, or it can be a vacuum.

According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device is provided. The method of the present disclosure forms an air gap wrapped conductor, and the conductor is sandwiched by the first redistribution layer and the second redistribution layer. The conductor may be further surrounded by a seed layer. Therefore, the air gap insulates the conductor and seed layer from surrounding components. The air gap can reduce parasitic capacitance, thereby improving the overall electrical performance of the semiconductor device. For example, the capacitance density and leakage current density of a semiconductor device with an air gap are about an order of magnitude and two orders of magnitude lower than that of a conventional semiconductor device using silicon oxide as an insulator, respectively.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone who is familiar with the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope shall be subject to the definition of the attached patent application scope.

10‧‧‧Method

12, 14, 16, 18‧‧‧Operation

Claims (10)

A method for manufacturing a semiconductor device includes: forming a precursor structure, including: a substrate having an upper surface, a lower surface, and a through hole penetrating the substrate; a spacer located on a sidewall of the through hole and the upper surface of the substrate On the surface and under the bottom surface; a conductor is located in the through hole; a seed layer is located between the spacer and the conductor; a first insulating layer and a second insulating layer are respectively located on the upper part of the substrate Above the surface and below the bottom surface, wherein the first insulating layer and the second insulating layer respectively have a first through hole and a second through hole exposing the conductor; and a first redistribution layer and a second The double distribution layer is respectively in contact with the conductor through the first through hole and the second through hole; a first opening and a second opening are respectively formed in the first insulating layer and the second insulating layer to expose Part of the gasket; etching the gasket through the first opening and the second opening to form an air gap surrounding the conductor; and filling the first opening and the second opening to seal the air gap. The method according to claim 1, wherein the conductor has a first surface, the spacer on the upper surface of the substrate has a top surface, and the first surface is flush with the top surface. The method according to claim 2, wherein the conductor has a diameter, the spacer on the upper surface of the substrate has a first length, and the first length is about 1/2-1/ of the diameter 3. The method according to claim 1, wherein the first redistribution layer and the second redistribution layer jointly clamp the conductor. The method according to claim 1, wherein the first redistribution layer has a lateral portion extending in a first direction on the first insulating layer, and the second redistribution layer has a lateral portion that is in contact with the first insulating layer. Extend in a second direction opposite to the direction. The method according to claim 1, wherein in a top view, the first opening has a continuous pattern around the first redistribution layer on the first through hole, and the second opening is positioned on the second through hole. There is a continuous pattern around the second redistribution layer under the hole. The method according to claim 1, wherein in a top view, the first opening includes a plurality of separated segments surrounding the first redistribution layer on the first through hole, and the second opening includes a plurality of separated The segment surrounds the second redistribution layer located under the second through hole. The method according to claim 1, wherein the conductor is electrically connected to the first redistribution layer and the second redistribution layer. The method of claim 1, wherein the air gap separates the conductor and the substrate. The method of claim 1, wherein forming the precursor structure comprises: forming a groove in the semiconductor substrate from a front side of the semiconductor substrate; and forming a first liner layer on the semiconductor substrate and in the groove , A seed material layer and the conductor; pattern the first liner layer by a first photoresist mask; form the first insulating layer on the semiconductor substrate; form the first redistribution layer on the second On an insulating layer and in the first through hole; thin the semiconductor substrate from a back side of the semiconductor substrate to expose the conductor; and form a patterned second liner layer on a second photoresist mask The back side; forming the second insulating layer under the substrate; and forming the second redistribution layer under the second insulating layer and in the second through hole.

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