TWI720773B - Low-input impedance current-mode sample and hold circuit and 2-1 mash delta-sigma modulator - Google Patents

Abstract

The present invention provides a low input impedance current-mode sample and hold circuit module, which comprises a common mode feedforward circuit, a first current switch feedback memory circuit connected to the first differential input of the common mode feedforward circuit, and a second current switch feedback memory circuit connected to the second differential input of the common mode feedforward circuit. The first current switch feedback memory circuit comprises a first switch which is controlled by the first clock signal to be connected to the first differential input, and the second current switch feedback memory circuit comprises a second switch which is controlled by the second clock signal to be connected to the second differential input end. The first current switch feedback memory circuit and the second current switch feedback memory circuit each comprise a reference current circuit, a current matching circuit corresponding to the reference current circuit, and an amplifier unit set between the current circuits and the current matching circuit to reduce the input impedance of the sample and holding circuit.

Description

Low-input impedance current sample-and-hold circuit module and two-plus-one-order delta-sigma analog-to-digital converter

The present invention relates to a current switch feedback memory module of an analog-to-digital converter, in particular to a current switch feedback memory module of a delta-sigma analog-to-digital converter.

Analog-to-digital converter (ADC) is a component used to convert continuous signals in analog form into discrete signals in digital form. The current common analog-to-digital converters include integral, successive approximation (SAR) ), parallel comparison type/serial parallel type, capacitor array successive comparison type, and delta-sigma analog-to-digital converter (Delta-Sigma Modulation, DSM), etc. Among them, the delta-sigma analog-to-digital converter (Delta-Sigma Modulation, DSM) is a widely used over-sampling analog-to-digital converter, which is used in various consumer electronic products, such as high-resolution data converters, DC-DC conversion Controllers, wireless sensor networks, motor controllers, etc.

The high-order delta-sigma analog-to-digital converter can be obtained through a single-loop or cascaded architecture. The cascaded architecture commonly referred to as the MASH architecture is the best architecture that uses a low-end architecture to achieve high-end, high-efficiency and high stability. One of the most important factors affecting the performance of the MASH architecture is the mismatch of circuit components, which affects its performance because they are very sensitive to process, voltage, and temperature changes. In order to overcome the mismatch problem, careful design and layout are essential for analog circuits.

Among them, the data sampling/holding (Sample & Hold) circuit plays a very important role in the analog-to-digital converter. At present, the main sampling techniques include switched capacitive (SC) and switched current (SI). Switched capacitive type (SC) mainly uses capacitors to store data to achieve the sampling function, and switched current type (SI) uses parasitic capacitance (Cgs) between the gate and source of MOSFET to memorize data; compared with switched capacitive type, switching The current type is more attractive due to its high speed, low power supply voltage and small chip area. However, the switching current mode has defects such as transmission error, pulse penetration effect, and non-linearity. Based on the above-mentioned deficiencies, the prior art has developed different technologies to improve the above-mentioned shortcomings of the switching current circuit. By using the minimum sampling sampling switch to optimize the pulse penetration effect, the transmission can be improved with the help of the feedback memory cell (FMC). Error, the input impedance is reduced by two times; the design of the common mode circuit (CMFF) eliminates the offset current, thereby solving the problem of non-linearity.

Although the above-mentioned switching current feedback memory unit has low input impedance and small transmission error, it is still limited by the mismatched process parameter variation, the transmission error of the circuit structure, and the MOS as the switch and the memory element. There is still room for improvement due to non-ideal effects such as the pulse penetration effect and the inherent noise of the active component itself.

The main purpose of the present invention is to provide a low-input impedance current sample-and-hold circuit module, which is equipped with the integrator of the delta-sigma analog-to-digital converter. The low input impedance current sample-and-hold circuit module includes a common mode feedforward circuit, a first current switch feedback memory circuit connected to the first differential input terminal of the common mode feedforward circuit, and a first current switch feedback memory circuit connected to the common mode front The second current switch at the second differential input terminal of the feed circuit feeds back the memory circuit. The first current switch feedback memory circuit is connected to the first switch of the first differential input terminal by a first clock signal, and the second current switch feedback memory circuit is connected to the second switch by a second clock signal. The second switch of the differential input. Wherein, the first current switch feedback memory circuit and the second current switch feedback memory circuit respectively include a reference current circuit, a matching current circuit corresponding to the reference current circuit, and a matching current circuit arranged on the reference current circuit and matching The operational amplifier between the current circuits uses the operational amplifier to reduce the input impedance of the reference current circuit.

；其中，

為輸出端的輸出訊號，

為該第一輸入端的第一量化取樣訊號，

為該第二輸入端的第二量化取樣訊號。 Another object of the present invention is to provide a two-plus-one-order delta-sigma analog-to-digital converter, which includes a digital signal modulator and a digital noise elimination circuit. The digital signal modulator includes a first-stage modulator that receives an external input signal, and a second-stage modulator whose input is connected to the first-stage modulator. The first-stage modulator includes an integral Quantizer, digital-analog converter, and first quantizer to output a first quantized sample signal. The second-stage modulator includes an integrator, a digital-analog converter, and a second quantizer for outputting a second quantized sample signal, wherein The integrator includes a low-input impedance current sample-and-hold circuit module, the low-input impedance current sample-and-hold circuit module includes a common-mode feedforward circuit, and a first differential input terminal connected to the common-mode feedforward circuit. A current switch feedback memory circuit, and a second current switch feedback memory circuit connected to the second differential input terminal of the common mode feedforward circuit, the first current switch feedback memory circuit is switched and connected by the first clock signal To the first switch of the first differential input terminal, the second current switch feedback memory circuit is connected to the second switch of the second differential input terminal by a second clock signal, wherein the first current switch feedback The memory circuit and the second current switch feedback memory circuit respectively include a reference current circuit, a matching current circuit corresponding to the reference current circuit, and an operational amplifier disposed between the reference current circuit and the matching current circuit, by The operational amplifier reduces the input impedance of the reference current circuit. The digital noise canceling circuit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is used to receive the first quantized sample signal, and the second input terminal is used to receive the second For the quantized sample signal, the output signal of the output terminal and the first quantized sample signal and the second quantized sample signal conform to the following relationship:

;among them,

Is the output signal of the output terminal,

Is the first quantized sample signal of the first input terminal,

Is the second quantized sample signal of the second input terminal.

Therefore, compared with the known technology, the present invention has the following advantages:

1. Compared with the traditional feedback memory cell (Feedback Memory Cell), the present invention can greatly reduce the input impedance, thereby reducing the transmission error.

2. The present invention revises and accelerates the response circuit and brings a stable output current through an improved feedback memory circuit (FMC) with a differential interleaved common mode circuit.

The detailed description and technical content of the present invention will now be described in conjunction with the drawings as follows. Furthermore, the figures in the present invention are not necessarily drawn according to actual proportions for the convenience of description, and these figures and their proportions are not used to limit the scope of the present invention, and are described here first.

The present invention mainly discloses a sample-and-hold circuit module 100 for a third-order (two plus one-order) multi-stage noise frequency shift (Multi-Stage Noise Shaping, MASH) delta-sigma modulator. In the specific implementation of the present invention, the feedback memory circuit finally used can reduce the input impedance by (1+A) times, which is much better than the traditional feedback memory circuit which can only reduce the input impedance by 2 times. As a result, compared with the conventional feedback memory circuit, the feedback memory circuit used in the present invention can increase the transmission speed and accuracy to reduce the transmission error. In addition, the staggered common-mode feedforward circuit (CMFF) can further improve the stability of the common-mode potential, thereby quickly responding to the circuit level and bringing a stable output current. Finally, the proposed digital noise elimination circuit can reduce the high-level quantization noise of the last stage, and at the same time eliminate the low-level quantization noise from the early stage of the modulator.

Regarding the specific implementation of the present invention, please refer to "FIG. 1" and "FIG. 2" below to disclose the block diagram of the delta-sigma analog-to-digital converter and the block diagram of the integrator in the present invention, as shown in the figure:

"Figure 1" shows a block diagram of a delta-sigma analog-to-digital converter 100 with a Digital Noise Cancellation Circuit (DNCC). The proposed delta-sigma analog-to-digital converter 100 includes a digital signal modulator 10 (Digital Signal Modulator, DSM) and the back-end digital noise cancellation circuit 20 (Digital Noise Cancellation Circuit, DNCC). The digital signal modulator 10 includes a first-stage modulator 11 and a second-stage modulator 12. As shown in FIG. 1, the analog coefficients of the delta-sigma analog-to-digital converter 100 are listed in Table 1 below. Table 1. The simulation coefficients of the fourth-order multi-stage noise frequency-shift delta-integral modulator Codename a ₁ b ₁ a ₂ b ₂ a ₃ b ₃ a ₄ b ₄ Simulation coefficient 0.5 1 0.5 1 0.5 1 2 1

、

)的操作，如「圖2」所示。 The main components of the digital signal modulator 10 include an integrator, a 1-bit quantizer, a digital-analog converter (DAC), and a non-overlapping clock generator. The performance of the overall digital signal modulator 10 is determined by two cascaded integrators (the first-stage modulator 11 and the second-stage modulator 12). Each one modulator consists of two integrators D1, D2 (integrator D3, D4) composed by the first sample and hold circuit SH1 and second sample and hold circuit SH2 establish an integrator, also known as delay unit (Z ^{- 1} ). The non-overlapping clock generator is used to control the switch in the sample-and-hold circuit (

,

) Operation, as shown in "Figure 2".

Specifically, the digital signal modulator 10 mainly includes four integrators (a first integrator D1, a second integrator D2, a third integrator D3, and a fourth integrator D4) and four digital analog converters ( The first digital-to-analog converter b ₁ , the second digital-to-analog converter b ₂ , the third digital-to-analog converter b ₃ , and the fourth digital-to-analog converter b _{4 )} , two 1-bit quantizers (first quantizer Q1) , Second quantizer Q2), four coefficient adjusters (first coefficient adjuster a ₁ , second coefficient adjuster a ₂ , third coefficient adjuster a ₃ , fourth coefficient adjuster a ₄₎ , one overlap Pulse generator (the figure is omitted), and a bias current generator (the figure is omitted). In a digital signal modulator 10, a first integrator D1 for receiving an external input signal IN and the first digital to analog converter output signal b of subtraction of _1, the first coefficient to produce a first adjuster through a ₁ output signal; a first output signal the output signal will be a second digital to analog converter and b _{2-subtraction,} and the subtraction result to the second integrator D2, then D2 by the second integrator via a second coefficient The adjuster a ₂ generates a second output signal; then, the second output signal is output to the first quantizer Q1; in addition, the third output signal generated by the output terminal of the first quantizer Q1 is connected to the first quantizer Q1. digital to analog converter _{b. 1} and a second digital to analog converter b ₂ inputs, and digital to eliminate a first receiving-end circuit 20 is 21, and by the first digital to analog converter _{b. 1} the output signal fed back to the first integrator D1, a second digital to analog converter output signal b _2-will be fed back to D2 of the second integrator; above the first stage 11 of the modulator architecture.

Meanwhile, the second output signal will be subtracted from the third digital to analog converter output signal b _3, and the subtraction result to the third integrator D3, and then adjusted by the third integrator via a third coefficient D3 A ₃ generates a fourth output signal; the fourth output signal _{is subtracted from the output signal of the fourth digital-to-analog converter b 4} , and the subtracted result is sent to the fourth integrator D4, which is then integrated by the fourth The fifth output signal generated by the fourth integrator D4 is connected to the input terminal of the second quantizer Q2 through the fourth coefficient adjuster a ₄ and the fifth output signal generated by the fourth integrator D4 is connected to the input terminal of the second quantizer Q2 through the second quantization. Q2 is generating a sixth output signal; the sixth output signal are simultaneously connected to a third digital to analog converter b ₃ and fourth digital to analog converter input digit b ₄ and a second receiving terminal elimination circuit 20 is 22, and D4 by the third digital to analog converter b ₃ and the fourth digital to analog converter output signal b ₄ will be fed back to the third integrator and a fourth integrator D3.

與

)來實現一切換電流式延遲單元D，以降低輸入阻抗同時減小傳輸誤差。 For the block diagram of the switching current type delay unit, please refer to "Figure 2". It is mainly composed of two first sample-and-hold circuits SH1, second sample-and-hold circuit SH2, and two non-overlapping clocks

versus

) To implement a switching current-type delay unit D to reduce the input impedance while reducing the transmission error.

Regarding the structure of the current sample-and-hold circuit module (SH1, SH2), please refer to "Figure 3", "Figure 4" and "Figure 5" together below to disclose the circuit diagram of the current sample-and-hold circuit module of the present invention. (1), the schematic diagram of the circuit (2), and the schematic diagram of the equivalent circuit, as shown in the figure:

In this embodiment, the current sample-and-hold circuit module SH mainly includes a common mode feedforward circuit CMF, a first current switch feedback memory circuit FMC1 connected to the first differential input terminal of the common mode feedforward circuit CMF, And a second current switch feedback memory circuit FMC2 connected to the second differential input terminal of the common mode feedforward circuit CMF, and the first current switch feedback memory circuit FMC1 is switched from the first clock signal to the first difference The first switch SW1 of the active input terminal, the second current switch feedback memory circuit FMC2 is connected to the second switch SW2 of the second differential input terminal by a second clock signal, wherein the first current switch feedback memory circuit FMC1 and the second current switch feedback memory circuit FMC2 respectively include a reference current circuit IRF1 (reference current circuit IRF2) and a matching current circuit IMA1 (matching current circuit IMA2) corresponding to the reference current circuit IRF1 (reference current circuit IRF2) ), and an operational amplifier AP1 (operational amplifier AP2) arranged between the reference current circuit IRF1 (reference current circuit IRF2) and the matching current circuit IMA1 (matching current circuit IMA2), by means of the operational amplifier AP1 (operational amplifier AP2) ) Reduce the input impedance of the reference current circuit IRF1 (reference current circuit IRF2).

The reference current circuit IRF1 includes a first P-type field effect transistor M1 and a first N-type field effect transistor M2. The source of the first P-type field effect transistor M1 is connected to the power supply voltage V _CC , The drain of the first P-type field effect transistor M1 is connected to the drain of the first N-type field effect transistor M2, and the source of the first N-type field effect transistor M2 is connected to the ground terminal G, The current signal input terminal ISS is fed between the drain of the first P-type field effect transistor M1 and the drain of a first N-type field effect transistor M2. The drain is connected to the gate of the first N-type field effect transistor M2; the matching current circuit IMA1 includes a second P-type field effect transistor M3 and a second N-type field effect transistor M4. The source of the two P-type field effect transistors M3 is connected to the power supply voltage V _CC , the drain of the second P-type field effect transistor M3 is connected to the drain of the second N-type field effect transistor M4, The source of the second N-type field effect transistor M4 is connected to the ground terminal G, and the drain of the second P-type field effect transistor M3 is connected to the gate of the second P-type field effect transistor M3, Wherein, the gate of the first P-type field effect transistor M1 is connected to the gate of the second P-type field effect transistor M3, and the input terminal of the operational amplifier AP1 is connected to the first N-type field effect transistor. The gate of the crystal M2, and the output terminal of the operational amplifier AP1 is connected to the gate of the second N-type field effect transistor M4. Among them, the first P-type field effect transistor M11, the second P-type field effect transistor M9, the first N-type field effect transistor M12, the second N-type field effect transistor M10 of the reference current circuit IRF2 and the reference current The circuit IRF1 is a symmetrical design.

The first current switch feedback memory circuit FMC1 is connected to the back end of its matching current circuit IMA1 with a first common mode feedback circuit CF1, and the second current switch feedback memory circuit FMC2 is connected to the back end of its matching current circuit IMA2. A second common mode feedback circuit CF2, the first common mode feedback circuit CF1 is connected to the second common mode feedback circuit CF2 to balance the first current switch feedback memory circuit FMC1 and the second current switch feedback The common mode point level of the memory circuit FMC2.

The first common mode feedback circuit CF1 includes a third P-type field effect transistor M5 and a third N-type field effect transistor M6. The source of the third P-type field effect transistor M5 is connected to the Power supply voltage V _CC , the gate of the third P-type field effect transistor M5 is connected to the gate of the second P-type field effect transistor M3 of the first current switch feedback memory circuit FMC1, and the third N-type The source of the field effect transistor M6 is connected to the ground terminal G, and the gate of the third N-type field effect transistor M6 is connected to the second N-type field effect of the first current switch feedback memory circuit FMC1 The drain of the transistor M4; the second common mode feedback circuit CF2 includes a fourth P-type field effect transistor M7, and a fourth N-type field effect transistor M8, the fourth P-type field effect transistor M7 The source of is connected to the power supply voltage, the gate of the fourth P-type field effect transistor M7 is connected to the gate of the second P-type field effect transistor M9 of the second current switch feedback memory circuit FMC2, The source of the fourth N-type field effect transistor M8 is connected to the ground terminal G, and the gate of the fourth N-type field effect transistor M8 is connected to the second current switch feedback memory circuit FMC2. Two drains of the N-type field effect transistor M10; wherein the drain (A) of the third P-type field effect transistor M5 is connected to the drain (A) of the fourth N-type field effect transistor M8, The drain (B) of the fourth P-type field effect transistor M7 is connected to the drain (B) of the third N-type field effect transistor M6.

；

； As shown in "Figure 4" and "Figure 5", according to the small signal model of the current sample-and-hold circuit module, the current transfer function is given by the following formula:

；

；

是第一N型場效電晶體M2的轉導、

是第五N型場效電晶體M13的轉導、

是第六N型場效電晶體M14的轉導、

是第二N型場效電晶體M4的轉導、

是第七N型場效電晶體M15的轉導、

是第一P型場效電晶體M1的轉導、

是第二P型場效電晶體M3的轉導。

等於[

]是電子控制的回授電阻，其中

是第五N型場效電晶體M13的輸出阻抗、其中

是第六N型場效電晶體M14的輸出阻抗。

是節點電壓

相對於節點電壓

的轉移函數(Transfer Function)。其中，輸出電流

等於

，輸入阻抗

可由下式給出：

； among them

It is the first N-type field effect transistor M2's transconductance,

It is the transconductance of the fifth N-type field effect transistor M13,

It is the transconductance of the sixth N-type field effect transistor M14,

It is the transconductance of the second N-type field effect transistor M4,

It is the transconductance of the seventh N-type field effect transistor M15,

It is the transconductance of the first P-type field effect transistor M1,

It is the transduction of the second P-type field effect transistor M3.

equal[

] Is an electronically controlled feedback resistor, where

Is the output impedance of the fifth N-type field effect transistor M13, where

It is the output impedance of the sixth N-type field effect transistor M14.

Is the node voltage

Relative to node voltage

The transfer function (Transfer Function). Among them, the output current

equal

,input resistance

It can be given by the following formula:

；

和

，經修改後電流開關回授記憶電路的輸入阻抗可以簡化為以下的式子：

； By appropriately adjusting the metric ratio, control

with

, After the modification, the input impedance of the current switch feedback memory circuit can be simplified to the following formula:

；

)/2倍，由於輸入阻抗的下降使得傳輸誤差大幅地降低。改良後的切換電流式回授記憶電路後端係配合設置耦合差動複製(Coupled Differential Replicate, CDR)的共模前饋電路CMF，透過該共模前饋電路CMF改善製程變異所導致的共模輸出準位漂移，使得共模位準的輸出穩定，當輸出至下一級電路時不影響其信號位準。如圖3所示，所述的共模前饋電路CMF利用場效電晶體M16、M17、M18所產生的補償電流吸引差動對場效電晶體M24、M20的誤差電流，使得共模輸出

可維持固定；同樣的，所述的共模前饋電路CMF利用場效電晶體M21、M22、M23所產生的補償電流吸引差動對場效電晶體M25、M19的誤差電流，使得共模輸出

可維持固定，透過上述的配置可大量改善傳輸誤差。 As shown in the above formula, it can be seen that the architecture of the present invention compared with the traditional feedback memory unit (1/2 times), the input impedance is further reduced (

)/2 times, the transmission error is greatly reduced due to the drop in input impedance. The back end of the improved switching current feedback memory circuit is equipped with a coupled differential replication (Coupled Differential Replicate, CDR) common mode feedforward circuit CMF, and the common mode caused by process variation is improved through the common mode feedforward circuit CMF. The output level drifts, so that the output of the common mode level is stable, and the signal level is not affected when output to the next-stage circuit. As shown in Figure 3, the common mode feedforward circuit CMF uses the compensation current generated by the field effect transistors M16, M17, and M18 to attract the error current of the differential pair field effect transistors M24, M20, so that the common mode output

It can be kept fixed; similarly, the common mode feedforward circuit CMF uses the compensation current generated by the field effect transistors M21, M22, M23 to attract the error current of the differential pair field effect transistors M25, M19, so that the common mode output

It can be kept fixed, and the transmission error can be greatly improved through the above configuration.

Please refer to "FIG. 6" and "FIG. 7" below to show the block diagram of the digital noise elimination circuit and the block diagram of the D-type flip-flop in the present invention, as shown in the figure:

The digital noise cancellation circuit 20 includes a first input terminal P1, a second input terminal P2, an output terminal P3, a delay 21, a first first-order difference operator 22, a second first-order difference operator 23, a first The coefficient adjuster d1 and the second coefficient adjuster d2.

The first quantized sample signal input from the first input terminal P1 is sent to the delayer 21 through the first coefficient adjuster d1, and the delayer 21 receives the first quantized sample signal according to the first quantized sample signal. The sampling signal generates a first output signal.

The second quantized sampling signal input from the second input terminal P2 is subtracted from the first output signal after passing through the second coefficient adjuster d2, and then input to the first first-order difference operator 22 and output a second Output signal; the second output signal is input to the second first-order differential arithmetic unit 23 and outputs a third output signal, the third output signal is added to the first output signal to output a fourth output signal to the output terminal P3.

可表示如下面的式子：

； "FIG. 6" shows a mathematical model of the Digital Noise Cancellation Circuit (DNCC) 20 (Digital Noise Cancellation Circuit, DNCC). Output

It can be expressed as the following formula:

；

和

分別用1.0和4.0表示，因此上述等式可以修改為下列的式子：

； Where the coefficient

with

Expressed by 1.0 and 4.0, respectively, so the above equation can be modified to the following equation:

；

，

，

，

，

。輸出數字介於-19和+19之間，分別作為A，B，C，D和E的輸入函數。6位元數字，從S1到S6，以2補數形式，用於表示輸出數字。其中S6是輸出數字的最高有效位元(Most Significant Bit, MSB)，S1是輸出數字的最低有效位元(Least Significant Bit, LSB)。 如上面的式子所示，實現數位雜訊消除電路20需要五個延遲單元(分別對應A、B、C、D、E)，可以使用一對D型正反器FF1、FF2(如圖7所示)產生一個延遲單元(

)，如圖7所示，非重疊時脈信號

、

分別輸出至該D型正反器FF1、及FF2，使用一對D型正反器FF1、FF2產生一個單位延遲(

)。該輸出數字可寫為： S6=Ʃm(0,2,3,6,7,8,10,11,14,15,18,19,22,26,27,30)； S5=Ʃm(0,3,6,7,8,11,14,15,18,19,21,22,26,27,29,30)； S4=Ʃm(0,2,5,7,8,10,13,15,17,19,20,22,25,27,28,30)； S3=Ʃm(0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15)； S2=Ʃm(0,1,2,3,4,5,6,7,16,17,18,19,20,21,22,23)； S1=1。 among them

,

,

,

,

. The output numbers are between -19 and +19 as input functions for A, B, C, D, and E, respectively. 6 digits, from S1 to S6, in the form of 2's complement, used to represent the output number. Among them, S6 is the most significant bit (Most Significant Bit, MSB) of the output number, and S1 is the least significant bit (Least Significant Bit, LSB) of the output number. As shown in the above formula, five delay units (respectively corresponding to A, B, C, D, E) are needed to realize the digital noise cancellation circuit 20, and a pair of D-type flip-flops FF1 and FF2 can be used (Figure 7 Shown) generates a delay unit (

), as shown in Figure 7, non-overlapping clock signal

,

Output to the D-type flip-flops FF1 and FF2 respectively, and use a pair of D-type flip-flops FF1 and FF2 to generate a unit delay (

). The output number can be written as: S6=Ʃm(0,2,3,6,7,8,10,11,14,15,18,19,22,26,27,30); S5=Ʃm(0, 3,6,7,8,11,14,15,18,19,21,22,26,27,29,30); S4=Ʃm(0,2,5,7,8,10,13,15 ,17,19,20,22,25,27,28,30); S3=Ʃm(0,1,2,3,4,5,6,7,8,9,10,11,12,13, 14,15); S2=Ʃm(0,1,2,3,4,5,6,7,16,17,18,19,20,21,22,23); S1=1.

；

；

；

；

； The above numbers can be simplified through Karnaugh map and Bollinger expressions. The Boolean expressions of S6, S5, S4, S3, and S2 are as follows:

；

；

；

；

；

將被延遲3個單位

和4個單位

以分別產生

和

；此外，輸入

以產生

，並且延遲1個單位

和2個單位

以分別產生

和

。其中，DNCC於六位元2的補數表格對應如下： 物件 輸入 輸出 2的補數值 A B C D E Y = F+G S ₆ S ₅ S ₄ S ₃ S ₂ S ₁ 0 -1 -1 -1 -1 -1 -1 1 1 1 1 1 1 1 -1 -1 -1 -1 1 7 0 0 0 1 1 1 2 -1 -1 -1 1 -1 -17 1 0 1 1 1 1 3 -1 -1 -1 1 1 -9 1 1 0 1 1 1 4 -1 -1 1 -1 -1 7 0 0 0 1 1 1 5 -1 -1 1 -1 1 15 0 0 1 1 1 1 6 -1 -1 1 1 -1 -9 1 1 0 1 1 1 7 -1 -1 1 1 1 -1 1 1 1 1 1 1 8 -1 1 -1 -1 -1 -3 1 1 1 1 0 1 9 -1 1 -1 -1 1 5 0 0 0 1 0 1 10 -1 1 -1 1 -1 -19 1 0 1 1 0 1 11 -1 1 -1 1 1 -11 1 1 0 1 0 1 12 -1 1 1 -1 -1 5 0 0 0 1 0 1 13 -1 1 1 -1 1 13 0 0 1 1 0 1 14 -1 1 1 1 -1 -11 1 1 0 1 0 1 15 -1 1 1 1 1 -3 1 1 1 1 0 1 16 1 -1 -1 -1 -1 3 0 0 0 0 1 1 17 1 -1 -1 -1 1 11 0 0 1 0 1 1 18 1 -1 -1 1 -1 -13 1 1 0 0 1 1 19 1 -1 -1 1 1 -5 1 1 1 0 1 1 20 1 -1 1 -1 -1 11 0 0 1 0 1 1 21 1 -1 1 -1 1 19 0 1 0 0 1 1 22 1 -1 1 1 -1 -5 1 1 1 0 1 1 23 1 -1 1 1 1 3 0 0 0 0 1 1 24 1 1 -1 -1 -1 1 0 0 0 0 0 1 25 1 1 -1 -1 1 9 0 0 1 0 0 1 26 1 1 -1 1 -1 -15 1 1 0 0 0 1 27 1 1 -1 1 1 -7 1 1 1 0 0 1 28 1 1 1 -1 -1 9 0 0 1 0 0 1 29 1 1 1 -1 1 17 0 1 0 0 0 1 30 1 1 1 1 -1 -7 1 1 1 0 0 1 31 1 1 1 1 1 1 0 0 0 0 0 1 "Figure 8" shows the analog input of the proposed DNCC realized by the proposed algorithm, the input

Will be delayed by 3 units

And 4 units

To produce separately

with

; In addition, enter

To produce

And delayed by 1 unit

And 2 units

To produce separately

with

. Among them, the DNCC in the six-bit 2's complement table corresponds to the following: object enter Output 2's complement A B C D E Y = F+G S ₆ S ₅ S ₄ S ₃ S ₂ S ₁ 0 -1 -1 -1 -1 -1 -1 1 1 1 1 1 1 1 -1 -1 -1 -1 1 7 0 0 0 1 1 1 2 -1 -1 -1 1 -1 -17 1 0 1 1 1 1 3 -1 -1 -1 1 1 -9 1 1 0 1 1 1 4 -1 -1 1 -1 -1 7 0 0 0 1 1 1 5 -1 -1 1 -1 1 15 0 0 1 1 1 1 6 -1 -1 1 1 -1 -9 1 1 0 1 1 1 7 -1 -1 1 1 1 -1 1 1 1 1 1 1 8 -1 1 -1 -1 -1 -3 1 1 1 1 0 1 9 -1 1 -1 -1 1 5 0 0 0 1 0 1 10 -1 1 -1 1 -1 -19 1 0 1 1 0 1 11 -1 1 -1 1 1 -11 1 1 0 1 0 1 12 -1 1 1 -1 -1 5 0 0 0 1 0 1 13 -1 1 1 -1 1 13 0 0 1 1 0 1 14 -1 1 1 1 -1 -11 1 1 0 1 0 1 15 -1 1 1 1 1 -3 1 1 1 1 0 1 16 1 -1 -1 -1 -1 3 0 0 0 0 1 1 17 1 -1 -1 -1 1 11 0 0 1 0 1 1 18 1 -1 -1 1 -1 -13 1 1 0 0 1 1 19 1 -1 -1 1 1 -5 1 1 1 0 1 1 20 1 -1 1 -1 -1 11 0 0 1 0 1 1 twenty one 1 -1 1 -1 1 19 0 1 0 0 1 1 twenty two 1 -1 1 1 -1 -5 1 1 1 0 1 1 twenty three 1 -1 1 1 1 3 0 0 0 0 1 1 twenty four 1 1 -1 -1 -1 1 0 0 0 0 0 1 25 1 1 -1 -1 1 9 0 0 1 0 0 1 26 1 1 -1 1 -1 -15 1 1 0 0 0 1 27 1 1 -1 1 1 -7 1 1 1 0 0 1 28 1 1 1 -1 -1 9 0 0 1 0 0 1 29 1 1 1 -1 1 17 0 1 0 0 0 1 30 1 1 1 1 -1 -7 1 1 1 0 0 1 31 1 1 1 1 1 1 0 0 0 0 0 1

In one embodiment, for example, A=-1, B=+1, C=-1, D=-1 and E=+1, Y(z)=(2A-B)+(4C-8D+4E) =5, the 2's complement value (S6 to S1) is output as 000101 (as shown in the table above).

Please refer to "Figure 9", "Figure 10" and "Figure 11" below, which reveal the transmission error simulation diagram of the traditional feedback memory circuit and the improved feedback memory circuit, and the linear relationship diagram of the input current and the output current, as shown in the figure Shown:

In "FIG. 9", the simulation diagram of the transmission error percentage of the traditional feedback memory circuit and the improved feedback memory circuit of the present invention is shown. As shown in the figure, the improved feedback memory circuit of the present invention is at ±35μA. Provides a transmission error of approximately 0.1%. In addition, when the feedback memory circuit provides oscillation, the transmission error is actually linear. Therefore, the improved feedback memory circuit provides better stability.

In "Figure 10", the linear relationship between input current and output current is shown; "Figure 11" shows the analog schematic diagram of the current mode sample-and-hold circuit when a sinusoidal input signal is applied. When the frequency is 500 kHz and the amplitude is 25 μA , The sampling frequency is 10.24 MHz, and the over-sampling rate is 256. According to the above-mentioned analog schematic diagram, it is shown that the accuracy and feasibility of the holding circuit of the present invention can achieve quite good performance.

In summary, compared with the traditional feedback memory cell (Feedback Memory Cell), the present invention can greatly reduce the input impedance, thereby reducing the transmission error. In addition, the present invention corrects and accelerates the response circuit and brings stable output current through the improved feedback memory circuit and the differentially interleaved common mode circuit.

The present invention has been described in detail above, but what has been described above is only a preferred embodiment of the present invention. It should not be used to limit the scope of implementation of the present invention, that is, everything made in accordance with the scope of patent application of the present invention is equal Changes and modifications should still fall within the scope of the patent of the present invention.

:非重疊時鐘信號

:非重疊時鐘信號 P1:第一輸入端 P2:第二輸入端 P3:輸出端100: Delta-sigma analog-to-digital converter 10: Digital signal modulator 11: First-stage modulator 12: Second-stage modulator 20: Digital noise elimination circuit SH1: First sample-and-hold circuit SH2: Second sampling Holding circuit D: switching current type delay unit D1: first integrator D2: second integrator D3: third integrator D4: fourth integrator a ₁ : first coefficient adjuster a ₂ : second coefficient adjuster a ₃ : The third coefficient adjuster a ₄ : The fourth coefficient adjuster b ₁ : The first digital analog converter b ₂ : The second digital analog converter b ₃ : The third digital analog converter b ₄ : The fourth digital analog converter Q1: First quantizer Q2: Second quantizer IN: External input signal SH: Current sample-and-hold circuit module FMC1: First current switch feedback memory circuit SW1: First switch IRF1: Reference current circuit M1: First P-type field effect transistor M2: first N-type field effect transistor IMA1: matching current circuit M3: second P-type field effect transistor M4: second N-type field effect transistor AP1: operational amplifier FMC2: second current Switch feedback memory circuit SW2: second switch IRF2: reference current circuit M11: first P-type field effect transistor M12: first N-type field effect transistor IMA2: matching current circuit M9: second P-type field effect transistor M10: second N-type field effect transistor AP2: operational amplifier M13: fifth N-type field effect transistor M14: sixth N-type field effect transistor M15: seventh N-type field effect transistor V _CC : power supply voltage G : Ground terminal ISS: Current signal input terminal CF1: First common mode feedback circuit M5: Third P-type field effect transistor M6: Third N-type field effect transistor CF2: Second common mode feedback circuit M7: No. Four P-type field effect transistor M8: Fourth N-type field effect transistor CMF: Common mode feedforward circuit M16: Field effect transistor M17: Field effect transistor M18: Field effect transistor M19: Field effect transistor M20: Field Effect Transistor M21: Field Effect Transistor M22: Field Effect Transistor M23: Field Effect Transistor M24: Field Effect Transistor M25: Field Effect Transistor FF1: D-type flip-flop FF2: D-type flip-flop

: Non-overlapping clock signal

: Non-overlapping clock signal P1: first input terminal P2: second input terminal P3: output terminal

Fig. 1 is a block diagram of the delta-sigma analog-to-digital converter in the present invention.

Figure 2 is a block diagram of the integrator in the present invention.

FIG. 3 is a schematic circuit diagram (1) of the current sample-and-hold circuit module of the present invention.

4 is a schematic circuit diagram (2) of the current sample-and-hold circuit module of the present invention.

Figure 5 is an equivalent circuit of the current sample-and-hold circuit module of the present invention.

FIG. 6 is a block diagram of the digital noise elimination circuit in the present invention.

Fig. 7 is a block diagram of the D-type flip-flop in the present invention.

Figure 8 is the analog input-output analog waveform diagram of the digital noise cancellation circuit (DNCC).

9 is a simulation diagram of the transmission error percentage of the traditional feedback memory circuit and the improved feedback memory circuit of the present invention.

Figure 10 shows the linear relationship between input current and output current.

Fig. 11 is a simulation diagram of the current mode sample-and-hold circuit when a sinusoidal input signal is applied.

SH: Current sample and hold circuit module

FMC1: The first current switch feedback memory circuit

SW1: The first switch

IRF1: Reference current circuit

M1: The first P-type field effect transistor

M2: The first N-type field effect transistor

IMA1: matching current circuit

M3: The second P-type field effect transistor

M4: The second N-type field effect transistor

AP1: Operational amplifier

FMC2: The second current switch feedback memory circuit

SW2: second switch

IRF2: Reference current circuit

M11: The first P-type field effect transistor

M12: The first N-type field effect transistor

IMA2: matching current circuit

M9: The second P-type field effect transistor

M10: The second N-type field effect transistor

AP2: Operational amplifier

V _CC : Power supply voltage

G: Ground terminal

ISS: Current signal input terminal

CF1: The first common mode feedback circuit

M5: The third P-type field effect transistor

M6: The third N-type field effect transistor

CF2: The second common mode feedback circuit

M7: The fourth P-type field effect transistor

M8: The fourth N-type field effect transistor

CMF: common mode feedforward circuit

M16: Field Effect Transistor

M17: Field Effect Transistor

M18: Field Effect Transistor

M19: Field Effect Transistor

M20: Field Effect Transistor

M21: Field Effect Transistor

M22: Field Effect Transistor

M23: Field Effect Transistor

M24: Field Effect Transistor

M25: field effect transistor

Claims (6)

A low-input impedance current sample-and-hold circuit module, matched with the integrator of a delta-sigma analog-to-digital converter. The low-input impedance current sample-and-hold circuit module includes a common-mode feedforward circuit and a common-mode feedforward circuit. A first current switch feedback memory circuit at the first differential input terminal of the circuit, and a second current switch feedback memory circuit connected to the second differential input terminal of the common mode feedforward circuit, the first current switch feedback memory circuit The first switch connected to the first differential input terminal is switched by the first clock signal, the second current switch feedback memory circuit is switched connected to the second switch of the second differential input terminal by the second clock signal, wherein , The first current switch feedback memory circuit and the second current switch feedback memory circuit respectively include a reference current circuit, a matching current circuit corresponding to the reference current circuit, and a reference current circuit and a matching current The operational amplifier between the circuits uses the operational amplifier to reduce the input impedance of the reference current circuit. The low-input impedance current sample-and-hold circuit module described in item 1 of the scope of patent application, wherein the reference current circuit includes a first P-type field effect transistor and a first N-type field effect transistor. The source of the first P-type field-effect transistor is connected to the power supply voltage, the drain of the first P-type field-effect transistor is connected to the drain of the first N-type field-effect transistor, the first N-type The source of the field-effect transistor is connected to the ground terminal, and the current signal input terminal is fed between the drain of the first P-type field-effect transistor and the drain of a first N-type field-effect transistor. The drain of the first N-type field effect transistor is connected to the gate of the first N-type field effect transistor; the matching current circuit includes a second P-type field effect transistor and a second N-type field effect transistor A transistor, the source of the second P-type field effect transistor is connected to the power supply voltage, and the drain of the second P-type field effect transistor is connected to the drain of the second P-type field effect transistor, The source of the second N-type field effect transistor is connected to the ground terminal, and the drain of the second P-type field effect transistor is connected to the gate of the first N-type field effect transistor. The gate of a P-type field-effect transistor is connected to the gate of the second P-type field-effect transistor, and the input terminal of the operational amplifier is connected to the gate of the first N-type field-effect transistor. The output terminal of the amplifier is connected to the gate of the second N-type field effect transistor. The low-input impedance current sample-and-hold circuit module described in item 2 of the scope of patent application, wherein the first current switch feedback memory circuit is connected to a first common mode feedback circuit at the back end of the matching current circuit, The second current switch feedback memory circuit is connected to a second common mode feedback circuit at the back end of the matching current circuit. The first common mode feedback circuit is connected to the second common mode feedback circuit to balance the first common mode feedback circuit. The common mode level of a current switch feedback memory circuit and the second current switch feedback memory circuit. The low-input impedance current sample-and-hold circuit module described in item 3 of the scope of patent application, wherein the first common mode feedback circuit includes a third P-type field effect transistor and a third N-type field effect The source of the third P-type field effect transistor is connected to the power supply voltage, and the gate of the third P-type field effect transistor is connected to the second P of the first current switch feedback memory circuit. The gate electrode of the third N-type field effect transistor is connected to the ground terminal, and the gate electrode of the third N-type field effect transistor is connected to the first current switch feedback The drain of the second N-type field effect transistor of the memory circuit; the second common mode feedback circuit includes a fourth P-type field effect transistor and a fourth N-type field effect transistor, the fourth P The source of the P-type field effect transistor is connected to the power supply voltage, and the gate of the fourth P-type field effect transistor is connected to the gate of the second P-type field effect transistor of the second current switch feedback memory circuit. The source of the fourth N-type field effect transistor is connected to the ground terminal, and the gate of the fourth N-type field effect transistor is connected to the second N of the second current switch feedback memory circuit. The drain of the third P-type field effect transistor is connected to the drain of the fourth N-type field effect transistor, and the drain of the fourth P-type field effect transistor is The pole is connected to the drain of the third N-type field effect transistor. A two-plus-one-order delta-sigma analog-to-digital converter includes: a digital signal modulator, including a first-stage modulator that receives an external input signal, and a first-stage modulator with an input connected to the first-stage modulator A two-stage modulator, the first-stage modulator includes an integrator, a digital-to-analog converter, and a first quantizer to output a first quantized sample signal, and the second-stage modulator includes an integrator and a digital-to-analog converter And the second quantizer is used to output a second quantized sampling signal, wherein the integrator includes a low input impedance current sample and hold circuit module, and the low input impedance current sample and hold circuit module includes a common mode feedforward circuit, a A first current switch feedback memory circuit connected to the first differential input terminal of the common mode feedforward circuit, and a second current switch feedback memory circuit connected to the second differential input terminal of the common mode feedforward circuit, the first A current switch feedback memory circuit is switched from the first clock signal to the first switch connected to the first differential input terminal, and the second current switch feedback memory circuit is switched from the second clock signal to the second differential input terminal The second switch at the input terminal, wherein the first current switch feedback memory circuit and the second current switch feedback memory circuit respectively include a reference current circuit, a matching current circuit corresponding to the reference current circuit, and a The operational amplifier between the reference current circuit and the matching current circuit, through which the operational amplifier reduces the input impedance of the reference current circuit; and a digital noise cancellation circuit, including a first input terminal, a second input terminal, and An output terminal, the first input terminal is used to receive the first quantized sample signal, the second input terminal is used to receive the second quantized sample signal, the output signal of the output terminal is the same as the first quantized sample signal and the second The quantized sampling signals conform to the following relationship:

; among them,

Is the output signal of the output terminal,

Is the first quantized sample signal of the first input terminal,

Is the second quantized sample signal of the second input terminal. For example, the two-plus-one-order delta-sigma analog-to-digital converter described in item 5 of the scope of patent application, wherein the first quantized sample signal input from the first input terminal is transmitted to the delayer after passing through the first coefficient adjuster After receiving the first quantized sample signal, the delayer generates a first output signal according to the first quantized sample signal; The second quantized sample signal input from the second output terminal is subtracted from the first output signal by a subtractor after passing through a second coefficient adjuster, and then input to the first first-order difference operator and output a second coefficient adjuster. Two output signals, the second output signal is input to the second first-order differential arithmetic unit and outputs a third output signal, the third output signal is added to the first output signal via an adder to output a fourth output signal To this output.

Images