TWI718829B - Memory device and method for fabricating the same - Google Patents

Abstract

A memory device includes a substrate. A first dielectric layer is disposed over the substrate. Multiple conductive layers and multiple dielectric layers are alternately and horizontally disposed on the substrate and in the conductive layer and the dielectric layer. A channel column is disposed in the first layer and stands on the substrate. A side wall of the channel column contacts the conductive layers. The channel column contacts the conductive layers. A second layer covers on the first layer. A conductive column is in the first and second layers, adjacent to the channel column and contacting one of the gate layers. The conductive column includes a liner insulating layer as a shell layer.

Description

Memory element and manufacturing method thereof

The present invention relates to semiconductor manufacturing, and particularly relates to memory devices and manufacturing methods thereof.

Memory components are essential components in digital electronic devices. When the processing function of the electronic device is greatly improved, the memory capacity of the memory device should be increased accordingly, and at the same time, the trend of reducing the size of the memory device should be maintained.

In response to demand, a three-dimensional NAND memory has been proposed. It is a flash memory. The structure is changed from a two-dimensional NAND memory to a three-dimensional structure. The channel layer is modified to a vertical channel structure perpendicular to the substrate, which is a channel column. (channel column) structure. The multi-layer character line layers are stacked in a direction perpendicular to the substrate to form a string of transistors. The end of the character line layer is a staircase-like structure, and the character line is connected upward to an external control circuit through a conductive pillar. In this way, under the three-dimensional structure, the transistor can be manufactured in a vertical direction, which can increase the memory capacity.

However, due to the limited area of the component, the lateral two-dimensional area still needs To reduce significantly, a high-density configuration is required for a large number of conductive pillar structures and channel pillar structures, and the distance between the pillars needs to be reduced. As the number of word line layers provided by the conductive pillar structure has been greatly increased, the lengths of the conductive pillar structure and the channel pillar structure are also increased to be connected to the upper control circuit.

Under this demand, how to arrange the configuration of the conductive column structure and the channel column structure is a need to consider.

In the memory device of the present invention, the conductive pillar structure is proposed in the manufacture of the conductive pillar structure and the channel pillar structure. Under the requirement that the distance between the conductive pillar structure and the channel pillar structure is reduced and the length thereof is greatly increased, the conductive pillars can be effectively reduced. The phenomenon of leakage or even short circuit at the end between the structure and the channel column structure.

In one embodiment, the present invention provides a memory device including a substrate. The first dielectric layer is disposed above the substrate. Multiple conductive layers and multiple dielectric layers are alternately and horizontally arranged on the substrate. The channel pillar structure is arranged on the substrate and in the multilayer conductive layer and the multilayer dielectric layer. The sidewall of the channel pillar structure is in contact with the multi-layer conductive layer. The second dielectric layer covers the first dielectric layer. The conductive pillar structure is in the first and second dielectric layers, adjacent to the channel pillar structure, and is in contact with one of the multilayer conductive layers. The conductive pillar structure includes an insulating lining layer as an outer layer.

In one embodiment, for the memory device, the channel pillar structure includes a silicon pillar perpendicular to the substrate and a charge storage layer. The charge storage layer covers the silicon pillar. The charge storage layer is in contact with the multilayer conductive layer. The silicon pillar provides a channel corresponding to each layer of the conductive layer.

In one embodiment, for the memory device described above, the charge storage layer is an oxide/nitride/oxide laminated structure.

In one embodiment, for the memory device, the conductive pillar structure includes a conductive central pillar perpendicular to the substrate, and is in contact with a predetermined one of the multilayer conductive layers. The insulating lining layer covers the conductive central pillar and assists in isolating the conductive central pillar from the channel pillar structure.

In one embodiment, for the memory device, the material of the conductive center post includes tungsten, copper, cobalt, silicon, or polysilicon.

In one embodiment, for the memory device, the liner insulating layer is silicon oxide, high-density plasma (HDP) dielectric, tetraethoxysilane (TEOS), thermal oxide or high-k dielectric Electricity.

In one embodiment, for the memory device, the contact surface of the upper end of the insulating liner layer and the conductive central pillar is an oblique curved surface.

In one embodiment, for the memory device described above, the bottom surface of the conductive central pillar includes a portion protruding in a lateral direction.

In one embodiment, for the memory device, the conductive pillar structure is higher than the channel pillar structure.

In one embodiment, for the memory device, the length of the conductive pillar structure is 3 micrometers or more than 3 micrometers.

In one embodiment, the present invention provides a method of manufacturing a memory device, including providing a substrate. A first dielectric layer is formed over the substrate. Multiple conductive layers and dielectric layers are formed alternately and horizontally arranged on the substrate. To form a channel column structure in the On the substrate and in the multilayer conductive layer and the multilayer dielectric layer, the sidewall of the channel pillar structure is in contact with the multilayer conductive layer. A second dielectric layer is formed to cover the first dielectric layer. A conductive pillar structure is formed in the first and second dielectric layers, adjacent to the channel pillar structure, and in contact with one of the multilayer conductive layers, wherein the conductive pillar structure includes an insulating lining layer as an outer layer.

In one embodiment, for the method of manufacturing a memory device, the step of forming the channel column structure includes forming a columnar recess in the first dielectric layer and passing through the multilayer conductive layer. A charge storage layer is formed on the sidewall of the columnar recess, wherein the charge storage layer is in contact with the multilayer conductive layer. A silicon pillar is formed to fill the pillar-shaped recess on the charge storage layer, wherein the silicon pillar provides a channel area corresponding to each layer of the conductive layer.

In one embodiment, for the method of manufacturing a memory device, the charge storage layer is an oxide/nitride/oxide laminated structure.

In one embodiment, for the method of manufacturing a memory device, the step of forming the conductive column structure includes forming columnar recesses in the first and second dielectric layers, and extending into the predetermined predetermined in the multilayer conductive layer One of them. Forming the insulating liner layer on the sidewall of the columnar recess. The columnar recess is filled with a conductive material to form a conductive central column, which is in contact with the predetermined one of the multiple conductive layers. The insulating liner layer covers the conductive material and also provides isolation between the conductive material and the channel column structure.

In one embodiment, for the method of manufacturing a memory device, the conductive material includes tungsten, copper, cobalt, silicon, or polysilicon.

In one embodiment, for the method of manufacturing a memory device, the material of the liner insulating layer includes silicon oxide, high-density plasma (HDP) dielectric, tetraethoxysilane (TEOS), thermal oxide, or High dielectric constant dielectric.

In one embodiment, for the method of manufacturing a memory device, the upper end of the insulating liner layer has an oblique curved surface structure generated after the insulating liner layer is etched back.

In one embodiment, for the method of manufacturing a memory device, the bottom surface of the conductive central pillar includes a portion protruding in the lateral direction, and this portion occupies the displacement caused by the surface cleaning performed before filling the conductive material. In addition to space.

In one embodiment, for the method of manufacturing a memory device, the conductive pillar structure is higher than the channel pillar structure.

In one embodiment, for the method for manufacturing a memory device, the length of the conductive pillar structure is 3 μm or more than 3 μm.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

100: substrate

102: Dielectric layer

104: conductive layer

106: first dielectric layer

108: Center Column

110: Silica column

112: charge storage layer

114: Channel column structure

118: Conductive pillar structure

120: second dielectric layer

122: Lining insulation layer

130: sunken

200: Conductive center column

202: Lining insulating layer

204: Conductive pillar structure

210: upper end

212: lower end

FIG. 1 is a schematic diagram of defects existing between the conductive pillar structure and the channel pillar structure explored according to the present invention.

2 is a schematic cross-sectional structure diagram of a conductive pillar structure and a channel pillar structure of a memory device according to an embodiment of the present invention.

3A to 3D are guides for manufacturing a memory device according to an embodiment of the present invention Schematic diagram of the flow of the electric column structure and the channel column structure.

4 is a schematic diagram of a cross-sectional structure of a conductive pillar structure and a channel pillar structure according to an embodiment of the present invention.

5 is a schematic cross-sectional structure diagram of a conductive pillar structure and a channel pillar structure according to an embodiment of the present invention.

The present invention proposes that the memory element can increase the isolation effect between the conductive pillar structure and the channel pillar structure by changing the conductive pillar structure and the channel pillar structure. In this way, as the distance between the conductive pillar structure and the channel pillar structure is reduced and the length thereof is greatly increased, the phenomenon of leakage or even short-circuit at the end between the conductive pillar structure and the channel pillar structure can be effectively reduced.

A number of embodiments are described below, but the present invention is not limited to the described embodiments. In addition, appropriate combinations between multiple embodiments are also allowed.

The present invention looks into the structure of the three-dimensional NAND memory device. FIG. 1 is a schematic diagram of defects existing between the conductive pillar structure and the channel pillar structure explored according to the present invention.

Referring to FIG. 1, for a three-dimensional NAND memory device, a series of transistors are arranged along the channel column structure 114 perpendicular to the substrate 100. The channel pillar structure 114 includes a silicon pillar 110 in the middle and a charge storage layer 112 covering the silicon pillar 110. The silicon column 110 is, for example, a hollow polycrystalline silicon column. According to the manufacturing method, the central pillar 108 is formed by filling the oxide layer later. Alternatively, it may be filled with polysilicon to form a solid silicon pillar 110. The present invention does not need to limit the specific structure of the channel column structure 114. Silicon The pillar structure 110 provides the channel layer required by the transistor. The charge storage layer 112 is, for example, an oxide/nitride/oxide (ONO) structure. The multi-layer conductive layer 104 is also used as a word line to control the gate electrode of the corresponding transistor on the channel column structure 114. According to the number of transistors in a string of NAND, at least the same number of conductive layers 104 are provided. The conductive layers 104 are isolated and supported by the dielectric layer 102. In this way, the multilayer dielectric layer 102 and the multilayer conductive layer 104 are alternately stacked on the substrate 100. Here, the number of conductive layers 104 is two layers as an example, which actually depends on the number of a series of transistors, such as 32 layers, 64 layers, or other numbers. Therefore, the length of the channel column structure 114 will be very long.

In addition, the conductive pillar structure 118 is also formed in the dielectrics 106 and 120 adjacent to the channel pillar structure 114. The conductive pillar structure 118 is in contact with a predetermined layer of the conductive layers 104 to provide the voltage required by the character line.

The present invention observes that when the components are dense, the distance between the conductive pillar structure 118 and the channel pillar structure 114 will be reduced, but the length of the conductive pillar structure 118 and the channel pillar structure 114 will also be large due to the number of layers. Therefore, the two ends will be close, which may cause leakage or even direct contact, causing the failure of the memory cell string.

The present invention, after exploring the conductive pillar structure 118 and the channel pillar structure 114, proposes that at least the isolation effect between the conductive pillar structure 118 and the channel pillar structure 114 can be improved.

2 is a schematic cross-sectional structure diagram of a conductive pillar structure and a channel pillar structure of a memory device according to an embodiment of the present invention. Referring to Figure 2, the memory device includes a base Board 100. The first dielectric layer 106 is disposed on the substrate 100. The multiple conductive layers 104 and the multiple dielectric layers 102 are alternately and horizontally arranged on the substrate 100. In one embodiment, the material of the conductive layer 104 may also be tungsten or other conductive bodies, such as tungsten, copper, cobalt, silicon, or polysilicon.

The channel pillar structure 114 is disposed on the substrate 100 and in the multilayer conductive layer 104 and the multilayer dielectric layer 102. The sidewall of the channel pillar structure 114 is in contact with the multilayer conductive layer 104. The second dielectric layer 120 covers the first dielectric layer 106. The conductive pillar structure 204 is adjacent to the channel pillar 114 in the first dielectric layer 106 and the second dielectric layer 120 and is in contact with a predetermined layer of the multilayer conductive layer 104. The outer layer of the conductive pillar structure 204 includes an insulating liner 202. The center of the conductive pillar structure 204 is the conductive central pillar 200.

The structure of the channel column structure 114 is, for example, the structure described in FIG. 1. It should be noted here that the conductive pillar structure 204 includes a conductive central pillar 200 perpendicular to the substrate 100 and is in contact with a predetermined one of the multilayer conductive layers 104. The insulating liner layer 202 covers the conductive central pillar 200 and is in contact with the first dielectric layer 106 to assist in isolating the conductive central pillar 200 from the channel pillar structure 114. The material of the conductive central pillar 200 includes tungsten, copper, cobalt, silicon, or polysilicon. The material of the liner insulating layer 202 is silicon oxide, high-density plasma (HDP) dielectric, tetraethoxysilane (TEOS), thermal oxide, or high-k dielectric.

Since the shell layer of the conductive pillar structure 204 is the liner insulating layer 202, it provides a further isolation effect. Without substantially changing the dense size of the conductive pillar structure 204, it can improve the isolation effect from the channel pillar structure 114.

Several embodiments of the manufacturing process are described below. Figure 3A to Figure 3D are based on According to an embodiment of the present invention, a schematic diagram of a process of manufacturing a conductive pillar structure and a channel pillar structure of a memory device.

Referring to FIG. 3A, the formation of the channel pillar structure 114 is first. In one embodiment, a pillar-shaped recess is formed in the first dielectric layer 106 first, which extends to the substrate 100. In one embodiment, the charge storage layer 112 is formed on the sidewall of the columnar recess by depositing an initial charge storage layer and etching back. By depositing an initial polysilicon layer and etching back, silicon pillars 110 are also formed on the charge storage layer 112. In one embodiment, the thickness of the initial polysilicon layer is small, which is not enough to completely fill the recesses, so it is a hollow silicon pillar 110. In one embodiment, the central pillar 108 may be filled in when the second dielectric layer 120 is subsequently formed. In another embodiment, the initial polysilicon layer can completely fill the recesses, so that the solid silicon pillar 110 is formed by grinding the polysilicon layer, which includes the center pillar 108 of polysilicon. The present invention is not limited to a specific way of forming the channel column structure 114.

After that, another second dielectric layer 120 is formed on the first dielectric layer 106. The thickness of the second dielectric layer 120 is determined according to the expected height of the conductive pillar structure 204. Through the use of lithography and etching processes, large-depth recesses 130 are formed in the first dielectric layer 106 and the second dielectric layer 120. The depth of the recess 130 will reach the corresponding conductive layer 104, but will not be in contact with other conductive layers 104.

Referring to FIG. 3B, the initial insulating liner layer 122 is conformally deposited on the surface of the recess 130. Referring to FIG. 3C, by etching back the liner insulating layer 122, the remaining part of the liner insulating layer 122 is the liner insulating layer 202 and is formed on the sidewall of the recess 130.

Referring to FIG. 3D, the conductive central pillar 200 is filled in the recess 130 to complete the formation of the conductive pillar structure 204. The present invention maintains the width of the conductive pillar structure 204, which is advantageous With the re-formed insulating liner layer 202, the isolation of the conductive central pillar 200 can be improved. In other words, although there is isolation between the first dielectric layer 106 and the second dielectric layer 120, the present invention further forms a liner insulating layer 202 to improve the isolation effect.

Based on the formation of the insulating liner 202, the conductive central pillar 200 will form a corresponding structure at the upper end 210 and the lower end 212.

4 is a schematic diagram of a cross-sectional structure of a conductive pillar structure and a channel pillar structure according to an embodiment of the present invention. Referring to FIG. 4, for the conductive center pillar 200 at the upper end 210, under detailed observation, the structure will expand in the lateral direction. This is because when the lining insulating layer 122 is etched back in FIG. 3C, the lining insulating layer 202 is etched back. The top of the structure has an oblique surface. When the conductive central pillar 200 is filled in, the expanded space will be filled by the conductive central pillar 200.

5 is a schematic cross-sectional structure diagram of a conductive pillar structure and a channel pillar structure according to an embodiment of the present invention. Referring to FIG. 5, for the conductive center pillar 200 at the lower end 212, under detailed observation, the bottom surface includes a part protruding in the lateral direction. This is because the exposed surface of the conductive layer 104 will be cleaned after the liner insulating layer 122 is etched back in FIG. 3C, for example, the cleaning of diluted hydrofluoric acid. This cleaning process will produce a small amount of etching on the bottom of the recess 130, causing the bottom surface to expand laterally. The expanded space will also be filled into the expanded space after filling the conductive center pillar 200.

The further formation of the insulating liner 202 of the present invention enables the conductive central pillar 200 to observe corresponding structures at the upper end 210 and the lower end 212. The conductive pillar structure 204 of the present invention includes a lining insulating layer 202, which can increase the isolation effect of the conductive central pillar 200.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100: substrate

102: Dielectric layer

104: conductive layer

106: first dielectric layer

108: Center Column

110: Silica column

112: charge storage layer

114: Channel column structure

120: second dielectric layer

200: Conductive center column

202: Lining insulating layer

204: Conductive pillar structure

Claims (10)

A memory device includes: a substrate; a first dielectric layer above the substrate; a multilayer conductive layer and a multilayer dielectric layer arranged alternately and horizontally on the substrate; a channel column structure, the multilayer conductive layer on the substrate Layer and the multilayer dielectric layer, wherein the sidewall of the channel pillar structure is in contact with the multilayer conductive layer; the second dielectric layer covers the first dielectric layer; and the conductive pillar structure is in the first and second The dielectric layer is adjacent to the channel pillar structure and is in contact with one of the multilayer conductive layers, wherein the conductive pillar structure includes an insulating lining layer as an outer layer. The memory device according to claim 1, wherein the channel pillar structure includes: a silicon pillar perpendicular to the substrate; and a charge storage layer covering the silicon pillar, and the charge storage layer is in contact with the multilayer conductive layer , Wherein the silicon pillar provides a channel corresponding to each layer of the multilayer conductive layer. The memory device according to claim 2, wherein the charge storage layer is an oxide/nitride/oxide laminated structure. According to the first item of the scope of patent application, the memory device, wherein the conductive pillar structure includes: The conductive central pillar perpendicular to the substrate is in contact with a predetermined one of the multilayer conductive layers; and the liner insulating layer covers the conductive central pillar to assist in isolating the conductive central pillar from the channel pillar structure. In the memory device described in the first item of the scope of patent application, the conductive pillar structure is higher than the channel pillar structure. A method of manufacturing a memory device includes: providing a substrate; forming a first dielectric layer on the substrate; forming a multilayer conductive layer and a multilayer dielectric layer, alternately and horizontally arranged on the substrate; forming a channel column structure on the substrate On and in the multilayer conductive layer and the multilayer dielectric layer, wherein the sidewall of the channel pillar structure is in contact with the multilayer conductive layer; forming a second dielectric layer covering the first dielectric layer; and forming a conductive pillar The structure is in the first and second dielectric layers, adjacent to the channel pillar structure, and in contact with one of the multilayer conductive layers, wherein the conductive pillar structure includes an insulating liner layer as an outer layer. The method of manufacturing a memory device as described in the scope of the patent application, wherein the step of forming the channel pillar structure includes: forming a pillar-shaped recess in the first dielectric layer and passing through the multilayer conductive layer; and forming a charge A storage layer is on the sidewall of the columnar recess, wherein the charge storage layer is in contact with the multilayer conductive layer; and A silicon pillar is formed to fill the pillar-shaped recess on the charge storage layer, wherein the silicon pillar provides a channel area corresponding to each layer of the multilayer conductive layer. According to the method for manufacturing a memory device as described in claim 7, wherein the charge storage layer is an oxide/nitride/oxide laminated structure. The method of manufacturing a memory device as described in the scope of patent application, wherein the step of forming the conductive pillar structure includes: forming a pillar-shaped recess in the first and second dielectric layers and extending to the multilayer conductive layer One of the predetermined one in the above; forming the insulating liner layer on the sidewall of the columnar recess; and filling the columnar recess with a conductive material to form a conductive central column, which is in contact with the predetermined one of the multilayer conductive layers, wherein The insulating liner layer covers the conductive material and also provides isolation between the conductive material and the channel column structure. According to the method for manufacturing a memory device as described in item 6 of the scope of patent application, the conductive pillar structure is higher than the channel pillar structure.

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