TWI718473B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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TWI718473B
TWI718473B TW108103732A TW108103732A TWI718473B TW I718473 B TWI718473 B TW I718473B TW 108103732 A TW108103732 A TW 108103732A TW 108103732 A TW108103732 A TW 108103732A TW I718473 B TWI718473 B TW I718473B
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conductor plate
external connection
semiconductor element
semiconductor
semiconductor device
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TW108103732A
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TW201936027A (en
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川島崇功
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日商豐田自動車股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Inverter Devices (AREA)
  • Power Conversion In General (AREA)
  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A semiconductor device may include a first conductive plate, a plurality of semiconductor chips disposed on the first conductive plate, and a first external connection terminal connected to the first conductive plate. The plurality of semiconductor chips may include first, second, and third semiconductor chips. The second semiconductor chip may be located between the first semiconductor chip and the third semiconductor chip. A portion of the first conductive plate where the first external connection terminal is connected may be closest to the second semiconductor chip among the first, second, and third semiconductor chips. The first conductive plate may be provided with an aperture located between the portion of the first conductive plate where the first external connection terminal is connected and a portion of the first conductive plate where the second semiconductor chip is connected.

Description

半導體裝置Semiconductor device

本說明書所公開的技術關於一種半導體裝置。The technology disclosed in this specification relates to a semiconductor device.

在日本特開2013-93343號公報中公開了一種半導體裝置。該半導體裝置具備導體板、被配置於導體板上的多個半導體元件、和與導體板連接的外部連接端子。A semiconductor device is disclosed in Japanese Patent Application Laid-Open No. 2013-93343. This semiconductor device includes a conductor plate, a plurality of semiconductor elements arranged on the conductor plate, and external connection terminals connected to the conductor plate.

在並聯地連接有多個半導體元件的半導體裝置中，期望電流均等地流向各個半導體元件。但是，當在公共的導體板上配置有三個以上的半導體元件時，和導體板連接的外部連接端子與各個半導體元件之間的距離並不完全一致。例如設為，在共用的導體板上，三個半導體元件沿著直線而被配置。在該情況下，無論使外部連接端子與導體板的哪個位置連接，均無法使外部連接端子與各個半導體元件之間的距離互為相等。如果存在這種距離的不同，則在外部連接端子與各個半導體元件之間的電阻上也會產生無法忽視的差值。其結果為，在各個半導體元件中，電流不均等地流動。本說明書提供一種能夠解決或改善這樣的問題的技術。 本說明書所公開的半導體裝置具備：第一導體板；多個半導體元件，其被配置於第一導體板上；第一外部連接端子，其與第一導體板連接。多個半導體元件包括第一半導體元件、第二半導體元件以及第三半導體元件，第二半導體元件被配置於第一半導體元件與第三半導體元件之間。在第一導體板中連接有第一外部連接端子的範圍在第一半導體元件、第二半導體元件以及第三半導體元件中最接近於第二半導體元件。而且，在第一導體板中，在連接有第一外部連接端子的範圍與連接有第二半導體元件的範圍之間設置有孔。 在上述的半導體裝置中，與從第一外部連接端子起至第一半導體元件為止的距離、或從第一外部連接端子起至第三半導體元件為止的距離相比，從第一外部連接端子起至第二半導體元件為止的距離較短。而且，在第一導體板中，在連接有第一外部連接端子的範圍與連接有第二半導體元件的範圍之間設置有孔。由此，在第一外部連接端子與第二半導體元件之間流動的電流的至少一部分需要迂回過孔而流動，由於實際上供電流流動的路徑長度變長，因此，電阻將增大。其結果為，通過抑制流過第二半導體元件的電流，從而消除或減少了流過各個半導體元件的電流的不均等。並且，此處所述的孔並未被限定於貫穿孔。In a semiconductor device in which a plurality of semiconductor elements are connected in parallel, it is desirable that current flows to each semiconductor element equally. However, when three or more semiconductor elements are arranged on the common conductor plate, the distances between the external connection terminals connected to the conductor plate and the respective semiconductor elements are not completely the same. For example, assume that three semiconductor elements are arranged along a straight line on a common conductor board. In this case, no matter where the external connection terminal is connected to the conductor plate, the distance between the external connection terminal and the respective semiconductor elements cannot be made equal to each other. If there is such a difference in distance, an unignorable difference will also occur in the resistance between the external connection terminal and each semiconductor element. As a result, the current flows unevenly in each semiconductor element. This specification provides a technique that can solve or ameliorate such problems. The semiconductor device disclosed in this specification includes: a first conductor plate; a plurality of semiconductor elements arranged on the first conductor plate; and a first external connection terminal connected to the first conductor plate. The plurality of semiconductor elements includes a first semiconductor element, a second semiconductor element, and a third semiconductor element, and the second semiconductor element is arranged between the first semiconductor element and the third semiconductor element. The range where the first external connection terminal is connected to the first conductor plate is closest to the second semiconductor element among the first semiconductor element, the second semiconductor element, and the third semiconductor element. Furthermore, in the first conductor plate, a hole is provided between the area where the first external connection terminal is connected and the area where the second semiconductor element is connected. In the above-mentioned semiconductor device, compared to the distance from the first external connection terminal to the first semiconductor element, or the distance from the first external connection terminal to the third semiconductor element, the distance from the first external connection terminal The distance to the second semiconductor element is short. Furthermore, in the first conductor plate, a hole is provided between the area where the first external connection terminal is connected and the area where the second semiconductor element is connected. As a result, at least a part of the current flowing between the first external connection terminal and the second semiconductor element needs to flow around the via hole, and since the length of the path through which the current flows actually becomes longer, the resistance increases. As a result, by suppressing the current flowing through the second semiconductor element, the unevenness of the current flowing through each semiconductor element is eliminated or reduced. In addition, the holes described here are not limited to through holes.

在本技術的一個實施方式中，也可以採用如下的方式，即，所述孔被形成為，在第一外部連接端子與第二半導體元件之間流動的電流全部迂回過孔。根據這樣的結構，能夠使第一外部連接端子與第二半導體元件之間的電阻充分增大。 在本技術的一個實施方式中，也可以採用如下的方式，即，第一半導體元件、第二半導體元件以及第三半導體元件將與第一導體板垂直且穿過所述第二半導體元件的平面作為對稱面而實質上被左右對稱(即，面對稱)地排列配置。根據這樣的結構，能夠在第一半導體元件與第三半導體元件之間充分地降低向各個半導體元件流動的電流的不均等。並且，此處所述的實質上左右對稱是指，與準確地左右對稱的排列配置相比而容許一定的誤差(例如半導體元件的尺寸(所謂的晶片尺寸)的一半以內的誤差)。 在本技術的一個實施方式中，也可以採用如下的方式，即，第一外部連接端子在與對稱面交叉的範圍內與第一導體板連接。根據這種結構，能夠使從第一外部連接端子起至第一半導體元件為止的距離與從第一外部連接端子起至第三半導體元件為止的距離互為相等。由此，能夠在第一半導體元件和第三半導體元件之間使向各個半導體元件流動的電流實質上相等。 在本技術的一個實施方式中，也可以採用如下的方式，即，所述孔具有關於所述對稱面而左右對稱的開口形狀。根據這樣的結構，能夠避免第一半導體元件與第三半導體元件之間的對稱性因孔的存在而消失的情況。 在本技術的一個實施方式中，也可以採用如下的方式，即，所述孔具有長孔形狀。在該情況下，長孔形狀的長邊軸只要與所述對稱面垂直即可。根據這樣的結構，能夠容易地實施適當的孔的設計或製造。但是，孔的開口形狀並未被限定於單純的長孔形狀，也可以具有更加複雜的形狀。 在本技術的一個實施方式中，也可以採用如下的方式，即，關於與所述對稱面垂直的方向，孔的尺寸大於第二半導體元件的尺寸。根據這樣的結構，雖然也基於第一外部連接端子的尺寸，但能夠利用孔而使在第一外部連接端子與第二半導體元件之間流動的電流中的多數或全部迂回過。 在本技術的一個實施方式中，也可以採用如下的方式，即，在與所述對稱面垂直的方向上，孔的尺寸小於第一半導體元件與第三半導體元件之間的中心間距離。根據這樣的結構，能夠避免在第一外部連接端子與第二半導體元件之間流動的電流因孔而過度地迂回的情況。 在本技術的一個實施方式中，也可以採用如下的方式，即，在第一導體板中連接有第一外部連接端子的範圍相對於所述對稱面左右對稱。根據這樣的結構，能夠進一步提高第一半導體元件與第三半導體元件之間的對稱性。 在本技術的一個實施方式中，也可以採用如下的方式，即，在與所述對稱面垂直的方向上，孔的尺寸大於在第一導體板中連接有第一外部連接端子的範圍的尺寸。根據這樣的結構，雖然也依賴於第二半導體元件的尺寸，但能夠利用孔而使在第一外部連接端子與第二半導體元件之間流動的電流中的多數或全部迂回過。 在本技術的一個實施方式中，也可以採用如下的方式，即，第一導體板具有擴大部分，所述擴大部分的與所述對稱面垂直的方向的尺寸從連接有第一外部連接端子的範圍起向連接有多個半導體元件的範圍而擴大。在該情況下，孔的至少一部分也可以位於該擴大部分處。根據這樣的結構，能夠設置較大的尺寸的孔。另外，藉由設置這樣的擴大部分，從而能夠縮短第一外部連接端子與第一半導體元件之間的電流路徑、或第一外部連接端子與第三半導體元件之間的電流路徑，從而能夠減少半導體裝置中的電力損失。 在本技術的一個實施方式中，也可以採用如下的方式，即，第一半導體元件、第二半導體元件以及第三半導體元件沿著與所述對稱面垂直的直線而被排列配置。根據這樣的結構，由於多個半導體元件的排列配置較單純，因此，即使關於例如孔也能夠設為單純的結構。 在本技術的一個實施方式中，也可以採用如下的方式，即，半導體裝置還具備第二導體板，所述第二導體板與第一導體板對置，並且與多個半導體元件中的每個半導體元件連接。在該情況下，雖然並未被特別地限定，但半導體裝置也還可以具備與第二導體板連接的至少一個第二外部連接端子。本說明書中公開的技術不依賴於例如導體板或外部連接端子的數量，而能夠應用於各種各樣的結構的半導體裝置中。 在上述的實施方式中，也可以採用如下的方式，即，至少一個第二外部連接端子包括兩個第二外部連接端子。在該情況下，兩個第二外部連接端子中的一方只要在所述對稱面的一側與第二導體板連接即可。而且，兩個第二外部連接端子中的另一方只要在所述對稱面的另一側與第二導體板連接即可。在該情況下，雖然未被特別地限定，但兩個第二外部連接端子也可以被設置為，相對於對稱面而實質上左右對稱。根據這樣的結構，即使在第二導體板中，也能夠減少向各個半導體元件流動的電流的不均等。 在本技術的一個實施方式中，也可以採用如下的方式，即，在從與第一導體板以及第二導體板垂直的方向上俯視觀察時，第二導體板的面積大於第一導體板的面積。根據這樣的結構，在半導體裝置的製造時，在將第一導體板向第二導體板進行組裝時，能夠利用在第二導體板的周圍豎立設置的夾具而對第一導體板進行支承，從而實施第一導體板與第二導體板之間的定位。另外，當與和第一導體板連接的半導體元件的電極(例如射極)的面積相比，和第二導體板連接的半導體元件的電極(例如集極)的面積較大時，由於第一導體板的面積大於第二導體板的面積，從而能夠提高從半導體元件中散熱的散熱性。 在本技術的一個實施方式中，也可以採用如下的方式，即，在從與第一導體板以及第二導體板垂直的方向俯視觀察時，第一導體板具有擴大部分，所述擴大部分為，第一導體板的寬度從連接有第一外部連接端子的範圍起向連接有多個半導體元件的範圍而擴大的部分。根據這樣的結構，能夠縮短第一外部連接端子與第一半導體元件之間的電流路徑、或第一外部連接端子與第三半導體元件之間的電流路徑，從而能夠減少半導體裝置中的電力損失。 在上述的實施方式中，也可以採用如下的方式，即，第一導體板的擴大部分中的厚度尺寸也可以小於第一導體板的連接有多個半導體元件的範圍內的厚度尺寸。在該情況下，第一導體板的擴大部分也可以由密封體覆蓋。藉由第一導體板的擴大部分由密封體覆蓋，從而在第一導體板的擴大部分與和第二導體板連接的第二外部連接端子之間，使密封體的沿著表面的沿面距離變長，由此能夠提高絕緣性。 在上述的實施方式中，也可以採用如下的方式，即，擴大部分的至少一部分與第二外部連接端子對置。在與第一外部連接端子連接的擴大部分中，電流在與第二外部連接端子相反的方向上流動。因此，當擴大部分的至少一部分與第二外部連接端子對置時，通過伴隨著通電而產生的磁場被抵消，從而能夠減少電流路徑的電感。 在上述的實施方式中，也可以採用如下的方式，即，第一半導體元件、第二半導體元件以及第三半導體元件各自包括具有射極以及集極的IGBT(Insulated Gate Bipolar Transistor，絕緣閘雙極型電晶體)。在該情況下，射極與第一導體板電連接，集極與第二導體板電連接。但是，在其他的實施方式中，第一半導體元件、第二半導體元件以及第三半導體元件各自也可以為MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，金屬-氧化物半導體場效應電晶體)或二極體那樣的、其他的半導體元件。 在本技術的一個實施方式中，也可以採用如下的方式，即，第一導體板為，具有內側導體層、外側導體層、位於內側導體層以及外側導體層之間的絕緣層的絕緣基板。在該情況下，第一外部連接端子也可以經由內側導體層而與多個半導體元件電連接。而且，所述孔也可以被設置於內側導體層。當第一導體板為絕緣基板時，能夠通過自由的分佈來形成內側導體層。例如，在第一導體板與第二導體板對置的情況下，能夠通過使內側導體層與第二導體板對置的面積增大，從而減少半導體裝置的阻抗。 在上述的實施方式中，孔只要僅被設置於所述內側導體層中，並具有由絕緣層劃分出的底面即可。根據這樣的結構，能夠避免第一導體板的剛性因孔的存在而降低的情況。另外，能夠避免內側導體層和外側導體層意外地導通的情況。 在本技術的一個實施方式中，也可以採用如下的方式，即，第二導體板為，具有內側導體層、外側導體層、位於內側導體層以及外側導體層之間的絕緣層的絕緣基板。在該情況下，第二外部連接端子也可以經由第二導體板的內側導體層而與多個半導體元件電連接。根據這樣的結構，能夠以較大的面積而使第一導體板的內側導體層和第二導體板的內側導體層對置，從而進一步減少半導體裝置的阻抗。 在上述的第一導體板和/或第二導體體的絕緣基板中，也可以採用如下的方式，即，內側導體層以及外側導體層各自為金屬層，絕緣層為陶瓷基板。在該情況下，絕緣基板也可以為為DBC(Direct Bonded Copper，直接敷銅)基板。 以下，參照附圖，對本發明的代表性或非限定的具體例進行詳細的說明。該詳細的說明單純地意圖將用於實施本發明的優選例的詳細情況向本領域技術人員進行表示，並未意圖對本發明的範圍進行限定。另外，為了提供進一步被改善後的半導體裝置、以及其使用方法以及製造方法，以下公開的追加的特徵以及發明能夠應用於與其他的特徵或發明不同的特徵或發明中，或者與其他的特徵或發明一起使用。 另外，以下的詳細說明中所公開的特徵或工程的組合並非在最廣泛的意義上實施本發明時所必需的組合，而是尤其僅用於對本發明的代表性的具體例進行說明而記載的組合。而且，在提供本發明的追加的且有用的實施方式時，上述以及下述的代表性的具體例的各種各樣的特徵、以及被記載於獨立項以及府屬請求項中的各種各樣的特徵並非必須如在此所記載的具體例那樣、或者如列舉的順序那樣而進行組合的特徵。 在本說明書和/或申請專利範圍中所記載的全部特徵為，與實施例和/或申請專利範圍所記載的特徵的結構相比，作為針對原始申請的公開以及要求保護的特定事項的限定而意圖個別或者相互獨立地被公開的特徵。而且，作為針對原始申請的公開以及要求保護的特定事項的限定，以具有公開它們的中間結構的意圖的方式而實施了與全部的數值範圍以及組或集團相關的記載。 [實施例] 參照附圖，對實施例的半導體裝置10進行說明。半導體裝置10能夠在例如電動汽車中應用於變換器或逆變器那樣的電力轉換電路中。此處所說的電動汽車廣泛地是指具有對車輪進行驅動的電機在內的汽車，例如，包括藉由外部的電力而被充電的電動汽車、在電機之外還具有引擎的混合動力汽車、以及以燃料電池為電源的燃料電池車等。 如圖1-圖4所示，半導體裝置10具備第一導體板12、第二導體板14、多個半導體元件22、24、26和密封體16。第一導體板12和第二導體板14相互平行，並相互對置。雖然是一個示例，但在多個半導體元件22、24、26中包括第一半導體元件22、第二半導體元件24以及第三半導體元件26。第一半導體元件22、第二半導體元件24以及第三半導體元件26沿著第一導體板12以及第二導體板14的長邊方向(圖2、圖3中的左右方向)而被直線地排列配置。多個半導體元件22、24、26被並列地配置於第一導體板12與第二導體板14之間。多個半導體元件22、24、26藉由密封體16而被密封。 第一導體板12以及第二導體板14藉由銅或其他的金屬那樣的導體而被形成。第一導體板12和第二導體板14隔著多個半導體元件22、24、26而相互對置。各個半導體元件22、24、26與第一導體板12接合，並且，也與第二導體板14接合。並且，在各個半導體元件22、24、26與第一導體板12之間設置有導體間隔件18。在此，第一導體板12以及第二導體板14的具體結構並未被特別限定。例如，第一導體板12和第二導體板14中的至少一方也可以為例如DBC (Direct Bonded Copper，直接敷銅)基板那樣的具有絕緣體(例如陶瓷)的中間層的絕緣基板。即，第一導體板12和第二導體板14各自也不一定整體由導體構成。 第一半導體元件22、第二半導體元件24以及第三半導體元件26為電力電路用的所謂的功率半導體元件，其具有彼此相同的結構。第一半導體元件22具有上表面電極22a、下表面電極22b、多個信號焊墊22c。上表面電極22a和下表面電極22b為電力用的電極，多個信號焊墊22c為信號用的電極。上表面電極22a以及多個信號焊墊22c位於第一半導體元件22的上表面上，下表面電極22b位於第一半導體元件22的下表面上。上表面電極22a經由導體間隔件18而與第一導體板12電連接，下表面電極22b與第二導體板14電連接。同樣地，關於第二半導體元件24以及第三半導體元件26，也分別具有上表面電極24a、26a、下表面電極24b、26b、多個信號焊墊24c、26c。上表面電極24a、26a經由導體間隔件18而與第一導體板12電連接，下表面電極24b、26b與第二導體板14電連接。 雖然是一個示例，但本實施例中的半導體元件22、24、26包含具有射極以及集極的IGBT結構。IGBT結構的射極與上表面電極22a、24a、26a連接，IGBT結構的集極與下表面電極22b、24b、26b連接。但是，半導體元件22、24、26的具體的種類或結構並未被特別地限定。半導體元件22、24、26也可以為還具有二極體結構的RC (Reverse Conducting，逆導型)-IGBT元件。或者，半導體元件22、24、26也可以代替IGBT結構、或者在具有IGBT結構的基礎上還具有例如MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，金屬-氧化物半導體場效應電晶體)結構。另外，關於在半導體元件22、24、26中所使用的半導體材料，也並未被特別地限定，例如也可以為矽(Si)、碳化矽(SiC)、或氮化鎵(GaN)那樣的氮化物半導體。 密封體16並未被特別地限定，能夠由例如環氧樹脂那樣的熱固化性樹脂或其他的絕緣體構成。密封體16例如也被稱為模制樹脂或封裝體。半導體裝置10並未限定於三個半導體元件22、24、26，也可以具備更多的半導體元件。在該情況下，多個半導體元件藉由單一的密封體16而被密封，在第一導體板12以及第二導體板14之間被並列配置。 第一導體板12以及第二導體板14不僅與多個半導體元件22、24、26電連接，還與多個半導體元件22、24、26熱連接。另外，第一導體板12以及第二導體板14分別露出於密封體16的表面，能夠將各個半導體元件22、24、26的熱量向密封體16的外部釋放。由此，本實施例的半導體裝置10具有在多個半導體元件22、24、26的兩側配置了散熱板的雙面冷卻結構。 半導體裝置10還具備第一外部連接端子32、兩個第二外部連接端子34、以及十一個第三外部連接端子36。各個外部連接端子32、34、36藉由銅或鋁那樣的導體而被構成，並從密封體16的內部跨至外部而延伸。第一外部連接端子32在密封體16的內部與第一導體板12連接。各個第二外部連接端子34在密封體16的內部與第二導體板14連接。由此，多個半導體元件22、24、26被並聯地電連接於第一外部連接端子32與各個第二外部連接端子34之間。各個第三外部連接端子36經由接合引線38而與半導體元件22、24、26的對應的一個信號焊墊22c、24c、26c連接。雖然是一個示例，但第一外部連接端子32藉由焊接而與第一導體板12接合，各個第二外部連接端子34被一體形成於第二導體板14上。但是，第一外部連接端子32也可以與第一導體板12一體形成。另外，各個第二外部連接端子34例如也可以藉由焊接而與第二導體板14接合。而且，各個第三外部連接端子36也可以不經由接合引線38而與對應的一個信號焊墊22c、24c、26c連接。 如圖5所示，第一半導體元件22、第二半導體元件24以及第三半導體元件26與第一導體板12垂直，並且將穿過第二半導體元件24的平面PS作為對稱面而被左右對稱地排列配置。而且，第一外部連接端子32在與對稱面PS交叉的範圍33內與第一導體板12連接。該範圍33在三個半導體元件22、24、26中最接近於第二半導體元件24。當採用這樣的結構時，和第一導體板12連接的第一外部連接端子32、與各個半導體元件22、24、26之間的距離並不完全一致。例如，從第一外部連接端子32起至第一半導體元件22為止的距離、與從第一外部連接端子32起至第三半導體元件26為止的距離相等。但是，關於從第一外部連接端子32起至第二半導體元件24為止的距離，其短於從第一外部連接端子32起至第一半導體元件22或第三半導體元件26為止的距離。如果存在這樣的距離的不同，則在第一外部連接端子32與各個半導體元件22、24、26之間的電阻上也會產生無法忽視的差值。其結果為，在各個半導體元件22、24、26中，電流會不均等地流動。 關於上述的問題，在本實施例中的第一導體板12中，在連接有第一外部連接端子32的範圍33和連接有第二半導體元件24的範圍之間，設置有孔40。由此，如圖6所示，在第一外部連接端子32與第二半導體元件24之間流動的電流C24的至少一部分需要以迂回過孔40的方式而流動，由於實際上電流流動的路徑長度變長，因此電阻將增大。其結果為，由於抑制了流動於第二半導體元件24中的電流，從而消除或降低了向各個半導體元件22、24、26流動的電流C22、C24、C26的不均等。而且，如圖7所示，由於在隔著孔40的兩側，電流C24彼此向反方向流動，因此，降低了在第一導體板12中產生的電感。這一點對半導體裝置10被應用於逆變器或變換器中、且各個半導體元件22、24、26被高頻地開關的情況特別有利。並且，雖然本實施例中的孔40為貫穿孔，但孔40也可以為有底的孔(即，凹部)。即使在該情況下，在孔40的位置中，藉由減少第一導體板12的厚度尺寸，從而也會使電阻上升。另外，在孔40的內部，配置有與構成第一導體板12的材料相比為高電阻的材料。 孔40的形狀以及尺寸並未被特別地限定。孔40的形狀以及尺寸能夠在藉由實驗或模擬而對向各個半導體元件22、24、26流動的電流C22、C24、C26進行驗證的同時，進行適當的設計。如圖5所示，本實施例中的孔40具有長孔形狀，該長孔形狀的長邊軸與對稱面PS垂直。另外，孔40具有關於對稱面PS而左右對稱的開口形狀，長孔形狀的中心位於對稱面PS上。當孔40的開口形狀關於對稱面PS而左右對稱時，能夠避免第一半導體元件22與第三半導體元件26之間的對稱性因孔40的存在而消失的情況。並且，孔40也可以代替較單純的長孔形狀，而以更加複雜的形狀來設計。另外，在第一導體板12上，並不限於一個孔40，也可以形成有多個孔。 大致而言，越使孔40的尺寸(尤其，與對稱面PS垂直的方向上的尺寸)增大，則越是有在第一外部連接端子32與第二半導體元件24之間流動的更多的電流C24迂回過孔40。關於這一點，本實施例中的孔40以在第一外部連接端子32與第二半導體元件24之間流動的電流C24全部迂回過孔40的方式而被形成。具體而言，關於與對稱面PS垂直的方向(即，關於圖5中的左右方向)，孔40的尺寸大於第二半導體元件24的尺寸，且大於在第一導體板12中連接有第一外部連接端子32的範圍33的尺寸。並且，第一外部連接端子32沿著對稱面PS而延伸，關於在第一導體板12中連接有第一外部連接端子32的範圍33也關於對稱面PS而左右對稱。 另一方面，當孔40的尺寸過大時，在第一外部連接端子32與第二半導體元件24之間流動的電流C24會因孔40而過度地迂回。在該情況下，在第一外部連接端子32與第二半導體元件24之間，電阻會不必要地增大。根據該情況，關於與對稱面PS垂直的方向，孔40的尺寸只要小於第一半導體元件22與第三半導體元件26之間的中心間距離即可。並且，在圖5中，點22X表示第一半導體元件22的中心，點24X表示第二半導體元件24的中心，點26X表示第三半導體元件26的中心。第一半導體元件22的中心22X位於對稱面PS的一側，第二半導體元件24的中心24X位於對稱面PS上，第三半導體元件26的中心26X位於對稱面PS的另一側。 如圖5所示，第一導體板12具有從連接有第一外部連接端子32的範圍33向連接有多個半導體元件22、24、26的範圍而擴大了與對稱面PS垂直的方向上的尺寸的部分13(以下，稱為擴大部分13)。而且，孔40位於該擴大部分13處。根據這樣的結構，能夠設置較大的尺寸的孔40。另外，藉由設置這樣的擴大部分13，從而能夠縮短第一外部連接端子32與第一半導體元件22之間的電流路徑、或第一外部連接端子32與第三半導體元件26之間的電流路徑，並能夠減少半導體裝置10中的電力損失。並且，本實施例中的孔40的整體被設置於上述的擴大部分13上，但作為其他的實施方式，也可以僅使孔40的一部分被設置於擴大部分13上。在此，第一導體板12的擴大部分13與第一導體板12的其他的範圍(即，連接有多個半導體元件22、24、26的範圍)相比被形成得較薄。 擴大部分13的具體的結構並未被特別限定。雖然是一個示例，但本實施例中的擴大部分13具有一對側緣13a。各個側緣13a從位於多個半導體元件22、24、26側的基端13b延伸至位於第一外部連接端子32側的前端13c。如圖5所示，當從與第一導體板12以及第二導體板14垂直的方向進行俯視觀察時，擴大部分13的側緣13a的基端13b位於與第二外部連接端子34的內側緣34a(即，位於第一外部連接端子32側的側緣34a)相比靠外側(即，從第一外部連接端子32觀察時較遠的一側)。另外，擴大部分13的側緣13a的前端13c位於與第二外部連接端子34的內側緣34a相比靠內側(即，從第一外部連接端子32觀察時較近的一側)，並位於第一外部連接端子32與第二外部連接端子34之間。 根據上述的結構，能夠在縮短第一外部連接端子32與第一半導體元件22或第三半導體元件26之間的各電流路徑的同時，提高擴大部分13與第二外部連接端子34之間的絕緣性。尤其是，在第二外部連接端子34上設置有朝向其前端側而向上方(即，擴大部分13側)進行位移的彎曲部34b(參照圖4、圖5)，由此，第一外部連接端子32與兩個第二外部連接端子34在至少從密封體16突出的部分中位於同一平面上。因此，假設擴大部分13的側緣13a的前端13c位於與第二外部連接端子34的內側緣34a相比靠外側時，由於擴大部分13和向擴大部分13彎曲的第二外部連接端子34接近，從而兩者之間的絕緣性有可能不足。與此相對，當擴大部分13的側緣13a的前端13c位於與第二外部連接端子34的內側緣34a相比靠內側時，能夠增大擴大部分13與第二外部連接端子34之間的距離，從而能夠提高兩者之間的絕緣性。 第一導體板12的擴大部分13中的厚度尺寸小於第一導體板12的連接有多個半導體元件22、24、26的範圍內的厚度尺寸。由此，第一導體板12的擴大部分13藉由密封體16而被覆蓋，並未露出於密封體16的表面。第一導體板12的擴大部分13藉由由密封體16覆蓋，從而在第一導體板12的擴大部分13、與連接於第二導體板14上的第二外部連接端子34之間，能夠延長沿著密封體16的表面的沿面距離，從而提高絕緣性。 如圖5所示，擴大部分13的至少一部分與第二外部連接端子34對置。在與第一外部連接端子32連接的擴大部分13中，電流向與第二外部連接端子34相反的方向流動。因此，當擴大部分13的至少一部分與第二外部連接端子34對置時，藉由伴隨著通電而產生的磁場被抵消，從而能夠減少電流路徑的電感。關於這一點，擴大部分13與第二外部連接端子34對置的面積越大，則減少電感的效果越高。根據該情況，如圖13所示，也可以進一步擴展與第一外部連接端子32連接的擴大部分13。由此，能夠使擴大部分13和第二外部連接端子34對置的面積進一步增大。雖然是一個示例，但在圖13所示的改變例中，擴大部分13的側緣13a從其基端13b跨至前端13c的整體而位於第二外部連接端子34上。 在本實施例中，第一半導體元件22、第二半導體元件24以及第三半導體元件26沿著與對稱面PS垂直的直線而被排列配置。根據這樣的結構，由於這些半導體元件22、24、26的排列配置較為單純，因此，例如關於孔40也能夠設置為單純的結構，從而能夠易於實施適當的孔40的設計以及形成。但是，第一半導體元件22、第二半導體元件24以及第三半導體元件26的排列能夠適當地進行變更。例如，第一半導體元件22、第二半導體元件24以及第三半導體元件26也可以被排列配置為，關於對稱面PS而左右對稱的V字狀或倒V字狀。另外，第一半導體元件22、第二半導體元件24以及第三半導體元件26並不一定被準確地左右對稱排列配置，在該排列配置中容許一定的誤差。作為該誤差，例如，設想了半導體元件22、24、26的尺寸(所謂的晶片尺寸)的一半以內的誤差或四分之一以內的誤差。 在本實施例的半導體裝置10中，在第二導體板14上連接有兩個第二外部連接端子34，兩個第二外部連接端子34被設置為關於對稱面PS而左右對稱。這樣，當兩個以上的第二外部連接端子34被設置為關於對稱面PS而左右對稱時，能夠將第二導體板14相對於各個半導體元件22、24、26的的電阻設為比較均等。並且，兩個第二外部連接端子34也不一定關於對稱面PS而嚴格地左右對稱。但是，兩個第二外部連接端子34中的一方只要在對稱面PS的一側與第二導體板14連接即可，兩個第二外部連接端子34中的另一方只要在對稱面PS的另一方側與第二導體板14連接即可。在第二導體板14中，也可以與第一導體板12同樣地應用具有孔40的結構，在該情況下，第二外部連接端子34的數量也可以為一個。 並且，也可以設為，與孔向第二導體板14的追加無關而使第二外部連接端子34的數量為一個。在該情況下，雖然是一個示例，但只要僅省略本實施例中的兩個第二外部連接端子34中的一方即可。關於省略兩個第二外部連接端子34中的哪一個，並未被特別地限定。無論省略哪一個第二外部連接端子34，只要使半導體裝置10的表背反轉，則第一外部連接端子32以及第二外部連接端子34的排列配置均為相同。但是，如果在第二導體板14上連接有兩個以上的第二外部連接端子34，則在半導體裝置10被組裝進電力轉換電路時，藉由兩個以上的第二外部連接端子34，從而能夠使半導體裝置10被穩定地支承。另外，在半導體裝置10的製造時，藉由兩個以上的第二外部連接端子34，也能夠使第二導體板14被穩定地支承。 接下來，參照圖8，對多個第三外部連接端子36所關於的結構進行說明。如前文所述，多個第三外部連接端子36與多個半導體元件22、24、26的信號焊墊22c、24c、26c連接。在此，在本實施例中，各個半導體元件22、24、26具有五個信號焊墊22c、24c、26c。在第一半導體元件22的五個信號焊墊22c、24c、26c中包括第一溫度感測焊墊K、第二溫度感測焊墊A、柵極驅動焊墊G、電流感測焊墊SE以及開爾文射極焊墊KE。第一溫度感測焊墊K以及第二溫度感測焊墊A與第一半導體元件22內的溫度感測器(例如二極體)連接。閘極驅動焊墊G與第一半導體元件22內的IGBT結構的閘極連接。電流感測焊墊SE輸出與向第一半導體元件22流動的電流成比例的微小的電流。而且，開爾文(Kelvin)射極焊墊KE與第一半導體元件22內的IGBT結構的射極連接。同樣地，在第二半導體元件24的五個信號焊墊24c以及第三半導體元件26的五個信號焊墊26c中，也包括第一溫度感測焊墊K、第二溫度感測焊墊A、閘極驅動焊墊G、電流感測焊墊SE以及開爾文射極焊墊KE。 如根據上述內容可理解的那樣，在本實施例的半導體裝置10中，存在總計15個的信號焊墊22c、24c、26c。與此相對，多個第三外部連接端子36的數量為11，少於信號焊墊22c、24c、26c的數量。這是因為，在第一半導體元件22的第一溫度感測焊墊K以及第二溫度感測焊墊A、和第三半導體元件26的第一溫度感測焊墊K以及第二溫度感測焊墊A上，未連接有多個第三外部連接端子36。在半導體裝置10中，與位於兩側的第一半導體元件22以及第三半導體元件26相比，位於中央的第二半導體元件24易於變成高溫。根據該情況，如果對第二半導體元件24的溫度進行監控，則也能夠避免第一半導體元件22以及第三半導體元件26過熱的情況。根據該觀點，在半導體裝置10中，關於第一半導體元件22的第一溫度感測焊墊K以及第二溫度感測焊墊A、和第三半導體元件26的第一溫度感測焊墊K以及第二溫度感測焊墊A，省略了第三外部連接端子36的連接。由此，削減了多個第三外部連接端子36的數量。藉由削減多個第三外部連接端子36的數量，例如，能夠削減與多個第三外部連接端子36連接的外部連接器的數量。雖然是一個示例，但在本實施例的半導體裝置10中，被設想了11個第三外部連接端子36與兩個外部連接器連接的情況，並以分為5個一組和6個一組的方式而被排列。 接下來，參照圖9-圖12，對半導體裝置10的製造方法的一個示例進行說明。首先，如圖9所示，實施第一回流工程。在該工程中，準備多個半導體元件22、24、26、多個導體間隔件18以及引線框19。在引線框19上，一體地設置有第二導體板14、第一外部連接端子32、兩個第二外部連接端子34以及多個第三外部連接端子36。接著，在引線框19的第二導體板14上，對多個半導體元件22、24、26以及多個導體間隔件18進行焊接。此時，多個半導體元件22、24、26分別被焊接在第二導體板14上，在各個半導體元件22、24、26上焊接有一個導體間隔件18。 接下來，如圖10所示，實施第二回流工程。在該工程中，準備第一導體板12，並將第一導體板12焊接在多個導體間隔件18上。接下來，如圖11所示，實施密封工程。在該工程中，藉由例如密封樹脂而對多個半導體元件22、24、26進行密封，從而形成密封體16。在該階段中，第一導體板12以及第二導體板14也可以藉由密封體16而被覆蓋。另外，也可以先於密封工程而實施在引線框19上塗布底塗劑的工程。最後，如圖12所示，藉由對引線框19的無用部分進行切除，並且對密封體16的表面進行切削或研削，從而能夠使第一導體板12以及第二導體板14露出於密封體16的表面上。由此，完成了半導體裝置10。 如上所述，在本說明書中公開的技術中，藉由在第一導體板12上形成孔40，從而改善了連接於第一導體板12上的第一外部連接端子32、與各個半導體元件22、24、26之間的電阻的不均等。使用了該孔40的技術也能夠同樣地被應用於第二導體板14中。或者，即使在半導體裝置10不具備第二導體板14的情況下，也同樣能夠應用。而且，作為其他的結構例，也可以代替孔40而在第一導體板12和/或第二導體板14上形成狹縫。在該情況下，也能夠在多個半導體元件22、24、26之間實現電流C22、C24、C26的路徑長度的均等化。或者，也可以根據第一外部連接端子32與各個半導體元件22、24、26之間的距離，而使各個半導體元件22、24、26的電流C22、C24、C26流動的路徑的截面積發生變化。根據這樣的結構，也能夠改善第一外部連接端子32與各個半導體元件22、24、26之間的電阻的不均等。 雖然在上述的實施例中，半導體裝置10具備兩個第二外部連接端子34，但第二外部連接端子34的數量並未被特別地限定。如前文所述，半導體裝置10既可以僅具有單一的第二外部連接端子34，也可以具有三個以上的第二外部連接端子34。另外，第二外部連接端子34既可以位於相對於密封體16而與第一外部連接端子32相同的一側，也可以位於與第一外部連接端子32不同的一側。 圖14、圖15表示具有單一的第二外部連接端子34的半導體裝置10a、10b。在圖14所示的半導體裝置10a中，省略了前文所述的半導體裝置10的兩個第二外部連接端子34中的一方的第二外部連接端子34。在圖15所示的半導體裝置10b中，省略了前文所述的半導體裝置10的兩個第二外部連接端子34中的另一方的第二外部連接端子34。 如前文所述，在本說明書中公開的半導體裝置10、10a、10b能夠應用於變換器或逆變器那樣的電力轉換電路中。在該情況下，如圖16所示，藉由對兩個半導體裝置10、10a、10b進行串聯連接，從而能夠構成變換器或逆變器中的上下的橋臂。在兩個半導體裝置10、10a、10b的各個半導體裝置中，可以採用本說明書中所公開的三個種類的半導體裝置10、10a、10b的任意一個。 圖17-圖20表示兩個半導體裝置10、10a、10b被串聯連接的幾個方式。在圖17所示的方式中，圖14所示的半導體裝置10a和圖15所示的半導體裝置10b被串聯連接。兩個半導體裝置10a、10b以對置的方式被配置，雖然在圖17中並未被圖示，但一方的(近前側的)半導體裝置10a的第二導體板14和另一方的(縱深側的)半導體裝置10b的第一導體板12相對。一方的半導體裝置10a的第二外部連接端子34經由匯流條11，而與另一方的半導體裝置10b的第一外部連接端子32連接。並且，圖17-圖20中的符號P、O、N分別與圖16中的符號P、O、N對應。 在圖18所示的方式中，圖14所示的半導體裝置10a與圖15所示的半導體裝置10b也被串聯連接。但是，與圖17所示的方式相比，交換了兩個半導體裝置10a、10b的位置，雖然在圖18中未圖示，但一方的(縱深側的)半導體裝置10a的第一導體板12與另一方的(近前側的)半導體裝置10b的第二導體板14相對。一方的半導體裝置10a的第二外部連接端子34經由匯流條11而與另一方的半導體裝置10b的第一外部連接端子32連接。 在圖19所示的方式中，圖14所示的半導體裝置10a的兩個被串聯連接。兩個半導體裝置10a以對置的方式被配置，雖然在圖19中未被圖示，但一方的(近前側的)半導體裝置10a的第一導體板12與另一方的(縱深側的)半導體裝置10a的第一導體板12相對。即，兩個半導體裝置10a成為相互被反轉後的姿態。一方的半導體裝置10a的第一外部連接端子32經由匯流條11而與另一方的半導體裝置10a的第二外部連接端子34連接。 在圖20所示的方式中，圖14所示的半導體裝置10a的兩個也被串聯連接。但是，與圖19所示的方式相比，各個半導體裝置10a的方向被反轉，雖然在圖20中未被圖示，但一方的半導體裝置10a的第二導體板14與另一方的半導體裝置10a的第二導體板14相對。一方的半導體裝置10a的第一外部連接端子32經由匯流條11而與另一方的半導體裝置10a的第二外部連接端子34連接。並且，對兩個以上的半導體裝置10、10a、10b進行連接的方式並未被限定於圖17-圖20所示的方式。 根據本說明書中所公開的技術，半導體裝置能夠具備第一導體板、被配置於第一導體板上的多個半導體元件、和與第一導體板連接的第一外部連接端子。在該情況下，多個半導體元件能夠包括第一半導體元件、第二半導體元件以及第三半導體元件。而且，能夠在第一導體板中設置至少一個孔，由此，能夠使向第一半導體元件、第二半導體元件以及第三半導體元件的各個半導體元件流動的電流均勻化。此處所述的均勻化是指，與不存在孔的情況相比電流的差異被減少的情況。 接下來，參照圖21-圖25，對實施例2的半導體裝置110進行說明。在該半導體裝置110中，在第一導體板112和第二導體板114中應用了絕緣基板，在這一點上與上述的半導體裝置10、10a、10b不同。第二點，第三外部連接端子36的數量被變更，詳細而言，第三外部連接端子36的數量與多個半導體元件22、24、26的信號焊墊22c、24c、26c的數量相等。第三點，各個半導體元件22、24、26不經由導體間隔件18而與第一導體板112接合。關於其他的結構，與上述的半導體裝置10、10a、10b相同或對應。關於與上述的半導體裝置10、10a、10b相同或對應的結構，藉由標記相同的符號，而省略重複的說明。 如圖21-圖25所示，第一導體板112具有內側導體層112a、絕緣層112b和外側導體層112c。絕緣層112b位於內側導體層112a與外側導體層112c之間。雖然是一個示例，但內側導體層112a以及外側導體層112c各自也可以為銅或鋁等的金屬層，絕緣層112b也可以為陶瓷基板。在這樣的第一導體板112中，能夠例如應用DBC(Direct Bonded Copper)或DBA(Direct Bonded Aluminum，直接敷鋁)。 在內側導體層112a中，在密封體16的內部接合有多個半導體元件22、24、26的上表面電極22a、24a、26a。另外，在內側導體層112a中，也接合有第一外部連接端子32。由此，第一外部連接端子32經由內側導體層112a而與半導體元件22、24、26電連接。而且，在內側導體層112a中，形成有用於使向各個半導體元件22、24、26流動的電流均勻化的孔40。關於孔40的功能，與前文所述的半導體裝置10同樣。即，孔40使在第二半導體元件24與第一外部連接端子32之間流動的電流迂回過，由此，使向距第一外部連接端子32的距離不同的多個半導體元件22、24、26流動的電流均勻化。關於孔40的具體結構(例如，位置、大小、形狀)，能夠與前文所述的半導體裝置10同樣地進行適當的設計。 並且，第一導體板112的內側導體層112a具有主要部分X和多個信號線性部分Y。在主要部分X上，接合有多個半導體元件22、24、26和第一外部連接端子32，且設置有孔40。多個信號線性部分Y從主要部分X起分離(絕緣)地設置，並使多個信號焊墊22c、24c、26c分別與多個第三外部連接端子36連接。這樣，在第一導體板112為絕緣基板時，能夠自由地對內側導體層112a的分佈進行設計，並能夠簡化半導體裝置110的內部結構。 第一導體板112的孔40被僅僅設置於內側導體層112a內，並具有由絕緣層112b劃分出的底面。根據這樣的結構，能夠避免第一導體板112的剛性因孔40的存在而降低的情況。另外，也能夠避免內側導體層112a和外側導體層112c意外地導通的情況。並且，外側導體層112c露出於密封體16的表面，並與例如外部的冷卻器鄰接地配置。 第二導體板114具有內側導體層114a、絕緣層114b和外側導體層114c。絕緣層114b位於內側導體層114a與外側導體層114c之間。第二導體板114的內側導體層114a與第一導體板112的內側導體層112a對置。雖然是一個示例，但內側導體層114a以及外側導體層114c各自可以為銅或鋁等的金屬層，絕緣層114b可以為陶瓷基板。在這樣的第二導體板114中，能夠應用例如DBC或DBA。 在內側導體層114a中，在密封體16的內部接合有多個半導體元件22、24、26的下表面電極22b、24b、26b。另外，在內側導體層114a中，也接合有兩個第二外部連接端子34。由此，兩個第二外部連接端子34經由內側導體層114a而與半導體元件22、24、26電連接。另一方面，外側導體層112c露出於密封體16的表面，並與例如外部的冷卻器鄰接地配置。 如上所述，在半導體裝置110中，在第一導體板112和第二導體板114中應用了絕緣基板。根據這樣的結構，能夠以自由分佈的方式而形成內側導體層112a、114a，例如，能夠以較大的面積使第一導體板112的內側導體層112a和第二導體板114的內側導體層114a對置。由於在第一導體板112的內側導體層112a和第二導體板114的內側導體層114a中流動有互為反向的電流，因此，當這些內側導體層112a、114a以較大的面積對置時，能夠有意地降低半導體裝置110的阻抗。由此，能夠抑制在例如半導體元件22、24、26的開關時產生的浪湧電壓。In one embodiment of the present technology, it is also possible to adopt a method in which the hole is formed so that all the current flowing between the first external connection terminal and the second semiconductor element bypasses the via hole. According to such a structure, the resistance between the first external connection terminal and the second semiconductor element can be sufficiently increased. In an embodiment of the present technology, the following manner may also be adopted, that is, the first semiconductor element, the second semiconductor element, and the third semiconductor element will be perpendicular to the first conductor plate and pass through the plane of the second semiconductor element. As a symmetry plane, they are arranged substantially side-by-side symmetrically (that is, plane symmetry). According to such a structure, it is possible to sufficiently reduce the unevenness of the current flowing to each semiconductor element between the first semiconductor element and the third semiconductor element. In addition, the term “substantially bilaterally symmetrical” as used herein means that a certain error (for example, an error within half of the size of a semiconductor element (so-called wafer size)) is allowed compared to an arrangement that is accurately left-right symmetrical. In one embodiment of the present technology, it is also possible to adopt a manner in which the first external connection terminal is connected to the first conductor plate within a range that intersects the symmetry plane. According to this structure, the distance from the first external connection terminal to the first semiconductor element and the distance from the first external connection terminal to the third semiconductor element can be made equal to each other. As a result, it is possible to make the currents flowing to the respective semiconductor elements substantially equal between the first semiconductor element and the third semiconductor element. In an embodiment of the present technology, it is also possible to adopt a manner in which the hole has an opening shape that is bilaterally symmetrical with respect to the symmetry plane. According to such a structure, it is possible to prevent the symmetry between the first semiconductor element and the third semiconductor element from disappearing due to the existence of the hole. In one embodiment of the present technology, it is also possible to adopt a manner in which the hole has an elongated hole shape. In this case, the long side axis of the long hole shape may be perpendicular to the plane of symmetry. According to such a structure, the design or manufacture of an appropriate hole can be easily implemented. However, the opening shape of the hole is not limited to a simple long hole shape, and it may have a more complicated shape. In one embodiment of the present technology, it is also possible to adopt a manner in which the size of the hole is larger than the size of the second semiconductor element with respect to the direction perpendicular to the symmetry plane. According to this structure, although it is also based on the size of the first external connection terminal, most or all of the current flowing between the first external connection terminal and the second semiconductor element can be bypassed by the hole. In one embodiment of the present technology, it is also possible to adopt a manner in which the size of the hole in the direction perpendicular to the symmetry plane is smaller than the center-to-center distance between the first semiconductor element and the third semiconductor element. According to such a structure, it is possible to prevent the current flowing between the first external connection terminal and the second semiconductor element from being excessively detoured by the hole. In an embodiment of the present technology, it is also possible to adopt a manner in which the range in which the first external connection terminal is connected to the first conductor plate is bilaterally symmetrical with respect to the symmetry plane. According to such a structure, the symmetry between the first semiconductor element and the third semiconductor element can be further improved. In an embodiment of the present technology, the following manner may also be adopted, that is, in the direction perpendicular to the symmetry plane, the size of the hole is larger than the size of the range where the first external connection terminal is connected to the first conductor plate . According to such a structure, although it also depends on the size of the second semiconductor element, it is possible to bypass most or all of the current flowing between the first external connection terminal and the second semiconductor element by using the hole. In an embodiment of the present technology, it is also possible to adopt a manner in which the first conductor plate has an enlarged portion, and the size of the enlarged portion in the direction perpendicular to the plane of symmetry is different from the one connected to the first external connection terminal. The range expands from the range in which a plurality of semiconductor elements are connected. In this case, at least a part of the hole may also be located at the enlarged portion. According to such a structure, a large-sized hole can be provided. In addition, by providing such an enlarged portion, the current path between the first external connection terminal and the first semiconductor element, or the current path between the first external connection terminal and the third semiconductor element can be shortened, and the semiconductor device can be reduced. Power loss in the installation. In one embodiment of the present technology, it is also possible to adopt a form in which the first semiconductor element, the second semiconductor element, and the third semiconductor element are arranged side by side along a straight line perpendicular to the plane of symmetry. According to such a structure, since the arrangement of the plurality of semiconductor elements is relatively simple, it is possible to have a simple structure even with regard to holes, for example. In one embodiment of the present technology, it is also possible to adopt a manner in which the semiconductor device further includes a second conductor plate, and the second conductor plate is opposed to the first conductor plate and is connected to each of the plurality of semiconductor elements. Two semiconductor components are connected. In this case, although not particularly limited, the semiconductor device may also include at least one second external connection terminal connected to the second conductor plate. The technology disclosed in this specification does not depend on, for example, the number of conductor plates or external connection terminals, and can be applied to semiconductor devices of various structures. In the above-mentioned embodiment, the following manner may also be adopted, that is, the at least one second external connection terminal includes two second external connection terminals. In this case, one of the two second external connection terminals only needs to be connected to the second conductor plate on one side of the symmetry plane. Furthermore, the other of the two second external connection terminals only needs to be connected to the second conductor plate on the other side of the symmetry plane. In this case, although not particularly limited, the two second external connection terminals may be provided so as to be substantially bilaterally symmetrical with respect to the symmetry plane. According to such a structure, even in the second conductor plate, it is possible to reduce the unevenness of the current flowing to the respective semiconductor elements. In an embodiment of the present technology, the following manner may also be adopted, that is, when viewed in a plan view from a direction perpendicular to the first conductor plate and the second conductor plate, the area of the second conductor plate is larger than that of the first conductor plate. area. According to such a structure, when assembling the first conductor plate to the second conductor plate during the manufacture of the semiconductor device, the first conductor plate can be supported by the jigs erected around the second conductor plate. The positioning between the first conductor plate and the second conductor plate is implemented. In addition, when the area of the electrode (e.g., collector) of the semiconductor element connected to the second conductor plate is larger than the area of the electrode (e.g., emitter) of the semiconductor element connected to the first conductor plate, the area of the electrode (e.g., collector) of the semiconductor element connected to the second conductor plate is larger. The area of the conductor plate is larger than the area of the second conductor plate, so that heat dissipation from the semiconductor element can be improved. In one embodiment of the present technology, it is also possible to adopt a manner in which, when viewed in plan from a direction perpendicular to the first conductor plate and the second conductor plate, the first conductor plate has an enlarged portion, and the enlarged portion is The width of the first conductor plate is expanded from the range where the first external connection terminal is connected to the range where the plurality of semiconductor elements are connected. According to such a structure, the current path between the first external connection terminal and the first semiconductor element or the current path between the first external connection terminal and the third semiconductor element can be shortened, and the power loss in the semiconductor device can be reduced. In the above-mentioned embodiment, it is also possible to adopt a manner in which the thickness dimension in the enlarged portion of the first conductor plate may be smaller than the thickness dimension of the first conductor plate in the range where the plurality of semiconductor elements are connected. In this case, the enlarged portion of the first conductor plate may be covered by the sealing body. The enlarged part of the first conductor plate is covered by the sealing body, so that the creeping distance of the sealing body along the surface is changed between the enlarged part of the first conductor plate and the second external connection terminal connected to the second conductor plate. Long, which can improve insulation. In the above-mentioned embodiment, it is also possible to adopt a form in which at least a part of the enlarged portion faces the second external connection terminal. In the enlarged portion connected to the first external connection terminal, current flows in the opposite direction to the second external connection terminal. Therefore, when at least a part of the enlarged portion is opposed to the second external connection terminal, the magnetic field generated by the energization is cancelled, so that the inductance of the current path can be reduced. In the above-mentioned embodiment, the following manner may also be adopted. That is, the first semiconductor element, the second semiconductor element, and the third semiconductor element each include an IGBT (Insulated Gate Bipolar Transistor) having an emitter and a collector. Type transistor). In this case, the emitter is electrically connected to the first conductor plate, and the collector is electrically connected to the second conductor plate. However, in other embodiments, each of the first semiconductor element, the second semiconductor element, and the third semiconductor element may also be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or Other semiconductor components such as diodes. In one embodiment of the present technology, the first conductive plate may be an insulating substrate having an inner conductor layer, an outer conductor layer, and an insulating layer between the inner conductor layer and the outer conductor layer. In this case, the first external connection terminal may be electrically connected to the plurality of semiconductor elements via the inner conductor layer. Furthermore, the hole may be provided in the inner conductor layer. When the first conductor plate is an insulating substrate, the inner conductor layer can be formed by free distribution. For example, when the first conductor plate and the second conductor plate face each other, the impedance of the semiconductor device can be reduced by increasing the area where the inner conductor layer and the second conductor plate face each other. In the above-mentioned embodiment, the hole may be provided only in the inner conductor layer and have a bottom surface partitioned by the insulating layer. According to such a structure, it is possible to prevent the rigidity of the first conductor plate from being lowered due to the existence of holes. In addition, it is possible to avoid accidental conduction between the inner conductor layer and the outer conductor layer. In one embodiment of the present technology, the second conductive plate may be an insulating substrate having an inner conductor layer, an outer conductor layer, and an insulating layer between the inner conductor layer and the outer conductor layer. In this case, the second external connection terminal may be electrically connected to the plurality of semiconductor elements via the inner conductor layer of the second conductor plate. According to such a structure, the inner conductor layer of the first conductor plate and the inner conductor layer of the second conductor plate can be opposed to each other with a large area, thereby further reducing the impedance of the semiconductor device. In the above-mentioned insulating substrate of the first conductor plate and/or the second conductor, it is also possible to adopt a mode in which the inner conductor layer and the outer conductor layer are each a metal layer, and the insulating layer is a ceramic substrate. In this case, the insulating substrate may also be a DBC (Direct Bonded Copper) substrate. Hereinafter, a representative or non-limiting specific example of the present invention will be described in detail with reference to the accompanying drawings. This detailed description simply intends to show the details of the preferred examples for implementing the present invention to those skilled in the art, and does not intend to limit the scope of the present invention. In addition, in order to provide a further improved semiconductor device, its use method, and its manufacturing method, the additional features and inventions disclosed below can be applied to features or inventions that are different from other features or inventions, or can be combined with other features or inventions. Inventions used together. In addition, the combination of features or processes disclosed in the following detailed description is not a combination necessary to implement the present invention in the broadest sense, but is described only for describing representative specific examples of the present invention. combination. In addition, in providing additional and useful embodiments of the present invention, various features of the above-mentioned and following representative specific examples, and various features described in independent items and government claims The features do not necessarily need to be combined as in the specific examples described here or in the order listed. All the features described in this specification and/or the scope of patent application are, compared with the structure of the features described in the embodiments and/or the scope of patent application, as a limitation for the disclosure of the original application and the specific matters claimed Features that are intended to be disclosed individually or independently of each other. In addition, as a limitation on the disclosure of the original application and the claimed specific matters, descriptions related to all numerical ranges and groups or groups are implemented with the intention of disclosing their intermediate structure. [Example] With reference to the drawings, the semiconductor device 10 of the embodiment will be described. The semiconductor device 10 can be applied to a power conversion circuit such as a converter or an inverter in an electric vehicle, for example. The electric vehicle referred to here broadly refers to vehicles that have motors that drive wheels. For example, they include electric vehicles that are charged by external electric power, hybrid vehicles that have an engine in addition to the motors, and Fuel cell vehicles, etc. that use fuel cells as power sources. As shown in FIGS. 1 to 4, the semiconductor device 10 includes a first conductor plate 12, a second conductor plate 14, a plurality of semiconductor elements 22, 24, and 26, and a sealing body 16. The first conductor plate 12 and the second conductor plate 14 are parallel to each other and face each other. Although it is an example, the first semiconductor element 22, the second semiconductor element 24, and the third semiconductor element 26 are included in the plurality of semiconductor elements 22, 24, and 26. The first semiconductor element 22, the second semiconductor element 24, and the third semiconductor element 26 are arranged linearly along the longitudinal direction of the first conductor plate 12 and the second conductor plate 14 (the left-right direction in FIGS. 2 and 3) Configuration. The plurality of semiconductor elements 22, 24, and 26 are arranged in parallel between the first conductor plate 12 and the second conductor plate 14. The plurality of semiconductor elements 22, 24, and 26 are sealed by the sealing body 16. The first conductor plate 12 and the second conductor plate 14 are formed of conductors such as copper or other metals. The first conductor plate 12 and the second conductor plate 14 are opposed to each other with a plurality of semiconductor elements 22, 24, and 26 interposed therebetween. The respective semiconductor elements 22, 24, and 26 are joined to the first conductor plate 12 and are also joined to the second conductor plate 14. In addition, a conductor spacer 18 is provided between each of the semiconductor elements 22, 24, and 26 and the first conductor plate 12. Here, the specific structures of the first conductor plate 12 and the second conductor plate 14 are not particularly limited. For example, at least one of the first conductor plate 12 and the second conductor plate 14 may be an insulating substrate having an intermediate layer of an insulator (for example, ceramic) such as a DBC (Direct Bonded Copper) substrate. That is, each of the first conductor plate 12 and the second conductor plate 14 may not necessarily be entirely composed of conductors. The first semiconductor element 22, the second semiconductor element 24, and the third semiconductor element 26 are so-called power semiconductor elements for power circuits, and have the same structure as each other. The first semiconductor element 22 has an upper surface electrode 22a, a lower surface electrode 22b, and a plurality of signal pads 22c. The upper surface electrode 22a and the lower surface electrode 22b are electrodes for electric power, and the plurality of signal pads 22c are electrodes for signal. The upper surface electrode 22 a and the plurality of signal pads 22 c are located on the upper surface of the first semiconductor element 22, and the lower surface electrode 22 b is located on the lower surface of the first semiconductor element 22. The upper surface electrode 22 a is electrically connected to the first conductor plate 12 via the conductor spacer 18, and the lower surface electrode 22 b is electrically connected to the second conductor plate 14. Similarly, the second semiconductor element 24 and the third semiconductor element 26 also have upper surface electrodes 24a, 26a, lower surface electrodes 24b, 26b, and a plurality of signal pads 24c, 26c, respectively. The upper surface electrodes 24 a and 26 a are electrically connected to the first conductor plate 12 via the conductor spacer 18, and the lower surface electrodes 24 b and 26 b are electrically connected to the second conductor plate 14. Although it is an example, the semiconductor elements 22, 24, and 26 in this embodiment include an IGBT structure having an emitter and a collector. The emitter of the IGBT structure is connected to the upper surface electrodes 22a, 24a, and 26a, and the collector of the IGBT structure is connected to the lower surface electrodes 22b, 24b, and 26b. However, the specific types or structures of the semiconductor elements 22, 24, and 26 are not particularly limited. The semiconductor elements 22, 24, and 26 may also be RC (Reverse Conducting)-IGBT elements that also have a diode structure. Alternatively, the semiconductor elements 22, 24, and 26 may replace the IGBT structure, or have a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) structure in addition to the IGBT structure. In addition, the semiconductor material used in the semiconductor elements 22, 24, and 26 is not particularly limited. For example, it may be silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). Nitride semiconductor. The sealing body 16 is not particularly limited, and can be made of thermosetting resin such as epoxy resin or other insulators. The sealing body 16 is also called a molded resin or a package body, for example. The semiconductor device 10 is not limited to the three semiconductor elements 22, 24, and 26, and may include more semiconductor elements. In this case, a plurality of semiconductor elements are sealed by a single sealing body 16 and are arranged in parallel between the first conductor plate 12 and the second conductor plate 14. The first conductor plate 12 and the second conductor plate 14 are not only electrically connected to the plurality of semiconductor elements 22, 24, and 26, but also thermally connected to the plurality of semiconductor elements 22, 24, and 26. In addition, the first conductor plate 12 and the second conductor plate 14 are respectively exposed on the surface of the sealing body 16, and the heat of the respective semiconductor elements 22, 24, and 26 can be released to the outside of the sealing body 16. Therefore, the semiconductor device 10 of the present embodiment has a double-sided cooling structure in which heat dissipation plates are arranged on both sides of the plurality of semiconductor elements 22, 24, and 26. The semiconductor device 10 further includes a first external connection terminal 32, two second external connection terminals 34, and eleven third external connection terminals 36. The external connection terminals 32, 34, and 36 are constituted by conductors such as copper or aluminum, and extend from the inside of the sealing body 16 to the outside. The first external connection terminal 32 is connected to the first conductor plate 12 inside the sealing body 16. Each second external connection terminal 34 is connected to the second conductor plate 14 inside the sealing body 16. As a result, the plurality of semiconductor elements 22, 24, and 26 are electrically connected in parallel between the first external connection terminal 32 and each of the second external connection terminals 34. Each third external connection terminal 36 is connected to a corresponding one of the signal pads 22 c, 24 c, and 26 c of the semiconductor elements 22, 24, and 26 via a bonding wire 38. Although it is an example, the first external connection terminals 32 are joined to the first conductor plate 12 by welding, and the respective second external connection terminals 34 are integrally formed on the second conductor plate 14. However, the first external connection terminal 32 may also be formed integrally with the first conductor plate 12. In addition, each of the second external connection terminals 34 may be joined to the second conductor plate 14 by welding, for example. Furthermore, each third external connection terminal 36 may be connected to one of the corresponding signal pads 22c, 24c, and 26c without the bonding wire 38. As shown in FIG. 5, the first semiconductor element 22, the second semiconductor element 24, and the third semiconductor element 26 are perpendicular to the first conductor plate 12, and the plane PS passing through the second semiconductor element 24 is regarded as a symmetry plane, and is symmetrical. Arrangement configuration. Furthermore, the first external connection terminal 32 is connected to the first conductor plate 12 in a range 33 intersecting the symmetry plane PS. This range 33 is closest to the second semiconductor element 24 among the three semiconductor elements 22, 24, and 26. When such a structure is adopted, the distance between the first external connection terminal 32 connected to the first conductor plate 12 and the respective semiconductor elements 22, 24, and 26 is not completely the same. For example, the distance from the first external connection terminal 32 to the first semiconductor element 22 is equal to the distance from the first external connection terminal 32 to the third semiconductor element 26. However, the distance from the first external connection terminal 32 to the second semiconductor element 24 is shorter than the distance from the first external connection terminal 32 to the first semiconductor element 22 or the third semiconductor element 26. If there is such a difference in distance, an unignorable difference will also occur in the resistance between the first external connection terminal 32 and the respective semiconductor elements 22, 24, and 26. As a result, in the respective semiconductor elements 22, 24, and 26, current flows unevenly. Regarding the above-mentioned problem, in the first conductor plate 12 in this embodiment, a hole 40 is provided between the area 33 where the first external connection terminal 32 is connected and the area where the second semiconductor element 24 is connected. Therefore, as shown in FIG. 6, at least a part of the current C24 flowing between the first external connection terminal 32 and the second semiconductor element 24 needs to flow around the via hole 40, due to the actual path length of the current flow. Becomes longer, so the resistance will increase. As a result, since the current flowing in the second semiconductor element 24 is suppressed, the unevenness of the currents C22, C24, and C26 flowing to the respective semiconductor elements 22, 24, 26 is eliminated or reduced. Furthermore, as shown in FIG. 7, since the currents C24 flow in opposite directions to each other on both sides of the hole 40 therebetween, the inductance generated in the first conductor plate 12 is reduced. This is particularly advantageous when the semiconductor device 10 is applied to an inverter or a converter, and the respective semiconductor elements 22, 24, and 26 are switched at a high frequency. In addition, although the hole 40 in this embodiment is a through hole, the hole 40 may also be a bottomed hole (that is, a recess). Even in this case, in the position of the hole 40, by reducing the thickness dimension of the first conductor plate 12, the resistance will increase. In addition, a material having a higher resistance than the material constituting the first conductor plate 12 is arranged inside the hole 40. The shape and size of the hole 40 are not particularly limited. The shape and size of the hole 40 can be appropriately designed while verifying the currents C22, C24, and C26 flowing to the respective semiconductor elements 22, 24, and 26 through experiments or simulations. As shown in FIG. 5, the hole 40 in this embodiment has a long hole shape, and the long side axis of the long hole shape is perpendicular to the symmetry plane PS. In addition, the hole 40 has an opening shape symmetrical about the symmetry plane PS, and the center of the long hole shape is located on the symmetry plane PS. When the opening shape of the hole 40 is bilaterally symmetrical with respect to the symmetry plane PS, it can be avoided that the symmetry between the first semiconductor element 22 and the third semiconductor element 26 disappears due to the existence of the hole 40. In addition, the hole 40 may be designed with a more complicated shape instead of a simpler long hole shape. In addition, the first conductor plate 12 is not limited to one hole 40, and a plurality of holes may be formed. Roughly speaking, the larger the size of the hole 40 (especially the size in the direction perpendicular to the symmetry plane PS), the more the flow between the first external connection terminal 32 and the second semiconductor element 24. The current C24 bypasses the via 40. In this regard, the hole 40 in the present embodiment is formed so that all the current C24 flowing between the first external connection terminal 32 and the second semiconductor element 24 bypasses the via 40. Specifically, regarding the direction perpendicular to the symmetry plane PS (ie, regarding the left-right direction in FIG. 5), the size of the hole 40 is larger than the size of the second semiconductor element 24, and larger than the first conductor plate 12 connected to the first The size of the range 33 of the external connection terminal 32. In addition, the first external connection terminal 32 extends along the symmetry plane PS, and the range 33 in which the first external connection terminal 32 is connected to the first conductor plate 12 is also bilaterally symmetrical with respect to the symmetry plane PS. On the other hand, when the size of the hole 40 is too large, the current C24 flowing between the first external connection terminal 32 and the second semiconductor element 24 will be excessively detoured by the hole 40. In this case, the resistance between the first external connection terminal 32 and the second semiconductor element 24 may increase unnecessarily. According to this situation, regarding the direction perpendicular to the plane of symmetry PS, the size of the hole 40 may be smaller than the center-to-center distance between the first semiconductor element 22 and the third semiconductor element 26. In addition, in FIG. 5, the point 22X represents the center of the first semiconductor element 22, the point 24X represents the center of the second semiconductor element 24, and the point 26X represents the center of the third semiconductor element 26. The center 22X of the first semiconductor element 22 is located on one side of the symmetry plane PS, the center 24X of the second semiconductor element 24 is located on the symmetry plane PS, and the center 26X of the third semiconductor element 26 is located on the other side of the symmetry plane PS. As shown in FIG. 5, the first conductor plate 12 has an area extending from the area 33 where the first external connection terminal 32 is connected to the area where the plurality of semiconductor elements 22, 24, and 26 are connected, and is enlarged in the direction perpendicular to the plane of symmetry PS. The size portion 13 (hereinafter referred to as the enlarged portion 13). Moreover, the hole 40 is located at the enlarged portion 13. According to such a structure, the hole 40 of a relatively large size can be provided. In addition, by providing such an enlarged portion 13, the current path between the first external connection terminal 32 and the first semiconductor element 22 or the current path between the first external connection terminal 32 and the third semiconductor element 26 can be shortened. , And can reduce the power loss in the semiconductor device 10. In addition, the entire hole 40 in this embodiment is provided on the enlarged portion 13 described above, but as another embodiment, only a part of the hole 40 may be provided on the enlarged portion 13. Here, the enlarged portion 13 of the first conductor plate 12 is formed thinner than the other area of the first conductor plate 12 (that is, the area where the plurality of semiconductor elements 22, 24, and 26 are connected). The specific structure of the enlarged portion 13 is not particularly limited. Although it is an example, the enlarged portion 13 in this embodiment has a pair of side edges 13a. Each side edge 13a extends from the base end 13b on the side of the plurality of semiconductor elements 22, 24, and 26 to the front end 13c on the side of the first external connection terminal 32. As shown in FIG. 5, when viewed in plan from a direction perpendicular to the first conductor plate 12 and the second conductor plate 14, the base end 13b of the side edge 13a of the enlarged portion 13 is located at the inner edge of the second external connection terminal 34 34a (that is, the side edge 34a located on the side of the first external connection terminal 32) is relatively outside (that is, the far side when viewed from the first external connection terminal 32). In addition, the front end 13c of the side edge 13a of the enlarged portion 13 is located on the inner side of the inner side edge 34a of the second external connection terminal 34 (that is, the closer side when viewed from the first external connection terminal 32), and is located at the first Between an external connection terminal 32 and a second external connection terminal 34. According to the above-mentioned structure, it is possible to shorten each current path between the first external connection terminal 32 and the first semiconductor element 22 or the third semiconductor element 26 while improving the insulation between the enlarged portion 13 and the second external connection terminal 34. Sex. In particular, the second external connection terminal 34 is provided with a bent portion 34b (refer to FIGS. 4 and 5) that is displaced upward (that is, the enlarged portion 13 side) toward the front end side thereof, whereby the first external connection The terminal 32 and the two second external connection terminals 34 are located on the same plane in at least a portion protruding from the sealing body 16. Therefore, assuming that the front end 13c of the side edge 13a of the enlarged portion 13 is located more outside than the inner edge 34a of the second external connection terminal 34, since the enlarged portion 13 and the second external connection terminal 34 bent toward the enlarged portion 13 are close to each other, Therefore, the insulation between the two may be insufficient. In contrast, when the front end 13c of the side edge 13a of the enlarged portion 13 is located more inside than the inner edge 34a of the second external connection terminal 34, the distance between the enlarged portion 13 and the second external connection terminal 34 can be increased , Which can improve the insulation between the two. The thickness dimension in the enlarged portion 13 of the first conductor plate 12 is smaller than the thickness dimension of the first conductor plate 12 in the range where the plurality of semiconductor elements 22, 24, and 26 are connected. Thus, the enlarged portion 13 of the first conductor plate 12 is covered by the sealing body 16 and is not exposed on the surface of the sealing body 16. The enlarged portion 13 of the first conductor plate 12 is covered by the sealing body 16, so that it can be extended between the enlarged portion 13 of the first conductor plate 12 and the second external connection terminal 34 connected to the second conductor plate 14 The creeping distance along the surface of the sealing body 16 improves insulation. As shown in FIG. 5, at least a part of the enlarged portion 13 is opposed to the second external connection terminal 34. In the enlarged portion 13 connected to the first external connection terminal 32, current flows in the opposite direction to the second external connection terminal 34. Therefore, when at least a part of the enlarged portion 13 is opposed to the second external connection terminal 34, the magnetic field generated by the energization is cancelled, so that the inductance of the current path can be reduced. In this regard, the larger the area where the enlarged portion 13 opposes the second external connection terminal 34, the higher the effect of reducing inductance. According to this situation, as shown in FIG. 13, the enlarged portion 13 connected to the first external connection terminal 32 may be further expanded. As a result, the area where the enlarged portion 13 and the second external connection terminal 34 face each other can be further increased. Although it is an example, in the modified example shown in FIG. 13, the side edge 13 a of the enlarged portion 13 spans from the base end 13 b to the entire front end 13 c and is located on the second external connection terminal 34. In this embodiment, the first semiconductor element 22, the second semiconductor element 24, and the third semiconductor element 26 are arranged side by side along a straight line perpendicular to the plane of symmetry PS. According to such a structure, since the arrangement of these semiconductor elements 22, 24, and 26 is relatively simple, for example, the hole 40 can also be provided as a simple structure, so that the design and formation of an appropriate hole 40 can be easily implemented. However, the arrangement of the first semiconductor element 22, the second semiconductor element 24, and the third semiconductor element 26 can be appropriately changed. For example, the first semiconductor element 22, the second semiconductor element 24, and the third semiconductor element 26 may be arranged in a V-shape or an inverted V-shape that is bilaterally symmetrical with respect to the symmetry plane PS. In addition, the first semiconductor element 22, the second semiconductor element 24, and the third semiconductor element 26 are not necessarily arranged in an accurate left-right symmetrical arrangement, and a certain error is allowed in this arrangement. As this error, for example, an error within a half or within a quarter of the size (so-called wafer size) of the semiconductor elements 22, 24, and 26 is assumed. In the semiconductor device 10 of this embodiment, two second external connection terminals 34 are connected to the second conductor plate 14, and the two second external connection terminals 34 are arranged to be symmetrical about the symmetry plane PS. In this way, when two or more second external connection terminals 34 are provided symmetrically about the symmetry plane PS, the resistance of the second conductor plate 14 with respect to the respective semiconductor elements 22, 24, and 26 can be made relatively uniform. In addition, the two second external connection terminals 34 are not necessarily strictly bilaterally symmetrical with respect to the symmetry plane PS. However, one of the two second external connection terminals 34 only needs to be connected to the second conductor plate 14 on one side of the symmetry plane PS, and the other of the two second external connection terminals 34 only needs to be on the other side of the symmetry plane PS. One side may be connected to the second conductor plate 14. In the second conductor plate 14, the structure having the hole 40 may be applied similarly to the first conductor plate 12. In this case, the number of the second external connection terminal 34 may also be one. In addition, regardless of the addition of holes to the second conductor plate 14, the number of the second external connection terminals 34 may be one. In this case, although it is an example, only one of the two second external connection terminals 34 in this embodiment may be omitted. Regarding which of the two second external connection terminals 34 is omitted, it is not particularly limited. No matter which of the second external connection terminals 34 is omitted, as long as the front and back of the semiconductor device 10 are reversed, the arrangement of the first external connection terminals 32 and the second external connection terminals 34 are the same. However, if two or more second external connection terminals 34 are connected to the second conductor plate 14, when the semiconductor device 10 is assembled into a power conversion circuit, the two or more second external connection terminals 34 will be used. The semiconductor device 10 can be stably supported. In addition, during the manufacture of the semiconductor device 10, the second conductor plate 14 can also be stably supported by the two or more second external connection terminals 34. Next, referring to FIG. 8, the structure related to the plurality of third external connection terminals 36 will be described. As described above, the plurality of third external connection terminals 36 are connected to the signal pads 22c, 24c, and 26c of the plurality of semiconductor elements 22, 24, and 26. Here, in this embodiment, each semiconductor element 22, 24, 26 has five signal pads 22c, 24c, 26c. The five signal pads 22c, 24c, and 26c of the first semiconductor element 22 include a first temperature sensing pad K, a second temperature sensing pad A, a gate drive pad G, and a current sensing pad SE And the Kelvin emitter pad KE. The first temperature sensing pad K and the second temperature sensing pad A are connected to a temperature sensor (such as a diode) in the first semiconductor device 22. The gate drive pad G is connected to the gate of the IGBT structure in the first semiconductor element 22. The current sensing pad SE outputs a minute current proportional to the current flowing to the first semiconductor element 22. Furthermore, the Kelvin emitter pad KE is connected to the emitter of the IGBT structure in the first semiconductor element 22. Similarly, the five signal pads 24c of the second semiconductor element 24 and the five signal pads 26c of the third semiconductor element 26 also include a first temperature sensing pad K and a second temperature sensing pad A , Gate drive pad G, current sense pad SE and Kelvin emitter pad KE. As can be understood from the foregoing, in the semiconductor device 10 of the present embodiment, there are a total of 15 signal pads 22c, 24c, and 26c. In contrast, the number of the plurality of third external connection terminals 36 is 11, which is less than the number of signal pads 22c, 24c, and 26c. This is because the first temperature sensing pad K and the second temperature sensing pad A of the first semiconductor element 22, and the first temperature sensing pad K and the second temperature sensing pad of the third semiconductor element 26 On the pad A, a plurality of third external connection terminals 36 are not connected. In the semiconductor device 10, the second semiconductor element 24 located in the center tends to become high temperature compared to the first semiconductor element 22 and the third semiconductor element 26 located on both sides. According to this situation, if the temperature of the second semiconductor element 24 is monitored, overheating of the first semiconductor element 22 and the third semiconductor element 26 can also be avoided. From this point of view, in the semiconductor device 10, the first temperature sensing pad K and the second temperature sensing pad A of the first semiconductor element 22, and the first temperature sensing pad K of the third semiconductor element 26 As for the second temperature sensing pad A, the connection of the third external connection terminal 36 is omitted. As a result, the number of the plurality of third external connection terminals 36 is reduced. By reducing the number of the plurality of third external connection terminals 36, for example, the number of external connectors connected to the plurality of third external connection terminals 36 can be reduced. Although it is an example, in the semiconductor device 10 of the present embodiment, it is assumed that 11 third external connection terminals 36 are connected to two external connectors, and are divided into a group of 5 and a group of 6. The way it is arranged. Next, referring to FIGS. 9-12, an example of a method of manufacturing the semiconductor device 10 will be described. First, as shown in Figure 9, the first reflow process is implemented. In this process, a plurality of semiconductor elements 22, 24, 26, a plurality of conductor spacers 18, and a lead frame 19 are prepared. The lead frame 19 is integrally provided with a second conductor plate 14, a first external connection terminal 32, two second external connection terminals 34, and a plurality of third external connection terminals 36. Next, on the second conductor plate 14 of the lead frame 19, the plurality of semiconductor elements 22, 24, and 26 and the plurality of conductor spacers 18 are soldered. At this time, the plurality of semiconductor elements 22, 24, and 26 are respectively soldered to the second conductor plate 14, and a conductor spacer 18 is soldered to each of the semiconductor elements 22, 24, and 26. Next, as shown in Figure 10, the second reflow process is implemented. In this process, the first conductor plate 12 is prepared, and the first conductor plate 12 is welded to the plurality of conductor spacers 18. Next, as shown in Figure 11, the sealing process is implemented. In this process, the plurality of semiconductor elements 22, 24, and 26 are sealed by, for example, a sealing resin, so that the sealed body 16 is formed. In this stage, the first conductor plate 12 and the second conductor plate 14 may be covered by the sealing body 16. In addition, the process of applying the primer on the lead frame 19 may be performed prior to the sealing process. Finally, as shown in FIG. 12, by cutting the useless part of the lead frame 19 and cutting or grinding the surface of the sealing body 16, the first conductor plate 12 and the second conductor plate 14 can be exposed to the sealing body. 16 on the surface. Thus, the semiconductor device 10 is completed. As described above, in the technique disclosed in this specification, by forming the hole 40 on the first conductor plate 12, the first external connection terminal 32 connected to the first conductor plate 12 and the respective semiconductor elements 22 are improved. The unequal resistance between, 24 and 26. The technique using the hole 40 can also be applied to the second conductor plate 14 in the same manner. Alternatively, even in the case where the semiconductor device 10 does not include the second conductor plate 14, the same can be applied. Furthermore, as another structural example, a slit may be formed in the first conductor plate 12 and/or the second conductor plate 14 instead of the hole 40. In this case, the path lengths of the currents C22, C24, and C26 can be equalized among the plurality of semiconductor elements 22, 24, and 26. Alternatively, according to the distance between the first external connection terminal 32 and each semiconductor element 22, 24, 26, the cross-sectional area of the path through which the current C22, C24, C26 of each semiconductor element 22, 24, 26 flows may be changed. . According to such a structure, it is also possible to improve the unevenness in resistance between the first external connection terminal 32 and the respective semiconductor elements 22, 24, and 26. Although in the above-mentioned embodiment, the semiconductor device 10 is provided with two second external connection terminals 34, the number of the second external connection terminals 34 is not particularly limited. As described above, the semiconductor device 10 may have only a single second external connection terminal 34 or may have more than three second external connection terminals 34. In addition, the second external connection terminal 34 may be located on the same side as the first external connection terminal 32 with respect to the sealing body 16, or may be located on a side different from the first external connection terminal 32. 14 and 15 show semiconductor devices 10a and 10b having a single second external connection terminal 34. In the semiconductor device 10a shown in FIG. 14, the second external connection terminal 34 of one of the two second external connection terminals 34 of the semiconductor device 10 described above is omitted. In the semiconductor device 10b shown in FIG. 15, the second external connection terminal 34 of the other of the two second external connection terminals 34 of the semiconductor device 10 described above is omitted. As described above, the semiconductor devices 10, 10a, and 10b disclosed in this specification can be applied to power conversion circuits such as converters and inverters. In this case, as shown in FIG. 16, by connecting two semiconductor devices 10, 10a, and 10b in series, the upper and lower arms of the converter or inverter can be configured. In each of the two semiconductor devices 10, 10a, and 10b, any one of the three types of semiconductor devices 10, 10a, and 10b disclosed in this specification can be used. FIGS. 17-20 show several ways in which two semiconductor devices 10, 10a, and 10b are connected in series. In the form shown in FIG. 17, the semiconductor device 10a shown in FIG. 14 and the semiconductor device 10b shown in FIG. 15 are connected in series. The two semiconductor devices 10a and 10b are arranged to face each other. Although not shown in FIG. 17, the second conductor plate 14 of the semiconductor device 10a on one side (on the front side) and the second conductor plate 14 on the other side (on the deep side) ) The first conductor plate 12 of the semiconductor device 10b is opposed to each other. The second external connection terminal 34 of one semiconductor device 10 a is connected to the first external connection terminal 32 of the other semiconductor device 10 b via the bus bar 11. In addition, the symbols P, O, and N in FIGS. 17-20 correspond to the symbols P, O, and N in FIG. 16, respectively. In the form shown in FIG. 18, the semiconductor device 10a shown in FIG. 14 and the semiconductor device 10b shown in FIG. 15 are also connected in series. However, compared with the method shown in FIG. 17, the positions of the two semiconductor devices 10a and 10b are exchanged. Although not shown in FIG. 18, the first conductor plate 12 of the semiconductor device 10a on one side (on the deep side) Opposite the second conductor plate 14 of the semiconductor device 10b on the other side (on the front side). The second external connection terminal 34 of one semiconductor device 10 a is connected to the first external connection terminal 32 of the other semiconductor device 10 b via the bus bar 11. In the form shown in FIG. 19, two of the semiconductor devices 10a shown in FIG. 14 are connected in series. The two semiconductor devices 10a are arranged to face each other. Although not shown in FIG. 19, the first conductor plate 12 of the semiconductor device 10a on one side (on the near side) and the semiconductor device on the other side (on the deep side) The first conductor plate 12 of the device 10a opposes. In other words, the two semiconductor devices 10a are in a posture that has been reversed to each other. The first external connection terminal 32 of one semiconductor device 10 a is connected to the second external connection terminal 34 of the other semiconductor device 10 a via the bus bar 11. In the form shown in FIG. 20, two of the semiconductor devices 10a shown in FIG. 14 are also connected in series. However, compared with the mode shown in FIG. 19, the direction of each semiconductor device 10a is reversed. Although not shown in FIG. 20, the second conductor plate 14 of one semiconductor device 10a and the other semiconductor device The second conductor plate 14 of 10a is opposed to each other. The first external connection terminal 32 of one semiconductor device 10 a is connected to the second external connection terminal 34 of the other semiconductor device 10 a via the bus bar 11. In addition, the method of connecting two or more semiconductor devices 10, 10a, and 10b is not limited to the method shown in FIGS. 17-20. According to the technology disclosed in this specification, a semiconductor device can include a first conductor plate, a plurality of semiconductor elements arranged on the first conductor plate, and a first external connection terminal connected to the first conductor plate. In this case, the plurality of semiconductor elements can include a first semiconductor element, a second semiconductor element, and a third semiconductor element. Furthermore, at least one hole can be provided in the first conductor plate, and thereby, the current flowing to each of the first semiconductor element, the second semiconductor element, and the third semiconductor element can be made uniform. The homogenization described here refers to a case where the difference in current is reduced compared to the case where there are no holes. Next, referring to FIGS. 21-25, the semiconductor device 110 of the second embodiment will be described. In this semiconductor device 110, an insulating substrate is applied to the first conductor plate 112 and the second conductor plate 114, and is different from the aforementioned semiconductor devices 10, 10a, and 10b in this point. The second point is that the number of third external connection terminals 36 is changed. Specifically, the number of third external connection terminals 36 is equal to the number of signal pads 22c, 24c, and 26c of the plurality of semiconductor elements 22, 24, and 26. The third point is that the respective semiconductor elements 22, 24, and 26 are joined to the first conductor plate 112 without passing through the conductor spacer 18. The other structures are the same as or corresponding to the above-mentioned semiconductor devices 10, 10a, and 10b. Regarding the structure that is the same as or corresponding to the above-mentioned semiconductor devices 10, 10a, and 10b, the same symbols are used to omit repeated descriptions. As shown in FIGS. 21-25, the first conductor plate 112 has an inner conductor layer 112a, an insulating layer 112b, and an outer conductor layer 112c. The insulating layer 112b is located between the inner conductor layer 112a and the outer conductor layer 112c. Although it is an example, each of the inner conductor layer 112a and the outer conductor layer 112c may be a metal layer such as copper or aluminum, and the insulating layer 112b may be a ceramic substrate. In such a first conductor plate 112, for example, DBC (Direct Bonded Copper) or DBA (Direct Bonded Aluminum) can be applied. In the inner conductor layer 112a, the upper surface electrodes 22a, 24a, and 26a of the plurality of semiconductor elements 22, 24, and 26 are joined to the inside of the sealing body 16. In addition, the first external connection terminal 32 is also joined to the inner conductor layer 112a. Thereby, the first external connection terminal 32 is electrically connected to the semiconductor elements 22, 24, and 26 via the inner conductor layer 112a. Furthermore, in the inner conductor layer 112a, a hole 40 for uniformizing the current flowing to the respective semiconductor elements 22, 24, and 26 is formed. The function of the hole 40 is the same as that of the semiconductor device 10 described above. In other words, the hole 40 bypasses the current flowing between the second semiconductor element 24 and the first external connection terminal 32, thereby directing the plurality of semiconductor elements 22, 24, and 24 with different distances from the first external connection terminal 32. 26 The flowing current is homogenized. The specific structure (for example, position, size, shape) of the hole 40 can be appropriately designed in the same manner as in the semiconductor device 10 described above. In addition, the inner conductor layer 112a of the first conductor plate 112 has a main part X and a plurality of signal linear parts Y. On the main part X, a plurality of semiconductor elements 22, 24, 26 and the first external connection terminal 32 are joined, and a hole 40 is provided. The plurality of signal linear portions Y are provided separately (insulated) from the main portion X, and the plurality of signal pads 22c, 24c, and 26c are connected to the plurality of third external connection terminals 36, respectively. In this way, when the first conductor plate 112 is an insulating substrate, the distribution of the inner conductor layer 112a can be freely designed, and the internal structure of the semiconductor device 110 can be simplified. The hole 40 of the first conductor plate 112 is provided only in the inner conductor layer 112a, and has a bottom surface partitioned by the insulating layer 112b. According to such a structure, it is possible to prevent the rigidity of the first conductor plate 112 from being lowered due to the existence of the hole 40. In addition, it is also possible to avoid accidental conduction between the inner conductor layer 112a and the outer conductor layer 112c. In addition, the outer conductor layer 112c is exposed on the surface of the sealing body 16, and is arranged adjacent to, for example, an external cooler. The second conductor plate 114 has an inner conductor layer 114a, an insulating layer 114b, and an outer conductor layer 114c. The insulating layer 114b is located between the inner conductor layer 114a and the outer conductor layer 114c. The inner conductor layer 114 a of the second conductor plate 114 is opposed to the inner conductor layer 112 a of the first conductor plate 112. Although it is an example, each of the inner conductor layer 114a and the outer conductor layer 114c may be a metal layer such as copper or aluminum, and the insulating layer 114b may be a ceramic substrate. In such a second conductor plate 114, for example, DBC or DBA can be applied. In the inner conductor layer 114a, the lower surface electrodes 22b, 24b, and 26b of the plurality of semiconductor elements 22, 24, and 26 are joined to the inside of the sealing body 16. In addition, two second external connection terminals 34 are also joined to the inner conductor layer 114a. Thereby, the two second external connection terminals 34 are electrically connected to the semiconductor elements 22, 24, and 26 via the inner conductor layer 114a. On the other hand, the outer conductor layer 112c is exposed on the surface of the sealing body 16, and is arranged adjacent to, for example, an external cooler. As described above, in the semiconductor device 110, insulating substrates are applied to the first conductor plate 112 and the second conductor plate 114. According to such a structure, the inner conductor layers 112a and 114a can be formed in a freely distributed manner. For example, the inner conductor layer 112a of the first conductor plate 112 and the inner conductor layer 114a of the second conductor plate 114 can be formed in a larger area. Opposite. Since currents in opposite directions flow through the inner conductor layer 112a of the first conductor plate 112 and the inner conductor layer 114a of the second conductor plate 114, when these inner conductor layers 112a, 114a face each other with a larger area At this time, the impedance of the semiconductor device 110 can be intentionally lowered. As a result, it is possible to suppress the surge voltage generated when the semiconductor elements 22, 24, and 26 are switched on and off, for example.

12‧‧‧第一導體板 13‧‧‧擴大部分 13a‧‧‧側緣 13b‧‧‧基端 13c‧‧‧前端 14‧‧‧第二導體板 22‧‧‧第一半導體元件 22X‧‧‧第一半導體元件的中心 24‧‧‧第二半導體元件 24X‧‧‧第二半導體元件的中心 26‧‧‧第三半導體元件 26X‧‧‧第三半導體元件的中心 PS‧‧‧穿過第二半導體元件24的平面(對稱面) 32‧‧‧第一外部連接端子 33‧‧‧與對稱面PS交叉的範圍 34‧‧‧第二外部連接端子 34a‧‧‧內側緣 34b‧‧‧彎曲部 40‧‧‧孔12‧‧‧First conductor plate 13‧‧‧Expanded part 13a‧‧‧Side edge 13b‧‧‧Base end 13c‧‧‧Front end 14‧‧‧Second Conductor Plate 22‧‧‧First Semiconductor Device 22X‧‧‧The center of the first semiconductor element 24‧‧‧Second semiconductor element 24X‧‧‧The center of the second semiconductor element 26‧‧‧The third semiconductor element 26X‧‧‧The center of the third semiconductor element PS‧‧‧A plane passing through the second semiconductor element 24 (plane of symmetry) 32‧‧‧The first external connection terminal 33‧‧‧The range of intersection with the symmetry plane PS 34‧‧‧Second external connection terminal 34a‧‧‧Inside edge 34b‧‧‧Bending part 40‧‧‧Hole

圖1為表示半導體裝置10的外觀的立體圖。 圖2為表示半導體裝置10的截面結構的圖。並且，該截面結構為與圖5所示的對稱面PS垂直的截面的結構。 圖3為省略了一部分的結構要素的圖示且表示半導體裝置10的內部結構的俯視圖 圖4為省略了一部分的結構要素的圖示且表示半導體裝置10的內部結構的分解圖。 圖5表示多個半導體元件22、24、26、第一導體板12中連接有第一外部連接端子32的範圍33以及被設置於第一導體板12中的孔40的位置關係。 圖6示意性地表示在第一外部連接端子32與各個半導體元件22、24、26之間流動的電流C22、C24、C26。 圖7示意性地表示電流C24在孔40的附近的流動。 圖8表示多個信號焊墊22c、24c、26c與多個第三外部連接端子36之間的連接關係。 圖9為對半導體裝置10的製造方法的一個工程進行說明的圖，並表示在引線框19上焊接有多個半導體元件22、24、26以及多個導體間隔件18的半成品。 圖10為對半導體裝置10的製造方法的一個工程進行說明的圖，並表示在多個導體間隔件18上焊接有第一導體板12的半成品。 圖11為對半導體裝置10的製造方法的一個工程進行說明的圖，並表示形成有密封體16的半成品。 圖12為對半導體裝置10的製造方法的一個工程進行說明的圖，並表示完成的半導體裝置10。 圖13表示使第一導體板12的擴大部分13擴展的改變例。 圖14表示具有單一的第二外部連接端子34的半導體裝置10a。 圖15表示具有單一的第二外部連接端子34的其他的半導體裝置10b。 圖16表示使兩個半導體裝置10(10a、10b)串聯連接時的電路結構。 圖17為表示使圖14所示的半導體裝置10a和圖15所示的半導體裝置10b串聯連接的一個方式的圖。 圖18表示使圖14所示的半導體裝置10a和圖15所示的半導體裝置10b串聯連接的其他的一個方式。 圖19表示使圖14所示的半導體裝置10a的兩個串聯連接的一個方式。 圖20表示使圖14所示的半導體裝置10a的兩個串聯連接的其他的一個方式。 圖21為表示第二實施例的半導體裝置110的俯視圖。 圖22為圖21中的XXII-XXII線上的剖視圖。 圖23為圖21中的XXIII-XXIII線上的剖視圖。 圖24為圖21中的XXIV-XXIV線上的剖視圖。 圖25為圖示了第一導體板112(絕緣基板)的內側導體層112a的俯視圖。FIG. 1 is a perspective view showing the appearance of a semiconductor device 10. FIG. 2 is a diagram showing a cross-sectional structure of the semiconductor device 10. In addition, this cross-sectional structure is a cross-sectional structure perpendicular to the symmetry plane PS shown in FIG. 5. FIG. 3 is a plan view showing the internal structure of the semiconductor device 10, omitting the illustration of a part of the structural elements FIG. 4 is an exploded view showing the internal structure of the semiconductor device 10 with a part of the structural elements omitted. FIG. 5 shows the positional relationship among the plurality of semiconductor elements 22, 24, and 26, the area 33 where the first external connection terminal 32 is connected in the first conductor plate 12, and the hole 40 provided in the first conductor plate 12. FIG. 6 schematically shows the currents C22, C24, and C26 flowing between the first external connection terminal 32 and the respective semiconductor elements 22, 24, and 26. FIG. 7 schematically shows the flow of the current C24 in the vicinity of the hole 40. FIG. 8 shows the connection relationship between the plurality of signal pads 22c, 24c, and 26c and the plurality of third external connection terminals 36. FIG. 9 is a diagram explaining one step of the method of manufacturing the semiconductor device 10 and shows a semi-finished product in which a plurality of semiconductor elements 22, 24, and 26 and a plurality of conductor spacers 18 are welded to a lead frame 19. FIG. 10 is a diagram explaining one process of the method of manufacturing the semiconductor device 10 and shows a semi-finished product in which the first conductor plate 12 is welded to the plurality of conductor spacers 18. FIG. 11 is a diagram explaining one step of the method of manufacturing the semiconductor device 10 and shows a semi-finished product in which the sealing body 16 is formed. FIG. 12 is a diagram explaining one step of the method of manufacturing the semiconductor device 10 and shows the completed semiconductor device 10. FIG. 13 shows a modified example in which the enlarged portion 13 of the first conductor plate 12 is expanded. FIG. 14 shows a semiconductor device 10 a having a single second external connection terminal 34. FIG. 15 shows another semiconductor device 10b having a single second external connection terminal 34. As shown in FIG. FIG. 16 shows a circuit configuration when two semiconductor devices 10 (10a, 10b) are connected in series. FIG. 17 is a diagram showing one mode of connecting the semiconductor device 10a shown in FIG. 14 and the semiconductor device 10b shown in FIG. 15 in series. FIG. 18 shows another mode of connecting the semiconductor device 10a shown in FIG. 14 and the semiconductor device 10b shown in FIG. 15 in series. FIG. 19 shows one mode of connecting two semiconductor devices 10a shown in FIG. 14 in series. FIG. 20 shows another mode of connecting two semiconductor devices 10a shown in FIG. 14 in series. FIG. 21 is a plan view showing the semiconductor device 110 of the second embodiment. Fig. 22 is a cross-sectional view on line XXII-XXII in Fig. 21. Fig. 23 is a cross-sectional view on line XXIII-XXIII in Fig. 21. Fig. 24 is a cross-sectional view on line XXIV-XXIV in Fig. 21. FIG. 25 is a plan view illustrating the inner conductor layer 112a of the first conductor plate 112 (insulating substrate).

12‧‧‧第一導體板 12‧‧‧First conductor plate

13‧‧‧擴大部分 13‧‧‧Expanded part

13a‧‧‧側緣 13a‧‧‧Side edge

13b‧‧‧基端 13b‧‧‧Base end

13c‧‧‧前端 13c‧‧‧Front end

14‧‧‧第二導體板 14‧‧‧Second Conductor Plate

22‧‧‧第一半導體元件 22‧‧‧First Semiconductor Device

22X‧‧‧第一半導體元件的中心 22X‧‧‧The center of the first semiconductor element

24‧‧‧第二半導體元件 24‧‧‧Second semiconductor element

24X‧‧‧第二半導體元件的中心 24X‧‧‧The center of the second semiconductor element

26‧‧‧第三半導體元件 26‧‧‧The third semiconductor element

26X‧‧‧第三半導體元件的中心 26X‧‧‧The center of the third semiconductor element

32‧‧‧第一外部連接端子 32‧‧‧The first external connection terminal

33‧‧‧與對稱面PS交叉的範圍 33‧‧‧The range of intersection with the symmetry plane PS

34‧‧‧第二外部連接端子 34‧‧‧Second external connection terminal

34a‧‧‧內側緣 34a‧‧‧Inside edge

34b‧‧‧彎曲部 34b‧‧‧Bending part

40‧‧‧孔 40‧‧‧Hole

PS‧‧‧穿過第二半導體元件24的平面(對稱面) PS‧‧‧A plane passing through the second semiconductor element 24 (plane of symmetry)

Claims (30)

一種半導體裝置，具備：第一導體板；多個半導體元件，其被配置於所述第一導體板上；第一外部連接端子，其與所述第一導體板連接，所述多個半導體元件包括第一半導體元件、第二半導體元件以及第三半導體元件，所述第二半導體元件被配置於所述第一半導體元件與所述第三半導體元件之間，在所述第一導體板中連接有所述第一外部連接端子的範圍在所述第一半導體元件、所述第二半導體元件以及所述第三半導體元件中最接近於所述第二半導體元件，在所述第一導體板中，在連接有所述第一外部連接端子的範圍與連接有所述第二半導體元件的範圍之間設置有孔。 A semiconductor device including: a first conductor plate; a plurality of semiconductor elements arranged on the first conductor plate; a first external connection terminal connected to the first conductor plate, the plurality of semiconductor elements It includes a first semiconductor element, a second semiconductor element, and a third semiconductor element. The second semiconductor element is arranged between the first semiconductor element and the third semiconductor element and is connected in the first conductor plate The range with the first external connection terminal is closest to the second semiconductor element among the first semiconductor element, the second semiconductor element, and the third semiconductor element, and is in the first conductor plate A hole is provided between the area where the first external connection terminal is connected and the area where the second semiconductor element is connected. 如申請專利範圍第1項所述的半導體裝置，其中，所述孔被形成為，在所述第一外部連接端子與所述第二半導體元件之間流動的電流的至少一部分迂回過所述孔。 The semiconductor device according to claim 1, wherein the hole is formed such that at least a part of the current flowing between the first external connection terminal and the second semiconductor element bypasses the hole . 如申請專利範圍第1項所述的半導體裝置，其中，所述孔被形成為，在所述第一外部連接端子與所述第 二半導體元件之間流動的電流全部迂回過所述孔。 The semiconductor device according to claim 1, wherein the hole is formed so that the first external connection terminal and the first external connection terminal The current flowing between the two semiconductor elements all bypass the hole. 如申請專利範圍第1至3項中任一項所述的半導體裝置，其中，所述第一半導體元件、所述第二半導體元件以及所述第三半導體元件將與所述第一導體板垂直的平面作為對稱面而實質上被左右對稱地排列配置。 The semiconductor device according to any one of claims 1 to 3, wherein the first semiconductor element, the second semiconductor element, and the third semiconductor element are perpendicular to the first conductor plate As a symmetry plane, the planes are arranged substantially symmetrically. 如申請專利範圍第4項所述的半導體裝置，其中，所述第一外部連接端子在與所述對稱面交叉的範圍內與所述第一導體板連接。 The semiconductor device according to claim 4, wherein the first external connection terminal is connected to the first conductor plate within a range intersecting the symmetry plane. 如申請專利範圍第4項所述的半導體裝置，其中，所述孔具有與所述對稱面呈左右對稱的開口形狀。 The semiconductor device according to claim 4, wherein the hole has an opening shape that is bilaterally symmetrical to the symmetry plane. 如申請專利範圍第4項所述的半導體裝置，其中，所述孔具有長孔形狀，所述長孔形狀的長邊軸與所述對稱面垂直。 The semiconductor device according to claim 4, wherein the hole has an elongated hole shape, and a long side axis of the elongated hole shape is perpendicular to the symmetry plane. 如申請專利範圍第4項所述的半導體裝置，其中，在與所述對稱面垂直的方向，所述孔的尺寸大於所述第二半導體元件的尺寸。 The semiconductor device according to claim 4, wherein, in a direction perpendicular to the symmetry plane, the size of the hole is larger than the size of the second semiconductor element. 如申請專利範圍第4項所述的半導體裝置，其中， 在與所述對稱面垂直的方向，所述孔的尺寸小於所述第一半導體元件與所述第三半導體元件之間的中心間距離。 The semiconductor device described in item 4 of the scope of patent application, wherein: In the direction perpendicular to the symmetry plane, the size of the hole is smaller than the center-to-center distance between the first semiconductor element and the third semiconductor element. 如申請專利範圍第4項所述的半導體裝置，其中，在所述第一導體板中連接有所述第一外部連接端子的所述範圍，係與所述對稱面呈左右對稱。 The semiconductor device according to claim 4, wherein the range in which the first external connection terminal is connected to the first conductor plate is bilaterally symmetric with the plane of symmetry. 如申請專利範圍第4項所述的半導體裝置，其中，在與所述對稱面垂直的方向，所述孔的尺寸大於在所述第一導體板中連接有所述第一外部連接端子的所述範圍的尺寸。 The semiconductor device according to claim 4, wherein, in a direction perpendicular to the symmetry plane, the size of the hole is larger than all of the first external connection terminals connected to the first conductor plate The size of the stated range. 如申請專利範圍第4項所述的半導體裝置，其中，所述第一導體板具有擴大部分，所述擴大部分的與所述對稱面垂直的方向上的尺寸從連接有所述第一外部連接端子的所述範圍起向連接有所述多個半導體元件的範圍而擴大，所述孔的至少一部分位於所述擴大部分處。 The semiconductor device according to claim 4, wherein the first conductor plate has an enlarged portion, and the size of the enlarged portion in a direction perpendicular to the plane of symmetry is different from the first external connection The range of the terminal is expanded from the range where the plurality of semiconductor elements are connected, and at least a part of the hole is located at the expanded portion. 如申請專利範圍第4項所述的半導體裝置，其中，所述第一半導體元件、所述第二半導體元件以及所述第三半導體元件沿著與所述對稱面垂直的方向而被直線地排列配置。 The semiconductor device according to claim 4, wherein the first semiconductor element, the second semiconductor element, and the third semiconductor element are linearly arranged along a direction perpendicular to the plane of symmetry Configuration. 如申請專利範圍第1至3項中任一項所述的半導體裝置，其中，所述第一導體板為，具有內側導體層、外側導體層、以及位於所述內側導體層與所述外側導體層之間的絕緣層的絕緣基板，所述第一外部連接端子經由所述內側導體層而與所述多個半導體元件電連接，所述孔被設置於所述內側導體層上。 The semiconductor device according to any one of claims 1 to 3, wherein the first conductor plate has an inner conductor layer, an outer conductor layer, and is located between the inner conductor layer and the outer conductor An insulating substrate of an insulating layer between layers, the first external connection terminal is electrically connected to the plurality of semiconductor elements via the inner conductor layer, and the hole is provided on the inner conductor layer. 如申請專利範圍第14項所述的半導體裝置，其中，所述孔僅被設置於所述內側導體層上，並具有由所述絕緣層劃分出的底面。 The semiconductor device according to claim 14, wherein the hole is provided only on the inner conductor layer and has a bottom surface divided by the insulating layer. 如申請專利範圍第14項所述的半導體裝置，其中，所述內側導體層以及所述外側導體層各自為金屬層，所述絕緣層為陶瓷基板。 The semiconductor device according to claim 14, wherein the inner conductor layer and the outer conductor layer are each a metal layer, and the insulating layer is a ceramic substrate. 如申請專利範圍第14項所述的半導體裝置，其中，所述絕緣基板為直接敷銅(DBC(Direct Bonded Copper))基板。 According to the semiconductor device described in item 14 of the scope of patent application, the insulating substrate is a direct bonded copper (DBC) substrate. 如申請專利範圍第1至3項中任一項所述的半導體裝置，其中， 還具備第二導體板，所述第二導體板與所述第一導體板對置並且與所述多個半導體元件中的每一個半導體元件連接。 The semiconductor device according to any one of items 1 to 3 in the scope of patent application, wherein: It also includes a second conductor plate that faces the first conductor plate and is connected to each of the plurality of semiconductor elements. 如申請專利範圍第18項所述的半導體裝置，其中，還具備與所述第二導體板連接的至少一個第二外部連接端子。 The semiconductor device according to claim 18, further comprising at least one second external connection terminal connected to the second conductor plate. 如申請專利範圍第19項所述的半導體裝置，其中，所述至少一個第二外部連接端子包括兩個第二外部連接端子。 The semiconductor device according to claim 19, wherein the at least one second external connection terminal includes two second external connection terminals. 如申請專利範圍第20項所述的半導體裝置，其中，所述第一半導體元件、所述第二半導體元件以及所述第三半導體元件將與所述第一導體板垂直的平面作為對稱面而實質上被左右對稱地排列配置，所述兩個第二外部連接端子中的一方在所述對稱面的一側與所述第二導體板連接，所述兩個第二外部連接端子中的另一方在所述對稱面的另一側與所述第二導體板連接。 The semiconductor device according to claim 20, wherein the first semiconductor element, the second semiconductor element, and the third semiconductor element have a plane perpendicular to the first conductor plate as a plane of symmetry. The two second external connection terminals are arranged substantially symmetrically, one of the two second external connection terminals is connected to the second conductor plate on one side of the symmetry plane, and the other of the two second external connection terminals One is connected to the second conductor plate on the other side of the symmetry plane. 如申請專利範圍第21項所述的半導體裝置，其中，所述兩個第二外部連接端子被設置為，與所述對稱面實質上左右對稱。 The semiconductor device according to claim 21, wherein the two second external connection terminals are arranged to be substantially bilaterally symmetrical to the symmetry plane. 如申請專利範圍第19項所述的半導體裝置，其中，在從與所述第一導體板以及所述第二導體板垂直的方向上俯視觀察時，所述第二導體板的面積大於所述第一導體板的面積。 The semiconductor device according to claim 19, wherein the area of the second conductor plate is larger than the area of the second conductor plate when viewed in a plan view in a direction perpendicular to the first conductor plate and the second conductor plate The area of the first conductor plate. 如申請專利範圍第19項所述的半導體裝置，其中，在從與所述第一導體板以及所述第二導體板垂直的方向俯視觀察時，所述第一導體板具有擴大部分，所述擴大部分為，所述第一導體板的寬度從連接有所述第一外部連接端子的範圍起向連接有所述多個半導體元件的範圍而擴大的部分。 The semiconductor device according to claim 19, wherein, when viewed in plan from a direction perpendicular to the first conductor plate and the second conductor plate, the first conductor plate has an enlarged portion, and the The enlarged portion is a portion in which the width of the first conductor plate is enlarged from the range where the first external connection terminal is connected to the range where the plurality of semiconductor elements are connected. 如申請專利範圍第24項所述的半導體裝置，其中，所述第一導體板的所述擴大部分處的厚度尺寸小於所述第一導體板的連接有所述多個半導體元件的範圍內的厚度尺寸，所述擴大部分被密封體覆蓋。 The semiconductor device according to claim 24, wherein the thickness dimension at the enlarged portion of the first conductor plate is smaller than that of the first conductor plate in the range where the plurality of semiconductor elements are connected The thickness dimension, the enlarged part is covered by the sealing body. 如申請專利範圍第24項所述的半導體裝置，其中，所述擴大部分具有一對側緣，所述一對側緣各自從位於所述多個半導體元件側的基端起而延伸至位於所述第一外部連接端子側的前端為止，所述擴大部分的所述側緣的所述基端位於，在從所述第一外部連接端子觀察時與第二外部連接端子的位於所述 第一外部連接端子側的側緣相比而較遠的一側。 The semiconductor device according to claim 24, wherein the enlarged portion has a pair of side edges, and each of the pair of side edges extends from the base end on the side of the plurality of semiconductor elements to the position where The base end of the side edge of the enlarged portion is located at the front end on the side of the first external connection terminal, and when viewed from the first external connection terminal, the base end of the second external connection terminal is located at the The side edge on the side of the first external connection terminal is farther than the side edge. 如申請專利範圍第24項所述的半導體裝置，其中，所述擴大部分的至少一部分與所述第二外部連接端子對置。 The semiconductor device according to claim 24, wherein at least a part of the enlarged portion is opposed to the second external connection terminal. 如申請專利範圍第18項所述的半導體裝置，其中，所述第一半導體元件、所述第二半導體元件以及所述第三半導體元件各自包括具有射極以及集極的絕緣閘雙極型電晶體，所述射極與所述第一導體板電連接，所述集極與所述第二導體板電連接。 The semiconductor device according to claim 18, wherein each of the first semiconductor element, the second semiconductor element, and the third semiconductor element includes an insulated gate bipolar electrical device having an emitter and a collector. In the crystal, the emitter is electrically connected with the first conductor plate, and the collector is electrically connected with the second conductor plate. 如申請專利範圍第18項所述的半導體裝置，其中，所述第二導體板為，具有內側導體層、外側導體層、以及位於所述內側導體層與所述外側導體層之間的絕緣層的絕緣基板，所述第二外部連接端子經由所述第二導體板的所述內側導體層而與所述多個半導體元件電連接。 The semiconductor device according to claim 18, wherein the second conductor plate has an inner conductor layer, an outer conductor layer, and an insulating layer located between the inner conductor layer and the outer conductor layer The second external connection terminal is electrically connected to the plurality of semiconductor elements via the inner conductor layer of the second conductor plate. 一種半導體裝置，具備：第一導體板；多個半導體元件，其被配置於所述第一導體板上；第一外部連接端子，其與所述第一導體板連接， 所述多個半導體元件包括第一半導體元件、第二半導體元件以及第三半導體元件，在所述第一導體板上，設置有使向所述第一半導體元件、所述第二半導體元件以及所述第三半導體元件中的每個半導體元件流動的電流均勻化的孔。 A semiconductor device including: a first conductor plate; a plurality of semiconductor elements arranged on the first conductor plate; a first external connection terminal connected to the first conductor plate, The plurality of semiconductor elements include a first semiconductor element, a second semiconductor element, and a third semiconductor element. On the first conductor plate, there are arranged so as to direct the first semiconductor element, the second semiconductor element, and the A hole through which the current flowing in each of the third semiconductor elements is uniformized.
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