TWI717250B - Semiconductor device and electrostatic discharge protection method - Google Patents

Abstract

The present disclosure relates to a semiconductor device, including a first source/drain region, a second source/drain region, a base region, a first electrostatic discharge region and a second electrostatic discharge region. The first source/drain region is configured to receive a first power voltage. The second source/drain region is configured to receive a second power voltage. The first source/drain region and the second source/drain region are formed on the base region. The first electrostatic discharge region includes a first doped region of a first type and a first well of a second type. The first doped region is configured to receive the second power voltage, and formed in the first well. The second electrostatic discharge region includes a second doped region of the first type and a second well of the second type. The second doped region is configured to receive the first power voltage, and formed in the second well. The first source/drain region and the second source/drain region are disposed between the first electrostatic discharge region and the second electrostatic discharge region.

Description

Semiconductor components and electrostatic discharge protection methods

The present disclosure relates to a semiconductor device and an electrostatic discharge protection method, especially a technology that can discharge static electricity from the semiconductor device to the outside world.

In the design of semiconductor components, due to human body discharge or machine discharge, the current caused by electrostatic discharge is likely to cause damage to the circuit. Therefore, an electrostatic discharge protection circuit needs to be provided in the semiconductor element to achieve the purpose of electrostatic protection.

One aspect of the present disclosure is a semiconductor device including a first source/drain region, a second source/drain region, a base region, a first electrostatic discharge region, and a second electrostatic discharge region. The first source/drain region is used for receiving the first power voltage. The second source/drain region is used for receiving the second power voltage. The first source/drain region and the second source/drain region are formed on the base region. The first electrostatic discharge region includes a first doped region of a first type and a first well region of a second type. The first doped region is used for receiving the second power supply voltage and is formed in the first well region. The second electrostatic discharge region includes a first-type second doped region and a second-type second well region. The second doped region is used for receiving the first power voltage and is formed in the second well region. The first source/drain region and the second source/drain region are arranged between the first electrostatic discharge region and the second electrostatic discharge region.

Another aspect of the present disclosure is an electrostatic discharge protection method, which includes the following steps: conducting a first electrostatic discharge path from the first doped region of the first type to the first source/drain region of the second type. The base region of the first type and the first well region of the second type are coupled between the first doped region and the first source/drain region. A second electrostatic discharge path connecting the second doped region of the first type to the second source/drain region of the second type. The base region and the second-type second well region are coupled between the second doped region and the second source/drain region.

One aspect of the present disclosure is a semiconductor device including a voltage control device and a first control circuit. The voltage control element includes a first source/drain region, a second source/drain region, and a gate region. The first source/drain region is used for receiving the first power voltage. The second source/drain region is used for receiving the second power voltage. The first control circuit includes a receiving circuit and a control switch. The receiving circuit is used for receiving the first power supply voltage and the second power supply voltage, and the receiving circuit is used for outputting the first control voltage according to the higher of the first power supply voltage and the second power supply voltage. The control switch is used for turning on in response to the first power supply voltage to output the first control voltage to the gate region of the voltage control element.

The present disclosure is to discharge the electrostatic discharge current through the bidirectional electrostatic discharge path in the semiconductor element. At the same time, through the first control circuit, it can be ensured that the semiconductor element can be completely turned off in the off state, and no leakage path will be generated.

Hereinafter, multiple embodiments of the present invention will be disclosed in the form of drawings. For clear description, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is, in some embodiments of the present invention, these practical details are unnecessary. In addition, in order to simplify the drawings, some conventionally used structures and elements will be shown in a simple schematic manner in the drawings.

In this text, when a component is referred to as “connected” or “coupled”, it can be referred to as “electrically connected” or “electrically coupled”. "Connected" or "coupled" can also be used to mean that two or more components cooperate or interact with each other. In addition, although terms such as “first”, “second”, etc. are used herein to describe different elements, the terms are only used to distinguish elements or operations described in the same technical terms. Unless clearly indicated by the context, the terms do not specifically refer to or imply order or sequence, nor are they used to limit the present invention.

The present disclosure relates to a semiconductor device and a method for preventing electrostatic discharge. Please refer to FIG. 1, the semiconductor device 100 includes a voltage control device 200. The voltage control element 200 includes a first source/drain region 210, a second source/drain region 220, a base region 230, a first electrostatic discharge region 250, and a second electrostatic discharge region 260. The first source/drain region 210 is used for receiving the first power voltage VDD. The second source/drain region 220 is used for receiving a second power voltage VDD0. The first source/drain region 210 and the second source/drain region 220 are formed in the base region 230.

In some embodiments, the voltage control device 200 further includes a gate region 240. The gate region 240 is disposed above the first source/drain region 210 and the second source/drain region 220 and is located between the first source/drain region 210 and the second source/drain region 220. In some embodiments, the first source/drain region 210 and the second source/drain region 220 are P-type doped regions, and the base region 230 is an N-type doped region. In this way, the first source/drain region 210, the second source/drain region 220, the base region 230, and the gate region 240 can be used to jointly operate as a P-type metal oxide semiconductor field effect transistor (PMOS). In some embodiments, the term "source/drain region" refers to a source region or a drain region. For example, when the first source/drain region 210 is used as the "source" of the P-type metal oxide semiconductor field effect transistor, the second source/drain region 220 is used as the P-type metal oxide semiconductor field effect transistor. "Dip pole". Similarly, when the first source/drain region 210 is used as the "drain" of the P-type metal oxide semiconductor field effect transistor, the second source/drain region 220 is used as the "drain" of the P-type metal oxide semiconductor field effect transistor. "Source".

To clearly illustrate the technology of the present case, the following embodiment uses the first source/drain region 210, the second source/drain region 220, the base region 230 and the gate region 240 to jointly operate as a P-type metal oxide semiconductor field effect. The transistor is taken as an example for illustration, but it is not limited to this. In other words, in some other embodiments, the first source/drain region 210, the second source/drain region 220, the base region 230, and the gate region 240 can also be configured in different configurations to realize N-type metal oxide Semiconductor field effect transistor.

In operation, when the voltage control element 200 operates in the "linear region" of the transistor, the voltage control element 200 has different impedance characteristics according to the voltage value received by the gate region 240, and the first source/drain The voltage across the pole region 210 and the second source/drain region 220 will also change accordingly. In some embodiments, the semiconductor device 100 is applied to a low dropout regulator (LDO). In operation, the voltage control device 200 is used to receive the first power supply voltage VDD and output the second power supply voltage VDD0, and The second power supply voltage VDD0 will be slightly lower than the first power supply voltage VDD, but the application of the present disclosure is not limited to this.

As shown in FIG. 1, the P-type metal oxide semiconductor field effect transistor system is located between the first electrostatic discharge region 250 and the second electrostatic discharge region 260. That is, the first source/drain region 210 and the second source/drain region 220 are disposed between the first ESD region 250 and the second ESD region 260, thereby being connected to the first ESD region 250 and the second ESD region. The two electrostatic discharge regions 260 respectively form an electrostatic discharge path.

The first electrostatic discharge region 250 includes an N-type first doped region 251 and a P-type first well region 252. The first doped region 251 is used to receive the second power supply voltage VDD0 and is formed in the first well region 252. The second electrostatic discharge region 260 includes an N-type second doped region 261 and a P-type second well region 262. The second doped region 261 is used to receive the first power supply voltage VDD and is formed in the second well region 262.

As shown in FIG. 1, the first source/drain region 210, the base region 230, the first well region 252, and the first doped region 251 form a "P-N-P-N" semiconductor structure. The semiconductor structure can be equivalent to a silicon controlled rectifier (SCR) as the first electrostatic discharge path SCR1. That is, in the electrostatic discharge state, the first electrostatic discharge current will be input from the first source/drain region 210 to the semiconductor device 100 and output from the first electrostatic discharge region 250.

In the same way, the second source/drain region 220, the base region 230, the second well region 262, and the second doped region 261 can also form an SCR structure and a second electrostatic discharge path SCR2. In the electrostatic discharge state, the second electrostatic discharge current will be input to the semiconductor device 100 from the second source/drain region 220 and output from the second electrostatic discharge region 260.

In some embodiments, the first well region 252 and the second well region 262 are formed in the base region 230. In some embodiments, the base region 230 may be implemented as an N-type doped well region.

Please refer to FIG. 1. In some embodiments, the semiconductor device 100 further includes a first control circuit 300. The first control circuit 300 includes a receiving circuit 310 and a control switch 320. The receiving circuit 310 is used for receiving the first power supply voltage VDD and the second power supply voltage VDD0. The receiving circuit 310 is further used for outputting the first control voltage V1 according to the higher one of the first power supply voltage VDD and the second power supply voltage VDD0. The control switch 320 is used to turn on in response to the first power supply voltage VDD to output the first control voltage V1 to the gate region 240 of the voltage control element 200. In this embodiment, the control switch 320 is a P-type transistor. Therefore, when the first power supply voltage VDD is at a high voltage level, the control switch 320 will be turned off according to the first power supply voltage VDD. Conversely, when the first power supply voltage VDD is at a low and high voltage level, the control switch 320 will be turned on according to the first power supply voltage VDD.

In some embodiments, the semiconductor device 100 further includes a second control circuit 400. The second control circuit 400 is used for transmitting the second control voltage V2 to the gate region 240 to control the voltage value on the gate region 240. In some embodiments, the second control circuit 400 is an operating circuit in a linear regulator, which includes an error amplifier (error amplifier, or operational amplifier for error detection) (not shown) and a feedback circuit (not shown) , Respectively coupled to the first power supply voltage VDD and the second power supply voltage VDD0. In operation, the second control circuit 400 is used to detect the magnitude of the second power supply voltage VDD0 to dynamically adjust the second control voltage V2 output to the gate region 240, thereby adjusting the impedance characteristic of the voltage control element 200. Since those skilled in the art can understand the circuit structure and principle of the linear regulator, it will not be repeated here.

In some embodiments, the first control circuit 300 is used to ensure that the voltage control device 200 is completely turned off when the semiconductor device 100 does not need to operate. Accordingly, it is possible to prevent the diode structure in the voltage control element 200 from forming a leakage path. The operation modes of the first control circuit 300 when the semiconductor device 100 is in different operating states are respectively described here.

Please refer to Figures 1 and 2. In some embodiments, the semiconductor device 100 is applied to the first integrated circuit Die1, and the I/O Pad P1 of the first integrated circuit Die1 And the input/output pad P2 of the second integrated circuit Die2 are mutually coupled and shared. In the "normal operation state", the semiconductor device 100 receives the first power supply voltage VDD, and through the voltage control device 200, the output voltage is slightly lower than the second power supply voltage VDD0 of the first power supply voltage VDD. As described above, the control switch 320 is turned off in response to the high voltage level of the first power supply voltage VDD. Therefore, in the "normal operation state", the first control circuit 300 does not affect the operation of the voltage control element 200. At this time, the impedance characteristic of the voltage control element 200 will be changed according to the second control voltage V2 output by the second control circuit 400.

On the other hand, in the “off state”, at this time, the first power supply voltage VDD may have a ground potential or be controlled at a low voltage level to reduce power consumption. However, as shown in Figure 2, if the second integrated circuit Die2 is in operation at this time, resulting in a high voltage on the input and output pad P2, the voltage control element 200 must be completely turned off, otherwise the input and output pad P2 The high voltage will be transmitted to the input and output pad P1 to form a second power supply voltage VDD0 with a high voltage level, and the reverse conduction voltage control element 200 (such as the dashed path across the voltage control element 200 in Figure 2), Damage to the semiconductor device 100 or affect the signal integrity of the second integrated circuit Die2. The present disclosure is to ensure that the voltage control element 200 is completely turned off in the "off state" through the operation of the first control circuit 300, as described below.

In conclusion, as shown in Figure 1, in the "off state", the second power supply voltage VDD0 is greater than the first power supply voltage VDD, and the control switch 320 will be turned on in response to the low voltage level of the first power supply voltage VDD. Therefore, the first control circuit 300 outputs the disable voltage (that is, the second power supply voltage VDD0 with a relatively high voltage level) to the gate region 240. At this time, since the second source/drain region 220 and the gate region 240 are both applied with the same second power supply voltage VDD0, no leakage current path will be formed inside the voltage control element 200. In some embodiments, the first control circuit 300 also outputs a disable voltage to the base region 230 of the voltage control element 200.

In addition, in the “electrostatic discharge state”, the electrostatic discharge voltage may be input to the voltage control element 200 from the first source/drain region 210 or the second source/drain region 220. As mentioned above, through the two SCR structures in the voltage control device 200, electrostatic discharge paths (such as SCR1 and SCR2) in different directions can be formed to ensure that the electrostatic discharge voltage will not damage the semiconductor device 100.

In some embodiments, the first control circuit 300 further includes an energy storage element C1. In some embodiments, the energy storage element C1 is a capacitor. An N-type heavily doped region is formed in the base region 230 as a buffer zone 231. The energy storage element C1 is coupled to the buffer zone 231. In the “electrostatic discharge state”, the internal equivalent resistance of the energy storage element C1 and the first control circuit 300 will form a delay circuit to maintain the base region 230 in a floating state.

In some embodiments, the doping concentration of the buffer zone 231 is greater than the doping concentration of other regions of the base region 230. As shown in Figure 1, when the first source/drain region 210 or the second source/drain region 220 receives the electrostatic discharge voltage, the electrostatic discharge voltage will be transferred to the energy storage device through the buffer 231 on the base region 230 C1, so that the voltage of the base region 230 remains floating during the delay period. In some embodiments, the length of the aforementioned delay period is determined according to the internal impedance of the energy storage element C1 and the first control circuit 300, for example, 100 ns to 1 ms.

In the foregoing embodiment, the energy storage device C1 is coupled to the base region 230 through the heavily doped buffer 231. In other embodiments, the energy storage device C1 can also be directly coupled to the base region 230, so that the base region 230 remains floating when the semiconductor device 100 is in the "static discharge state".

In some embodiments, the receiving circuit 310 includes a first switching element 311 and a second switching element 312. The first switching element 311 is used for turning on in response to the first power supply voltage VDD. The first terminal of the first switch element 311 is used to receive the second power voltage VDD0, and the second terminal of the first switch element 311 is coupled to the control switch 320. The second switching element 312 is used to turn on in response to the second power supply voltage VDD0. The first terminal of the second switch element 312 is used to receive the first power supply voltage VDD, and the second terminal of the second switch element 312 is coupled to the control switch 320. In addition, in this embodiment, the bases of the first switching element 311 and the second switching element 312 are coupled to each other.

Please refer to Figure 3, which is another embodiment of the present disclosure. Compared with FIG. 1, in this embodiment, the positions of the first electrostatic discharge region 250 and the second electrostatic discharge region 260 are reversed, but the structure is still substantially the same as the structure shown in FIG. 1.

Please refer to FIG. 4, which is another embodiment of the present disclosure. In Figure 4, similar elements related to the embodiment in Figure 1 are denoted by the same reference numerals for ease of understanding, and the specific principles of the similar elements have been described in detail in the previous paragraphs, if not between the elements in Figure 4 Those who have a cooperative operation relationship and are necessary to introduce will not be repeated here.

In some embodiments, the first well region 252 and the second well region 262 of Figure 1 above are implemented by the same doped well region. Compared to Figure 1, as shown in Figure 4, the semiconductor device 100 includes a P-type doped well region 270, wherein the well region structure corresponding to the first well region 252 and the second well region 262 is doped Well area 270 to achieve. That is, the doped well region 270 can be used as the first well region 252 and the second well region 262 in Figure 1 to realize the corresponding semiconductor structure. In addition, as shown in FIG. 4, the base region 230 is also formed in the doped well region 270.

In some embodiments, an N-type third well 251B and a fourth well 261B are also formed in the doped well 270. As shown in FIG. 4, the first doped region 251A is formed in the third well region 251B, and is coupled to the doped well region 270 through the third well region 251B. The second doped region 261A is formed in the fourth well region 261B, and is coupled to the doped well region 270 through the fourth well region 261B. Through the third well area 251B and the fourth well area 261B, the equivalent distance between the anode and the cathode in the SCR structure (such as the distance between N-P) can be shortened to increase the discharge speed of the electrostatic discharge current.

Figure 5 is a flow chart of the electrostatic discharge protection method of the present disclosure. As shown in Figures 1 and 5, in step S501, in the "off state", the receiving circuit 310 receives the first power supply voltage VDD or the second power supply voltage VDD0, and according to the first power supply voltage VDD and the second power supply The higher one of the voltages VDD0 outputs the first control voltage V1. In step S502, the control switch 320 outputs the first control voltage V1 to the gate region 240 to turn off the voltage control element 200. For example: when the second power supply voltage VDD0 is greater than the first power supply voltage VDD, the control switch 320 will be turned on, and the first control voltage V1 will be used as the disable voltage to keep the voltage control element 200 turned off.

In step S503, in the "normal operation state", the control switch 320 is turned off by the first power supply voltage VDD, and the voltage control element 200 controls the gate region 240 according to the second control voltage V2 output by the second control circuit 400 Voltage value.

In step S504, when the semiconductor device 100 is in the "electrostatic discharge state" and the first source/drain region 210 receives the electrostatic discharge voltage, the first doped region 251 to the first source/drain region 210 is turned on. An electrostatic discharge path SCR1 allows the first electrostatic discharge current to flow from the first source/drain region 210 to the first electrostatic discharge region 250 and output to the outside of the voltage control element 200.

In step S505, when the semiconductor device 100 is in the "electrostatic discharge state" and the second source/drain region 220 receives the electrostatic discharge voltage, the second doped region 261 to the second source/drain region 220 is turned on. The electrostatic discharge path SCR2 allows the second electrostatic discharge current to flow from the second source/drain region 220 to the second electrostatic discharge region 260 and output to the outside of the voltage control element 200.

Please refer to FIGS. 1 and 2 to illustrate the semiconductor device 100 of the present disclosure from another perspective. In some embodiments, the semiconductor device 100 includes a voltage control device 200, a first control circuit 300, and a second control circuit 400. The voltage control device 200 includes a first source/drain region 210, a second source/drain region 22 and a gate region 240. The first source/drain region 210 is used for receiving the first power voltage VDD. The second source/drain region 220 is used for receiving the second power voltage VDD0.

In summary, the first control circuit 300 includes a receiving circuit 310 and a control switch 320. The receiving circuit 310 is used for receiving the first power supply voltage VDD and the second power supply voltage VDD0, and the receiving circuit 310 is further used for outputting the first control voltage V1 according to the higher one of the first power supply voltage VDD and the second power supply voltage VDD0 . The control switch 320 is turned on in response to the first power supply voltage VDD to output the first control voltage V1 to the gate region 240 of the voltage control element 200. The second control circuit 400 is used to transmit the second control voltage V2 to the gate region 240 to control the voltage value on the gate region 240.

The various elements, method steps, or technical features in the foregoing embodiments can be combined with each other, and are not limited to the order of description or presentation of figures in the present disclosure.

Although the content of the present invention has been disclosed in the above embodiments, it is not intended to limit the content of the present invention. Anyone who is familiar with the art can make various changes and modifications without departing from the spirit and scope of the content of the present invention. Therefore, the present invention The scope of protection of the content shall be subject to the scope of the attached patent application.

100: Semiconductor components 200: Voltage control element 210: first source/drain region 220: second source/drain region 230: base area 231: Buffer 240: gate area 250: The first electrostatic discharge zone 251: first doped region 251A: first doped region 251B: The third well area 252: The first well area 260: second electrostatic discharge zone 261: second doped region 261A: second doped region 261B: The fourth well area 262: Second Well Area 270: doped well 300: The first control circuit 310: receiving circuit 311: first switching element 312: second switching element 320: control switch 400: second control circuit VDD: first power supply voltage VDD0: second power supply voltage C1: Energy storage element SCR1: The first electrostatic discharge path SCR2: second electrostatic discharge path Die1: The first integrated circuit Die2: second integrated circuit V1: first control voltage V2: second control voltage P1: Input and output pads P2: Input and output pads S501~S505: steps

FIG. 1 is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure. FIG. 2 is a schematic diagram of a semiconductor device applied to an integrated circuit according to some embodiments of the present disclosure. FIG. 3 is a schematic diagram of a semiconductor device according to other embodiments of the present disclosure. FIG. 4 is a schematic diagram of a semiconductor device according to other embodiments of the present disclosure. FIG. 5 is a flowchart of an electrostatic discharge protection method according to some embodiments of the present disclosure.

Domestic deposit information (please note in the order of deposit institution, date and number) no Foreign hosting information (please note in the order of hosting country, institution, date and number) no

100: Semiconductor components

200: Voltage control element

210: first source/drain region

220: second source/drain region

230: base area

231: Buffer

240: gate area

250: The first electrostatic discharge zone

251: first doped region

252: The first well area

260: second electrostatic discharge zone

261: second doped region

262: Second Well Area

300: The first control circuit

310: receiving circuit

311: first switching element

312: second switching element

320: control switch

400: second control circuit

VDD: first power supply voltage

VDD0: second power supply voltage

C1: Energy storage element

SCR1: The first electrostatic discharge path

SCR2: second electrostatic discharge path

V1: first control voltage

V2: second control voltage

Claims (10)

A semiconductor component, including: A first source/drain region for receiving a first power voltage; A second source/drain region for receiving a second power supply voltage; and A base region, the first source/drain region and the second source/drain region are formed on the base region; A first electrostatic discharge region includes a first doped region of a first type and a first well region of a second type, wherein the first doped region is used to receive the second power voltage and is formed in the In the first well area; and A second electrostatic discharge region includes a second doped region of the first type and a second well region of the second type, wherein the second doped region is used to receive the first power voltage and is formed in the first In the second well area, the first source/drain area and the second source/drain area are arranged between the first electrostatic discharge area and the second electrostatic discharge area. The semiconductor device according to claim 1, wherein when the first source/drain region receives an electrostatic discharge voltage, the first source/drain region, the base region, the first well region, and the first The doped region forms a first electrostatic discharge path; when the second source/drain region receives an electrostatic discharge voltage, the second source/drain region, the base region, the second well region, and the second The doped region forms a second electrostatic discharge path. The semiconductor device according to claim 1, wherein the first well region and the second well region are realized by the same doped well region, and the base region is formed in the doped well region. The semiconductor device according to claim 1, further comprising a first control circuit, the first control circuit comprising: A receiving circuit for receiving the first power supply voltage and the second power supply voltage, and the receiving circuit is also used for outputting a first control according to the higher one of the first power supply voltage and the second power supply voltage Voltage; and A control switch is used to turn on in response to the first power supply voltage to output the first control voltage to a gate region of the semiconductor device. The semiconductor device according to claim 4, further comprising a second control circuit for transmitting a second control voltage to the gate region to control the voltage value on the gate region. The semiconductor device according to claim 4, wherein the first control circuit further includes: An energy storage element is coupled to the base region. An electrostatic discharge protection method, including: A first electrostatic discharge path from a first doped region of the first type to a first source/drain region of the second type, wherein a base region of the first type and a first well of the second type are conducted The region is coupled between the first doped region and the first source/drain region; and Conducting a second doped region of the first type to a second electrostatic discharge path of a second source/drain region of the second type, wherein the base region and a second well region of the second type are coupled Between the second doped region and the second source/drain region. The electrostatic discharge protection method according to claim 7, wherein the first well region and the second well region are implemented by the same doped well region, and the base region is formed in the doped well region . The electrostatic discharge protection method described in claim 7 further includes: Receiving a first power supply voltage or a second power supply voltage through a receiving circuit; Outputting a first control voltage according to the higher one of the first power supply voltage and the second power supply voltage; and Through a control switch, the first control voltage is output to a gate region between the first source/drain region and the second source/drain region. The electrostatic discharge protection method described in claim 9 further includes: When the second power supply voltage is greater than the first power supply voltage, the control switch is turned on according to the first power supply voltage to apply a disable voltage to the gate region.

Images