TWI715025B - Pixel circuit and driving method - Google Patents

Abstract

A pixel circuit and a driving method are provided. A first terminal of the pixel unit of the pixel circuit is configured to receive the selected voltage, and a second terminal of the pixel unit is configured to receive a first reference voltage. The pixel circuit selects one of the first reference voltage and a second reference voltage as the selected voltage according to the scan signal and the data signal in a first time interval. The pixel circuit is configured to provide an inverted selected voltage in an inversion time interval. The pixel circuit selects the first reference voltage as the selected voltage during a second time interval.

Description

Pixel circuit and driving method

The present invention relates to a pixel circuit and a driving method, and more particularly to a pixel circuit with a pixel memory circuit and a driving method thereof.

Thin Film Transistor Liquid Crystal Displays (TFT-LCDs, Thin Film Transistor Liquid Crystal Display, TFT-LCD) have become the mainstream of modern display technology products, especially used in mobile phones, which are lightweight and easy to carry. Compared with Poly-Si TFT, the use of amorphous silicon thin film transistors (a-Si TFT) can reduce production costs and can be fabricated on large-area glass substrates at low temperatures , Improve production rate. When the screen of an electronic device such as a mobile phone or a computer is on a standby screen without screen change, the data line still has to maintain a certain frequency for input, which means continuous power consumption. Therefore, in a static image, how to maintain a certain voltage while reducing the transmission frequency of the data line to reduce the dynamic power consumption generated by the input AC voltage is a topic that is currently being widely studied.

Many display products have begun to develop solutions to reduce power consumption. One of the solutions is to use memory in pixel circuit (MIP) in the pixel to reduce the power consumption of the data driver.

However, current MIPs often require larger capacitors or more transistors for implementation. Although such implementations will consume the power of the data driving circuit, they will increase the power consumption of the MIP itself. Therefore, how to reduce the power consumption of MIP itself is the research focus of optimizing MIP. In addition, how to avoid image sticking caused by charge accumulation when the screen is not being transformed is also the research focus of optimizing MIP.

The present invention provides a pixel circuit and a driving method capable of reducing power consumption. The above-mentioned pixel circuit and driving method can also avoid image sticking caused by charge accumulation when the picture is not changed.

The pixel circuit of the present invention includes a switch circuit, a reverse circuit, a pixel unit, and a voltage selection circuit. The switch circuit is used for receiving the data signal and the scan signal, and provides the data signal according to the scan signal in the first time interval and the second time interval. The reverse circuit is coupled to the switch circuit. The reverse circuit is used for providing the first selection signal and the second selection signal according to the scan signal and the data signal provided by the switch circuit. The first terminal of the pixel unit is used for receiving the selected voltage, and the second terminal of the pixel unit is used for receiving the first reference voltage. The voltage selection circuit is coupled to the inverter circuit and the pixel unit. The voltage selection circuit is used for receiving the first reference voltage, the second reference voltage, the first selection signal, and the second selection signal. The voltage selection circuit selects one of the first reference voltage and the second reference voltage as the selected voltage in the first time interval according to the first selection signal and the second selection signal. The voltage selection circuit provides an inverted selected voltage during the inversion time interval. And the voltage selection circuit selects the first reference voltage as the selected voltage according to the first selection signal and the second selection signal in the second time interval. The voltage level of the first reference voltage in the first time interval and the second time interval is lower than the voltage level of the second reference voltage, and the voltage level of the first reference voltage in the inversion time interval is higher than that of the second reference voltage Voltage level.

The driving method of the present invention is used to drive the pixel unit. The first terminal of the pixel unit is used to receive the selected voltage. The second end of the pixel unit is used for receiving the first reference voltage. The driving method includes: providing a data signal according to the scanning signal in a first time interval, providing a first selection signal and a second selection signal according to the scanning signal and the data signal, and selecting the first reference voltage and the second selection signal according to the first selection signal and the second selection signal; One of the second reference voltages is used as the selected voltage; the inverted selected voltage is provided during the inversion time interval; and the data signal is provided according to the scan signal in the second time interval, and the first selection is provided according to the scan signal and the data signal Signal and the second selection signal, and the first reference voltage is selected as the selected voltage according to the first selection signal and the second selection signal. The voltage level of the first reference voltage in the first time interval and the second time interval is lower than the voltage level of the second reference voltage. The voltage level of the first reference voltage in the inversion time interval is higher than the voltage level of the second reference voltage.

Based on the above, the pixel circuit and driving method of the present invention select one of the first reference voltage and the second reference voltage as the selected voltage according to the scan signal and the data signal in the first time interval, and provide the reversed voltage during the inversion time interval. The selected voltage of the phase. Next, the pixel circuit and the driving method provide a data signal according to the scan signal in the second time interval, and select the first reference voltage as the selected voltage. In this way, the present invention can reduce the power consumption of the pixel circuit and avoid image sticking caused by charge accumulation.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a pixel circuit according to a first embodiment of the present invention. In this embodiment, the pixel circuit PX1 includes a switch circuit 110, an inverter circuit 120, a voltage selection circuit 130, and a pixel unit 140. The switch circuit 110 is used for receiving the data signal Sdata and the scan signal Sscan. The switch circuit 110 provides the data signal Sdata according to the scan signal Sscan in the first time interval. The switch circuit 110 also provides the data signal Sdata according to the scan signal Sscan in the second time interval. The reverse circuit 120 is coupled to the switch circuit 110. The reverse circuit 120 is used for providing a first selection signal Ssel1 and a second selection signal Ssel2 according to the scan signal Sscan and the data signal Sdata provided by the switch circuit 110. In this embodiment, when the inverter circuit 120 receives the scan signal Sscan at a high voltage level, it starts to depend on the voltage level of the first selection signal Ssel1 and the voltage level of the second selection signal Ssel2 based on the voltage level of the data signal Sdata The level is converted. In this way, the power consumption of the inverter circuit 120 can be reduced.

In this embodiment, the voltage selection circuit 130 is coupled to the inverter circuit 120 and the pixel unit 140. The voltage selection circuit 130 is used for receiving the first reference voltage Vref1, the second reference voltage Vref2, the first selection signal Ssel1, and the second selection signal Ssel2. The voltage selection circuit 130 selects one of the first reference voltage Vref1 and the second reference voltage Vref2 as the selected voltage Vsel according to the first selection signal Ssel1 and the second selection signal Ssel2 in the first time interval. The voltage selection circuit 130 inverts the selected voltage Vsel during the inversion time interval, thereby providing an inverted selected voltage Vsel. The voltage selection circuit 130 selects the first reference voltage Vref1 as the selected voltage Vsel according to the first selection signal Ssel1 and the second selection signal Ssel2 in the second time interval. The voltage level of the first reference voltage Vref1 in the first time interval and the second time interval is lower than the voltage level of the second reference voltage Vref2. The voltage level of the first reference voltage Vref1 in the inversion time interval is higher than the voltage level of the second reference voltage Vref2.

Take an example to illustrate the cooperative operation of the inverter circuit 120 and the voltage selection circuit 130. When receiving the scan signal Sscan of the high voltage level and the data signal Sdata of the high voltage level, the inverter circuit 120 provides the first selection signal Ssel1 of the low voltage level and the second selection signal of the high voltage level Ssel2. When receiving the scan signal Sscan of the high voltage level and the data signal Sdata of the low voltage level, the inverter circuit 120 provides the first selection signal Ssel1 of the high voltage level and the second selection signal of the low voltage level Ssel2. The voltage selection circuit 130 selects the second reference voltage Vref2 as the selected voltage Vsel according to the first selection signal Ssel1 of the low voltage level and the second selection signal Ssel2 of the high voltage level. On the other hand, the voltage selection circuit 130 selects the first reference voltage Vref1 as the selected voltage Vsel according to the first selection signal Ssel1 of the high voltage level and the second selection signal Ssel2 of the low voltage level. That is, the voltage selection circuit 130 selects the second reference voltage Vref2 as the selected voltage Vsel according to the scan signal Sscan of the high voltage level and the data signal Sdata of the high voltage level, and according to the scan signal Sscan and the high voltage level The data signal Sdata of the low voltage level selects the first reference voltage Vref1 as the selected voltage Vsel.

In this embodiment, the first terminal of the pixel unit 140 is used to receive the selected voltage Vsel. The second terminal of the pixel unit 140 is used to receive the first reference voltage Vref1. The pixel unit 140 can provide a corresponding display result according to the selected voltage Vsel and the first reference voltage Vref1. The pixel unit 140 may include a liquid crystal capacitor. Therefore, the pixel circuit PX1 can be applied to any type of liquid crystal display. The pixel unit 140 determines the deflection angle of the liquid crystal of the pixel unit 140 according to the first reference voltage Vref1 and the selected voltage Vsel. In this embodiment, the reversal time interval is continued after the first time interval, and the second time interval is continued after the reversal time interval. That is to say, the reversal time interval in this embodiment occurs between the first time interval and the second time interval. In some embodiments, the second time interval is continued after the first time interval, and the inversion time interval is continued after the second time interval.

For specific description, please refer to FIG. 1 and FIG. 2 at the same time. FIG. 2 is a flowchart of the driving method according to the first embodiment. The driving method of this embodiment can be applied to the pixel circuit PX1. In step S110 of this embodiment, the switch circuit 110 provides the data signal Sdata according to the scan signal Sscan in the first time interval. The reverse circuit 120 provides a first selection signal Ssel1 and a second selection signal Ssel2 according to the scan signal Sscan and the data signal Sdata. When receiving the first selection signal Ssel1 and the second selection signal Ssel2, the voltage selection circuit 130 selects one of the first reference voltage Vref1 and the second reference voltage Vref2 as the control signal according to the first selection signal Ssel1 and the second selection signal Ssel2. Select the voltage Vsel. In the first time interval, the voltage level of the first reference voltage Vref1 is lower than the voltage level of the second reference voltage Vref2. For example, in the first time interval, when the data signal Sdata is at a high voltage level, the voltage selection circuit 130 will select the second reference voltage Vref2 as the selected voltage Vsel. On the other hand, when the data signal Sdata is at a low voltage level, the voltage selection circuit 130 will select the first reference voltage Vref1 as the selected voltage Vsel. The pixel unit 140 deflects the liquid crystal of the pixel unit 140 corresponding to the voltage level of the data signal Sdata according to the voltage difference between the first reference voltage Vref1 and the selected voltage Vsel.

Next, in step S120, the voltage selection circuit 130 provides the inverted selected voltage Vsel during the inversion time interval. In this embodiment, the voltage level of the first reference voltage Vref1 and the voltage level of the second reference voltage Vref2 are inverted during the inversion time interval. Therefore, during the inversion time interval, the voltage level of the first reference voltage Vref1 is higher than the voltage level of the second reference voltage Vref2. The voltage selection circuit 130 can provide the inverted selected voltage Vsel through the inverted first reference voltage Vref1 and the inverted second reference voltage Vref2 during the inversion time interval. In step S120, the liquid crystal of the pixel unit 140 undergoes polarity inversion by the inverted selected voltage Vsel and the inverted first reference voltage Vref1 to avoid image sticking caused by charge accumulation.

Next, in step S130, the switch circuit 110 provides the data signal Sdata according to the scan signal Sscan in the second time interval. The reverse circuit 120 provides a first selection signal Ssel1 and a second selection signal Ssel2 according to the scan signal Sscan and the data signal Sdata. The voltage selection circuit 130 selects the first reference voltage Vref1 as the selected voltage Vsel according to the first selection signal Ssel1 and the second selection signal Ssel2. Therefore, the voltage difference between the first reference voltage Vref1 and the selected voltage Vsel in the second time interval will be equal to 0 Volts (V). In this way, the liquid crystal will not be deflected, so that the display result provided by the pixel unit 140 is maintained.

It is worth mentioning that in this embodiment, the pixel circuit PX1 receives the first reference voltage Vref1 and the second reference voltage Vref2. In the first time interval, the pixel circuit PX1 selects one of the first reference voltage Vref1 and the second reference voltage Vref2 as the selected voltage Vsel. During the inversion time interval, the pixel circuit PX1 provides the inverted selected voltage Vsel. Next, the pixel circuit PX1 selects the first reference voltage Vref1 as the selected voltage Vsel in the second time interval. In this way, the pixel circuit PX1 can reduce power consumption and avoid image retention caused by charge accumulation.

Please refer to FIG. 3, which is a schematic diagram of a pixel circuit according to a second embodiment of the present invention. In this embodiment, the pixel circuit PX2 can be applied to the operation method shown in FIG. 2. The pixel circuit PX2 includes a switch circuit 210, an inverter circuit 220, a voltage selection circuit 230, and a pixel unit 240. The pixel unit 240 includes a liquid crystal capacitor Clc. The first terminal of the liquid crystal capacitor Clc is used to receive the selected voltage Vsel. The second terminal of the liquid crystal capacitor Clc is used to receive the first reference voltage Vref1. The switching circuit 210 includes a switching transistor M1. The first terminal of the switching transistor M1 is coupled to the data line Ldata to receive the data signal Sdata. The second terminal of the switching transistor M1 is coupled to the inverter circuit 220. The control terminal of the switching transistor M1 is coupled to the scan line Lscan. The first terminal of the switching transistor M1 receives the data signal Sdata via the data line Ldata. The control terminal of the switching transistor M1 receives the scan signal Sscan via the scan line Lscan. When the switching transistor M1 receives the scan signal Sscan at the high voltage level, the switching transistor M1 is turned on, and the data signal Sdata is provided to the reverse circuit 220 through the second terminal of the switching transistor M1. On the other hand, when the switching transistor M1 receives the scan signal Sscan at a low voltage level, the switching transistor M1 will be disconnected and stop supplying the data signal Sdata to the inverter circuit 220.

In this embodiment, the reverse circuit 220 includes a first transistor M2, a second transistor M3, and a third transistor M4. The first terminal of the first transistor M2 is coupled to a high voltage source VDD (for example, 25 volts). The control terminal of the first transistor M2 is used for receiving the scan signal Sscan. The second terminal (ie, node B) of the first transistor M2 is used to provide the first selection signal Ssel1. The first end of the second transistor M3 is coupled to the second end of the first transistor M2. The control terminal (ie, node A) of the second transistor M3 is used to receive the data signal Sdata provided by the switch circuit 210. The first end of the third transistor M4 is coupled to the second end of the second transistor M3. The control terminal of the third transistor M4 is used to receive the data signal Sdata provided by the switch circuit 210. The second terminal of the third transistor M4 is coupled to the reference potential VSS (for example, 0 volt or ground). In this embodiment, the switch circuit 210 uses the provided data signal Sdata as the second selection signal Ssel2. It can be seen that, in the first time interval and the second time interval, if the inverter circuit 220 receives the scan signal Sscan at the high voltage level and the data signal Sdata at the high voltage level, the first transistor M2 and the second transistor The transistor M3 and the third transistor M4 are turned on. The voltage level of the first selection signal Ssel1 is pulled down to a low voltage level by the turned-on second transistor M3 and the third transistor M4. Therefore, the reverse circuit 220 provides the first selection signal Ssel1 at a low voltage level, and provides the second selection signal Ssel2 at a high voltage level. In this embodiment, in the design of the first transistor M2, the second transistor M3, and the third transistor M4, the width-to-length ratio of the channel of the second transistor M3 and the third transistor M4 will be greater than that of the first transistor M2. A transistor M2 channel width to length ratio.

If the inverter circuit 220 receives the scan signal Sscan at the high voltage level and the data signal Sdata at the low voltage level, the first transistor M2 is turned on, and the second transistor M3 and the third transistor M4 are turned off. Therefore, the reverse circuit 220 provides the first selection signal Ssel1 with a high voltage level and the second selection signal Ssel2 with a low voltage level.

It is worth mentioning here that the first transistor M2 is turned on according to the scan signal Sscan at a high voltage level, and turned off according to the scan signal Sscan at a low voltage level. Compared with a diode-connected transistor, the leakage current generated by the first transistor M2 due to being turned on does not continue to occur. In this way, the power consumption of the pixel circuit PX2 can be reduced.

In this embodiment, the voltage selection circuit 230 includes a first selection circuit 232 and a second selection circuit 234. The first selection circuit 232 is used for receiving the first selection signal Ssel1 and the first reference voltage Vref1. The first selection circuit 232 provides the first reference voltage Vref1 according to the first selection signal Ssel1 of the high voltage level, and stops providing the first reference voltage Vref1 according to the first selection signal Ssel1 of the low voltage level. The second selection circuit 234 is used for receiving the second selection signal Ssel2 and the second reference voltage Vref2. The second selection circuit 234 provides the second reference voltage Vref2 according to the second selection signal Ssel2 of the high voltage level, and stops providing the second reference voltage Vref2 according to the second selection signal Ssel2 of the low voltage level.

The implementation details of the first selection circuit 232 and the second selection circuit 234 are further described. In this embodiment, the first selection circuit 232 includes a first selection transistor M5 and a capacitor C. The first terminal of the first selection transistor M5 is used to receive the first reference voltage Vref1, the second terminal of the first selection transistor M5 is coupled to the first terminal of the pixel unit 240, and the control terminal of the first selection transistor M5 Used to receive the first selection signal Ssel1. The first terminal of the capacitor C is coupled to the control terminal of the first selection transistor M5, and the second terminal of the capacitor C is coupled to the reference potential VSS. In this embodiment, the capacitor C is used to maintain the voltage level of the first selection signal Ssel1.

The second selection circuit 234 includes a second selection transistor M6, a first coupling capacitor CC1, and a second coupling capacitor CC2. The first terminal of the second selection transistor M6 is used to receive the second reference voltage Vref2, the second terminal of the second selection transistor M6 is coupled to the first terminal of the pixel unit 240, and the control terminal of the second selection transistor M6 Used to receive the second selection signal Ssel2. The first coupling capacitor CC1 is coupled between the first terminal of the second selection transistor M6 and the control terminal of the second selection transistor M6. The second coupling capacitor CC2 is coupled between the second terminal of the second selection transistor M6 and the control terminal of the second selection transistor M6. The first coupling capacitor CC1 and the second coupling capacitor CC2 are used for voltage coupling to the second selection signal Ssel2 when the second selection transistor M6 is turned on to increase the voltage value of the second selection signal Ssel2. The above-mentioned voltage coupling can compensate the change of the threshold voltage of the second selection transistor M6. In this way, the pixel circuit PX2 can be prevented from being completely turned on due to the aging of the second selection transistor M6 under long-time operation. The switching transistor M1, the first transistor M2, the second transistor M3, the third transistor M4, the first selection transistor M5, and the second selection transistor M6 of this embodiment may be made of N-type amorphous silicon ( a-Si) Thin Film Transistor (TFT) or N-type poly-Si (poly-Si) thin film transistor.

Please refer to FIG. 2, FIG. 3, and FIG. 4 at the same time. FIG. 4 is a schematic diagram of waveforms according to an embodiment of the present invention. In the first time interval T1 (in step S110), the voltage level of the first reference voltage Vref1 (for example, 0 volt) is lower than the voltage level of the second reference voltage Vref2 (for example, 5 volt). Taking the high-voltage level data signal Sdata (for example, 5 volts) received by the switching circuit 210 as an example, the switching transistor M1 of the switching circuit 210 is based on the scanning signal of the high-voltage level during the sub-time interval T11 of the first time interval T1 Sscan (for example, 10 volts) is turned on, so as to provide the data signal Sdata to the reverse circuit 220. In the sub-time interval T11, the inverter circuit 220 turns on the first transistor M2, the second transistor M3, and the third transistor M4 according to the data signal Sdata of the high voltage level and the scan signal Sscan of the high voltage level to provide The first selection signal Ssel1 at a low voltage level and the second selection signal Ssel2 at a high voltage level. The voltage selection circuit 230 turns off the first selection transistor M5 according to the first selection signal Ssel1 of the low voltage level, and turns on the second selection transistor M6 according to the second selection signal Ssel2 of the high voltage level, thereby selecting the second reference The voltage Vref2 is used as the selected voltage Vsel. Therefore, the voltage difference VLC across the liquid crystal capacitor Clc is equal to the difference between the voltage level of the second reference voltage Vref2 and the voltage level of the first reference voltage Vref1, that is, the voltage difference VLC is equal to +5 volts.

Next, in the sub-time interval T12 of the first time interval T1, the data signal Sdata is at a low voltage level (for example, 0 volts) and the scan signal Sscan is at a low voltage level (for example, -8 volts). In the sub-time interval T12, the switching transistor M1 is turned off to stop supplying the data signal Sdata to the inverter circuit 220. In the sub-time interval T12, the first selection signal Ssel1 is still maintained at a low voltage level, and the second selection signal Ssel2 is still maintained at a high voltage level. Therefore, the voltage difference VLC across the liquid crystal capacitor Clc is maintained at +5 volts.

In the inversion time interval Tr (in step S120), the voltage level of the first reference voltage Vref1 and the voltage level of the second reference voltage Vref2 are inverted. That is, the voltage level of the first reference voltage Vref1 in the inversion time interval Tr (for example, 5 volts) is higher than the voltage level of the second reference voltage Vref2 in the inversion time interval Tr (for example, 0 volts). Therefore, in the inversion time interval Tr, the voltage difference VLC between the two ends of the liquid crystal capacitor Clc is inverted from +5 volts (such as dot inversion) to -5 volts, so as to avoid image retention caused by charge accumulation.

The voltage level of the first reference voltage Vref1 and the voltage level of the second reference voltage Vref2 are restored in the second time interval T2. In this embodiment, the frequency of the scanning signal Sscan, the frequency of the first reference voltage Vref1, and the frequency of the second reference voltage Vref2 can be reduced from 60 hertz (Hz) to 1 under the premise that the display result of the pixel unit 240 is not affected. hertz. In other words, the time length of the first time interval T1 and the reversal time interval Tr can be extended from 0.016 seconds to 1 second. In this way, the dynamic switching power of the pixel circuit PX2 can be greatly reduced.

In the second time interval T2 (in step S130), the switching transistor M1 of the switching circuit 210 is turned on in the sub-time interval T21 of the second time interval T2 according to the scan signal Sscan (for example, 10 volts) of the high voltage level. In this way, the data signal Sdata (for example, 0 volt) of the low voltage level is provided to the inverter circuit 220. In the sub-time interval T21, the inverter circuit 220 will turn on the first transistor M2 and turn off the second transistor M3 and the third transistor M4 according to the data signal Sdata at the low voltage level and the scan signal Sscan at the high voltage level. , Thereby providing a first selection signal Ssel1 of a high voltage level and a second selection signal Ssel2 of a low voltage level. The voltage selection circuit 230 turns on the first selection transistor M5 according to the first selection signal Ssel1 of the high voltage level, and turns off the second selection transistor M6 according to the second selection signal Ssel2 of the low voltage level, thereby selecting the first reference The voltage Vref1 is used as the selected voltage Vsel. Therefore, the voltage difference VLC across the liquid crystal capacitor Clc is equal to 0 volts. In this way, the liquid crystal will not be deflected, so as to maintain the display result provided by the pixel unit 240.

Next, in the sub-time interval T22 of the second time interval T2, the data signal Sdata is at a low voltage level (for example, 0 volt) and the scan signal Sscan is at a low voltage level (for example, -8 volt). In the sub-time interval T12, the switching transistor M1 is turned off to stop supplying the data signal Sdata to the inverter circuit 220. In the sub-time interval T12, the first selection signal Ssel1 is still maintained at a high voltage level, and the second selection signal Ssel2 is still maintained at a low voltage level. Therefore, the voltage difference VLC across the liquid crystal capacitor Clc is maintained at 0 volts, so that the liquid crystal will not be deflected and the display result provided by the pixel unit 240 is also maintained.

Please refer to FIG. 5, which is a schematic diagram of the configuration of a plurality of pixel circuits according to an embodiment of the present invention. In this embodiment, the pixel circuits PX_1 to PX_n can be implemented by the pixel circuit PX1 of the first embodiment or the pixel circuit PX2 of the second embodiment, respectively. The pixel circuits PX_1~PX_n collectively receive the high voltage source VDD, the reference potential VSS, and the first reference voltage Vref1 and the second reference voltage Vref2. The pixel circuit PX_1 receives the scan signal Sscan_1 and the data signal Sdata_1. The pixel circuit PX_2 receives the scan signal Sscan_2 and the data signal Sdata_2, and so on. Based on the above configuration, the pixel circuits PX_1~PX_n can perform frame inversion, sub-frame inversion, column inversion, or column inversion during operation. row inversion). The scan signals Sscan_1 to Sscan_n can be provided by shift registers, for example. Similarly, the data signals Sdata_1~Sdata_n can be provided by another shift register, for example. The configuration or arrangement of the multiple pixel circuits of the present invention can be adjusted according to requirements by those skilled in the art. The configuration mentioned in this embodiment is only an example, and does not limit the scope of the present invention.

In summary, the pixel circuit and driving method of the present invention select one of the first reference voltage and the second reference voltage as the selected voltage in the first time interval according to the data signal provided by the scan signal. During the inversion time interval, the first reference voltage and the second reference voltage are inverted to provide an inverted selected voltage. Next, the pixel circuit and the driving method select the first reference voltage as the selected voltage in the second time interval. In this way, the present invention can reduce the power consumption of the pixel circuit and avoid image sticking caused by charge accumulation.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

110, 210: switch circuit 120, 220: Reverse circuit 130, 230: Voltage selection circuit 140, 240: pixel unit 232: First selection circuit 234: Second selection circuit A, B: Node C: Capacitance CC1: the first coupling capacitor CC2: second coupling capacitor Clc: liquid crystal capacitor Ldata: data line Lscan: scan line M1: Switching transistor M2: The first transistor M3: second transistor M4: The third transistor M5: First choice transistor M6: second choice transistor PX1, PX2, PX_1~PX_n: pixel circuit S110, S120, S130, S140: steps Sdata, Sdata_1~Sdata_n: data signal Sscan, Sscan_1~Sscan_n: scan signal Ssel1: First choice signal Ssel2: second choice signal T1: the first time interval T11, T12, T21, T22: sub-time interval T2: the second time interval Tr: Reversal time interval VDD: High voltage source VLC: The voltage difference across the liquid crystal capacitor Vref1: the first reference voltage Vref2: second reference voltage Vsel: selected voltage VSS: Reference potential

FIG. 1 is a schematic diagram of a pixel circuit according to the first embodiment of the present invention. FIG. 2 is a flowchart of the driving method according to the first embodiment. FIG. 3 is a schematic diagram of a pixel circuit according to a second embodiment of the invention. FIG. 4 is a schematic diagram of waveforms drawn according to an embodiment of the invention. FIG. 5 is a schematic diagram showing the configuration of multiple pixel circuits according to an embodiment of the invention.

110: Switch circuit 120: Reverse circuit 130: Voltage selection circuit 140: pixel unit PX1: Pixel circuit Sdata: data signal Sscan: Scan signal Ssel1: First choice signal Ssel2: second choice signal Vref1: the first reference voltage Vref2: second reference voltage Vsel: selected voltage

Claims (16)

A pixel circuit includes: a switch circuit for receiving a data signal and a scanning signal, and providing the data signal according to the scanning signal in a first time interval and a second time interval; a reverse circuit, coupled Connected to the switch circuit for providing a first selection signal and a second selection signal according to the scan signal and the data signal provided by the switch circuit; a pixel unit, the first end of the pixel unit is used for Receiving a selected voltage, the second terminal of the pixel unit is used to receive a first reference voltage; and a voltage selection circuit, coupled to the inverter circuit and the pixel unit, is used to receive the first reference voltage, A second reference voltage, the first selection signal, and the second selection signal, selecting one of the first reference voltage and the second reference voltage according to the first selection signal and the second selection signal in the first time interval One is the selected voltage, the inverted selected voltage is provided in an inversion time interval, and the first reference voltage is selected as the first reference voltage in the second time interval according to the first selection signal and the second selection signal The selected voltage, wherein the voltage level of the first reference voltage in the first time interval and the voltage level of the second time interval is lower than the voltage level of the second reference voltage, and the first reference voltage is in the inversion time The voltage level of the interval is higher than the voltage level of the second reference voltage. According to the pixel circuit described in claim 1, wherein the pixel unit provides a display result according to the selected voltage and the first reference voltage. As for the pixel circuit described in item 1 of the scope of patent application, in the first time interval and the second time interval, when the inverter circuit receives the scan signal at a high voltage level and the high voltage level The data signal provides the first selection signal of low voltage level and the second selection signal of high voltage level. When the inverter circuit receives the scan signal of high voltage level and the scan signal of low voltage level The data signal provides the first selection signal at a high voltage level, and provides the second selection signal at a low voltage level. For the pixel circuit described in item 1 of the scope of patent application, in the first time interval and the second time interval, the voltage selection circuit is based on the first selection signal of the low voltage level and the high voltage level The second selection signal selects the second reference voltage as the selected voltage, and selects the first reference voltage as the selected voltage according to the first selection signal at a high voltage level and the second selection signal at a low voltage level . The pixel circuit according to claim 1, wherein the switching circuit includes: a switching transistor, the first end of the switching transistor is coupled to a data line, and the second end of the switching transistor is coupled to To the reverse circuit, the control terminal of the switching transistor is coupled to a scan line, the first terminal of the switching transistor receives the data signal through the data line, and the control terminal of the switching transistor receives the data signal through the scan line Scan the signal. The pixel circuit described in claim 1, wherein the reverse circuit includes: a first transistor, the first end of the first transistor is coupled to a high voltage source, and the The control terminal is used to receive the scanning signal, the second terminal of the first transistor is used to provide the first selection signal; a second transistor, the first terminal of the second transistor is coupled to the first transistor The second end of the second transistor is used to receive the data signal provided by the switch circuit; and a third transistor, the first end of the third transistor is coupled to the second transistor The control terminal of the third transistor is used to receive the data signal provided by the switch circuit, the second terminal of the third transistor is coupled to a reference potential, and the control terminal of the third transistor is The data signal is the second selection signal. As described in the first item of the scope of patent application, the voltage selection circuit includes: a first selection circuit for receiving the first selection signal and the first reference voltage, and the first selection circuit according to the high voltage level A selection signal provides the first reference voltage, and stops providing the first reference voltage according to the first selection signal at a low voltage level; and a second selection circuit for receiving the second selection signal and the second reference Voltage, providing the second reference voltage according to the second selection signal of the high voltage level, and stopping providing the second reference voltage according to the second selection signal of the low voltage level. According to the pixel circuit described in claim 7, wherein the first selection circuit includes: a first selection transistor, the first terminal of the first selection transistor is used to receive the first reference voltage, and the first selection transistor The second terminal of a selection transistor is coupled to the first terminal of the pixel unit, and the control terminal of the first selection transistor is used to receive the first selection signal; and a capacitor, the first terminal of which is coupled At the control terminal of the first selection transistor, the second terminal of the capacitor is coupled to a reference potential for maintaining the voltage level of the first selection signal. According to the pixel circuit described in claim 7, wherein the second selection circuit includes: a second selection transistor, the first terminal of the second selection transistor is used to receive the second reference voltage, and the second selection transistor The second end of the second selection transistor is coupled to the first end of the pixel unit, and the control end of the second selection transistor is used to receive the second selection signal; a first coupling capacitor is coupled to the second Between the first terminal of the selection transistor and the control terminal of the second selection transistor; and a second coupling capacitor coupled to the second terminal of the second selection transistor and the control terminal of the second selection transistor between. For the pixel circuit described in item 1 of the scope of patent application, in the second time interval, the voltage level of the data signal is a low voltage level. A driving method for driving a pixel unit, wherein a first terminal of the pixel unit is used for receiving a selected voltage, and a second terminal of the pixel unit is used for receiving a first reference voltage, wherein the driving method includes : Provide a data signal based on a scan signal in a first time interval, provide a first selection signal and a second selection signal based on the scan signal and the data signal, and based on the first selection signal and the second selection signal Selecting one of the first reference voltage and a second reference voltage as the selected voltage; providing the selected voltage in an inverted time interval; and providing the selected voltage in a second time interval according to the scan signal The data signal provides the first selection signal and the second selection signal according to the scan signal and the data signal, and selects the first reference voltage as the selected voltage according to the first selection signal and the second selection signal, The voltage level of the first reference voltage in the first time interval and the second time interval is lower than the voltage level of the second reference voltage, and the voltage level of the first reference voltage in the inversion time interval A voltage level higher than the second reference voltage. According to the driving method described in claim 11, the pixel unit provides a display result according to the selected voltage and the first reference voltage. According to the driving method described in item 11 of the scope of patent application, in the first time interval and the second time interval, the step of providing the first selection signal and the second selection signal according to the scan signal and the data signal includes : When receiving the scan signal at high voltage level and the data at high voltage level Signal, provide the first selection signal of low voltage level, and provide the second selection signal of high voltage level; and when receiving the scan signal of high voltage level and the data signal of low voltage level , Providing the first selection signal at a high voltage level, and providing the second selection signal at a low voltage level. According to the driving method described in claim 11, in the first time interval and the second time interval, the first reference voltage and the second reference are selected according to the first selection signal and the second selection signal The step of using one of the voltages as the selected voltage includes: selecting the second reference voltage as the selected voltage according to the first selection signal at a low voltage level and the second selection signal at a high voltage level; and according to The first selection signal of high voltage level and the second selection signal of low voltage level select the first reference voltage as the selected voltage. The driving method according to claim 14, wherein the step of selecting the second reference voltage as the selected voltage according to the first selection signal of low voltage level and the second selection signal of high voltage level includes : Provide the second reference voltage according to the second selection signal of the high voltage level, and stop providing the first reference voltage according to the first selection signal of the low voltage level; and the first selection according to the high voltage level The signal provides the first reference voltage, and the second selection signal stops providing the second reference voltage according to the low voltage level. According to the driving method described in item 11 of the scope of patent application, in the second time interval, the voltage level of the data signal is a low voltage level.

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