TWM540366U - Pixel circuit - Google Patents

Abstract

A pixel circuit includes a switching transistor, an inverter circuit, a first driving transistor, a second driver transistor, a coupling capacitor, a bootstrap capacitor and a liquid crystal capacitor is provided. The switching transistor receives a pixel voltage and a scanning signal. The inverter circuit coupled to the switching transistor to receive the pixel voltage, and provides an inverted pixel voltage. The first drive transistor receives a first reference voltage and the inverted pixel voltage. The second drive transistor receives a second reference voltage and the pixel voltage. The coupling capacitor is coupled between the second reference voltage and the second driving transistor. The bootstrap capacitor is coupled between the second drive transistor and the liquid crystal capacitor. The liquid crystal capacitor is coupled to the first driving transistor, the second driving transistor and the first reference voltage.

Description

Pixel circuit

The novel creation is related to a circuit layout, and in particular to a pixel circuit.

Since Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) have high image quality, good space utilization efficiency, low power consumption, and no radiation, they have become the mainstream of modern display technology products. Compared with a polycrystalline silicon transistor (Poly-Si TFT), a display made of an amorphous germanium thin film transistor (a-Si TFT) can reduce the production cost and can be fabricated on a large-area glass substrate at a low temperature. On, increase the production rate.

As the power consumption of liquid crystal displays becomes more and more important, many display products have begun to develop a power-saving scheme. One is to use a memory in pixel circuit (MIP) to reduce the data driving circuit (Data Driver) power consumption. However, most of the current polycrystalline germanium film transistors are used to design memory circuits in pixels, but the memory circuits in pixels cannot be applied to large billboards or electronic tags using amorphous germanium film transistors, so they must be taken in a new way. The memory circuit in the design pixel is used to achieve the same effect as the polycrystalline silicon thin transistor by using the amorphous germanium thin film transistor.

The novel creation provides a pixel circuit with a memory circuit to prevent the liquid crystal from being polarized at a low picture update rate.

The pixel circuit of the present invention comprises a switching transistor, an inverting circuit, a first driving transistor, a second driving transistor, a coupling capacitor, a shoe capacitor and a liquid crystal capacitor. A first end of the switching transistor receives a pixel voltage, and a control terminal of the switching transistor receives a scanning signal. The inverting circuit is coupled to a second end of the switching transistor to receive the pixel voltage and to provide an inverted pixel voltage. A first terminal of the first driving transistor receives a first reference voltage, and a control terminal of the first driving transistor is coupled to the inverter circuit to receive the inverted pixel voltage. A first end of the second driving transistor receives a second reference voltage, a control end of the second driving transistor receives the pixel voltage, and a second end of the second driving transistor is coupled to the first driving transistor Second end. The coupling capacitor is coupled between the second reference voltage and the control terminal of the second driving transistor. The boot strap is capacitively coupled between the control end of the second drive transistor and the second end of the second drive transistor. The liquid crystal capacitor is coupled between the second end of the first driving transistor and the first reference voltage.

Based on the above, the pixel circuit of the novel creation embodiment automatically converts the polarity of the liquid crystal capacitor across the voltage through the inverter circuit, the first driving transistor, the second driving transistor, the coupling capacitor, and the shoe band capacitance to At the update rate, avoid the liquid crystal being polarized.

The above described features and advantages of the present invention will become more apparent and understood from the following description.

1 is a circuit diagram of a pixel circuit in accordance with an embodiment of the present invention. Referring to FIG. 1, in the embodiment, the pixel circuit 100 includes a switching transistor TSW, an inverting circuit INT, a first driving transistor TD1, a second driving transistor TD2, a coupling capacitor Ccp, a shoe capacitor Cbs, and a liquid crystal. Capacitor Clc. The inverter circuit INT, the first driving transistor TD1, the second driving transistor TD2, the coupling capacitor Ccp, and the shoe capacitor Cbs can be regarded as a memory circuit in the pixel circuit 100.

The drain (corresponding to the first end) of the switching transistor TSW receives the pixel voltage Vdata provided by the data driving circuit (not shown), and the gate (corresponding control terminal) of the switching transistor TSW receives the gate driving circuit (not drawn Show) the scan signal Sscan provided. The inverting circuit INT is coupled to the source of the switching transistor TSW (corresponding to the second end) to receive the pixel voltage Vdata transmitted by the switching transistor TSW, and to provide the inverted pixel voltage VBdata. The drain (corresponding to the first end) of the first driving transistor TD1 receives the first reference voltage Vref1 provided by the power supply (not shown), and the gate (corresponding control end) of the first driving transistor TD1 is coupled to the opposite The phase circuit INT receives the inverted pixel voltage VBdata.

The drain of the second driving transistor TD2 (corresponding to the first end) receives the second reference voltage Vref2 provided by the power supply (not shown), and the gate of the second driving transistor TD2 (corresponding to the control terminal) receives the pixel The source (corresponding to the second end) of the second driving transistor TD is coupled to the source (corresponding to the second end) of the first driving transistor TD1. The coupling capacitor Ccp is coupled between the two reference voltages Vref2 and the gate of the second driving transistor TD2. The shoe strap capacitor Cbs is coupled between the gate of the second driving transistor TD2 and the source of the second driving transistor TD2. The liquid crystal capacitor Clc is coupled between the source of the first driving transistor TD1 and the first reference voltage Vref1.

In the present embodiment, the inverter circuit INT includes a first transistor T1, a second transistor T2, and a third transistor T3. The drain (corresponding to the first end) of the first transistor T1 and the gate (corresponding to the control terminal) receive the first reference voltage Vref1, and the source (corresponding to the second end) of the first transistor T1 provides the inverted pixel voltage VBdata . The drain (corresponding to the first end) of the second transistor T2 and the gate (corresponding to the control terminal) receive the second reference voltage Vref2, and the source (corresponding to the second end) of the second transistor T2 is coupled to the first transistor T1 The source. The drain of the third transistor T3 (corresponding to the first end) is coupled to the source of the first transistor T1, and the gate of the third transistor T3 (corresponding to the control terminal) receives the pixel voltage Vdata, and the third transistor T3 The source (corresponding to the second end) receives the ground voltage.

In this embodiment, the switching transistor TSW, the first driving transistor TD1, the second driving transistor TD2, the first transistor T1, the second transistor T2, and the third transistor T3 are respectively an amorphous germanium (a -Si) thin film transistor, and switching transistor TSW, first driving transistor TD1, second driving transistor TD2, first transistor T1, second transistor T2 and third transistor T3 are respectively an N-type film Transistor. The aspect ratio of the third transistor T3 is greater than the aspect ratio of the first transistor T1 and the second transistor T2.

2 is a schematic diagram of driving waveforms of a pixel circuit in accordance with an embodiment of the present invention. Referring to FIG. 1 and FIG. 2, in the present embodiment, it is assumed that the duration of one picture period (eg, periods PF1, PF2) is 1 second, that is, the picture update rate of the pixel 100 is 1 Hz (Hz). The switching transistor TSW has a conduction frequency of 1 hertz (Hz). Also, assume that one picture period (eg, periods PF1, PF2) is three time segments (eg, period T1~T3 or T4~T6), wherein the length of time period T3 (or T6) may be equal to period T1, T2 (or T4) The sum of the lengths of time, T5).

In addition, the first reference voltage Vref1 and the second reference voltage Vref2 are respectively an alternating voltage, and the first reference voltage Vref1 and the second reference voltage Vref2 are a system high voltage VH and a system low voltage VL, respectively, and the first reference voltage Vref1 and the first The frequency of the second reference voltage Vref2 is equal to 2 Hz.

In the period T1, the scan signal Sscan is enabled, and the switching transistor TSW is turned on by the rise of the scan signal Sscan, so that the pixel voltage Vdata which is the system high voltage VH is transmitted to the node A. At this time, the transistor T3 and the second driving transistor TD2 are turned on, so the inverted pixel voltage VBdata is the system low voltage VL, so that the first driving transistor TD1 is turned off, and the second reference voltage Vref2 is low. The voltage VL is such that the voltage level of the node B is the system low voltage VL. At this time, the voltage VLC across the liquid crystal capacitor Clc is VL-VH=-VH.

In the period T2, the scan signal Sscan is disabled, but the voltage levels of the nodes A, B and the inverted pixel voltage VBdata remain the same as the period T1, that is, the voltage VLC remains at -VH.

In the period T3, the first reference voltage Vref1 is converted from the system high voltage VH to the system low voltage VL, and the second reference voltage Vref2 is converted from the system low voltage VL to the system high voltage VH. At this time, through the coupling capacitor Ccp, the voltage level of the node A is coupled to the system high voltage VH+ΔV, that is, the voltage level of the node A is coupled to a higher voltage level, so that the system high voltage VH is transmitted to Node B, and raises the voltage level of node A through the bootstrap capacitor Cbs, where ΔV is greater than zero but less than the system high voltage VH and ΔV is close to the system high voltage VH. Further, the voltage VLC is VH-VL=VH, and the polarity inversion operation is completed.

In the period T4, the scan signal Sscan is enabled, and the switching transistor TSW is turned on by the rise of the scan signal Sscan, so that the pixel voltage Vdata of the system low voltage VL is transmitted to the node A. At this time, the transistor T3 and the second driving transistor TD2 are turned off, so the inverted pixel voltage VBdata is the system high voltage VH minus the threshold voltage Vth of the transistor, so that the first driving transistor TD1 is turned on. At this time, the first reference voltage Vref1 for the system high voltage VH is transmitted to the node B through the turned-on first driving transistor TD1, so that the voltage VLC of the liquid crystal capacitor Clc is (VH-2Vth)-VH=-2Vth.

In the period T5, the scan signal Sscan is disabled, but the voltage levels of the nodes A, B and the inverted pixel voltage VBdata remain the same as the period T1, that is, the voltage VLC remains at -2 Vth.

In the period T6, the first reference voltage Vref1 is converted from the system high voltage VH to the system low voltage VL, and the second reference voltage Vref2 is converted from the system low voltage VL to the system high voltage VH. At this time, the voltage level of the node A remains at the system low voltage VL, and the system low voltage VL is transmitted to the node B through the turned-on first driving transistor TD1, so that the voltage across the VLC is VL-VL=0.

In this embodiment, the frequencies of the first reference voltage Vref1 and the second reference voltage Vref2 are equal to 2 Hz, but in other embodiments, the frequencies of the first reference voltage Vref1 and the second reference voltage Vref2 may be equal to 2 Hz, It is determined by those of ordinary skill in the art.

In summary, the pixel circuit of the novel embodiment of the present invention automatically converts the polarity of the liquid crystal capacitor across the voltage through the inverter circuit, the first driving transistor, the second driving transistor, the coupling capacitor, and the bootstrap capacitor. Under low picture update rate, avoid liquid crystal being polarized. Moreover, the pixel circuit of the novel creation embodiment has the following advantages:

1. The present invention creates a first driving transistor, a second driving transistor, a first transistor, a second transistor, and a third transistor through two inverted first reference voltages and a second reference voltage. The time for positive bias is shortened to half to extend the service life of the first driving transistor, the second driving transistor, the first transistor, the second transistor, and the third transistor.

2. The novel embodiment uses the coupling capacitor and the shoe strap capacitor to pull the gate voltage of the second driving transistor up to a higher point when the first reference voltage and the second reference voltage fluctuate, so that the second driving transistor It can transmit the system high voltage more completely and reduce the influence of the gate voltage limit.

3. The novel creation embodiment can replace the polycrystalline germanium film transistor with an amorphous germanium film transistor, the cost overhead is greatly reduced, the process difficulty is greatly reduced, and the process speed and reliability can be increased.

4. The novel authoring embodiment can reduce the range of the input voltage by using the first reference voltage of the alternating current and the second reference voltage (that is, the structure of the alternating current common voltage (AC Vcom)) to effectively reduce the dynamic power consumption.

5. The novel creation embodiment controls the pixel circuit to operate at an operating frequency of 1 Hz, which ensures that the circuit can be directly used for updating operations in the standby screen, and can be re-transferred without using a data driving circuit (not shown). The voltage is applied to the pixel electrodes, thereby reducing the operation of the data driving circuit (not shown) to save AC power consumption.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the novel creation, and any person skilled in the art can make some changes without departing from the spirit and scope of the novel creation. Retouching, the scope of protection of this new creation is subject to the definition of the scope of the patent application attached.

100‧‧‧ pixel circuit
A, B‧‧‧ nodes
Cbs‧‧‧ boots with capacitor
Ccp‧‧‧Coupling Capacitor
Clc‧‧ liquid crystal capacitor
GND‧‧‧ Grounding voltage
INT‧‧‧ inverter circuit
PF1, PF2, T1~T6‧‧‧
Sscan‧‧‧ scan signal
T1‧‧‧first transistor
T2‧‧‧second transistor
T3‧‧‧ third transistor
TD1‧‧‧first drive transistor
TD2‧‧‧second drive transistor
TSW‧‧‧Switching transistor
VBdata‧‧‧ inverse pixel voltage
Vdata‧‧‧ pixel voltage
VH‧‧‧ system high voltage
VL‧‧‧ system low voltage
Vref1‧‧‧ first reference voltage
Vref2‧‧‧second reference voltage
Vth‧‧‧ threshold voltage ΔV‧‧‧ voltage

1 is a circuit diagram of a pixel circuit in accordance with an embodiment of the present invention. 2 is a schematic diagram of driving waveforms of a pixel circuit in accordance with an embodiment of the present invention.

100‧‧‧ pixel circuit

A, B‧‧‧ nodes

Cbs‧‧‧ boots with capacitor

Ccp‧‧‧Coupling Capacitor

Clc‧‧ liquid crystal capacitor

GND‧‧‧ Grounding voltage

INT‧‧‧ inverter circuit

Sscan‧‧‧ scan signal

T1‧‧‧first transistor

T2‧‧‧second transistor

T3‧‧‧ third transistor

TD1‧‧‧first drive transistor

TD2‧‧‧second drive transistor

TSW‧‧‧Switching transistor

VBdata‧‧‧ inverse pixel voltage

Vdata‧‧‧ pixel voltage

Vref1‧‧‧ first reference voltage

Vref2‧‧‧second reference voltage

Claims (8)

A pixel circuit includes: a switching transistor, a first end of the switching transistor receives a pixel voltage, a control terminal of the switching transistor receives a scan signal; and an inverter circuit coupled to the switch a second end of the crystal to receive the pixel voltage and provide an inverted pixel voltage; a first driving transistor, a first end of the first driving transistor receiving a first reference voltage, the first A control terminal of the driving transistor is coupled to the inverter circuit to receive the inverted pixel voltage; a second driving transistor, a first terminal of the second driving transistor receives a second reference voltage, the second A control terminal of the driving transistor receives the pixel voltage, a second end of the second driving transistor is coupled to a second end of the first driving transistor; a coupling capacitor coupled to the second reference voltage Between the control terminal of the second driving transistor; a bootband capacitor coupled between the control terminal of the second driving transistor and the second end of the second driving transistor; and a liquid crystal a capacitor coupled to the first driving transistor The second end is between the first reference voltage and the first reference voltage. The pixel circuit of claim 1, wherein the inverter circuit comprises: a first transistor, a first end of the first transistor and a control terminal receiving the first reference voltage, the first a second end of a transistor provides the inverted pixel voltage; a second transistor, a first end of the second transistor and a control terminal receive the second reference voltage, the second transistor The second end is coupled to the second end of the first transistor; and a third transistor, a first end of the third transistor is coupled to the second end of the first transistor, the third A control terminal of the crystal receives the pixel voltage, and a second terminal of the third transistor receives a ground voltage. The pixel circuit of claim 2, wherein the switching transistor, the first driving transistor, the second driving transistor, the first transistor, the second transistor, and the third device The crystals are each an amorphous germanium (a-Si) thin film transistor. The pixel circuit of claim 3, wherein the switching transistor, the first driving transistor, the second driving transistor, the first transistor, the second transistor, and the third device The crystals are each an N-type thin film transistor. The pixel circuit of claim 1, wherein the first reference voltage and the second reference voltage are each an alternating voltage. The pixel circuit of claim 5, wherein the first reference voltage and the second reference voltage are a system high voltage and a system low voltage, respectively. The pixel circuit of claim 1, wherein the first reference voltage and the second reference voltage have a frequency less than or equal to 2 Hertz (Hz). The pixel circuit of claim 7, wherein the switching transistor has a turn-on frequency of 1 hertz (Hz).