TWI713202B - Flash memories and methods for forming the same - Google Patents
Flash memories and methods for forming the same Download PDFInfo
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Abstract
Description
本發明實施例是關於半導體製造技術,特別是有關於快閃記憶體及其形成方法。The embodiments of the present invention are related to semiconductor manufacturing technology, in particular to flash memory and its forming method.
快閃記憶體為非揮發性的記憶體的一種型態。一般而言,一個快閃記憶體包含兩個閘極,第一個閘極為儲存資料的浮置閘極(floating gate),而第二個閘極為進行資料的輸入和輸出的控制閘極(control gate)。浮置閘極係位於控制閘極之下方且為「漂浮」的狀態。所謂漂浮係指以絕緣材料環繞且隔離浮置閘極以防止電荷流失。控制閘極係連接至字元線(word line,WL)以控制裝置。快閃記憶體的優點之一為可以區塊-區塊抹除資料(block-by-block erasing)。快閃記憶體廣泛地用於企業伺服器、儲存和網路科技,以及廣泛的消費電子產品,例如隨身碟(USB)快閃驅動裝置、行動電話、數位相機、平板電腦、筆記型電腦的個人電腦插卡(PC cards)和嵌入式控制器等等。Flash memory is a type of non-volatile memory. Generally speaking, a flash memory contains two gates. The first gate stores the data floating gate (floating gate), and the second gate carries out the data input and output control gate. gate). The floating gate is located below the control gate and is in a "floating" state. The so-called floating refers to the use of insulating materials to surround and isolate the floating gate to prevent charge loss. The control gate is connected to a word line (WL) to control the device. One of the advantages of flash memory is that it can block-by-block erasing. Flash memory is widely used in corporate servers, storage and network technology, as well as a wide range of consumer electronics products, such as personal storage devices such as flash drives, mobile phones, digital cameras, tablets, and laptops PC cards and embedded controllers, etc.
市場上可得到許多不同種類的非揮發性記憶體,例如快閃記憶體、電子抹除式可複寫唯讀記憶體(electrically erasable programmable read-only memory,EEPROM)和多次寫入(multi-time programmable,MTP)非揮發性記憶體。然而,嵌入式(embedded)快閃記憶體,特別是嵌入式分離閘極(split-gate)快閃記憶體,相較於其他的非揮發性記憶體的技術具有較大的優勢。Many different types of non-volatile memory are available on the market, such as flash memory, electronically erasable programmable read-only memory (EEPROM) and multi-time programmable, MTP) non-volatile memory. However, embedded flash memory, especially embedded split-gate flash memory, has a greater advantage than other non-volatile memory technologies.
雖然現有的快閃記憶體及其製造方法已足夠應付它們原先預定的用途,但它們仍未在各個方面皆令人滿意,因此快閃記憶體的技術目前仍有需克服的問題。Although the existing flash memory and its manufacturing method are sufficient for their original intended use, they are still not satisfactory in all aspects. Therefore, the flash memory technology still has problems to be overcome.
本發明實施例提供一種快閃記憶體。此快閃記憶體包括半導體基板、位於半導體基板上的浮置閘極結構、覆蓋浮置閘極結構的側壁及頂表面的閘極間介電層、以及位於閘極間介電層上的控制閘極。上述浮置閘極結構包括位於半導體基板上的浮置閘極介電層、位於浮置閘極介電層上的一對介電間隔物,其中此對介電間隔物具有朝向彼此的傾斜側壁、以及位於浮置閘極介電層上,且位於此對介電間隔物之間的浮置閘極。上述浮置閘極具有一對尖端,此對尖端各別位於介電間隔物的傾斜側壁上。The embodiment of the present invention provides a flash memory. The flash memory includes a semiconductor substrate, a floating gate structure located on the semiconductor substrate, an inter-gate dielectric layer covering the sidewall and top surface of the floating gate structure, and a control located on the inter-gate dielectric layer Gate. The above-mentioned floating gate structure includes a floating gate dielectric layer on the semiconductor substrate, a pair of dielectric spacers on the floating gate dielectric layer, wherein the pair of dielectric spacers have inclined sidewalls facing each other , And a floating gate located on the floating gate dielectric layer and between the pair of dielectric spacers. The above-mentioned floating gate has a pair of tips, and the pair of tips are respectively located on the inclined sidewall of the dielectric spacer.
本發明實施例提供一種快閃記憶體的形成方法。此方法包括提供半導體基板、在半導體基板上形成遮罩層,其中遮罩層具有開口,此開口露出半導體基板的一部分、在開口中形成浮置閘極結構、去除遮罩層、形成覆蓋浮置閘極結構的閘極間介電層、以及在閘極間介電層上形成控制閘極。上述形成浮置閘極結構的步驟包括在半導體基板上形成浮置閘極介電層,且在開口的相對側壁上及在浮置閘極介電層上形成一對介電間隔物、以及在開口中形成浮置閘極,其中浮置閘極設置在浮置閘極介電層上,且浮置閘極位於此對介電間隔物之間,且其中浮置閘極具有一對尖端,此對尖端各別位於介電間隔物上。The embodiment of the present invention provides a method for forming a flash memory. The method includes providing a semiconductor substrate, forming a mask layer on the semiconductor substrate, wherein the mask layer has an opening that exposes a part of the semiconductor substrate, forming a floating gate structure in the opening, removing the mask layer, and forming a cover floating The inter-gate dielectric layer of the gate structure and the control gate are formed on the inter-gate dielectric layer. The step of forming a floating gate structure includes forming a floating gate dielectric layer on a semiconductor substrate, and forming a pair of dielectric spacers on opposite sidewalls of the opening and on the floating gate dielectric layer, and A floating gate is formed in the opening, wherein the floating gate is disposed on the floating gate dielectric layer, and the floating gate is located between the pair of dielectric spacers, and the floating gate has a pair of tips, The pair of tips are respectively located on the dielectric spacer.
以下的實施例與所附的參考圖式將提供詳細的描述。The following embodiments and accompanying reference drawings will provide a detailed description.
以下的揭示內容提供許多不同的實施例或範例,以展示本發明實施例的不同部件。以下將揭示本說明書各部件及其排列方式之特定範例,用以簡化本揭露敘述。當然,這些特定範例並非用於限定本揭露。例如,若是本說明書以下的發明內容敘述了將形成第一部件於第二部件之上或上方,即表示其包括了所形成之第一及第二部件是直接接觸的實施例,亦包括了尚可將附加的部件形成於上述第一及第二部件之間,則第一及第二部件為未直接接觸的實施例。此外,本揭露說明中的各式範例可能使用重複的參照符號及/或用字。這些重複符號或用字的目的在於簡化與清晰,並非用以限定各式實施例及/或所述配置之間的關係。The following disclosure provides many different embodiments or examples to illustrate different components of the embodiments of the present invention. The following will disclose specific examples of the components and their arrangement in this specification to simplify the description of this disclosure. Of course, these specific examples are not used to limit the disclosure. For example, if the following invention content of this specification describes that the first part is formed on or above the second part, it means that it includes an embodiment in which the formed first and second parts are in direct contact, and also includes Additional components can be formed between the above-mentioned first and second components, and the first and second components are embodiments that are not in direct contact. In addition, the various examples in this disclosure may use repeated reference symbols and/or words. The purpose of these repeated symbols or words is for simplification and clarity, and is not used to limit the relationship between the various embodiments and/or the configurations.
再者,為了方便描述圖式中一元件或部件與另一(些)元件或部件的關係,可使用空間相對用語,例如「在…之下」、「下方」、「下部」、「上方」、「上部」及諸如此類用語。除了圖式所繪示之方位外,空間相對用語亦涵蓋使用或操作中之裝置的不同方位。當裝置被轉向不同方位時(例如,旋轉90度或者其他方位),則其中所使用的空間相對形容詞亦將依轉向後的方位來解釋。應可理解的是,於本發明實施例所述的方法之前、之中、及/或之後可提供額外的操作,且在方法的其他實施例中,可替換或省略一些所述的操作。Furthermore, in order to facilitate the description of the relationship between one element or component and another element or component(s) in the diagram, spatial relative terms can be used, such as "below", "below", "lower", "above" , "Upper" and the like. In addition to the orientation shown in the diagram, the relative terms of space also cover different orientations of the device in use or operation. When the device is turned in different directions (for example, rotated by 90 degrees or other directions), the spatially relative adjectives used therein will also be interpreted according to the turned position. It should be understood that additional operations may be provided before, during, and/or after the method described in the embodiments of the present invention, and in other embodiments of the method, some of the operations may be replaced or omitted.
在此,「約」、「大約」、「大抵」之用語通常表示在一給定值或範圍的20%之內,較佳是10%之內,且更佳是5%之內,或3%之內,或2%之內,或1%之內,或0.5%之內。應注意的是,說明書中所提供的數量為大約的數量,亦即在沒有特定說明「約」、「大約」、「大抵」的情況下,仍可隱含「約」、「大約」、「大抵」之含義。Here, the terms "about", "approximately", and "approximately" usually mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3 Within %, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantity provided in the manual is an approximate quantity, that is, without specific description of "about", "approximately", "approximately", "about", "approximately" and "approximately" can still be implied. The meaning of "probably".
此處描述示例方法及結構的一些變化。本領域具有通常知識者將可容易理解在其他實施例的範圍內可做其他的修改。雖然討論的一些方法實施例以特定順序進行,各式其他方法實施例可以另一合乎邏輯的順序進行,且可包括少於或多於此處討論的步驟。在一些圖示中,其中所示的一些組件或部件的元件符號可被省略,以避免與其他組件或部件混淆;此係為了便於描繪此些圖示。Some changes to the example method and structure are described here. Those with ordinary knowledge in the art will easily understand that other modifications can be made within the scope of other embodiments. Although some of the method embodiments discussed are performed in a specific order, various other method embodiments can be performed in another logical order, and may include fewer or more steps than those discussed herein. In some figures, the symbol of some components or parts shown therein may be omitted to avoid confusion with other components or parts; this is for the convenience of depicting these figures.
本發明實施例提供一種快閃記憶體及其形成方法,特別是嵌入式分離閘極快閃記憶體。在本發明一些實施例中,使用一對介電間隔物以創造出具有一對尖銳尖端的浮置閘極。由於裝置的抹除(erase)效率係取決於尖端的尖銳程度,此對尖銳尖端可以改善分離閘極快閃記憶體的性能。在本發明中將討論根據本發明實施例的用於形成快閃記憶體的方法。The embodiment of the present invention provides a flash memory and a forming method thereof, particularly an embedded split gate flash memory. In some embodiments of the invention, a pair of dielectric spacers are used to create a floating gate with a pair of sharp tips. Since the erase efficiency of the device depends on the sharpness of the tip, the pair of sharp tips can improve the performance of the split gate flash memory. In the present invention, a method for forming a flash memory according to an embodiment of the present invention will be discussed.
第1-9圖係根據一些實施例,繪示出用於形成第9圖之快閃記憶體10之示例方法的各個中間階段的剖面示意圖。FIGS. 1-9 are schematic cross-sectional diagrams illustrating various intermediate stages of an exemplary method for forming the
第1圖根據本發明實施例繪示出形成快閃記憶體10之方法的起始步驟。如第1圖所示,提供半導體基板100。上述基板100可以為或包括塊體半導體(bulk semiconductor)基板、絕緣體上覆半導體(semiconductor-on-insulator, SOI)基板或類似基板,其可為摻雜(例如,使用p-型或n-型摻質(dopant))或未摻雜的。一般而言,絕緣體上覆半導體基板包括形成於絕緣體上的半導體材料的膜層。舉例來說,此絕緣層可為,埋藏氧化物(buried oxide, BOX)層、氧化矽(silicon oxide)層、或類似膜層。提供上述絕緣層於基板上,通常是矽(silicon)或玻璃(glass)基板。亦可使用其他基板,例如多層(multi-layered)或梯度(gradient)基板。在一些實施例中,半導體基板之半導體材料可包括含矽(silicon, Si)或鍺(germanium, Ge)的元素半導體;包括碳化矽(silicon carbide)、砷化鎵(gallium arsenic)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)或銻化銦(indium antimonide)的化合物(compound)半導體;包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、或GaInAsP的合金半導體;或上述之組合。FIG. 1 illustrates the initial steps of a method of forming a
在一些實施例中,半導體基板100為p型矽基板。舉例來說,p型矽基板100的摻質可包括硼(boron)、鋁(aluminum)、鎵(gallium)、銦(indium)、其他適當的摻質、或上述之組合,且p型矽基板100之摻質濃度可為5x1014
至5x1016
cm-3
。在其他的實施例中,半導體基板100可為n型矽基板。舉例來說,n型矽基板100的摻質可包括砷(arsenic)、磷(phosphorus)、銻(antimony)、其他適當的摻質或上述之組合,且n型矽基板100之摻質濃度可為5x1014
至5x1016
cm-3
。後文之實施例將以使用p型矽基板100為例進行說明,但本發明並不以此為限。In some embodiments, the
接下來,如第2圖所示,在半導體基板100上形成遮罩層102,且在遮罩層102中形成開口104。如第2圖所示,藉由開口104暴露一部分的半導體基板100,且上述開口104係形成以定義將於後形成的浮置閘極結構的位置。Next, as shown in FIG. 2, a
在一些實施例中,遮罩層102可以包括氮化物,例如氮化矽(silicon nitride)、氮氧化矽(silicon oxynitride)、其他適當的材料、或上述之組合。舉例來說,可以藉由低壓化學氣相沉積 (low-pressure chemical vapor deposition, LPCVD) 製程、電漿增強化學氣相沉積 (plasma-enhanced chemical vapor deposition, PECVD) 製程、其他適當的製程、或上述之組合來形成遮罩層102。舉例來說,遮罩層102的厚度可為0.1微米至1微米,但不以此為限。In some embodiments, the
在一些實施例中,可以藉由圖案化製程以在遮罩層102中形成開口104。舉例來說,上述圖案化製程可以包括微影製程(例如,光阻塗佈(photoresist coating)、軟烘烤、遮罩對準(mask aligning)、曝光、曝光後烘烤、光阻顯影、其他適當的製程、或上述之組合)、蝕刻製程(例如,濕式蝕刻製程、乾式蝕刻製程、其他適當的製程、或上述之組合)、其他適當的製程、或上述之組合。在一些實施例中,可以藉由微影製程以在遮罩層102上形成具有對應於開口104之開口的圖案化光阻層(未繪示),接著可以進行蝕刻製程來去除上述圖案化光阻層之開口所露出之部分遮罩層102,以在遮罩層102中形成開口104。In some embodiments, the opening 104 may be formed in the
第3圖繪示出第一介電層106的形成。第一介電層106係順應性地形成於遮罩層102之上,因此第一介電層106沿著開口104的相對側壁及底表面。在後續製程中,位於開口104之底表面的第一介電層106將作為浮置閘極介電層110c,且位於開口104之相對側壁的第一介電層106將作為一部分之介電間隔物110a及110b(沒有繪示於第3圖中,但可參照下述關於第5圖的說明)。FIG. 3 illustrates the formation of the
在一些實施例中,第一介電層106可以為氧化矽、氮化矽、氮氧化矽、高介電常數(high-k)介電材料、或其它任何適合之介電材料、或上述之組合。此高介電常數(high-k)介電材料之材料可以為金屬氧化物、金屬氮化物、金屬矽化物、過渡金屬氧化物、過渡金屬氮化物、過渡金屬矽化物、金屬的氮氧化物、金屬鋁酸鹽、鋯矽酸鹽、鋯鋁酸鹽。舉例來說,此高介電常數(high-k)介電材料可為LaO、AlO、ZrO、TiO、Ta2
O5
、Y2
O3
、SrTiO3(STO)、BaTiO3
(BTO)、BaZrO、HfO2
、HfO3
、HfZrO、HfLaO、HfSiO、HfSiON、LaSiO、AlSiO、HfTaO、HfTiO、HfTaTiO、HfAlON、(Ba,Sr)TiO3
(BST)、Al2
O3
、其它適當材料之其它高介電常數介電材料、或上述組合。在一些實施例中,可藉由化學氣相沉積製程(例如,電漿增強化學氣相沉積 (plasma-enhanced chemical vapor deposition,PECVD)製程、或有機金屬化學氣相沉積(metalorganic chemical vapor deposition, MOCVD)製程)、原子層沉積(atomic layer deposition, ALD)製程(例如,電漿增強原子層沉積(plasma enhanced atomic layer deposition, PEALD)製程)、其他適當的製程、或上述之組合來形成第一介電層106。In some embodiments, the
在一些實施例中,第一介電層106的厚度可以為50埃(Å)至300埃,但本發明實施例並不限於此。In some embodiments, the thickness of the
接下來,如第4圖所示,在第一介電層106上形成第二介電層108,其中第二介電層108過填充開口104。部分之第二介電層108將在後續製程中作為一部分之介電間隔物110a及110b(沒有繪示於第4圖中,但可參照下述關於第5圖的說明)。用於形成第二介電層108之材料可相似於用於形成第一介電層106之材料,故於此不再贅述。在一些實施例中,第二介電層108及第一介電層106可以由相同的材料所形成。在其他實施例中,第二介電層108及第一介電層106可以由不同的材料所形成。Next, as shown in FIG. 4, a
在一些實施例中,可藉由化學氣相沉積製程(例如,電漿增強化學氣相沉積 (plasma-enhanced chemical vapor deposition,PECVD) 製程、或有機金屬化學氣相沉積(metalorganic chemical vapor deposition, MOCVD)製程)、原子層沉積(atomic layer deposition, ALD)製程(例如,電漿增強原子層沉積(plasma enhanced atomic layer deposition, PEALD)製程)、旋轉塗佈玻璃(spin-on-glass, SOG)製程、其他適當的製程、或上述之組合來形成第一介電層106。In some embodiments, a chemical vapor deposition process (for example, plasma-enhanced chemical vapor deposition (PECVD) process, or metalorganic chemical vapor deposition (MOCVD) ) Process), atomic layer deposition (ALD) process (for example, plasma enhanced atomic layer deposition (PEALD) process), spin-on-glass (SOG) process , Other appropriate processes, or a combination of the above to form the
第5圖繪示出浮置閘極介電層110c及一對介電間隔物110a及110b的形成。在一些實施例中,對第一介電層106及第二介電層108進行異向性回蝕刻製程(anisotropic etching back process),以去除部分之第一介電層106及第二介電層108。如第5圖所示,在異向性回蝕刻製程之後,位於開口104之底表面的第一介電層106作為浮置閘極介電層110c,且位於開口104之相對側壁的第一介電層106以及剩餘的第二介電層108作為上述介電間隔物110a及110b。FIG. 5 illustrates the formation of a floating
在後續製程中,上述介電間隔物110a及110b將用以創造具有一對尖端120a及120b的浮置閘極120(沒有繪示於第5圖中,但可參照下述關於第6圖的說明),其中此對尖端120a及120b各別位於介電間隔物110a及110b之上。In the subsequent process, the above-mentioned
如第5圖所示,在一些實施例中,在異向性回蝕刻製程之後,介電間隔物110a可以具有傾斜側壁110a’,且介電間隔物110b可以具有朝向傾斜側壁110a’的傾斜側壁110b’。上述這對傾斜側壁110a’及110b’具有增加尖端120a及120b的尖銳度的好處(參照第6圖)。As shown in FIG. 5, in some embodiments, after the anisotropic etch-back process, the
在一些實施例中,在異向性回蝕刻製程之後,上述這對介電間隔物110a及110b可以與遮罩層102具有相同的高度,如第5圖所示。換句話說,此對介電間隔物110a及110b的最頂部處與遮罩層102的頂表面位於同一水平,這也有助於提升尖端120a及120b的尖銳度(參照第6圖)。In some embodiments, after the anisotropic etch-back process, the pair of
在一些實施例中,上述異向性回蝕刻製程可以是乾蝕刻製程,例如電漿蝕刻製程(plasma etching process)、反應離子蝕刻製程(reactive ion etching process)、其他適當的製程、或上述之組合。In some embodiments, the anisotropic etch-back process may be a dry etching process, such as a plasma etching process, a reactive ion etching process, other appropriate processes, or a combination of the foregoing .
第6圖繪示出浮置閘極120的形成。在一些實施例中,形成浮置閘極120以填充開口104,其中浮置閘極120係設置在浮置閘極介電層110c上,且位於介電間隔物110a及110b之間。上述浮置閘極120、介電間隔物110a及110b、以及浮置閘極介電層110c一起構成浮置閘極結構200。此外,如第6圖所示,浮置閘極120具有一對尖端120a及120b,此對尖端120a及120b各別位於上述介電間隔物110a及110b的傾斜側壁110a’及110b’上。浮置閘極120的尖端120a及120b可以增加浮置閘極120及將於後續製程中形成的控制閘極之間的電流,從而改善快閃記憶體的性能(例如,縮短抹除時間)。FIG. 6 illustrates the formation of the floating
在一些實施例中,上述浮置閘極120的材料包括多晶矽(poly-silicon)。在其他實施例中,上述浮置閘極120的材料可以包括金屬(例如,鎢(tungsten)、鈦(titanium)、鋁(aluminum)、銅(copper)、鉬(molybdenum)、鎳(nickel)、鉑(platinum)、類似材料、或上述之組合)、金屬合金、金屬氮化物(例如,氮化鎢(tungsten nitride)、氮化鉬(molybdenum nitride)、氮化鈦(titanium nitride)、氮化鉭(tantalum nitride)、類似材料、或上述之組合)、金屬矽化物(例如,矽化鎢(tungsten silicide)、矽化鈦(titanium silicide)、矽化鈷(cobalt silicide)、矽化鎳(nickel silicide)、矽化鉑(platinum silicide)、矽化鉺(erbium silicide)、類似材料、或上述之組合)、金屬氧化物(例如,氧化釕(ruthenium oxide)、氧化銦錫(indium tin oxide)、類似材料、或上述之組合)、其他適當的材料、或上述之組合。In some embodiments, the material of the floating
舉例來說,可以藉由化學氣相沉積製程(例如,低壓化學氣相沉積(LPCVD)製程、電漿增強化學氣相沉積(PECVD)製程)、物理氣相沉積(physical vapor deposition, PVD)製程(例如,真空蒸鍍(vacuum evaporation)製程、或濺鍍(sputtering)製程)、其他適當的製程、或上述之組合來形成上述浮置閘極120。在一些實施例中,浮置閘極120的材料可以形成為過填充開口104,且接著進行回蝕刻(etch back)或平坦化製程(例如,化學機械研磨(chemical-mechanical-polishing, CMP)製程)以去除位於開口104外之浮置閘極120的材料的多餘部分,以在開口104中形成浮置閘極120。For example, a chemical vapor deposition process (for example, a low pressure chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process), a physical vapor deposition (PVD) process can be used (For example, a vacuum evaporation process, or a sputtering process), other appropriate processes, or a combination of the foregoing, to form the floating
在一些實施例中,如第6圖所示,浮置閘極120可以具有平坦的頂表面120s。在平坦化製程或回蝕刻製程之後,此平坦的頂表面120s與上述介電間隔物110a及110b的最頂部處齊平。在一些實施例中,如第6圖所示,浮置閘極120及介電間隔物110a及110b在剖面示意圖中共同構成一矩形形狀(rectangular shape)。
In some embodiments, as shown in FIG. 6, the floating
接下來,如第7圖所示,進行蝕刻製程(例如,濕式蝕刻、乾式蝕刻製程、其他合適的製程、或上述之組合)以選擇性的從半導體基板100去除遮罩層102,而在蝕刻製程之後,浮置閘極結構200留在半導體基板100上。
Next, as shown in FIG. 7, an etching process (eg, wet etching, dry etching, other suitable processes, or a combination of the above) is performed to selectively remove the
如第7圖所示,介電間隔物110a及110b各可以具有底部寬度W1,且浮置閘極結構200可以具有底部寬度W2,其中W2大於W1。當W1越大時,由於尖端120a及120b更尖銳,因此裝置的抹除效率越好。
As shown in FIG. 7, each of the
接著,如第8圖所示,在半導體基板100及浮置閘極結構200上順應性地形成閘極間介電層220。在一些實施例中,閘極間介電層220、介電間隔物110a及110b、以及浮置閘極介電層110c完全地包覆浮置閘極120。
Next, as shown in FIG. 8, an inter-gate
在所繪示的實施例中,閘極間介電層220可以包括氧化矽。可以藉由氧化製程、化學氣相沉積製程、其他適當的製程、或上述之組合來形成上述氧化矽。舉例來說,上述氧化製程可以包括乾式氧化製程(例如:Si+O2 → SiO2)、濕式氧化製程(例如:Si+2H2O → SiO2+2H2)、或上述之組合。
In the illustrated embodiment, the inter-gate
在其他實施例中,閘極間介電層220可以包括高介電常數介電材料。此高介電常數介電材料可以包括LaO、AlO、ZrO、TiO、Ta2
O5
、Y2
O3
、SrTiO3(STO)、BaTiO3
(BTO)、BaZrO、HfO2
、HfO3
、HfZrO、HfLaO、HfSiO、HfSiON、LaSiO、AlSiO、HfTaO、HfTiO、HfTaTiO、HfAlON、(Ba,Sr)TiO3
(BST)、Al2
O3
、其它適當材料之其它高介電常數介電材料、或上述組合。舉例來說,可藉由化學氣相沉積製程(例如,電漿增強化學氣相沉積 (PECVD)製程、或有機金屬化學氣相沉積(MOCVD)製程)、原子層沉積(ALD)製程(例如,電漿增強原子層沉積(PEALD)製程)、物理氣相沉積製程(例如,真空蒸鍍(vacuum evaporation)製程、或濺鍍(sputtering)製程)、其他適當的製程、或上述之組合來形成此高介電常數介電材料。In other embodiments, the inter-gate
在一些實施例中,閘極間介電層220的厚度可以為50埃至250埃,但本發明實施例並不限於此。In some embodiments, the thickness of the inter-gate
第9圖繪示出控制閘極300的形成。在一些實施例中,控制閘極300形成在閘極間介電層220上。更具體而言,如第9圖所示,控制閘極300覆蓋介電間隔物110a,且控制閘極300沒有覆蓋介電間隔物110b。應注意的是,控制閘極300藉由閘極間介電層220與浮置閘極結構200分開。在所繪示的實施例中,上述控制閘極300包括多晶矽。在其他實施例中,上述控制閘極300的材料可以包括金屬(例如,鎢(tungsten)、鈦(titanium)、鋁(aluminum)、銅(copper)、鉬(molybdenum)、鎳(nickel)、鉑(platinum)、類似材料、或上述之組合)、金屬合金、金屬氮化物(例如,氮化鎢(tungsten nitride)、氮化鉬(molybdenum nitride)、氮化鈦(titanium nitride)、氮化鉭(tantalum nitride)、類似材料、或上述之組合)、金屬矽化物(例如,矽化鎢(tungsten silicide)、矽化鈦(titanium silicide)、矽化鈷(cobalt silicide)、矽化鎳(nickel silicide)、矽化鉑(platinum silicide)、矽化鉺(erbium silicide)、類似材料、或上述之組合)、金屬氧化物(例如,氧化釕(ruthenium oxide)、氧化銦錫(indium tin oxide)、類似材料、或上述之組合)、其他適當的材料、或上述之組合。FIG. 9 illustrates the formation of the
在一些實施例中,可以藉由沉積製程且接著進行圖案化製程來形成控制閘極300。上述沉積製程可以包括化學氣相沉積製程(例如,低壓化學氣相沉積(LPCVD)製程、或電漿增強化學氣相沉積(PECVD)製程)、物理氣相沉積製程(例如,真空蒸鍍製程、濺鍍製程)、其他適當的製程、或上述之組合。上述圖案化製程可以包括蝕刻製程。In some embodiments, the
第9圖亦繪示出一對源極/汲極區400的形成。在一些實施例中,藉由將離子佈植至半導體基板100中以形成上述源極/汲極區400。浮置閘極結構200和控制閘極300位於此對源極/汲極區400之間。FIG. 9 also illustrates the formation of a pair of source/
在本實施例中,半導體基板100為p型基板,且源極/汲極區400係藉由在半導體基板100內佈植n型摻雜物所形成,例如磷(phosphorous, P)或砷(arsenic, As)。在其他實施例中,半導體基板100為n型基板,且源極/汲極區400係藉由在半導體基板100內佈植p型摻雜物所形成,例如硼(B)。半導體基板100的導電類型與源極/汲極區400的導電類型相反。In this embodiment, the
如第9圖所示,快閃記憶體10包括半導體基板100、位於半導體基板100上的浮置閘極結構200、覆蓋浮置閘極結構200的側壁及頂表面的閘極間介電層220、以及位於閘極間介電層220上的控制閘極300。上述浮置閘極結構200包括位於半導體基板100上的浮置閘極介電層110c、位於浮置閘極介電層110c上的一對介電間隔物110a及110b,其中此對介電間隔物110a及110b具有朝向彼此的傾斜側壁110a’及110b’、以及位於浮置閘極介電層110c上,且位於此對介電間隔物110a及110b之間的浮置閘極120。上述浮置閘極120具有一對尖端120a及120b,此對尖端120a及120b各別位於介電間隔物110a及110b的傾斜側壁110a’及110b’上。裝置的抹除效率係取決於尖端120a及120b的尖銳程度。上述傾斜側壁110a’及110b’具有增加尖端120a及120b的尖銳度的好處,從而改善快閃記憶體10的性能。As shown in FIG. 9, the
在一些實施例中,此對介電間隔物110a及110b的最頂部處與遮罩層102的頂表面位於同一水平,這也有助於提升尖端120a及120b的尖銳度,從而進一步增加快閃記憶體10的性能。In some embodiments, the top of the pair of
第10、11圖係根據一些實施例,繪示出用於形成第11圖中之快閃記憶體20之另一示例方法的各個中間階段的剖面示意圖。為了清楚起見,相似或相同的元件及製程將使用相同的參照符號。為了簡明之目的,此處不再重複對這些製程及裝置的描述。FIGS. 10 and 11 are schematic cross-sectional diagrams illustrating the intermediate stages of another exemplary method for forming the
除了形成額外的氧化物結構140以進一步使浮置閘極的尖端更尖銳以外,快閃記憶體20相似於快閃記憶體10。如此一來,浮置閘極120’即具有凹陷的頂表面120s’,且快閃記憶體20之浮置閘極120’的尖端120a’及120b’較第9圖之快閃記憶體10之浮置閘極120的尖端120a及120b更尖銳。The
參照第10圖,在形成如第6圖所述的浮置閘極120之後,在去除遮罩層102之前,在浮置閘極120’的頂表面上形成氧化物結構140。如第10圖所示,在一些實施例中,對浮置閘極120進行氧化製程,以形成浮置閘極120’及位於浮置閘極120’上的氧化物結構140,其中浮置閘極120’具有凹陷的頂表面120s’,且浮置閘極120’的最頂部處與上述介電間隔物110a及110b的最頂部處位於同一水平。上述浮置閘極120’的尖端120a’及120b’較第9圖之快閃記憶體10之尖端120a及120b更尖銳,因此將於後續製程中形成的快閃記憶體20相較於快閃記憶體10具有更佳的抹除效率。Referring to FIG. 10, after forming the floating
接下來,去除遮罩層102,並且對第10圖中所示的結構進行相似於第7至9圖所述之製程的一系列製程,以完成如第11圖中所示的快閃記憶體20。Next, the
如第11圖所示,快閃記憶體20包括半導體基板100、位於半導體基板100上的浮置閘極結構200’、覆蓋浮置閘極結構200’的側壁及頂表面的閘極間介電層220、以及位於閘極間介電層220上的控制閘極300。上述浮置閘極結構200’包括位於半導體基板100上的浮置閘極介電層110c、位於浮置閘極介電層110c上的一對介電間隔物110a及110b,其中此對介電間隔物110a及110b具有朝向彼此的傾斜側壁110a’及110b’、以及位於浮置閘極介電層110c上,且位於此對介電間隔物110a及110b之間的浮置閘極120’。 上述浮置閘極120’具有一對尖端120a’及120b’,此對尖端120a’及120b’各別位於介電間隔物110a及110b的傾斜側壁110a’及110b’上。上述傾斜側壁110a’及110b’具有增加尖端120a’及120b’的尖銳度的好處,從而改善快閃記憶體20的性能。As shown in FIG. 11, the
在一些實施例中,此對介電間隔物110a及110b的最頂部處與遮罩層102的頂表面位於同一水平,這也有助於提升尖端120a’及120b’的尖銳度,從而進一步改善快閃記憶體20的性能。In some embodiments, the top of the pair of
在一些實施例中,上述浮置閘極結構200’更包括位於浮置閘極120’及閘極間介電層220之間的氧化物結構140。在此實施例中,浮置閘極120’具有凹陷的頂表面120s’,這可以進一步使尖端120a’及120b’更尖銳。在此實施例中,浮置閘極120’的最頂部處與上述介電間隔物110a及110b的最頂部處位於同一水平。如此一來,即可更進一步改善快閃記憶體20的抹除效率。In some embodiments, the above-mentioned floating gate structure 200' further includes an
綜合上述,本發明實施例之快閃記憶體元件包括一對介電間隔物,此對介電間隔物用以創造具有一對尖銳尖端的浮置閘極。此對尖銳尖端可以增加浮置閘極及控制閘極之間的電流,從而改善快閃記憶體的性能(例如,縮短抹除時間)。In summary, the flash memory device of the embodiment of the present invention includes a pair of dielectric spacers, and the pair of dielectric spacers are used to create a floating gate with a pair of sharp points. The pair of sharp tips can increase the current between the floating gate and the control gate, thereby improving the performance of the flash memory (for example, shortening the erasure time).
以上概略說明了本發明數個實施例的特徵,使所屬技術領域內具有通常知識者對於本揭露可更為容易理解。任何所屬技術領域內具有通常知識者應瞭解到本說明書可輕易作為其他結構或製程的變更或設計基礎,以進行相同於本揭露實施例的目的及/或獲得相同的優點。任何所屬技術領域內具有通常知識者亦可理解與上述等同的結構或製程並未脫離本揭露之精神及保護範圍內,且可在不脫離本揭露之精神及範圍內,當可作更動、替代與潤飾。The above briefly describes the features of several embodiments of the present invention, so that those with ordinary knowledge in the technical field can more easily understand the present disclosure. Anyone with ordinary knowledge in the relevant technical field should understand that this specification can easily be used as a basis for other structural or manufacturing changes or design to perform the same purpose and/or obtain the same advantages as the embodiments of the present disclosure. Anyone with ordinary knowledge in the technical field can also understand that the structure or process equivalent to the above-mentioned structure or process does not depart from the spirit and protection scope of this disclosure, and can be changed or substituted without departing from the spirit and scope of this disclosure And retouch.
10、20:快閃記憶體100:半導體基板102:遮罩層104:開口106:第一介電層108:第二介電層110a、110b:介電間隔物110a’、110b’:側壁110c:浮置閘極介電層120、120':浮置閘極120a、120b、120a'、120b':尖端120s、120s':頂表面140:氧化物結構200:浮置閘極結構220:閘極間介電層300:控制閘極400:源極/汲極區W1、W2:底部寬度10.20: Flash memory 100: semiconductor substrate 102: mask layer 104: opening 106: first dielectric layer 108:
以下將配合所附圖式詳述本發明的一些實施例。應注意的是,依據在業界的標準做法,各種部件並未按照比例繪製且僅用以說明例示。事實上,可能任意地放大或縮小元件的尺寸,以清楚地表現出本發明實施例的部件。 第1-9圖係根據一些實施例,繪示出用於形成第9圖之快閃記憶體之示例方法的各個中間階段的剖面示意圖。 第10、11圖係根據一些實施例,繪示出用於形成第11圖之快閃記憶體之另一示例方法的各個中間階段的剖面示意圖。Hereinafter, some embodiments of the present invention will be described in detail with the accompanying drawings. It should be noted that, according to standard practices in the industry, various components are not drawn to scale and are only used for illustration. In fact, it is possible to arbitrarily enlarge or reduce the size of the element to clearly show the components of the embodiment of the present invention. FIGS. 1-9 are schematic cross-sectional diagrams illustrating various intermediate stages of an exemplary method for forming the flash memory of FIG. 9 according to some embodiments. FIGS. 10 and 11 are schematic cross-sectional diagrams illustrating various intermediate stages of another example method for forming the flash memory of FIG. 11 according to some embodiments.
10:快閃記憶體 10: Flash memory
100:半導體基板 100: Semiconductor substrate
110a、110b:介電間隔物 110a, 110b: Dielectric spacer
110a’、110b’:側壁 110a’, 110b’: side wall
110c:浮置閘極介電層 110c: floating gate dielectric layer
120:浮置閘極 120: floating gate
120a、120b:尖端 120a, 120b: tip
200:浮置閘極結構 200: Floating gate structure
220:閘極間介電層 220: Inter-gate dielectric layer
300:控制閘極 300: control gate
400:源極/汲極區 400: source/drain region
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US6635533B1 (en) * | 2003-03-27 | 2003-10-21 | Powerchip Semiconductor Corp. | Method of fabricating flash memory |
US6660588B1 (en) * | 2002-09-16 | 2003-12-09 | Advanced Micro Devices, Inc. | High density floating gate flash memory and fabrication processes therefor |
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US6660588B1 (en) * | 2002-09-16 | 2003-12-09 | Advanced Micro Devices, Inc. | High density floating gate flash memory and fabrication processes therefor |
US6635533B1 (en) * | 2003-03-27 | 2003-10-21 | Powerchip Semiconductor Corp. | Method of fabricating flash memory |
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