CN111524980A - Flash memory and forming method thereof - Google Patents

Abstract

An embodiment of the present invention provides a flash memory and a method for forming the same. The flash memory includes a semiconductor substrate, a floating gate structure located on the semiconductor substrate, an inter-gate dielectric layer covering the sidewalls and top surface of the floating gate structure, and a control gate located on the inter-gate dielectric layer. The floating gate structure includes a floating gate dielectric layer located on the semiconductor substrate, a pair of dielectric spacers located on the floating gate dielectric layer, wherein the pair of dielectric spacers have inclined sidewalls facing each other, and a floating gate located on the floating gate dielectric layer and between the pair of dielectric spacers. The floating gate has a pair of tips, and the pair of tips are respectively located on the inclined sidewalls of the dielectric spacers. The flash memory and the method for forming the same provided by the present invention can shorten the erasing time of the flash memory and improve the performance of the flash memory.

Description

Flash memory and method of forming the same

technical field

Embodiments of the present invention relate to semiconductor manufacturing technology, and in particular, to a flash memory and a method for forming the same.

Background technique

Flash memory is a type of non-volatile memory. Generally speaking, a flash memory includes two gates, the first gate is a floating gate for storing data, and the second gate is a control gate for data input and output . The floating gate is located below the control gate and is in a "floating" state. Floating means surrounding and isolating the floating gate with insulating material to prevent charge loss. The control gate is connected to a wordline (WL) to control the device. One of the advantages of flash memory is that it can block-by-block erasing data. Flash memory is widely used in enterprise server, storage, and networking technologies, as well as in a wide range of consumer electronics, such as USB flash drives, PC plug-ins for mobile phones, digital cameras, tablet computers, and notebook computers. Cards (PC cards) and embedded controllers, etc.

There are many different types of non-volatile memory available on the market, such as flash memory, electronically erasable programmable read-only memory (EEPROM), and multi-time programmable memory. MTP) non-volatile memory. However, embedded flash memory, especially embedded split-gate flash memory, has great advantages over other non-volatile memory technologies.

Although the existing flash memories and their manufacturing methods are sufficient for their original intended use, they are still not satisfactory in all aspects, so there are still problems to be overcome in the flash memory technology.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a flash memory. The flash memory includes a semiconductor substrate, a floating gate structure on the semiconductor substrate, an inter-gate dielectric layer covering sidewalls and a top surface of the floating gate structure, and a control gate on the inter-gate dielectric layer . The floating gate structure described above includes a floating gate dielectric layer on a semiconductor substrate, a pair of dielectric spacers on the floating gate dielectric layer, wherein the pair of dielectric spacers have sloped sidewalls facing each other, and A floating gate on the floating gate dielectric layer and between the pair of dielectric spacers. The floating gate has a pair of tips, and the pair of tips are respectively located on the inclined sidewalls of the dielectric spacer.

Embodiments of the present invention provide a method for forming a flash memory. The method includes providing a semiconductor substrate, forming a mask layer on the semiconductor substrate, wherein the mask layer has an opening that exposes a portion of the semiconductor substrate, forming a floating gate structure in the opening, removing the mask layer, and forming a covering floating gate an inter-gate dielectric layer of the structure, and a control gate is formed on the inter-gate dielectric layer. The above-described steps of forming a floating gate structure include forming a floating gate dielectric layer on a semiconductor substrate, and forming a pair of dielectric spacers on opposite sidewalls of the opening and on the floating gate dielectric layer, and forming a pair of dielectric spacers in the opening A floating gate is formed, wherein the floating gate is disposed on the floating gate dielectric layer, and the floating gate is located between the pair of dielectric spacers, and wherein the floating gate has a pair of tips, and the pair of tips are respectively located in the dielectric spacer on electrical spacers.

The flash memory and its forming method provided by the present invention can shorten the erasing time of the flash memory and improve the performance of the flash memory.

The following examples and accompanying reference drawings will provide a detailed description.

Description of drawings

Some embodiments of the present invention will be described in detail below with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale and are for illustration purposes only. In fact, the dimensions of elements may be arbitrarily enlarged or reduced to clearly represent components of the embodiments of the invention.

1-9 are cross-sectional schematic diagrams illustrating various intermediate stages of an example method for forming the flash memory of FIG. 9, according to some embodiments.

10 and 11 are schematic cross-sectional views illustrating various intermediate stages of another example method for forming the flash memory of FIG. 11, according to some embodiments.

Reference number:

10, 20～flash memory;

100～semiconductor substrate;

102～mask layer;

104 ~ opening;

106～the first dielectric layer;

108～the second dielectric layer;

110a, 110b～dielectric spacers;

110a', 110b'～side walls;

110c～floating gate dielectric layer;

120, 120'～floating gate;

120a, 120b, 120a', 120b' ~ tip;

120s, 120s’ ~ top surface;

140～oxide structure;

200, 200'～floating gate structure;

220 ~ inter-gate dielectric layer;

300～Control grid;

400～source/drain region;

W1, W2 ~ Bottom width.

Detailed ways

The following disclosure provides many different embodiments or examples to illustrate different components of embodiments of the invention. The following will disclose specific examples of the various components of the present specification and their arrangement, so as to simplify the description of the present invention. Of course, these specific examples are not intended to limit the invention. For example, if the following summary of the present specification describes that the first part is formed on or above the second part, it means that it includes the embodiment in which the first and second parts are formed in direct contact, and also includes further Additional components may be formed between the first and second components described above, the first and second components being embodiments that are not in direct contact. Furthermore, the various examples in the description may use repeated reference symbols and/or wording. These repeated symbols or words are used for simplicity and clarity, and are not used to limit the relationships between the various embodiments and/or the configurations.

Furthermore, for convenience in describing the relationship of one element or component to another element or component(s) in the figures, spatially relative terms such as "below", "below", "lower", "above" may be used , "upper" and similar terms. In addition to the orientation depicted in the drawings, spatially relative terms also encompass different orientations of the device in use or operation. When the device is turned in a different orientation (eg, rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted according to the turned orientation. It should be understood that additional operations may be provided before, during, and/or after the method described in the embodiments of the present invention, and in other embodiments of the method, some of the described operations may be replaced or omitted.

Herein, the terms "about", "approximately", "approximately" generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range, or within 3% Within %, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, “about”, “approximately” and “approximately” can still be implied without the specific description of “about”, “approximately” and “approximately”. probably" meaning.

Several variations of example methods and structures are described herein. Those skilled in the art will readily appreciate that other modifications may be made within the scope of other embodiments. Although some method embodiments are discussed as being performed in a particular order, various other method embodiments can be performed in another logical order and can include fewer or more steps than those discussed herein. In some figures, reference numerals of some components or parts shown therein may be omitted to avoid confusion with other components or parts; this is to facilitate the depiction of such figures.

Embodiments of the present invention provide a flash memory and a method for forming the same, particularly an embedded split gate flash memory. In some embodiments of the invention, a pair of dielectric spacers is used to create a floating gate with a pair of sharp tips. Since the erase efficiency of the device depends on the sharpness of the tips, the pair of sharp tips can improve the performance of the split gate flash memory. A method for forming a flash memory according to an embodiment of the present invention will be discussed in this disclosure.

1-9 are cross-sectional schematic diagrams illustrating various intermediate stages of an example method for forming the flash memory 10 of FIG. 9, according to some embodiments.

FIG. 1 illustrates initial steps of a method of forming a flash memory 10 according to an embodiment of the present invention. As shown in FIG. 1, a semiconductor substrate 100 is provided. The substrate 100 described above may be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (eg, using p-type or n-type) doped (dopant) or undoped. In general, a semiconductor-on-insulator substrate includes a layer of semiconductor material formed on an insulator. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide (silicon oxide) layer, or the like. The above-mentioned insulating layer is provided on a substrate, which is usually a silicon (silicon) or glass (glass) substrate. Other substrates may also be used, such as multi-layered or gradient substrates. In some embodiments, the semiconductor material of the semiconductor substrate may include elemental semiconductors containing silicon (Si) or germanium (Ge); including silicon carbide (silicon carbide), gallium arsenide (gallium arsenic), gallium phosphide ( Compound semiconductors of gallium phosphide, indium phosphide, indiumarsenide, or indium antimonide; including alloys of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP semiconductor; or a combination of the above.

In some embodiments, the semiconductor substrate 100 is a p-type silicon substrate. For example, the dopant of the p-type silicon substrate 100 may include boron, aluminum, gallium, indium, other suitable dopants, or a combination thereof, and the p-type silicon substrate The dopant concentration of 100 can be 5x1014 to 5x1016 cm ^-3 . In other embodiments, the semiconductor substrate 100 may be an n-type silicon substrate. For example, the dopant of the n-type silicon substrate 100 may include arsenic, phosphorus, antimony, other suitable dopants, or a combination thereof, and the dopant concentration of the n-type silicon substrate 100 may be 5x1014 to 5x1016cm ^-3 . The following embodiments will be described by using the p-type silicon substrate 100 as an example, but the present invention is not limited thereto.

Next, as shown in FIG. 2 , a mask layer 102 is formed on the semiconductor substrate 100 , and openings 104 are formed in the mask layer 102 . As shown in FIG. 2, a portion of the semiconductor substrate 100 is exposed through the opening 104, and the opening 104 is formed to define the position of the floating gate structure to be formed later.

In some embodiments, the mask layer 102 may include a nitride, such as silicon nitride, silicon oxynitride, other suitable materials, or a combination thereof. For example, it can be formed by a low-pressure chemical vapor deposition (LPCVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, other suitable processes, or a combination thereof. A mask layer 102 is formed. For example, the thickness of the mask layer 102 may be 0.1 micrometer to 1 micrometer, but not limited thereto.

In some embodiments, the openings 104 may be formed in the mask layer 102 by a patterning process. For example, the patterning process described above may include a photolithography process (eg, photoresist coating, soft bake, mask aligning, exposure, post exposure bake, photoresist development) , other suitable processes, or combinations of the above), etching processes (eg, wet etch processes, dry etch processes, other suitable processes, or combinations of the above), other suitable processes, or combinations of the above. In some embodiments, a patterned photoresist layer (not shown) having openings corresponding to the openings 104 may be formed on the mask layer 102 by a photolithography process, and then an etching process may be performed to remove the patterning A portion of the mask layer 102 exposed by the opening of the photoresist layer to form an opening 104 in the mask layer 102 .

FIG. 3 illustrates the formation of the first dielectric layer 106 . The first dielectric layer 106 is conformally formed over the mask layer 102 , so that the first dielectric layer 106 is along opposite sidewalls and bottom surfaces of the opening 104 . In subsequent processes, the first dielectric layer 106 on the bottom surface of the opening 104 will serve as the floating gate dielectric layer 110c, and the first dielectric layer 106 on the opposite sidewalls of the opening 104 will serve as a part of the dielectric spacer Objects 110a and 110b (not shown in FIG. 3, but can refer to the description of FIG. 5 below).

In some embodiments, the first dielectric layer 106 may be silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material, or any other suitable dielectric material, or the above combination. The high dielectric constant (high-k) dielectric material can be metal oxide, metal nitride, metal silicide, transition metal oxide, transition metal nitride, transition metal silicide, metal oxynitride, Metal aluminates, zirconium silicates, zirconium aluminates. For example, the high-k dielectric material can be LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3(STO), BaTiO3(BTO), BaZrO, HfO2, HfO3, HfZrO, HfLaO , HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba,Sr)TiO3(BST), Al2O3, other high dielectric constant dielectric materials of other suitable materials, or combinations thereof. In some embodiments, a chemical vapor deposition process (eg, a plasma-enhanced chemical vapor deposition (PECVD) process, or a metalorganic chemical vapor deposition (MOCVD) process), The first dielectric layer 106 is formed by an atomic layer deposition (ALD) process (eg, a plasma enhanced atomic layer deposition (PEALD) process), other suitable processes, or a combination thereof.

至300埃，但本发明实施例并不限于此。In some embodiments, the thickness of the first dielectric layer 106 may be

to 300 angstroms, but the embodiment of the present invention is not limited thereto.

Next, as shown in FIG. 4 , a second dielectric layer 108 is formed on the first dielectric layer 106 , wherein the second dielectric layer 108 overfills the opening 104 . A portion of the second dielectric layer 108 will be used as a portion of the dielectric spacers 110a and 110b in the subsequent process (not shown in FIG. 4 , but please refer to the description of FIG. 5 below). The material used to form the second dielectric layer 108 may be similar to the material used to form the first dielectric layer 106 , and thus will not be repeated here. In some embodiments, the second dielectric layer 108 and the first dielectric layer 106 may be formed of the same material. In other embodiments, the second dielectric layer 108 and the first dielectric layer 106 may be formed of different materials.

In some embodiments, a chemical vapor deposition process (eg, a plasma-enhanced chemical vapor deposition (PECVD) process, or a metalorganic chemical vapor deposition (MOCVD) process), Atomic layer deposition (ALD) process (eg, plasma enhanced atomic layer deposition (PEALD) process), spin-on-glass (SOG) process, other suitable process, or The above-mentioned combination forms the first dielectric layer 106 .

5 illustrates the formation of a floating gate dielectric layer 110c and a pair of dielectric spacers 110a and 110b. In some embodiments, an anisotropic etching back process is performed on the first dielectric layer 106 and the second dielectric layer 108 to remove part of the first dielectric layer 106 and the second dielectric layer 108 . As shown in FIG. 5 , after the anisotropic etch back process, the first dielectric layer 106 on the bottom surface of the opening 104 serves as the floating gate dielectric layer 110 c , and the first dielectric layer 106 on the opposite sidewalls of the opening 104 serves as the floating gate dielectric layer 110 c Layer 106 and the remaining second dielectric layer 108 serve as the above-described dielectric spacers 110a and 110b.

In the subsequent process, the above-mentioned dielectric spacers 110a and 110b will be used to create the floating gate 120 having a pair of tips 120a and 120b (not shown in FIG. 5, but please refer to the description of FIG. 6 below), The pair of tips 120a and 120b are located above the dielectric spacers 110a and 110b, respectively.

As shown in FIG. 5, in some embodiments, after the anisotropic etch back process, the dielectric spacers 110a may have sloped sidewalls 110a', and the dielectric spacers 110b may have slopes toward the sloped sidewalls 110a' side wall 110b'. The above-described pair of sloping side walls 110a' and 110b' has the benefit of increasing the sharpness of the tips 120a and 120b (see Fig. 6).

In some embodiments, after the anisotropic etch back process, the pair of dielectric spacers 110 a and 110 b may have the same height as the mask layer 102 , as shown in FIG. 5 . In other words, the topmost portion of the pair of dielectric spacers 110a and 110b is at the same level as the top surface of the mask layer 102, which also helps to improve the sharpness of the tips 120a and 120b (refer to FIG. 6).

In some embodiments, the above-mentioned anisotropic etching process may be a dry etching process, such as a plasma etching process, a reactive ion etching process, other suitable processes, or a combination thereof.

FIG. 6 illustrates the formation of the floating gate 120 . In some embodiments, floating gate 120 is formed to fill opening 104, wherein floating gate 120 is disposed on floating gate dielectric layer 110c and between dielectric spacers 110a and 110b. The floating gate 120 , the dielectric spacers 110 a and 110 b, and the floating gate dielectric layer 110 c together constitute the floating gate structure 200 . In addition, as shown in FIG. 6, the floating gate 120 has a pair of tips 120a and 120b located on the inclined sidewalls 110a' and 110b' of the dielectric spacers 110a and 110b, respectively. The tips 120a and 120b of the floating gate 120 can increase the current flow between the floating gate 120 and the control gate to be formed in a subsequent process, thereby improving the performance of the flash memory (eg, shortening the erase time).

In some embodiments, the material of the floating gate 120 includes poly-silicon. In other embodiments, the material of the floating gate 120 may include metals (eg, tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum) (platinum, similar materials, or combinations of the above), metal alloys, metal nitrides (eg, tungsten nitride, molybdenum nitride, titanium nitride, tantalum nitride) Nitride, similar materials, or a combination of the foregoing), metal silicides (eg, tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide) silicide), erbium silicide (erbium silicide, similar materials, or a combination of the above), metal oxides (eg, ruthenium oxide, indium tin oxide, similar materials, or a combination of the above), other Appropriate materials, or a combination of the above.

For example, chemical vapor deposition (eg, low pressure chemical vapor deposition (LPCVD) process, plasma enhanced chemical vapor deposition (PECVD) process), physical vapor deposition (PVD) process (eg, vacuum evaporation) (vacuum evaporation process, or sputtering process), other suitable processes, or a combination of the above to form the floating gate 120 . In some embodiments, the material of the floating gate 120 may be formed to overfill the opening 104 and then subjected to an etch back or planarization process (eg, a chemical-mechanical-polishing (CMP) process) To remove excess portion of the material of the floating gate 120 outside the opening 104 to form the floating gate 120 in the opening 104 .

In some embodiments, as shown in FIG. 6 , the floating gate 120 may have a flat top surface 120s. After the planarization process or the etch-back process, the planar top surface 120s is flush with the topmost portions of the above-described dielectric spacers 110a and 110b. In some embodiments, as shown in FIG. 6 , the floating gate 120 and the dielectric spacers 110 a and 110 b together form a rectangular shape in the schematic cross-sectional view.

Next, as shown in FIG. 7, an etching process (eg, wet etching, dry etching process, other suitable processes, or a combination of the above) is performed to selectively remove the mask layer 102 from the semiconductor substrate 100, while etching After the process, the floating gate structure 200 remains on the semiconductor substrate 100 .

As shown in FIG. 7, each of the dielectric spacers 110a and 110b may have a bottom width W1, and the floating gate structure 200 may have a bottom width W2, where W2 is greater than W1. When W1 is smaller, since the tips 120a and 120b are sharper, the erasing efficiency of the device is better.

Next, as shown in FIG. 8 , an inter-gate dielectric layer 220 is conformally formed on the semiconductor substrate 100 and the floating gate structure 200 . In some embodiments, the inter-gate dielectric layer 220 , the dielectric spacers 110 a and 110 b , and the floating gate dielectric layer 110 c completely encapsulate the floating gate 120 .

In the illustrated embodiment, the inter-gate dielectric layer 220 may include silicon oxide. The above silicon oxide may be formed by an oxidation process, a chemical vapor deposition process, other suitable processes, or a combination thereof. For example, the above oxidation process may include a dry oxidation process (eg, Si+O2→SiO2), a wet oxidation process (eg, Si+2H2O→SiO2+2H2), or a combination thereof.

In other embodiments, the inter-gate dielectric layer 220 may include a high-k dielectric material. The high-k dielectric material may include LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3(STO), BaTiO3(BTO), BaZrO, HfO2, HfO3, HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba,Sr)TiO3(BST), Al2O3, other high dielectric constant dielectric materials of other suitable materials, or combinations thereof. For example, chemical vapor deposition (eg, plasma-enhanced chemical vapor deposition (PECVD) processes, or metal-organic chemical vapor deposition (MOCVD) processes), atomic layer deposition (ALD) processes (eg, plasma-enhanced atomic layer deposition (PEALD) process), physical vapor deposition process (eg, vacuum evaporation process, or sputtering process), other suitable processes, or a combination of the above to form the high-k dielectric material .

In some embodiments, the thickness of the inter-gate dielectric layer 220 may be 50 angstroms to 250 angstroms, but the embodiments of the present invention are not limited thereto.

FIG. 9 illustrates the formation of the control gate 300 . In some embodiments, the control gate 300 is formed on the inter-gate dielectric layer 220 . More specifically, as shown in FIG. 9, the control gate 300 covers the dielectric spacer 110a, and the control gate 300 does not cover the dielectric spacer 110b. It should be noted that the control gate 300 is separated from the floating gate structure 200 by the inter-gate dielectric layer 220 . In the illustrated embodiment, the control gate 300 includes polysilicon. In other embodiments, the material of the control gate 300 may include metals (eg, tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum) (platinum, similar materials, or combinations of the above), metal alloys, metal nitrides (eg, tungsten nitride, molybdenum nitride, titanium nitride, tantalum nitride) Nitride, similar materials, or a combination of the foregoing), metal silicides (eg, tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide) silicide), erbium silicide (erbium silicide, similar materials, or a combination of the above), metal oxides (eg, ruthenium oxide, indium tin oxide, similar materials, or a combination of the above), other Appropriate materials, or a combination of the above.

In some embodiments, the control gate 300 may be formed by a deposition process followed by a patterning process. The above-mentioned deposition processes may include chemical vapor deposition processes (eg, low pressure chemical vapor deposition (LPCVD) processes, or plasma enhanced chemical vapor deposition (PECVD) processes), physical vapor deposition processes (eg, vacuum evaporation processes, sputtering processes), other appropriate process, or a combination of the above. The above-mentioned patterning process may include an etching process.

FIG. 9 also illustrates the formation of a pair of source/drain regions 400 . In some embodiments, the above-described source/drain regions 400 are formed by implanting ions into the semiconductor substrate 100 . The floating gate structure 200 and the control gate 300 are located between the pair of source/drain regions 400 .

In the present embodiment, the semiconductor substrate 100 is a p-type substrate, and the source/drain regions 400 are formed by implanting n-type dopants, such as phosphorous (P) or arsenic (arsenic,) into the semiconductor substrate 100 . As). In other embodiments, the semiconductor substrate 100 is an n-type substrate, and the source/drain regions 400 are formed by implanting p-type dopants, such as boron (B), into the semiconductor substrate 100 . The conductivity type of the semiconductor substrate 100 is opposite to that of the source/drain regions 400 .

As shown in FIG. 9 , the flash memory 10 includes a semiconductor substrate 100 , a floating gate structure 200 on the semiconductor substrate 100 , an inter-gate dielectric layer 220 covering sidewalls and a top surface of the floating gate structure 200 , and an inter-gate dielectric layer 220 on the semiconductor substrate 100 . Control gate 300 on inter-gate dielectric layer 220 . The above floating gate structure 200 includes a floating gate dielectric layer 110c on the semiconductor substrate 100, a pair of dielectric spacers 110a and 110b on the floating gate dielectric layer 110c, wherein the pair of dielectric spacers 110a and 110b 110b has sloped sidewalls 110a' and 110b' facing each other, and a floating gate 120 on floating gate dielectric layer 110c between the pair of dielectric spacers 110a and 110b. The floating gate 120 described above has a pair of tips 120a and 120b located on the inclined sidewalls 110a' and 110b' of the dielectric spacers 110a and 110b, respectively. The erasing efficiency of the device depends on how sharp the tips 120a and 120b are. The sloped sidewalls 110a' and 110b' described above have the benefit of increasing the sharpness of the tips 120a and 120b, thereby improving the performance of the flash memory 10.

In some embodiments, the topmost portion of the pair of dielectric spacers 110a and 110b is at the same level as the top surface of the mask layer 102, which also helps to improve the sharpness of the tips 120a and 120b, thereby further increasing the flash memory 10 performance.

FIGS. 10 and 11 are schematic cross-sectional views illustrating various intermediate stages of another example method for forming the flash memory 20 of FIG. 11 , according to some embodiments. For the sake of clarity, similar or identical elements and processes will use the same reference numerals. For the sake of brevity, the descriptions of these processes and apparatus are not repeated here.

Flash memory 20 is similar to flash memory 10 except that an additional oxide structure 140 is formed to further sharpen the tip of the floating gate. As such, the floating gate 120' has the recessed top surface 120s', and the tips 120a' and 120b' of the floating gate 120' of the flash memory 20 are smaller than those of the floating gate 120 of the flash memory 10 of FIG. The tips 120a and 120b are sharper.

10, after forming the floating gate 120 as described in FIG. 6, before removing the mask layer 102, an oxide structure 140 is formed on the top surface of the floating gate 120'. As shown in FIG. 10 , in some embodiments, an oxidation process is performed on the floating gate 120 to form the floating gate 120 ′ and the oxide structure 140 on the floating gate 120 ′, wherein the floating gate 120 ′ has a recess The top surface 120s' of the floating gate 120' is at the same level as the tops of the above-mentioned dielectric spacers 110a and 110b. The tips 120a' and 120b' of the floating gate 120' are sharper than the tips 120a and 120b of the flash memory 10 in FIG. Best erasing efficiency.

Next, the mask layer 102 is removed, and a series of processes similar to those described in FIGS. 7 to 9 are performed on the structure shown in FIG. 10 to complete the flash memory 20 as shown in FIG. 11 .

As shown in FIG. 11 , the flash memory 20 includes a semiconductor substrate 100 , a floating gate structure 200 ′ on the semiconductor substrate 100 , an inter-gate dielectric layer 220 covering sidewalls and a top surface of the floating gate structure 200 ′, and the control gate 300 on the inter-gate dielectric layer 220 . The above floating gate structure 200' includes a floating gate dielectric layer 110c on the semiconductor substrate 100, a pair of dielectric spacers 110a and 110b on the floating gate dielectric layer 110c, wherein the pair of dielectric spacers 110a and 110b have sloped sidewalls 110a' and 110b' facing each other, and a floating gate 120' on the floating gate dielectric layer 110c and between the pair of dielectric spacers 110a and 110b. The floating gate 120' has a pair of tips 120a' and 120b' located on the inclined sidewalls 110a' and 110b' of the dielectric spacers 110a and 110b, respectively. The sloping sidewalls 110a' and 110b' described above have the benefit of increasing the sharpness of the tips 120a' and 120b', thereby improving the performance of the flash memory 20 .

In some embodiments, the topmost portion of the pair of dielectric spacers 110a and 110b is at the same level as the top surface of the mask layer 102, which also helps to improve the sharpness of the tips 120a' and 120b', thereby further improving the speed Flash memory 20 performance.

In some embodiments, the above floating gate structure 200' further includes an oxide structure 140 between the floating gate 120' and the inter-gate dielectric layer 220. In this embodiment, the floating gate 120' has a recessed top surface 120s', which can further sharpen the tips 120a' and 120b'. In this embodiment, the topmost portion of the floating gate 120' is at the same level as the topmost portion of the dielectric spacers 110a and 110b described above. In this way, the erasing efficiency of the flash memory 20 can be further improved.

In summary, the flash memory device of the embodiments of the present invention includes a pair of dielectric spacers, and the pair of dielectric spacers is used to create a floating gate with a pair of sharp tips. The pair of sharp tips can increase the current between the floating gate and the control gate, thereby improving the performance of the flash memory (eg, shortening the erase time).

The features of several embodiments of the present invention have been briefly described above, so that those skilled in the art can more easily understand the present invention. Those skilled in the art should appreciate that this description can easily be used as a basis for modification or design of other structures or processes to achieve the same purpose and/or obtain the same advantages of the embodiments of the present invention. Any person skilled in the art can also understand that the structures or processes equivalent to the above do not depart from the spirit and protection scope of the present invention, and can be changed, replaced and modified without departing from the spirit and scope of the present invention. .

Claims (20)

1. a flash memory, is characterized in that, comprises: a semiconductor substrate; A floating gate structure on the semiconductor substrate, the floating gate structure includes: a floating gate dielectric layer on the semiconductor substrate; a pair of dielectric spacers on the floating gate dielectric layer, wherein the pair of dielectric spacers have sloped sidewalls facing each other; and a floating gate on the floating gate dielectric layer and between the pair of dielectric spacers, wherein the floating gate has a pair of apexes, the pair of apexes are respectively located at the inclination of the pair of dielectric spacers on the side wall; an inter-gate dielectric layer covering the sidewalls and the top surface of the floating gate structure; and a control gate on the inter-gate dielectric layer. 2. The flash memory of claim 1, wherein the floating gate has a flat top surface. 3 . The flash memory of claim 2 , wherein a top surface of the floating gate and a topmost portion of the pair of dielectric spacers are at the same level. 4 . 4 . The flash memory of claim 2 , wherein the floating gate and the pair of dielectric spacers together form a rectangular shape in a schematic cross-sectional view. 5 . 5. The flash memory of claim 1, wherein the floating gate structure further comprises an oxide structure between the floating gate and the inter-gate dielectric layer. 6. The flash memory of claim 5, wherein the floating gate has a recessed top surface. 7 . The flash memory of claim 5 , wherein the topmost position of the floating gate and the topmost position of the pair of dielectric spacers are at the same level. 8 . 8. The flash memory of claim 1, wherein the floating gate and the control gate comprise polysilicon. 9. The flash memory of claim 1, wherein the inter-gate dielectric layer, the pair of dielectric spacers, and the floating gate dielectric layer completely cover the floating gate. 10. A method for forming a flash memory, comprising: providing a semiconductor substrate; forming a mask layer on the semiconductor substrate, wherein the mask layer has an opening, and the opening exposes a part of the semiconductor substrate; A floating gate structure is formed in the opening, and the steps of forming the floating gate structure include: forming a floating gate dielectric layer on the semiconductor substrate, and forming a pair of dielectric spacers on opposite sidewalls of the opening and on the floating gate dielectric layer; and A floating gate is formed in the opening, wherein the floating gate is disposed on the floating gate dielectric layer, and the floating gate is located between the pair of dielectric spacers, and wherein the floating gate has a pair of a tip, the pair of tips are respectively located on the pair of dielectric spacers; remove the mask layer; forming an inter-gate dielectric layer overlying the floating gate structure; and A control gate is formed on the inter-gate dielectric layer. 11. The method of claim 10, wherein the step of forming the floating gate dielectric layer and the pair of dielectric spacers comprises: conformably forming a first dielectric layer along opposite sidewalls and bottom surfaces of the opening; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer overfills the opening; and An anisotropic etch-back process is performed on the first dielectric layer and the second dielectric layer. After the anisotropic etch-back process, the first dielectric layer on the bottom surface of the opening serves as the floating A gate dielectric layer, and the first dielectric layer and the remaining second dielectric layer on opposite sidewalls of the opening serve as the pair of dielectric spacers. 12 . The method of claim 10 , wherein the topmost portion of the pair of dielectric spacers is at the same level as the top surface of the mask layer. 13 . 13. The method of forming a flash memory as claimed in claim 10, wherein the pair of dielectric spacers have inclined sidewalls facing each other. 14. The method of claim 10, wherein the floating gate has a flat top surface. 15 . The method of claim 14 , wherein the topmost position of the floating gate and the topmost position of the pair of dielectric spacers are at the same level. 16 . 16. The method for forming a flash memory as claimed in claim 10, wherein the step of forming the floating gate structure further comprises performing an oxidation process on the floating gate, so as to form the floating gate and the gate An oxide structure is formed between the inter-dielectric layers. 17. The method of claim 16, wherein the floating gate has a recessed top surface. 18. The method for forming a flash memory as claimed in claim 10, wherein the mask layer comprises nitride. 19. The method of claim 10, wherein the floating gate and the control gate comprise polysilicon. 20. The method of claim 10, wherein the inter-gate dielectric layer, the pair of dielectric spacers, and the floating gate dielectric layer completely cover the floating gate pole.

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