TW202029473A - Flash memories and methods for forming the same - Google Patents

Abstract

A flash memory is provided. The flash memory includes a semiconductor substrate, a floating gate structure on the semiconductor substrate, an inter-gate dielectric layer covering sidewalls and a top surface of the floating gate structure, and a control gate on the inter-gate dielectric layer. The floating gate structure includes a floating gate dielectric layer on the semiconductor substrate, a pair of dielectric spacers on the floating gate dielectric layer, wherein the pair of dielectric spacers have sloped sidewalls that face each other, and a floating gate on the floating gate dielectric layer and between the pair of dielectric spacers. The floating gate has a pair of tips over the respective sloped sidewalls of the pair of dielectric spacers.

Description

Flash memory and its forming method

The embodiments of the present invention are related to semiconductor manufacturing technology, in particular to flash memory and its forming method.

Flash memory is a type of non-volatile memory. Generally speaking, a flash memory contains two gates. The first gate stores the data floating gate (floating gate), and the second gate carries out the data input and output control gate. gate). The floating gate is located below the control gate and is in a "floating" state. The so-called floating refers to the use of insulating materials to surround and isolate the floating gate to prevent charge loss. The control gate is connected to a word line (WL) to control the device. One of the advantages of flash memory is that it can block-by-block erasing. Flash memory is widely used in corporate servers, storage and network technology, as well as a wide range of consumer electronics products, such as personal storage devices such as flash drives, mobile phones, digital cameras, tablets, and laptops PC cards and embedded controllers, etc.

Many different types of non-volatile memory are available on the market, such as flash memory, electronically erasable programmable read-only memory (EEPROM) and multi-time programmable, MTP) non-volatile memory. However, embedded flash memory, especially embedded split-gate flash memory, has a greater advantage than other non-volatile memory technologies.

Although the existing flash memory and its manufacturing method are sufficient for their original intended use, they are still not satisfactory in all aspects. Therefore, the flash memory technology still has problems to be overcome.

The embodiment of the present invention provides a flash memory. The flash memory includes a semiconductor substrate, a floating gate structure located on the semiconductor substrate, an inter-gate dielectric layer covering the sidewall and top surface of the floating gate structure, and a control located on the inter-gate dielectric layer Gate. The above-mentioned floating gate structure includes a floating gate dielectric layer on the semiconductor substrate, a pair of dielectric spacers on the floating gate dielectric layer, wherein the pair of dielectric spacers have inclined sidewalls facing each other , And a floating gate located on the floating gate dielectric layer and between the pair of dielectric spacers. The above-mentioned floating gate has a pair of tips, and the pair of tips are respectively located on the inclined sidewall of the dielectric spacer.

The embodiment of the present invention provides a method for forming a flash memory. The method includes providing a semiconductor substrate, forming a mask layer on the semiconductor substrate, wherein the mask layer has an opening that exposes a part of the semiconductor substrate, forming a floating gate structure in the opening, removing the mask layer, and forming a cover floating The inter-gate dielectric layer of the gate structure and the control gate are formed on the inter-gate dielectric layer. The step of forming a floating gate structure includes forming a floating gate dielectric layer on a semiconductor substrate, and forming a pair of dielectric spacers on opposite sidewalls of the opening and on the floating gate dielectric layer, and A floating gate is formed in the opening, wherein the floating gate is disposed on the floating gate dielectric layer, and the floating gate is located between the pair of dielectric spacers, and the floating gate has a pair of tips, The pair of tips are respectively located on the dielectric spacer.

The following embodiments and accompanying reference drawings will provide a detailed description.

The following disclosure provides many different embodiments or examples to illustrate different components of the embodiments of the present invention. The following will disclose specific examples of the components and their arrangement in this specification to simplify the description of this disclosure. Of course, these specific examples are not used to limit the disclosure. For example, if the following invention content of this specification describes that the first part is formed on or above the second part, it means that it includes an embodiment in which the formed first and second parts are in direct contact, and also includes Additional components can be formed between the above-mentioned first and second components, and the first and second components are embodiments that are not in direct contact. In addition, the various examples in this disclosure may use repeated reference symbols and/or words. The purpose of these repeated symbols or words is for simplification and clarity, and is not used to limit the relationship between the various embodiments and/or the configurations.

Furthermore, in order to facilitate the description of the relationship between one element or component and another element or component(s) in the diagram, spatial relative terms can be used, such as "below", "below", "lower", "above" , "Upper" and the like. In addition to the orientation shown in the diagram, the relative terms of space also cover different orientations of the device in use or operation. When the device is turned in different directions (for example, rotated by 90 degrees or other directions), the spatially relative adjectives used therein will also be interpreted according to the turned position. It should be understood that additional operations may be provided before, during, and/or after the method described in the embodiments of the present invention, and in other embodiments of the method, some of the operations may be replaced or omitted.

Here, the terms "about", "approximately", and "approximately" usually mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3 Within %, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantity provided in the manual is an approximate quantity, that is, without specific description of "about", "approximately", "approximately", "about", "approximately" and "approximately" can still be implied. "Roughly" means.

Some changes to the example method and structure are described here. Those with ordinary knowledge in the art will easily understand that other modifications can be made within the scope of other embodiments. Although some of the method embodiments discussed are performed in a specific order, various other method embodiments can be performed in another logical order, and may include fewer or more steps than those discussed herein. In some figures, the symbol of some components or parts shown therein may be omitted to avoid confusion with other components or parts; this is for the convenience of depicting these figures.

The embodiment of the present invention provides a flash memory and a forming method thereof, particularly an embedded split gate flash memory. In some embodiments of the invention, a pair of dielectric spacers are used to create a floating gate with a pair of sharp tips. Since the erase efficiency of the device depends on the sharpness of the tip, the pair of sharp tips can improve the performance of the split gate flash memory. In the present invention, a method for forming a flash memory according to an embodiment of the present invention will be discussed.

FIGS. 1-9 are schematic cross-sectional diagrams illustrating various intermediate stages of an exemplary method for forming the flash memory 10 of FIG. 9 according to some embodiments.

FIG. 1 illustrates the initial steps of a method of forming a flash memory 10 according to an embodiment of the present invention. As shown in FIG. 1, a semiconductor substrate 100 is provided. The above-mentioned substrate 100 may be or include a bulk semiconductor (bulk semiconductor) substrate, a semiconductor-on-insulator (SOI) substrate or the like, which may be doped (for example, using p-type or n-type Dopant (dopant)) or undoped. Generally speaking, the semiconductor-on-insulator substrate includes a film layer of semiconductor material formed on the insulator. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide (silicon oxide) layer, or the like. The above-mentioned insulating layer is provided on a substrate, which is usually a silicon or glass substrate. Other substrates, such as multi-layered or gradient substrates, can also be used. In some embodiments, the semiconductor material of the semiconductor substrate may include elemental semiconductors containing silicon (Si) or germanium (Ge); including silicon carbide, gallium arsenic, and gallium phosphide. (gallium phosphide), indium phosphide (indium phosphide), indium arsenide (indium arsenide) or indium antimonide (indium antimonide) compound semiconductor; including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP The alloy semiconductor; or a combination of the above.

In some embodiments, the semiconductor substrate 100 is a p-type silicon substrate. For example, the dopants of the p-type silicon substrate 100 may include boron, aluminum, gallium, indium, other appropriate dopants, or a combination of the above, and the p-type silicon substrate The dopant concentration of 100 can be 5x10 ¹⁴ to 5x10 ¹⁶ cm ^-3 . In other embodiments, the semiconductor substrate 100 may be an n-type silicon substrate. For example, the dopant of the n-type silicon substrate 100 may include arsenic, phosphorous, antimony, other appropriate dopants, or a combination of the above, and the dopant concentration of the n-type silicon substrate 100 may be It is 5x10 ¹⁴ to 5x10 ¹⁶ cm ^-3 . The following embodiments will use the p-type silicon substrate 100 as an example for description, but the invention is not limited to this.

Next, as shown in FIG. 2, a mask layer 102 is formed on the semiconductor substrate 100, and an opening 104 is formed in the mask layer 102. As shown in FIG. 2, a part of the semiconductor substrate 100 is exposed through the opening 104, and the opening 104 is formed to define the position of the floating gate structure to be formed later.

In some embodiments, the mask layer 102 may include nitride, such as silicon nitride, silicon oxynitride, other suitable materials, or a combination thereof. For example, a low-pressure chemical vapor deposition (LPCVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, other appropriate processes, or the above The combination of these forms the mask layer 102. For example, the thickness of the mask layer 102 may be 0.1 μm to 1 μm, but is not limited thereto.

In some embodiments, the opening 104 may be formed in the mask layer 102 by a patterning process. For example, the above-mentioned patterning process may include a photolithography process (e.g., photoresist coating, soft baking, mask aligning, exposure, post-exposure baking, photoresist development, etc. Appropriate process, or a combination of the foregoing), etching process (for example, wet etching process, dry etching process, other appropriate process, or combination of the foregoing), other appropriate process, or combination of the foregoing. In some embodiments, a patterned photoresist layer (not shown) having an opening corresponding to the opening 104 may be formed on the mask layer 102 by a photolithography process, and then an etching process may be performed to remove the patterned light. The part of the mask layer 102 exposed by the opening of the barrier layer forms an opening 104 in the mask layer 102.

FIG. 3 illustrates the formation of the first dielectric layer 106. The first dielectric layer 106 is formed on the mask layer 102 compliantly, so the first dielectric layer 106 is along the opposite sidewalls and bottom surface of the opening 104. In the subsequent process, the first dielectric layer 106 located on the bottom surface of the opening 104 will serve as the floating gate dielectric layer 110c, and the first dielectric layer 106 located on the opposite sidewall of the opening 104 will serve as a part of the dielectric spacer Objects 110a and 110b (not shown in Figure 3, but refer to the description of Figure 5 below).

In some embodiments, the first dielectric layer 106 may be silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material, or any other suitable dielectric material, or the above combination. The material of this high-k dielectric material can be metal oxide, metal nitride, metal silicide, transition metal oxide, transition metal nitride, transition metal silicide, metal oxynitride, Metal aluminate, zirconium silicate, zirconium aluminate. For example, the high-k dielectric material can be LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, HfO ₂ , HfO ₃ , HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba,Sr)TiO ₃ (BST), Al ₂ O ₃ , other suitable materials and other high dielectric materials Constant dielectric material, or a combination of the above. In some embodiments, a chemical vapor deposition process (for example, plasma-enhanced chemical vapor deposition (PECVD) process, or metalorganic chemical vapor deposition (MOCVD) ) Process), atomic layer deposition (ALD) process (for example, plasma enhanced atomic layer deposition (PEALD) process), other appropriate processes, or a combination of the above to form the first dielectric Electric layer 106.

In some embodiments, the thickness of the first dielectric layer 106 may be 50 angstroms (Å) to 300 angstroms, but the embodiment of the present invention is not limited thereto.

Next, as shown in FIG. 4, a second dielectric layer 108 is formed on the first dielectric layer 106, wherein the second dielectric layer 108 overfills the opening 104. Part of the second dielectric layer 108 will be part of the dielectric spacers 110a and 110b in the subsequent process (not shown in FIG. 4, but please refer to the description of FIG. 5 below). The material used to form the second dielectric layer 108 may be similar to the material used to form the first dielectric layer 106, so it will not be repeated here. In some embodiments, the second dielectric layer 108 and the first dielectric layer 106 may be formed of the same material. In other embodiments, the second dielectric layer 108 and the first dielectric layer 106 may be formed of different materials.

In some embodiments, a chemical vapor deposition process (for example, plasma-enhanced chemical vapor deposition (PECVD) process, or metalorganic chemical vapor deposition (MOCVD) ) Process), atomic layer deposition (ALD) process (for example, plasma enhanced atomic layer deposition (PEALD) process), spin-on-glass (SOG) process , Other appropriate processes, or a combination of the above to form the first dielectric layer 106.

FIG. 5 illustrates the formation of a floating gate dielectric layer 110c and a pair of dielectric spacers 110a and 110b. In some embodiments, an anisotropic etching back process is performed on the first dielectric layer 106 and the second dielectric layer 108 to remove part of the first dielectric layer 106 and the second dielectric layer 108. As shown in Figure 5, after the anisotropic etch-back process, the first dielectric layer 106 located on the bottom surface of the opening 104 serves as the floating gate dielectric layer 110c, and the first dielectric layer located on the opposite sidewall of the opening 104 The electrical layer 106 and the remaining second dielectric layer 108 serve as the aforementioned dielectric spacers 110a and 110b.

In the subsequent process, the above-mentioned dielectric spacers 110a and 110b will be used to create a floating gate 120 with a pair of tips 120a and 120b (not shown in Figure 5, but refer to the following about Figure 6 Explanation), where the pair of tips 120a and 120b are respectively located on the dielectric spacers 110a and 110b.

As shown in FIG. 5, in some embodiments, after the anisotropic etch-back process, the dielectric spacer 110a may have inclined sidewalls 110a', and the dielectric spacer 110b may have inclined sidewalls facing the inclined sidewalls 110a' 110b'. The above-mentioned pair of inclined side walls 110a' and 110b' have the advantage of increasing the sharpness of the tips 120a and 120b (refer to Fig. 6).

In some embodiments, after the anisotropic etch-back process, the pair of dielectric spacers 110a and 110b may have the same height as the mask layer 102, as shown in FIG. 5. In other words, the top of the pair of dielectric spacers 110a and 110b are at the same level as the top surface of the mask layer 102, which also helps to improve the sharpness of the tips 120a and 120b (refer to FIG. 6).

In some embodiments, the anisotropic etch-back process may be a dry etching process, such as a plasma etching process, a reactive ion etching process, other appropriate processes, or a combination of the foregoing .

FIG. 6 illustrates the formation of the floating gate 120. In some embodiments, a floating gate 120 is formed to fill the opening 104, wherein the floating gate 120 is disposed on the floating gate dielectric layer 110c and located between the dielectric spacers 110a and 110b. The above-mentioned floating gate 120, the dielectric spacers 110a and 110b, and the floating gate dielectric layer 110c together constitute the floating gate structure 200. In addition, as shown in FIG. 6, the floating gate 120 has a pair of tips 120a and 120b, and the pair of tips 120a and 120b are respectively located on the inclined sidewalls 110a' and 110b' of the dielectric spacers 110a and 110b. The tips 120a and 120b of the floating gate 120 can increase the current between the floating gate 120 and the control gate to be formed in a subsequent process, thereby improving the performance of the flash memory (for example, shortening the erasing time).

In some embodiments, the material of the floating gate 120 includes poly-silicon. In other embodiments, the material of the above-mentioned floating gate 120 may include metal (for example, tungsten, titanium, aluminum, copper, molybdenum, nickel, nickel, etc.). Platinum (platinum, similar materials, or a combination of the above), metal alloys, metal nitrides (for example, tungsten nitride, molybdenum nitride, titanium nitride, tantalum nitride) (tantalum nitride, similar materials, or a combination of the above), metal silicides (for example, tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide) (platinum silicide, erbium silicide, similar materials, or a combination of the above), metal oxides (for example, ruthenium oxide, indium tin oxide, similar materials, or a combination of the above) ), other appropriate materials, or a combination of the above.

For example, a chemical vapor deposition process (for example, a low pressure chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process), a physical vapor deposition (PVD) process can be used (For example, a vacuum evaporation process, or a sputtering process), other appropriate processes, or a combination of the foregoing, to form the floating gate 120. In some embodiments, the material of the floating gate 120 can be formed to overfill the opening 104, and then an etch back or planarization process (eg, chemical-mechanical-polishing, CMP) process is performed ) To remove the excess material of the floating gate 120 located outside the opening 104 to form the floating gate 120 in the opening 104.

In some embodiments, as shown in FIG. 6, the floating gate 120 may have a flat top surface 120s. After the planarization process or the etch-back process, the flat top surface 120s is flush with the top of the dielectric spacers 110a and 110b. In some embodiments, as shown in FIG. 6, the floating gate 120 and the dielectric spacers 110a and 110b jointly form a rectangular shape in the schematic cross-sectional view.

Next, as shown in FIG. 7, an etching process (eg, wet etching, dry etching, other suitable processes, or a combination of the above) is performed to selectively remove the mask layer 102 from the semiconductor substrate 100, and After the etching process, the floating gate structure 200 remains on the semiconductor substrate 100.

As shown in FIG. 7, each of the dielectric spacers 110a and 110b may have a bottom width W1, and the floating gate structure 200 may have a bottom width W2, where W2 is greater than W1. When W1 is smaller, since the tips 120a and 120b are sharper, the erasing efficiency of the device is better.

Next, as shown in FIG. 8, an inter-gate dielectric layer 220 is conformably formed on the semiconductor substrate 100 and the floating gate structure 200. In some embodiments, the inter-gate dielectric layer 220, the dielectric spacers 110a and 110b, and the floating gate dielectric layer 110c completely cover the floating gate 120.

In the illustrated embodiment, the inter-gate dielectric layer 220 may include silicon oxide. The silicon oxide can be formed by an oxidation process, a chemical vapor deposition process, other suitable processes, or a combination of the foregoing. For example, the foregoing oxidation process may include a dry oxidation process (for example: Si + O ₂ → SiO ₂ ), a wet oxidation process (for example: Si + 2H ₂ O → SiO ₂ + 2H ₂ ), or a combination of the foregoing.

In other embodiments, the inter-gate dielectric layer 220 may include a high-k dielectric material. This high dielectric constant dielectric material may include LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, HfO ₂ , HfO ₃ , HfZrO, HfLaO , HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba,Sr)TiO ₃ (BST), Al ₂ O ₃ , other suitable materials, other high-k dielectric materials, or a combination of the above. For example, a chemical vapor deposition process (for example, a plasma enhanced chemical vapor deposition (PECVD) process, or a metal organic chemical vapor deposition (MOCVD) process), an atomic layer deposition (ALD) process (for example, Plasma Enhanced Atomic Layer Deposition (PEALD) process), physical vapor deposition process (for example, vacuum evaporation process, or sputtering process), other appropriate processes, or a combination of the above to form this High dielectric constant dielectric material.

In some embodiments, the thickness of the inter-gate dielectric layer 220 may be 50 angstroms to 250 angstroms, but the embodiment of the present invention is not limited thereto.

FIG. 9 illustrates the formation of the control gate 300. In some embodiments, the control gate 300 is formed on the inter-gate dielectric layer 220. More specifically, as shown in FIG. 9, the control gate 300 covers the dielectric spacer 110a, and the control gate 300 does not cover the dielectric spacer 110b. It should be noted that the control gate 300 is separated from the floating gate structure 200 by the inter-gate dielectric layer 220. In the illustrated embodiment, the control gate 300 described above includes polysilicon. In other embodiments, the material of the aforementioned control gate 300 may include metals (for example, tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum). (platinum, similar materials, or a combination of the above), metal alloys, metal nitrides (for example, tungsten nitride, molybdenum nitride, titanium nitride, tantalum nitride ( tantalum nitride), similar materials, or a combination of the above), metal silicides (e.g., tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide) platinum silicide), erbium silicide (erbium silicide, similar materials, or combinations of the above), metal oxides (for example, ruthenium oxide, indium tin oxide, similar materials, or combinations of the above) , Other appropriate materials, or a combination of the above.

In some embodiments, the control gate 300 can be formed by a deposition process followed by a patterning process. The foregoing deposition process may include a chemical vapor deposition process (for example, a low pressure chemical vapor deposition (LPCVD) process, or a plasma enhanced chemical vapor deposition (PECVD) process), a physical vapor deposition process (for example, a vacuum evaporation process, Sputtering process), other appropriate processes, or a combination of the above. The patterning process described above may include an etching process.

FIG. 9 also illustrates the formation of a pair of source/drain regions 400. In some embodiments, the source/drain regions 400 are formed by implanting ions into the semiconductor substrate 100. The floating gate structure 200 and the control gate 300 are located between the pair of source/drain regions 400.

In this embodiment, the semiconductor substrate 100 is a p-type substrate, and the source/drain regions 400 are formed by implanting n-type dopants in the semiconductor substrate 100, such as phosphorous (P) or arsenic ( arsenic, As). In other embodiments, the semiconductor substrate 100 is an n-type substrate, and the source/drain regions 400 are formed by implanting p-type dopants in the semiconductor substrate 100, such as boron (B). The conductivity type of the semiconductor substrate 100 is opposite to the conductivity type of the source/drain regions 400.

As shown in FIG. 9, the flash memory 10 includes a semiconductor substrate 100, a floating gate structure 200 on the semiconductor substrate 100, and an inter-gate dielectric layer 220 covering the sidewall and top surface of the floating gate structure 200 , And the control gate 300 on the inter-gate dielectric layer 220. The above-mentioned floating gate structure 200 includes a floating gate dielectric layer 110c on the semiconductor substrate 100, a pair of dielectric spacers 110a and 110b on the floating gate dielectric layer 110c, wherein the pair of dielectric spacers The objects 110a and 110b have inclined sidewalls 110a' and 110b' facing each other, and a floating gate 120 located on the floating gate dielectric layer 110c and between the pair of dielectric spacers 110a and 110b. The floating gate 120 has a pair of tips 120a and 120b, and the pair of tips 120a and 120b are respectively located on the inclined sidewalls 110a' and 110b' of the dielectric spacers 110a and 110b. The erasing efficiency of the device depends on the sharpness of the tips 120a and 120b. The above-mentioned inclined sidewalls 110a' and 110b' have the advantage of increasing the sharpness of the tips 120a and 120b, thereby improving the performance of the flash memory 10.

In some embodiments, the top of the pair of dielectric spacers 110a and 110b is at the same level as the top surface of the mask layer 102, which also helps to increase the sharpness of the tips 120a and 120b, thereby further increasing the flash memory The performance of the body 10.

FIGS. 10 and 11 are schematic cross-sectional diagrams illustrating the intermediate stages of another exemplary method for forming the flash memory 20 in FIG. 11 according to some embodiments. For the sake of clarity, similar or identical components and processes will use the same reference symbols. For the sake of brevity, the description of these processes and devices will not be repeated here.

The flash memory 20 is similar to the flash memory 10 except that an additional oxide structure 140 is formed to further sharpen the tip of the floating gate. In this way, the floating gate 120' has a recessed top surface 120s', and the tips 120a' and 120b' of the floating gate 120' of the flash memory 20 are compared with those of the flash memory 10 in FIG. 9 The tips 120a and 120b of the floating gate 120 are sharper.

Referring to FIG. 10, after forming the floating gate 120 as described in FIG. 6, before removing the mask layer 102, an oxide structure 140 is formed on the top surface of the floating gate 120'. As shown in FIG. 10, in some embodiments, the floating gate 120 is subjected to an oxidation process to form a floating gate 120' and an oxide structure 140 on the floating gate 120', wherein the floating gate 120' The pole 120' has a recessed top surface 120s', and the top of the floating gate 120' is at the same level as the top of the above-mentioned dielectric spacers 110a and 110b. The tips 120a' and 120b' of the floating gate 120' are sharper than the tips 120a and 120b of the flash memory 10 in FIG. 9. Therefore, the flash memory 20 formed in the subsequent process is compared with the flash The memory 10 has better erasing efficiency.

Next, the mask layer 102 is removed, and a series of processes similar to the processes described in FIGS. 7-9 are performed on the structure shown in FIG. 10 to complete the flash memory shown in FIG. 11 20.

As shown in FIG. 11, the flash memory 20 includes a semiconductor substrate 100, a floating gate structure 200' on the semiconductor substrate 100, and an inter-gate dielectric covering the sidewall and top surface of the floating gate structure 200' The layer 220 and the control gate 300 located on the inter-gate dielectric layer 220. The above-mentioned floating gate structure 200' includes a floating gate dielectric layer 110c on the semiconductor substrate 100, a pair of dielectric spacers 110a and 110b on the floating gate dielectric layer 110c, wherein the pair of dielectric The spacers 110a and 110b have inclined sidewalls 110a' and 110b' facing each other, and a floating gate 120' located on the floating gate dielectric layer 110c and between the pair of dielectric spacers 110a and 110b. The floating gate 120' has a pair of tips 120a' and 120b', and the pair of tips 120a' and 120b' are respectively located on the inclined sidewalls 110a' and 110b' of the dielectric spacers 110a and 110b. The above-mentioned inclined sidewalls 110a' and 110b' have the advantage of increasing the sharpness of the tips 120a' and 120b', thereby improving the performance of the flash memory 20.

In some embodiments, the top of the pair of dielectric spacers 110a and 110b is at the same level as the top surface of the mask layer 102, which also helps to improve the sharpness of the tips 120a' and 120b', thereby further improving the speed The performance of flash memory 20.

In some embodiments, the above-mentioned floating gate structure 200' further includes an oxide structure 140 located between the floating gate 120' and the inter-gate dielectric layer 220. In this embodiment, the floating gate 120' has a recessed top surface 120s', which can further make the tips 120a' and 120b' sharper. In this embodiment, the top of the floating gate 120' is at the same level as the top of the above-mentioned dielectric spacers 110a and 110b. In this way, the erasing efficiency of the flash memory 20 can be further improved.

In summary, the flash memory device of the embodiment of the present invention includes a pair of dielectric spacers, and the pair of dielectric spacers are used to create a floating gate with a pair of sharp points. The pair of sharp tips can increase the current between the floating gate and the control gate, thereby improving the performance of the flash memory (for example, shortening the erasure time).

The above briefly describes the features of several embodiments of the present invention, so that those with ordinary knowledge in the technical field can more easily understand the present disclosure. Anyone with ordinary knowledge in the relevant technical field should understand that this specification can easily be used as a basis for other structural or manufacturing changes or design to perform the same purpose and/or obtain the same advantages as the embodiments of the present disclosure. Anyone with ordinary knowledge in the technical field can also understand that the structure or process equivalent to the above-mentioned structure or process does not depart from the spirit and protection scope of this disclosure, and can be changed or substituted without departing from the spirit and scope of this disclosure And retouch.

10.20: Flash memory 100: semiconductor substrate 102: mask layer 104: opening 106: first dielectric layer 108: second dielectric layer 110a, 110b: dielectric spacer 110a', 110b': sidewall 110c : Floating gate dielectric layer 120, 120': floating gate 120a, 120b, 120a', 120b': tip 120s, 120s': top surface 140: oxide structure 200: floating gate structure 220: gate Inter-electrode dielectric layer 300: control gate 400: source/drain regions W1, W2: bottom width

Hereinafter, some embodiments of the present invention will be described in detail with the accompanying drawings. It should be noted that, according to standard practices in the industry, various components are not drawn to scale and are only used for illustration. In fact, the size of the element may be arbitrarily enlarged or reduced to clearly show the components of the embodiment of the present invention. FIGS. 1-9 are schematic cross-sectional diagrams illustrating various intermediate stages of an exemplary method for forming the flash memory of FIG. 9 according to some embodiments. FIGS. 10 and 11 are schematic cross-sectional diagrams illustrating various intermediate stages of another example method for forming the flash memory of FIG. 11 according to some embodiments.

10: Flash memory

100: Semiconductor substrate

110a, 110b: Dielectric spacer

110a’, 110b’: side wall

110c: floating gate dielectric layer

120: floating gate

120a, 120b: tip

200: Floating gate structure

220: Inter-gate dielectric layer

300: control gate

400: source/drain region

Claims (20)

A flash memory includes: a semiconductor substrate; a floating gate structure located on the semiconductor substrate, the floating gate structure including: a floating gate dielectric layer located on the semiconductor substrate; a pair A dielectric spacer is located on the floating gate dielectric layer, wherein the pair of dielectric spacers have inclined sidewalls facing each other; and a floating gate is located on the floating gate dielectric layer and is located Between the pair of dielectric spacers, wherein the floating gate has a pair of tips, and the pair of tips are respectively located on the inclined sidewalls of the pair of dielectric spacers; an inter-gate dielectric layer covering the floating gate Sidewalls and top surface of the pole structure; and a control gate located on the inter-gate dielectric layer. In the flash memory described in item 1 of the patent application, the floating gate has a very flat top surface. In the flash memory described in item 2 of the scope of patent application, the top surface of the floating gate is at the same level as the top of the pair of dielectric spacers. In the flash memory described in item 2 of the scope of patent application, the floating gate and the pair of dielectric spacers together form a rectangular shape in the schematic cross-sectional view. In the flash memory described in claim 1, wherein the floating gate structure further includes an oxide structure located between the floating gate and the inter-gate dielectric layer. In the flash memory described in item 5 of the patent application, the floating gate has a concave top surface. The flash memory described in item 5 of the scope of patent application, wherein the top of the floating gate is at the same level as the top of the pair of dielectric spacers. In the flash memory described in item 1 of the scope of patent application, the floating gate and the control gate include polysilicon. The flash memory described in the first item of the patent application, wherein the inter-gate dielectric layer, the pair of dielectric spacers, and the floating gate dielectric layer completely cover the floating gate. A method for forming a flash memory includes: providing a semiconductor substrate; forming a mask layer on the semiconductor substrate, wherein the mask layer has an opening that exposes a part of the semiconductor substrate; forming in the opening A floating gate structure, the step of forming the floating gate structure includes: forming a floating gate dielectric layer on the semiconductor substrate, and on opposite sidewalls of the opening and on the floating gate dielectric A pair of dielectric spacers are formed on the layer; and a floating gate is formed in the opening, wherein the floating gate is disposed on the floating gate dielectric layer, and the floating gate is located on the pair of dielectric Between the electrical spacers, and wherein the floating gate has a pair of tips, which are respectively located on the pair of dielectric spacers; removing the mask layer; forming an inter-gate dielectric layer to cover the floating Gate structure; and forming a control gate on the inter-gate dielectric layer. The method for forming a flash memory as described in claim 10, wherein the step of forming the floating gate dielectric layer and the pair of dielectric spacers includes: conforming along opposite sidewalls and bottom surfaces of the opening Sexually form a first dielectric layer; form a second dielectric layer on the first dielectric layer, wherein the second dielectric layer overfills the opening; and the first dielectric layer and the second dielectric layer The dielectric layer undergoes an anisotropic etch-back process. After the anisotropic etch-back process, the first dielectric layer on the bottom surface of the opening serves as the floating gate dielectric layer and is located in the opening The first dielectric layer and the remaining second dielectric layer on the opposite sidewalls serve as the pair of dielectric spacers. The method for forming a flash memory as described in claim 10, wherein the top of the pair of dielectric spacers is at the same level as the top surface of the mask layer. According to the method for forming a flash memory described in claim 10, the pair of dielectric spacers have inclined sidewalls facing each other. According to the method for forming a flash memory described in claim 10, the floating gate has a very flat top surface. According to the method for forming a flash memory described in claim 14, wherein the top of the floating gate is at the same level as the top of the pair of dielectric spacers. According to the method for forming the flash memory described in claim 10, wherein the step of forming the floating gate structure further includes performing an oxidation process on the floating gate to deposit the floating gate and the floating gate An oxide structure is formed between the inter-gate dielectric layers According to the method for forming a flash memory described in claim 16, wherein the floating gate has a concave top surface. According to the method for forming a flash memory as described in claim 10, the mask layer includes nitride. According to the method for forming a flash memory described in claim 10, the floating gate and the control gate comprise polysilicon. The method for forming a flash memory as described in claim 10, wherein the inter-gate dielectric layer, the pair of dielectric spacers, and the floating gate dielectric layer completely cover the floating gate dielectric layer Gate.

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