TWI713043B - Cell current measurement method for three-dimensional memory - Google Patents

Abstract

A method for measuring memory cell current of a 3D memory, the method includes applying a first test voltage to a source line pad of a peripheral circuit of a 3D memory device, wherein the source line pad is electrically connected to a common source line of a 3D memory array of the 3D memory device, and the peripheral circuit formed on a first substrate and the 3D memory array formed on a second substrate are electrically connected by direct bonding. The method further includes applying a second test voltage to bit line pads of the 3D memory array, wherein the bit line pads and the 3D memory array are formed on opposite sides of the second substrate. In some embodiments, the method includes applying a second test voltage to a power pad, wherein the power pad is electrically connected to a page buffer of a peripheral circuit.

Description

Unit current measurement method for three-dimensional memory

The present invention generally relates to the field of semiconductor technology, and more specifically relates to a method for forming a three-dimensional (3D) memory.

As memory components are reduced to smaller die sizes to reduce manufacturing costs and increase storage density, the reduction of planar storage units faces challenges due to processing technology limitations and reliability issues. Three-dimensional (3D) storage architecture can solve the density and performance limitations of planar storage units.

In 3D memory, the storage unit can be programmed or erased for data storage. Sometimes multiple states can be stored in the same storage unit. Therefore, after programming or erasing, it is necessary to verify the component parameters of the storage unit. Generally speaking, the state and component parameters of the storage unit can be extracted from the current flowing through the storage unit. Therefore, there is a need for a storage cell current measurement method that can be easily implemented and provide accurate data.

The present invention describes an embodiment of a three-dimensional (3D) memory device and a method for current measurement.

In an embodiment of the present invention, a method for measuring the current of a storage unit in a three-dimensional (3D) memory device is provided. The method includes applying a first test voltage to a source line pad of a peripheral circuit of a 3D memory device, wherein the source line pad is electrically connected to a common source of a 3D storage array of the 3D memory device The peripheral circuit formed on the first substrate and the 3D storage array formed on the second substrate are electrically connected through direct bonding. The method further includes applying a second test voltage to the bit line pads of the 3D storage array, wherein the bit line pads and the 3D storage array are formed on opposite sides of the second substrate, and the The bit line pads are electrically connected with the bit lines of the storage cells through the array contacts. The method further includes applying the operation step voltage to the word line of the storage unit, wherein the word line is electrically connected to the control gate of the storage unit. The method further includes applying a pass voltage to a word line of a memory cell that is not selected, and measuring a current flowing through the bit line pad or the source line pad.

In some embodiments, applying the second test voltage includes applying a voltage between 0 volts (V) and 10 volts (V).

In some embodiments, applying the first test voltage includes applying a voltage of 0 volts (V).

In some embodiments, applying the operation step voltage includes applying a voltage between 0.5 volt (V) and 5 volt (V).

In some embodiments, applying the pass voltage includes applying a voltage between 0 volts (V) and 10 volts (V), but is not limited thereto.

In some embodiments, the method further includes electrically disconnecting the common source line from the internal ground node through the first transistor of the peripheral circuit, and electrically disconnecting the common source line through the second transistor of the peripheral circuit. The pole line is electrically connected to the source line pad.

In some embodiments, the method further includes applying a switching voltage on the lower selection gate and the top selection gate of the memory string corresponding to the memory cell. In some embodiments, applying the switching voltage includes applying a voltage between 0.5 volt (V) and 5 volt (V), but is not limited thereto.

In some embodiments, the method further includes electrically connecting the common source line and the source terminal of the memory string of the memory cell through the doped source line region and the array common source.

In some embodiments, the through-array contact through the second substrate is configured to form an electrical contact between the bit line pad and the bit line.

In some embodiments, the method further includes electrically connecting the source line pad and the common source line of the 3D storage array through one or more interconnect vias (VIA) at the bonding interface .

Another aspect of the present invention provides a method for measuring the current of a storage unit in a three-dimensional (3D) memory device. The method includes applying a first test voltage to a source line pad of a peripheral circuit of a 3D memory device, wherein the source line pad is electrically connected to a common source of a 3D storage array of the 3D memory device The peripheral circuit formed on the first substrate and the 3D storage array formed on the second substrate are electrically connected through direct bonding. The method further includes applying a second test voltage to a power supply pad, wherein the power supply pad is electrically connected to a page buffer of a peripheral circuit, and the page buffer is configured to provide temporary storage for the storage unit. The method further includes applying the operation step voltage to the word line of the storage unit, wherein the word line is electrically connected to the control gate of the storage unit. The method further includes applying a pass voltage to a word line of a memory cell that is not selected, and detecting a current flowing through the power supply pad or the source line pad.

In some embodiments, the method further includes disconnecting the common source line from the internal ground node through the first transistor of the peripheral circuit, and disconnecting the common source line from the internal ground node through the second transistor of the peripheral circuit. The source line pad is electrically connected.

In some embodiments, the method further includes: providing a first data signal to a first output terminal of a sensing latch of the page buffer, wherein the first data signal is configured as Turning on the third transistor of the peripheral circuit to realize the electrical connection between the power supply pad and the sensing node; and turning off the fourth transistor of the peripheral circuit to turn on the second output terminal of the sensing latch The electrical connection is disconnected from the sensing node. In some embodiments, the method further includes electrically connecting the sensing node and the bit line of the storage unit through a fifth transistor of the peripheral circuit.

In some embodiments, the method further includes electrically disconnecting the page buffer from the internal power supply through a sixth transistor of the peripheral circuit.

Those skilled in the art can understand other aspects of the present invention based on the specification, the scope of patent application and the drawings of the present invention.

Although specific configurations and arrangements are discussed, it should be understood that the discussion is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the invention. It is obvious to those skilled in the art that the present invention can also be used in various other applications.

It should be pointed out that reference to "one embodiment", "embodiment", "exemplary embodiment", "some embodiments", etc. in the specification means that the described embodiment may include specific features, structures or characteristics, but not necessarily each The embodiments all include the specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when specific features, structures, or characteristics are described in combination with embodiments, it is within the knowledge of those skilled in the art to implement such features, structures, or characteristics in combination with other embodiments explicitly or not explicitly described.

Generally speaking, terms should be understood at least in part based on the context in which they are used. For example, based at least in part on the context, the term "one or more" used in the text can be used to describe any feature, structure, or characteristic in the singular sense, or can be used to describe the feature, structure, or characteristic in the plural sense The combination. Similarly, depending at least in part on the context, the terms "a", "an" or "the" can also be understood as conveying singular usage or conveying plural usage. In addition, depending at least in part on the context, the term "based on" can be understood as a set of factors that is not necessarily intended to convey an exclusive set of factors, but on the contrary may allow other factors that are not necessarily expressly stated.

It should be easily understood that "on", "above" and "above" in the present invention should be interpreted in the broadest way, so that "on" does not only mean directly on Something also includes the meaning of being on something with intermediate features or layers in between. "Above..." or "above..." not only means above or above something, but also includes The meaning of being above or on something with no intermediate features or layers in between (ie, directly on something).

In addition, for the convenience of description, spatial relative terms may be used in the text, for example, "below", "below", "below", "above", "above", etc., to describe one element or feature and other elements or features as shown in the figure Relationship. Spatial relative terms are intended to encompass different orientations of elements in use or operation steps other than those shown in the drawings. The device can have other orientations (rotated by 90 degrees or located in other orientations), and the relative spatial descriptors used in the text should be explained accordingly.

As used herein, the term "substrate" refers to a material on which a subsequent layer of material is added. The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is usually where the semiconductor element is formed, so the semiconductor element is formed on the top side of the substrate unless otherwise specified. The bottom surface is opposite to the top surface, so the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself can be patterned. The material added on the top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be formed of a non-conductive material such as glass, plastic, or sapphire wafer.

As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer has a top side and a bottom side, where the bottom side of the layer is relatively close to the substrate and the top side is relatively away from the substrate. The layer may extend over the entire lower or upper structure, or its range may be smaller than that of the lower or upper structure. In addition, the layer may be a region of a uniform or non-uniform continuous structure whose thickness is less than that of the continuous structure. For example, the layer may be located between or at any pair of horizontal planes between the top surface and the bottom surface of the continuous structure. The layers can extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, the substrate may include one or more layers therein, and/or the substrate may have one or more layers on, above, and/or below it. The layer may include multiple layers. For example, the interconnection layer may include one or more conductive layers and contact layers in which contacts, interconnect lines, and/or vertical interconnect vias (VIA) are formed, and one or more dielectric layers.

In the present invention, for the convenience of description, “level” is used to refer to elements having substantially the same height in the vertical direction. For example, the word lines and the lower gate dielectric layer may be called "levels", the word lines and the lower insulating layer together may be called "levels", and the word lines having substantially the same height may be called "levels". Character line level", and so on.

As used herein, the term "nominal/nominal" refers to the expected value or target value, and higher and/or lower values, of characteristics or parameters of components or process steps set during the design phase of a product or process The range of values ​​that are less than expected. The range of values ​​can be caused by slight changes in manufacturing processes or tolerances. As used herein, the term "about" refers to a given amount of value that can vary based on the specific technology node associated with the subject semiconductor element. Based on a specific technical node, the term "approximately" can mean a given amount of value, which varies, for example, within 10-30% of the value (for example, ±10%, ±20%, or ±30% of the value) .

In the present invention, the term “horizontal/horizontal/lateral/lateral” refers to the lateral surface of the substrate nominally parallel to the lateral surface, and the term “vertical” or “vertical” refers to the nominally perpendicular The lateral surface of the substrate.

As used herein, the term "3D memory" refers to the three-dimensional (hereinafter referred to as "memory string", such as NAND memory string) of memory cell transistor strings with vertical orientation on a laterally oriented substrate. 3D) The semiconductor device makes the memory string extend in the vertical direction relative to the substrate.

According to various embodiments of the present invention, a circuit and method for current measurement of a 3D memory device are provided. In the 3D memory device, existing circuits can be used, or structural measurements made with the help of existing manufacturing processes can be used to store cell currents. It is possible to reduce manufacturing costs without relying on circuits used only for measurement purposes.

FIG. 1 shows a top view of an exemplary three-dimensional (3D) memory device 100 according to some embodiments of the present invention. The 3D memory device 100 may be a storage chip (package), a storage die, or any part of a storage die, and may include one or more storage planes 101, and each of the storage planes 101 may include multiple Storage block 103. The same operation steps can occur at each storage plane 101. The storage block 103, which can have a size of several megabytes (MB), is the smallest size for performing the erase operation step. As shown in FIG. 1, the exemplary 3D memory device 100 includes four storage planes 101, and each storage plane 101 includes six storage blocks 103. Each storage block 103 may include a plurality of storage cells, where each storage cell may be addressed (positioned) through, for example, the interconnection of bit lines and word lines. The bit lines and the word lines can be arranged vertically (for example, in columns and rows, respectively) to form an array of metal lines. In FIG. 1, the directions of the word lines and bit lines are marked as "BL" and "WL". In the present invention, the storage block 103 is also called "storage array" or "array". The storage array is the core area of the memory device that performs storage functions.

The 3D memory device 100 further includes a peripheral area 105, that is, an area surrounding the storage plane 101. The peripheral area 105 contains many digital, analog, and/or mixed-signal circuits to support the functions of the storage array, such as page buffers, row decoders and column decoders, and sense amplifiers. The peripheral circuit uses active and/or passive semiconductor components, such as transistors, diodes, capacitors, resistors, etc., which will be obvious to those skilled in the art.

It should be pointed out that the arrangement or arrangement distribution position of the storage plane 101 in the 3D memory device 100 shown in FIG. 1 and the arrangement or arrangement distribution position of the storage block 103 in each storage plane 101 are only used as examples. It does not limit the scope of the present invention.

Refer to FIG. 2, which shows an enlarged top view of area 108 in FIG. 1 according to some embodiments of the present invention. The region 108 of the 3D memory device 100 may include a step region 210 and a channel structure region 211. The channel structure region 211 may include an array of memory strings 212, each memory string including a plurality of stacked memory cells. The step area 210 may include a step structure and an array of contact structures 214 formed on the step structure. In some embodiments, a plurality of slit structures 216 extending in the WL direction across the channel structure region 211 and the step region 210 can divide the storage block into a plurality of storage fingers 218. At least some of the gap structures 216 may serve as common source contacts for the array of memory strings 212 in the channel structure region 211 (eg, array common source). The top selection gate cutout 220 can be set to (for example) the center of each storage finger 218, thereby dividing the top selection gate (top selection gate (TSG)) of the storage finger 218 into two parts, and further The storage means is divided into two storage slices 224. The storage units in the storage slices 224 that share the same character line form a programmable (read/write) storage page. Although the erasing operation steps of the 3D NAND memory can be performed at the storage block level, the read operation steps and the write operation steps can also be performed at the storage page level. A storage page can have a size of thousands of bytes (KB). In some embodiments, the area 108 further includes a dummy memory string 222 for use in process change control during manufacturing and/or for additional mechanical support.

FIG. 3 shows a perspective view of a portion of an exemplary three-dimensional (3D) storage array structure 300 according to some embodiments of the invention. The storage array structure 300 includes a substrate 330, an insulating film 331 on the substrate 330, a level of lower select gate (LSG) 332 on the insulating film 331, and multiple levels of control gates 333 (also known as "words Element line (WL)"), the multiple levels of control gates are stacked on top of the lower selection gate (LSG) 332, thereby forming a film stack 335 composed of alternating conductive layers and dielectric layers. In FIG. 3, for the sake of clarity, the dielectric layer adjacent to the control gate of each level is not shown.

The control gates of each level are separated by the slit structure 216-1 and the slit structure 216-2 penetrating the film stack 335. The storage array structure 300 also includes a top select gate (TSG) 334 of one level above the stack of control gates 333. The stack composed of the top selection gate (TSG) 334, the control gate 333, and the lower selection gate (LSG) 332 is also called a "gate electrode". The storage array structure 300 further includes a memory string 212 and a doped source line region 344 located in a part of the substrate 330 and adjacent to the lower select gate (LSG) 332. Each memory string 212 includes a channel hole 336 extending through an insulating film 331 and a film stack 335 of alternating conductive and dielectric layers. The memory string 212 further includes a storage film 337 on the sidewall of the channel hole 336, a channel layer 338 on the storage film 337, and a core filling film 339 surrounded by the channel layer 338. The storage unit 340 may be formed at the intersection of the control gate 333 and the memory string 212. The storage array structure 300 further includes a plurality of bit lines (BL) 341 connected to the memory string 212 above the top select gate (TSG) 334. The storage array structure 300 further includes a plurality of metal interconnections 343 connected to the gate electrode through a plurality of contact structures 214. The edges of the film stack 335 are configured to have a stepped shape, thereby allowing electrical connections to gate electrodes of each level.

In Figure 3, for illustrative purposes, three levels of control gate 333-1, control gate 333-2, and control gate 333-3 are combined with one level of top selection gate (TSG) 334 and one The lower selection gate (LSG) 332 of the hierarchy is shown together. In this example, each memory string 212 may include three storage units 340-1 and 340- corresponding to the control gate 333-1, the control gate 333-2, and the control gate 333-3, respectively. 2 and storage unit 340-3. In some embodiments, the number of control gates and the number of storage units may exceed three to increase storage capacity. The storage array structure 300 may also include other structures, such as top select gate (TSG) cutouts, common source contacts (ie, array common source), and dummy memory strings. For simplicity, these structures are not shown in FIG. 3.

In order to achieve higher storage density, the number of vertical WL stacks of 3D memory, or the number of storage cells per memory string has been greatly increased, for example, from 24 stacked WL layers (ie, 24L) To 128 floors or more. In order to further reduce the size of the 3D memory, the storage array can be stacked on top of the peripheral circuit, or vice versa. For example, the peripheral circuit can be fabricated on the first wafer, and the storage array can be fabricated on the second wafer. After that, by bonding the first wafer and the second wafer together, the storage array and the peripheral circuits can be connected through various interconnections. In this way, not only can the 3D storage density be increased, but also the communication between the peripheral circuit and the storage array can achieve higher frequency bandwidth and lower power consumption, because the interconnection length can be shortened through substrate (wafer) bonding. It can be found in the co-pending patent application entitled "Embedded Pad Structures of Three-Dimensional Memory Devices and Fabrication Methods Thereof" (Patent No. 16/163,274, filed on October 17, 2018) for forming 3D memory devices The detailed structure and method of (where the peripheral circuit is connected to the storage array through wafer bonding) is incorporated into this article by citation.

FIG. 4 shows a cross-section of an exemplary peripheral circuit 400 of a 3D memory device according to some embodiments of the present invention. The peripheral circuit 400 may include a first substrate 430. In some embodiments, the first substrate 430 includes surfaces on the top side and the bottom side (also referred to as the first side 430-1 and the second side 430-2, or the front and back, respectively).

The peripheral circuit 400 may include one or more peripheral elements 450 (for example, the peripheral element 450-1 and the peripheral element 450-2) on the first side 430-1 of the first substrate 430. The peripheral element 450 may include any suitable semiconductor element, for example, a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), a diode, a resistor, a capacitor, an inductor, etc. Among semiconductor elements, p-type and/or n-type MOSFETs (ie, CMOS) are widely implemented in logic circuit design, and are used as examples of peripheral elements 450 in the present invention. In this example, the peripheral circuit 400 is also referred to as a CMOS wafer 400.

The peripheral element 450 may be a p-channel MOSFET (for example, peripheral element 450-1) or an n-channel MOSFET (for example, peripheral element 450-2), and may include, but is not limited to, surrounded by shallow trench isolation (STI) 452 Active device region, well 454 with n-type or p-type doping formed in the active device region (for example, n-well 454-1, p-well 454-2, deep n-well 454-3, etc.), including gates A gate stack 451 with a dielectric layer, a gate conductor layer and/or a gate hard mask. The peripheral element 450 may also include a source/drain 453 (for example, a source/drain 453-1, a source/drain 453-2, etc.) on each side of the gate stack 451. In some embodiments, the peripheral element 450 may be a high-voltage MOSFET with a lightly doped drain 453-3 (for example, the peripheral element 450-3). The structure and manufacturing method of the peripheral element 450 are known to those skilled in the art, and are incorporated herein in its entirety.

In some embodiments, the peripheral circuit 400 may include a peripheral interconnection layer 455 (or a first interconnection layer) and an insulating layer 460 (above the peripheral element 450) located on the first side 430-1, and then the peripheral elements Electrical connection is provided between 450 and external components (for example, a power supply, another chip, input/output components, etc.). The peripheral interconnection layer 455 may include one or more interconnection structures, for example, one or more vertical contact structures 456 and one or more lateral wires 458 (eg, lateral wires 458-1, lateral wires 458-2, etc.). The contact structure 456 and the lateral wires 458 may broadly include any suitable type of interconnection, such as mid-line (MOL) interconnection and back-line (BEOL) interconnection. In some embodiments, the peripheral circuit 400 further includes one or more substrate contacts 462, wherein the substrate contacts 462 provide electrical connection with the first substrate 430.

In some embodiments, multiple peripheral elements 450 may be used to form any digital, analog, and/or mixed-signal circuit used in the operation steps of the peripheral circuit 400. The peripheral circuit 400 can perform, for example, row/column decoding, timing and control of the storage array, as well as data reading, writing and erasing.

FIG. 5 shows a cross-section of a 3D storage array 500 according to some embodiments of the invention. The 3D storage array 500 may be a 3D NAND storage array, and may include a second substrate 530 (having a first surface 530-1 and a second surface 530-2) and a substrate formed on the first surface 530-1 of the second substrate 530 The memory cell 340 and the array interconnection layer 555 (or the second interconnection layer). The array interconnection layer 555 may be similar to the peripheral interconnection layer 455. For example, the interconnection structure (for example, the vertical contact structure 556 and the lateral wire 558) and the insulating layer 560 of the array interconnection layer 555 and the interconnection structure (for example, the contact structure 456 and the wire 458) and the insulating layer 560 of the peripheral interconnection layer 455, respectively Layer 460 is similar.

In some embodiments, the 3D storage array 500 may be a storage array of 3D NAND flash memory, where the storage unit 340 may be vertically stacked as a memory string 212. The memory string 212 extends through an alternating conductor/dielectric stack 568 including a plurality of conductor layers 564 and dielectric layers 566.

In some embodiments, the array element further includes a plurality of word line contact structures 214 (also called word line contacts) located in the stepped area. Each character line contact structure 214 can form electrical contact with the corresponding conductor layer 564 in the alternating conductor/dielectric stack 568, thereby controlling the storage unit 340 individually.

As shown in FIG. 5, the 3D storage array 500 further includes a bit line contact 570 formed on the top of the memory string 212 to provide individual access to the channel layer of the memory string 212. The wires connected to the word line contact structure 214 and the bit line contact 570 respectively form the word line (WL) and the bit line (BL) of the 3D storage array 500 (for example, WL 333 and BL 341 shown in FIG. 3). ). Typically, word lines (WL) and bit lines (BL) are arranged perpendicular to each other (for example, in columns and rows, respectively) to form an "array" of memory.

In some embodiments, the 3D storage array 500 includes the substrate contact 562 of the second substrate 530. The substrate contact 562 can provide an electrical connection with the second substrate 530 of the 3D storage array 500.

FIG. 6 shows a cross-section of a 3D memory device 600 according to some embodiments of the present invention. The 3D memory device 600 includes a peripheral circuit 400 fabricated on a first substrate 430 and a 3D storage array 500 fabricated on a second substrate 530. In this example, the 3D storage array 500 is flipped and connected to the peripheral circuit 400 by means of direct bonding or hybrid bonding. At the bonding interface 674, the peripheral circuit 400 and the 3D storage array 500 are electrically connected through a plurality of interconnect vias (VIA) 472/interconnect vias (VIA) 572. In this way, any lateral wire 458 or vertical contact structure 456 of the peripheral interconnection layer 455 can be electrically connected to any lateral wire 558 or vertical contact structure 556 of the array interconnection layer 555. In other words, the peripheral circuit 400 and the 3D storage array 500 can be electrically connected.

Through bonding, the 3D memory device 600 can function in a manner similar to a 3D memory in which peripheral circuits and storage arrays are formed on the same substrate. By stacking the 3D storage array 500 and the peripheral circuit 400 on top, the density of the 3D memory device 600 can be increased. At the same time, since the interconnection distance between the peripheral circuit 400 and the 3D storage array 500 can be reduced through the stacked design, the bandwidth of the 3D memory device 600 can be increased.

FIG. 7 shows a cross-sectional view of a 3D memory device 700 according to some embodiments of the present invention. The 3D memory device 700 includes a through array contact (TAC) 770 and an input/output (I/O) pad 772 formed on the second side 530-2 of the second substrate 530 of the 3D memory device 600 in FIG. 6 . In some embodiments, the second substrate 530 may be thinned downward before forming the through array contact (TAC) 770 and the input/output pad 772. It is to be noted that the structure and number of through-array contacts (TAC) 770 and input/output pads 772 are not limited to the example shown in FIG. 7.

In some embodiments, the through-array contact (TAC) 770 may be electrically connected to any vertical contact structure 556 or any lateral wire 558 of the array interconnection layer 555, and thus from the second side 530-2 of the second substrate 530 An electrical connection with any word line or bit line of the 3D storage array 500 is formed. In some embodiments, the through-array contact (TAC) 770 can also pass through one or more of the interconnect via (VIA) 472 or the interconnect via (VIA) 572 to communicate with any of the peripheral interconnect layers 455 The contact structure 456 or any wire 458 is electrically connected. In this way, an electrical connection between the input/output pad 772, the through array contact (TAC) 770 and any peripheral element 450 of the peripheral circuit 400 can be formed from the second side 530-2 of the second substrate 530. In some embodiments, the through-array contact (TAC) 770 and the input/output pad 772 may also be electrically connected to the substrate contact 462 or the substrate contact 562.

For 3D memory devices, accurate measurement of storage cell current is important for improved memory design and operation procedures, such as estimating storage cell sensing time, noise level, and storage cell component performance. In the past, the storage cell current was measured indirectly by using a current mirror circuit. However, in circuit design, it may be difficult to accurately measure the current of the storage cell through an indirect method. Inserting a current mirror circuit with a large area into the chip of a memory product may also increase the area of the memory storage capacity and increase the manufacturing cost of the memory. It is also possible to directly measure the storage cell current through external input/output pads with connections designed to bypass the page buffer circuit. Therefore, there is a need for a method to accurately measure the current of the storage cell of a three-dimensional (3D) memory without using an additional circuit designed only for this measurement purpose, and thereby avoiding area or performance loss.

FIG. 8 shows a schematic circuit diagram of a 3D memory device 800 configured to provide cell current measurement according to some embodiments of the present invention. The 3D memory device 800 includes a storage array wafer (for example, the 3D storage array 500) bonded to a CMOS wafer (for example, the peripheral circuit 400) at the bonding layer 676 and the bonding interface 674. As described above, the 3D storage array 500 includes a plurality of memory strings 212, and each memory string 212 has a plurality of stacked storage units 340. The memory string 212 also includes at least one field effect transistor (eg, MOSFET) at each end. For example, the field-effect transistor closest to the second substrate 530 may be controlled through the lower selection gate (lower selection gate (LSG)) 332, and is referred to as the lower selection transistor 332-T accordingly. The field-effect transistor at the other end far from the second substrate 530 can be controlled by a top selection gate (top selection gate (TSG)) 334, and is referred to as a top selection transistor 334-T. The stacked storage cells 340 can be controlled by the control gate 333, wherein the control gate 333 is connected to the word line of the 3D memory device 800 (not shown in FIG. 8). The drain of the top selection transistor 334-T may be connected to the bit line 341, and the bit line 341 may be composed of one or more lateral wires 558 and/or conductive structures 556 (as shown in FIG. 7). The source of the lower selection transistor 332-T may be connected to a well in the second substrate 530 (for example, the doped source line region 344), and a plurality of array common sources (ACS) 880 may be formed from the well and the ACS Electrical connection of grid 882. The ACS grid 882 can be shared by the memory string 212 in the entire storage block, so it is also called a common source line. The ACS 880 may be composed of a slit structure 216 (shown in FIGS. 2 and 3) with an additional conductive core, or may be composed of the substrate contact 562 shown in FIG. It should be noted that the formation and configuration of word lines, bit lines, ACS, and ACS grids are not limited to the configurations described above, and may also include other interconnect structures.

In some embodiments, the 3D memory device 800 further includes a plurality of through-array contacts (for example, through-array contacts (TAC) 770), thereby connecting the bit line 341 and the bit line (BL) pad 872-1. The bit line pad 872-1 may be similar to the input/output pad 772 in FIG. 7. In some embodiments, each bit line 341 may be electrically connected to one BL pad 872-1. In some embodiments, the through-array contact (TAC) 770 may be connected to the bit line 341 through one or more of the contact line 558 and the vertical contact structure 556. In some embodiments, the through-array contact (TAC) 770 may also be connected to one or more of the interconnect via (VIA) 572 at the bonding interface 674. In some embodiments, the interconnect via (VIA) 572 of the 3D storage array 500 may also be connected to the interconnect via (VIA) 472 of the peripheral circuit 400. In some embodiments, the bit line 341, the word line (control gate 333), top select gate (TSG) 334, lower select gate (LSG) 332, ACS grid 882, and 3D storage array 500 Other structures can pass through one or more of the interconnection via (VIA) 472/interconnection via (VIA) 572, the vertical contact structure 556/vertical contact structure 456 of the peripheral circuit 400 and the 3D storage array 500, and/or One or more of the lateral wires 558 / the lateral wires 458 are connected to any circuit of the peripheral circuit 400.

In a NAND flash memory, a read operation step and a write operation step can be performed in a storage page, where the storage page includes storage cells that share the same word line. FIG. 8 shows an exemplary storage page 886. During the read operation step and the write operation step, the storage unit 340 in the same storage page 886 can be accessed at the same time, and the single metadata can be transferred to the page buffer for temporary storage. In some embodiments, one page buffer can be connected to one bit line. In some embodiments, a page buffer can be shared between two adjacent bit lines. A column decoder (not shown) can be used to decode the single metadata in the page buffer.

According to some embodiments of the present invention, FIG. 8 shows a simplified schematic circuit diagram of the page buffer 888 of the 3D memory device 800. In this example, the page buffer 888 is formed on the CMOS wafer 400 and can be connected to the bit line 341 across the bonding interface 674 through an interconnect via (VIA) 472/interconnect via (VIA) 572. In some embodiments, the page buffer 888 includes a sense latch 878 and a sense transistor (not shown) connected at the sense node 884. The page buffer 888 also includes a power supply pad 872-2 (also referred to as a Vdd pad) to provide an electrical connection for the power supply of the page buffer 888. The page buffer also includes a plurality of transistors, for example, n-channel MOSFETs 850-N3 to 850-N6 and p-channel MOSFETs 850-P1 to 850-P3.

和

處的第一輸出端和第二輸出端。每一反相器對包括p溝道MOSFET和n溝道MOSFET（例如，878-P1和878-N1）。兩個p溝道MOSFET 878-P1和p溝道MOSFET 878-P2的源極端子連接至節點890-1處的內部電源，兩個n-MOSFET 878-N1和n-MOSFET 878-N2的源極端子連接至內部接地節點892-1。兩個反相器的第一輸出端和第二輸出端被標記為節點

和

，進而含有相反（或者互補）的資料信號。例如，當節點

處於高電位時，節點

可以處於低電位，或反之。為了形成感測拴鎖器，一對反相器的輸出端可以連接至另一對的電晶體的閘極。例如，節點

處的第二輸出端與n溝道MOSFET 878-N1和p溝道MOSFET 878-P1的閘極連接，而節點

處的第一輸出端則與n溝道MOSFET 878-N2和p溝道MOSFET 878-P2的閘極連接。 In some embodiments, the sense latch 878 includes two n-channel MOSFET 878-N1 and n-channel MOSFET 878-N2 and two p-channel MOSFET 878-P1 and p-channel MOSFET 878-P2, thereby forming Two inverter pairs, and have at the node

with

At the first output terminal and the second output terminal. Each inverter pair includes a p-channel MOSFET and an n-channel MOSFET (for example, 878-P1 and 878-N1). The source terminals of the two p-channel MOSFETs 878-P1 and p-channel MOSFET 878-P2 are connected to the internal power supply at node 890-1, and the source terminals of the two n-MOSFETs 878-N1 and n-MOSFET 878-N2 The sub is connected to the internal ground node 892-1. The first and second output terminals of the two inverters are marked as nodes

with

, And then contain the opposite (or complementary) data signal. For example, when the node

At high potential, the node

It can be at a low potential, or vice versa. In order to form a sense latch, the output terminals of a pair of inverters can be connected to the gate of another pair of transistors. For example, node

The second output terminal is connected to the gates of n-channel MOSFET 878-N1 and p-channel MOSFET 878-P1, and the node

The first output terminal is connected to the gates of the n-channel MOSFET 878-N2 and the p-channel MOSFET 878-P2.

，即感測拴鎖器878的輸出端之一。感測拴鎖器878的位於節點

處的另一輸出端連接至電晶體850-N6的閘極，而電晶體850-N6的汲極端子則與電晶體850-N5（又被稱為週邊電路的第四電晶體）的源極共用。電晶體850-N6的源極連接至內部接地節點892-3。又被稱為週邊電路的第五電晶體的兩個n溝道MOSFET 850-N3和n溝道MOSFE 850-N4的源極/汲極端子串聯連接，進而控制頁緩衝器和對應位元線341之間的通信。 In some embodiments, the source of the p-channel MOSFET 850-P1 is connected to the Vdd pad 872-2, and the drain is connected to the p-channel MOSFET 850-P2 and the p-channel MOSFET 850-P3 (also called respectively It is the node 883 shared by the corresponding sixth transistor and the third transistor of the peripheral circuit. The other terminal (source) of transistor 850-P2 is connected to the internal power supply at node 890-2. In some embodiments, the internal power supply at node 890-1 and node 890-2 may have the same voltage (for example, referred to as Vdd). The drain terminal of the transistor 850-P3 is connected to the source/drain terminals of the transistor 850-N4 and the transistor 850-N5 at the node 885. The node 885 is at the same potential as the sensing node 884, so it is It is called a sensor node. The gate of transistor 850-P3 is connected to the node

, Which is one of the output terminals of the sensing latch 878. Sense the location of the latch 878 at the node

The other output terminal is connected to the gate of transistor 850-N6, and the drain terminal of transistor 850-N6 is connected to the source of transistor 850-N5 (also known as the fourth transistor of the peripheral circuit) Shared. The source of the transistor 850-N6 is connected to the internal ground node 892-3. The source/drain terminals of the two n-channel MOSFET 850-N3 and n-channel MOSFE 850-N4, which are also called the fifth transistor of the peripheral circuit, are connected in series to control the page buffer and the corresponding bit line 341 Communication between.

In some embodiments, the 3D memory device 800 further includes a source line (SL) pad 872-3 and two transistors in the peripheral circuit 400 (for example, n-channel MOSFET 850-N1 and n-channel MOSFET 850 -N2), where the source terminals of n-channel MOSFET 850-N1 (also known as the first transistor of the peripheral circuit) and n-channel MOSFET 850-N2 (also known as the second transistor of the peripheral circuit) The sub is connected to the internal ground node 892-2 and the SL pad 872-3, respectively. In some embodiments, the internal ground node 892-1, the internal ground node 892-2, and the internal ground node 892-3 are electrically connected to maintain the same potential. The drain terminals of n-channel MOSFET 850-N1 and n-channel MOSFET 850-N2 are connected at node 887, where node 887 can be connected to via interconnect via (VIA) 472/interconnect via (VIA) 572 The ACS grid 882 of the 3D storage array 500. In some embodiments, the SL pad 872-3 may be used to connect to a source line driver circuit (not shown in FIG. 8). In this example, the ACS grid 882 can be connected to the internal ground node 892-2 or to the source line driver circuit by turning on or off the transistor 850-N1 and the transistor 850-N2.

In some embodiments, through the use of through-array contact (TAC) 770, interconnect via (VIA) 572/interconnect via (VIA) 472 and/or vertical contact structure 556/direct contact structure 456 and/or lateral wires 558/lateral wire 458, Vdd pad 872-2 and SL pad 872-3 may be formed on the second surface 530-2 of the second substrate 530. In some embodiments, the Vdd pad 872-2 and the SL pad 872-3 may be formed on the second surface 430 of the first substrate 430 by means of through-array contacts passing through the first substrate 430 (as shown in FIG. 7). This is similar to the method used to form the BL pad 872-1 and through-array contact (TAC) 770.

In some embodiments, the programmed or erased storage unit can be verified by measuring the current flowing through the storage unit. According to the present invention, the storage cell current of the 3D memory device 800 can be measured using three methods.

In the first method, according to some embodiments of the present invention, it is possible to apply a first test voltage (for example, an external ground node) to the SL pad 872-3 and scan the second test voltage on the BL pad 872-1 (For example, from 0 volts (V) to 10 volts (V)) and directly measure the storage cell current. There are many ways to switch the SL pad 872-3 from the source line driver circuit (not shown) to the external ground node by adding additional switching transistors, which is known to those skilled in the art. .

In some embodiments, a bias voltage (for example, between 1V and 5 volts (V)) can be applied to the gate of the transistor 850-N2 to turn it on so that the storage cell current can flow through the BL pad 872- Flow between 1 and SL pad 872-3. The method further includes applying another bias voltage (for example, 0 volt (V)) to the gate of the transistor 850-N1 to turn it off, thereby enabling the storage cell current to be disconnected from the internal ground node 892-2 connection. By turning off the transistor 850-N1, noise from the peripheral circuit 400 can be avoided during the measurement of the storage cell current.

In the first method, among the word lines 333, the operation step voltage (for example, 0.5 volts (V) to 5 volts (V)) can be applied to the selected word line in the target storage unit 340, and the The selected word line applies a pass voltage (Vpass) that is high enough to turn on other storage cells on the same memory string 212, for example, higher than any threshold voltage of the storage cell, for example, at 0 volts (V ) To 10 Volts (V). It is also possible to apply a switching voltage (for example, between 0.5 Volt (V) to 5 Volt (V)) to the top selection gate (TSG) 334 and the lower selection gate (LSG) 332, the switching voltage being high enough to conduct The lower selection transistor 334-T and the top selection transistor 332-T. In this example, current flows from the BL pad 872-1 through the through array contact (TAC) 770, the corresponding bit line 341, the corresponding memory string 212, ACS 880, ACS grid 882, node 887, transistor 850-N2 flows to SL pad 872-3 (or reverse flow, depending on the applied voltage on the Vdd pad and SL pad). The current may also flow through one or more vertical contact structures 456/vertical contact structures 556 and/or lateral wires 458/transverse wires 558. In some embodiments, the parasitic resistance of the current path described here is much smaller than the inherent resistance of the target storage cell 340, and thus can be ignored. In some embodiments, the parasitic resistance of the current path can be extracted through curve fitting. In this way, the component parameters of the target storage unit can be obtained, and the programming status can be verified.

In some embodiments, the current of multiple storage units can be measured by adding multiplexer and decoder circuits, which is known to those skilled in the art.

In the second method and the third method, according to some embodiments of the present invention, the storage cell current can be measured indirectly through the Vdd pad 872-2 and the SL pad 872-3. In this method, the storage cell current can be obtained by calculating the difference between the measured current before and after the target storage cell is turned on.

In some embodiments, a second test voltage (for example, from 0 volts (V) to 10 volts (V)) may be applied to the Vdd pad 872-2. In this example, the SL pad 872-3 can be disconnected from the source line driver, and the SL pad 872-3 can be connected to an external ground node. In some embodiments, the SL pad 872-3 may be connected to another external power source with a first test voltage (for example, from 0 volts (V) to 10 volts (V)) different from the Vdd pad 872-2 . In some embodiments, the current at the Vdd pad 872-2 can be measured. In some embodiments, the current at the SL pad 872-3 can be measured.

As with the first method, the transistor 850-N1 can be cut off, and then the ACS grid can be disconnected from the internal ground node 892-2, and the transistor 850-N2 can be turned on, and then the ACS grid and SL can be welded. An electrical path is formed between the disks 872-3.

和節點

處的各個輸出端。在這一示例中，可以對節點

供應從低到高電壓的資料信號，同時可以對其互補節點

供應從高到低電壓的資料信號。例如，可以使節點

從3V切換至0伏特（V），並且可以使節點

從0伏特（V）切換至3V。這樣，p溝道MOSFET 850-P3可以在閘極處接收到0伏特（V）之後被導通。在一些實施例中，兩個電晶體850-N4和850-N3可以被導通，進而允許建立從節點885跨越鍵合介面674（透過互連導通孔（VIA） 472/572）抵達位元線341的導電通路。在一些實施例中，電晶體850-N5可以被截止，進而使得沒有電流可以流經感測拴鎖器878。 In some embodiments, the transistor 850-P1 can be turned on to connect the Vdd pad 872-2 to the node 883. The transistor 850-P2 can be turned off, thereby disconnecting the other components and circuits of the page buffer 888 from the internal power supply at the node 890-2. In some embodiments, a data line (not shown) can be connected to the sensing latch 878 at the node

And node

At the various output terminals. In this example, the node

Supply data signals from low to high voltages, and can be complementary nodes

Supply data signals from high to low voltage. For example, you can make the node

Switch from 3V to 0 volts (V), and can make the node

Switch from 0 volts (V) to 3V. In this way, the p-channel MOSFET 850-P3 can be turned on after receiving 0 volts (V) at the gate. In some embodiments, the two transistors 850-N4 and 850-N3 can be turned on, thereby allowing the establishment of the slave node 885 across the bonding interface 674 (via the interconnect via (VIA) 472/572) to the bit line 341 The conductive path. In some embodiments, the transistor 850-N5 can be turned off, so that no current can flow through the sensing latch 878.

Therefore, it is possible to establish through the Vdd pad 872-2 through the transistor 850-P1, node 883, transistor 850-P3, node 885, transistor 850-N4/transistor 850-N3, interconnect via (VIA) 472 /Interconnection via (VIA) 572, corresponding bit line 341, corresponding memory string 212, ACS 880, ACS grid 882, interconnection via (VIA) 572/interconnection via (VIA) 472, node 887 Current path to SL pad 872-3. Current can also flow in the opposite direction, depending on the voltage applied on the Vdd pad 872-2 and the SL pad 872-3.

In the second method and the third method, the target storage unit and the corresponding character line can be selected in a similar manner to the first method. However, only in the second and third methods, the measurement current flows through additional transistors and current paths. Therefore, in order to accurately determine the current passing through the target storage cell, the current flowing from the Vdd pad 872-2 to the SL pad 872-3 can be measured twice, that is, when the target storage cell is turned on, and the target When the storage unit is not turned on. The difference between these two measurements can remove possible parasitic (or leakage) circuit paths of non-ideal transistors.

In summary, the present invention describes various embodiments of methods for measuring the current of a storage cell of a three-dimensional memory. The direct and indirect measurement methods disclosed herein can be performed on a wafer, which utilizes existing circuits and/or structures without requiring additional design or manufacturing steps. Therefore, the programming and erasure of the storage unit can be verified through the production line test. The yield of the die can be screened and stored at the wafer level before dicing and packaging. In this way, the manufacturing cost can be reduced.

In an embodiment of the present invention, a method for measuring the current of a storage unit in a three-dimensional (3D) memory device is provided. The method includes applying a first test voltage to a source line pad of a peripheral circuit of a 3D memory device, wherein the source line pad is electrically connected to a common source of a 3D storage array of the 3D memory device The peripheral circuit formed on the first substrate and the 3D storage array formed on the second substrate are electrically connected through direct bonding. The method further includes applying a second test voltage to the bit line pads of the 3D storage array, wherein the bit line pads and the 3D storage array are formed on opposite sides of the second substrate, and the bit The wire pads are electrically connected to the bit wires of the storage unit through the array contacts. The method further includes applying the operation step voltage to the word line of the storage unit, wherein the word line is electrically connected to the control gate of the storage unit. The method further includes applying a pass voltage to a word line of a memory cell that is not selected, and measuring a current flowing through the bit line pad or the source line pad.

Another aspect of the present invention provides a method for measuring the current of a storage unit in a three-dimensional (3D) memory device. The method includes applying a first test voltage to a source line pad of a peripheral circuit of a 3D memory device, wherein the source line pad is electrically connected to a common source of a 3D storage array of the 3D memory device The peripheral circuit formed on the first substrate and the 3D storage array formed on the second substrate are electrically connected through direct bonding. The method further includes applying a second test voltage to a power supply pad, wherein the power supply pad is electrically connected to a page buffer of a peripheral circuit, and the page buffer is configured to provide temporary storage for the storage unit. The method further includes applying the operation step voltage to the word line of the storage unit, wherein the word line is electrically connected to the control gate of the storage unit. The method further includes applying a pass voltage to a word line of a memory cell that is not selected, and detecting a current flowing through the power supply pad or the source line pad.

The above description of specific embodiments will fully demonstrate the general nature of the present invention, so that others can easily analyze such specific embodiments without undue experimentation and without departing from the general concept of the present invention. Various applications of the embodiments are modified and/or adjusted. Therefore, based on the teachings and guidance presented herein, such adjustments and modifications are intended to be within the meaning and scope of equivalents of the embodiments disclosed herein. It should be understood that the terms or terms in this article are for illustrative purposes, not for limitation, so the terms or terms in this specification will be interpreted by the skilled person in accordance with the teaching and guidance.

The embodiments of the present invention have been described above with the help of functional building blocks, which exemplify the implementation of specified functions and their relationships. The boundaries of these functional building blocks are arbitrarily defined in this article for the convenience of description. Alternative boundaries can be defined as long as their designated functions and relationships are appropriately performed.

The content of the invention and the abstract part may describe one or more of the invention conceived by the inventor, but not all exemplary embodiments. Therefore, it is not intended to limit the scope of the invention and the attached patent application in any way.

The breadth and scope of the present invention should not be limited by any of the above-mentioned exemplary embodiments, and should be limited only according to the following patent scope and equivalents. The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

:節點

:節點100: Three-dimensional (3D) memory device 101: Storage plane 103: Storage block 105: Peripheral area 108: Area 210: Step area 211: Channel structure area 212: Memory string (character line contact) 214: Contact structure 216 : Slot structure 216-1: slot structure 216-2: slot structure 218: storage finger 220: top selection gate cutout 222: dummy memory string 224: storage chip 300: three-dimensional (3D) storage array structure 330: substrate 331: Insulating film 332: lower selection gate 332-T: lower selection transistor 333: character line 333-1: control gate (character line) 333-2: control gate (character line) 333-3: control Gate (character line) 334: Top selection gate (TSG) 334-T: Top selection transistor 335: Membrane stack 336: Channel hole 337: Storage film 338: Channel layer 339: Core filling film 340: Storage unit 340-1: Storage unit 340-2: Storage unit 340-3: Storage unit 341: Bit line (BL) 343: Metal interconnection line 344: Doped source line area 400: Peripheral circuit (CMOS wafer ) 430: first substrate 430-1: first side 430-2: second side 450-1: peripheral element 450-2: peripheral element 450-3: peripheral element 451: gate stack 452: shallow trench isolation (STI) 453-1: source/drain 453-2: source/drain 453-3: drain 454-1: n-well 454-2: p-well 454-3: deep n-well 455: peripheral mutual Connection layer (first interconnection layer) 456: vertical contact structure 458: lateral wire 458-1: lateral wire 458-2: lateral wire 460: insulating layer 462: substrate contact 472: interconnect via (VIA) 500: 3D Storage array 530: second substrate 530-1: first surface 530-2: second surface 555: array interconnection layer (second interconnection layer) 556: vertical contact structure 558: lateral wire 560: insulating layer 562: substrate Contact 564: Conductor layer 566: Dielectric layer 568: Alternating conductor/dielectric stack 570: Bit line contact 572: Interconnect via (VIA) 600: 3D memory element 674: Bonding interface 676: Bonding Layer 700: 3D memory device 770: through array contact (TAC) 772: input/output (I/O) pad 800: 3D memory device 850-P1: p-channel MOSFET (transistor) 850-P2: p Channel MOSFET (the sixth transistor in the peripheral circuit) 850-P3: p-channel MOSFET (the third transistor in the peripheral circuit) 850-N1: n-channel MOSFET (the first transistor in the peripheral circuit) 850-N2: n-channel MOSFET (second transistor in the peripheral circuit) 850-N3: n-channel MOSFET (peripheral The fifth transistor of the circuit) 850-N4: n-channel MOSFET (the fifth transistor of the peripheral circuit) 850-N5: the n-channel MOSFET (the fourth transistor of the peripheral circuit) 850-N6: the n-channel MOSFET ( Transistor) 872-1: BL pad 872-2: Power supply pad (Vdd pad) 872-3: Source line (SL) pad 878: Sense latch 878-N1: n-channel MOSFET ( Transistor) 878-N2: n-channel MOSFET (transistor) 878-P1: p-channel MOSFET (transistor) 878-P2: p-channel MOSFET (transistor) 880: Array common source (ACS) 882: ACS grid 883: node 884: sensing node 885: node (sensing node) 886: storage page 887: node 888: page buffer 890-1: node 890-2: node 892-1: internal ground node 892- 2: Internal ground node 892-3: Internal ground node

:node

:node

The drawings incorporated herein and forming part of the specification illustrate embodiments of the present invention and together with the description are further used to explain the principles of the present invention, and enable those skilled in the relevant art to make and use the present invention. FIG. 1 shows a schematic top view of an exemplary three-dimensional (3D) storage die according to some embodiments of the present invention. FIG. 2 shows a schematic top view of a region of a 3D storage die according to some embodiments of the present invention. Figure 3 shows a perspective view of a portion of an exemplary 3D storage array structure according to some embodiments of the invention. Figure 4 shows a cross-sectional view of a peripheral circuit according to some embodiments of the present invention. Figure 5 shows a cross-sectional view of a storage array according to some embodiments of the invention. FIG. 6 shows a cross-sectional view of the 3D memory device after bonding the peripheral circuit and the storage array according to some embodiments of the present invention. FIG. 7 shows a cross-sectional view of a 3D memory device in a certain process stage according to some embodiments of the present invention. FIG. 8 shows a circuit for measuring the current of a 3D memory device according to some embodiments of the present invention. When considering the accompanying drawings, the features and advantages of the present invention will become more apparent through the detailed description set forth below. In the accompanying drawings, similar reference numerals are always used to denote corresponding elements. In the drawings, similar reference signs generally indicate equivalent, functionally similar, and/or structurally similar elements. In the corresponding reference numeral, the leftmost bit indicates the figure where the element first appears. The embodiments of the present invention will be described with reference to the drawings.

212: memory string (character line contact)

332: Lower selection gate

332-T: Select the transistor at the bottom

333: Character line

334: Top Select Gate (TSG)

334-T: Top select transistor

340: storage unit

341: bit line (BL)

344: doped source line region

400: Peripheral circuit (CMOS wafer)

456: Vertical contact structure

458: Transverse wire

472: Interconnect Via (VIA)

500: 3D storage array

530: second base

556: Vertical contact structure

558: Transverse wire

572: Interconnect Via (VIA)

674: Bonding Interface

676: Bonding layer

770: Through Array Contact (TAC)

800: 3D memory device

850-P1: p-channel MOSFET (transistor)

850-P2: p-channel MOSFET (the sixth transistor of the peripheral circuit)

850-P3: p-channel MOSFET (the third transistor of the peripheral circuit)

850-N1: n-channel MOSFET (the first transistor of the peripheral circuit)

850-N2: n-channel MOSFET (second transistor for peripheral circuits)

850-N3: n-channel MOSFET (the fifth transistor in the peripheral circuit)

850-N4: n-channel MOSFET (the fifth transistor in the peripheral circuit)

850-N5: n-channel MOSFET (the fourth transistor of the peripheral circuit)

850-N6: n-channel MOSFET (transistor)

872-1: BL pad

872-2: Power supply pad (Vdd pad)

872-3: Source line (SL) pad

878: Sense Latch

878-N1: n-channel MOSFET (transistor)

878-N2: n-channel MOSFET (transistor)

878-P1: p-channel MOSFET (transistor)

878-P2: p-channel MOSFET (transistor)

880: Array Common Source (ACS)

882: ACS grid

883: Node

884: sensor node

885: Node (sensing node)

886: save page

887: Node

888: page buffer

890-1: Node

890-2: Node

892-1: internal ground node

892-2: Internal ground node

892-3: internal ground node

D : node

:節點

:node

Claims (20)

A method for measuring the current of a storage unit in a three-dimensional (3D) memory device includes: A first test voltage is applied to a source line pad of a peripheral circuit of the 3D memory device, wherein: The source line pad is electrically connected to a common source line of a 3D storage array of the 3D memory device; and The peripheral circuit formed on a first substrate and the 3D storage array formed on a second substrate are electrically connected by direct bonding; A second test voltage is applied to the bit line pads of the 3D storage array, wherein the bit line pads and the 3D storage array are formed on opposite sides of the second substrate, and the The bit line pad is electrically connected to the bit line of the storage unit by using at least one through-array contact; Applying an operation step voltage to a word line of the storage unit, wherein the word line is electrically connected to a control gate of the storage unit; Applying a pass voltage to another word line of the unselected memory cell; and Measure the current flowing through the bit line pad or the source line pad. The method according to item 1 of the scope of patent application, wherein applying the second test voltage includes applying a voltage between 0 volts (V) and 10 volts (V). The method according to claim 1, wherein applying the first test voltage includes applying a voltage of 0 volts (V). The method according to item 1 of the scope of patent application, wherein applying the operating step voltage includes applying a voltage between 0.5 volt (V) and 5 volt (V). The method according to item 1 of the scope of patent application, wherein applying the pass voltage includes applying a voltage between 0 volts (V) and 10 volts (V). According to the method described in item 1 of the scope of patent application, it also includes: Disconnecting the common source line from an internal ground node through a first transistor of the peripheral circuit; and Through a second transistor of the peripheral circuit, the common source line and the source line pad are electrically connected. According to the method described in item 1 of the scope of patent application, it also includes: A switching voltage is applied to a lower selection gate and a top selection gate of a memory string corresponding to the storage cell. The method according to item 7 of the scope of patent application, wherein applying the switching voltage includes applying a voltage between 0.5 volt (V) and 5 volt (V). According to the method described in item 1 of the scope of patent application, it also includes: Through a doped source line region and an array common source, the common source line and a source terminal of a memory string of the storage unit are electrically connected. The method according to claim 1, wherein the through-array contact passing through the second substrate is arranged between the bit line pad and the bit line so that the bit The line pad and the bit line are in electrical contact with each other. According to the method described in item 1 of the scope of patent application, it also includes: The source line pad is electrically connected to the common source line of the 3D storage array through one or more interconnect vias (VIA) at a bonding interface. A method for measuring the current of a storage unit in a three-dimensional (3D) memory device includes: Applying a first test voltage to a source line pad of a peripheral circuit of the 3D memory device, wherein The source line pad is electrically connected to a common source line of a 3D storage array of the 3D memory device; and The peripheral circuit formed on a first substrate and the 3D storage array formed on a second substrate are electrically connected by direct bonding; Applying a second test voltage to a power supply pad, wherein the power supply pad is electrically connected to a page buffer of the peripheral circuit, and the page buffer is configured to provide temporary storage for the storage unit; Applying an operation step voltage to a word line of the storage unit, wherein the word line is electrically connected to a control gate of the storage unit; Applying a pass voltage to another word line of the memory cell that is not selected; and Detect current flowing through the power supply pad or the source line pad. The method according to claim 12, wherein applying the first test voltage includes applying a voltage between 0 volts (V) and 10 volts (V). The method according to claim 12, wherein applying the second test voltage includes applying a voltage between 0 volts (V) and 10 volts (V). The method according to item 12 of the scope of patent application, wherein applying the operating step voltage includes applying a voltage between 0.5 volt (V) and 5 volt (V). The method according to item 12 of the scope of patent application, wherein applying the penetration test voltage includes applying a voltage between 0 volts (V) and 10 volts (V). According to the method described in the 12th scope of the patent application, it also includes: Disconnecting the common source line from an internal ground node through a first transistor of the peripheral circuit; and Through a second transistor of the peripheral circuit, the common source line and the source line pad are electrically connected. According to the method described in item 12 of the scope of patent application, it also includes: A data signal is provided to a first output terminal of a sensing latch of the page buffer, wherein the data signal is configured to turn on a third transistor of the peripheral circuit for the The electrical connection between the power pad and a sensing node; and A fourth transistor of the peripheral circuit is turned off, so that a second output terminal of the sensing latch is electrically disconnected from the sensing node. According to the method described in item 18 of the scope of patent application, it also includes: Through a fifth transistor of the peripheral circuit, the sensing node is electrically connected with the bit line of the storage unit. According to the method described in item 12 of the scope of patent application, it also includes: Through a sixth transistor of the peripheral circuit, the page buffer is electrically disconnected from an internal power source.

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