JP7177291B2 - Cell current measurement for 3D memory - Google Patents

Description

TECHNICAL FIELD This disclosure relates generally to the field of semiconductor technology, and more particularly to methods for forming three-dimensional (3D) memories.

As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling of planar memory cells is difficult due to process technology limitations and reliability issues. to face. Three-dimensional (3D) memory architectures can address density and performance limitations in planar memory cells.

In 3D memory, memory cells can be programmed or erased for data storage. Sometimes multiple states can be stored in a single memory cell. Therefore, verification of device parameters of memory cells after programming or erasing is necessary. Generally, the state and device parameters of a memory cell can be derived from the current flowing through the memory cell.

U.S. Patent Application No. 16/163,274

Therefore, a need exists for a method for measuring memory cell current that is easy to implement and can provide accurate data.

Embodiments of three-dimensional (3D) memory devices and methods for current measurement are described in this disclosure.

One aspect of the present disclosure provides a method for measuring memory cell current in a three-dimensional (3D) memory device. The method comprises applying a first test voltage to a source line pad of a peripheral circuit of the 3D memory device, the source line pad being electrically coupled to a common source line of a 3D memory array of the 3D memory device; A step is included in which the peripheral circuitry formed on the first substrate and the 3D memory array formed on the second substrate are electrically coupled through direct coupling. The method includes applying a second test voltage to bitline pads of a 3D memory array, the bitline pads and the 3D memory array being formed on opposite sides of a second substrate, the bitline pads passing through A step is also included in which the array contacts are used to electrically couple the bit lines of the memory cells. The method further includes applying an operating voltage to a word line of the memory cell, the word line electrically coupled to a control gate of the memory cell. The method also includes applying a pass voltage to the wordlines of the unselected memory cells and measuring the current flowing through the bitline or sourceline pads.

In some embodiments, applying the second test voltage comprises applying a voltage between 0V and 10V.

In some embodiments, applying the first test voltage includes applying a voltage of 0V.

In some embodiments, applying the operating voltage comprises applying a voltage between 0.5V and 5V.

In some embodiments, applying a pass voltage includes, but is not limited to, applying a voltage between 0V and 10V.

In some embodiments, the method comprises electrically disconnecting the common source line and internal ground by a first transistor of the peripheral circuit; and electrically coupling with the line pads.

In some embodiments, the method further includes applying a switching voltage to lower select gates and upper select gates corresponding to a memory string of memory cells. In some embodiments, applying a switching voltage includes, but is not limited to, applying a voltage between 0.5V and 5V.

In some embodiments, the method further includes electrically coupling the common source line and the source terminals of the memory strings of the memory cells through the doped source line region and the array common source.

In some embodiments, through array contacts through the second substrate are configured to form electrical contact between the bitline pads and the bitlines.

In some embodiments, the method also includes electrically coupling the source line pad with a common source line of the 3D memory array through one or more interconnect VIA at the bonding interface.

Another aspect of the present disclosure provides a method of measuring memory cell current in a three-dimensional (3D) memory device. The method comprises applying a first test voltage to a source line pad of a peripheral circuit of the 3D memory device, the source line pad being electrically coupled to a common source line of a 3D memory array of the 3D memory device; A step is included in which the peripheral circuitry formed on the first substrate and the 3D memory array formed on the second substrate are electrically coupled through direct coupling. The method includes applying a second test voltage to a power source pad, the power source pad electrically coupled to a page buffer of the peripheral circuit, the page buffer providing temporary storage for the memory cell. Also includes a step comprising: The method further includes applying an operating voltage to a word line of the memory cell, the word line electrically coupled to a control gate of the memory cell. The method also includes applying a pass voltage to the word lines of the unselected memory cells and sensing current flowing through the power source or source line pads.

In some embodiments, the method comprises electrically disconnecting the common source line and internal ground by a first transistor of the peripheral circuit; and electrically coupling with the line pads.

In some embodiments, the method comprises providing a first data signal to a first output of a sense latch of the page buffer, the first data signal being between the power source pad and the sense node. a step configured to switch on a third transistor of the peripheral circuit for electrical coupling between and to electrically disconnect the second output of the sense latch and the sense node; , and switching off the fourth transistor of the peripheral circuit. In some embodiments, the method further includes electrically coupling the sense node and the bit line of the memory cell by a fifth transistor of the peripheral circuitry.

In some embodiments, the method also includes electrically decoupling the page buffer and the internal power source by a sixth transistor of the peripheral circuit.

Other aspects of the disclosure can be understood by one of ordinary skill in the art in light of the description, claims and drawings of the disclosure.

The accompanying drawings, which are incorporated in and form a part of the specification, illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure and It is further provided to enable traders to prepare and use the present disclosure.

1 is a schematic top-down view of an exemplary three-dimensional (3D) memory die, according to some embodiments of the present disclosure; FIG. FIG. 3A is a schematic top down view of an area of a 3D memory die, according to some embodiments of the present disclosure; FIG. 3 is a perspective view of a portion of an exemplary 3D memory array structure, according to some embodiments of the present disclosure; FIG. 3 is a cross-sectional view of peripheral circuitry, according to some embodiments of the present disclosure; FIG. 3 is a cross-sectional view of a memory array, according to some embodiments of the present disclosure; FIG. 3B is a cross-sectional view of a 3D memory device after combining peripheral circuitry and a memory array according to some embodiments of the present disclosure; 3A-3D are cross-sectional views of a 3D memory device at particular process stages, according to some embodiments of the present disclosure; FIG. 4 is a diagram of a circuit for measuring current in a 3D memory device according to some embodiments of the present disclosure;

Features and advantages of the present invention will become more apparent from the detailed description set forth when taken in conjunction with the drawings, in which like numerals identify corresponding elements throughout. In the drawings, like numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the most significant digit in the corresponding number.

Embodiments of the present disclosure are described with reference to the accompanying drawings.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that the present disclosure can also be employed in various other applications.

It should be noted that in this specification, references to "one embodiment," "an embodiment," "example embodiment," "some embodiments," and the like refer to the specific features, It is meant that although a structure or property may be included, not all embodiments may include a particular feature, structure or property. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when specific features, structures, or characteristics are recited in the context of an embodiment, such features, structures, or characteristics may or may not be explicitly recited in other embodiments. It is within the knowledge of those skilled in the art to influence the relationship between

Generally, the terminology can be understood, at least in part, from its use in context. For example, the term "one or more," as used herein, is used, at least in part, to describe any feature, structure, or property in the singular sense. or may be used to describe a combination of features, structures, or properties in more than one sense. Similarly, terms such as "one" or "the" can also be understood to convey usage in the singular or to convey usage in the plural, depending at least in part on the context. Also, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, but instead, again depending at least in part on the context, necessarily explicitly Additional factors not listed may be allowed to be present.

The meanings of "to," "above," and "across" in this disclosure do not mean that "to" only means "directly to," should be construed in a broader manner that also includes the meaning of being "in" something with features or layers of. Further, "above" or "over" does not mean only "above" or "over" anything, but rather anything without intermediate features or layers between them. It can also include the meaning of being "above" or "over" (that is, directly to) something.

Furthermore, spatially relative terms such as “below,” “below,” “below,” “above,” and “above” are used herein to May be used for ease of description to describe the relationship of one element or feature to other elements or features as indicated. Spatially relative terms are intended to cover different orientations of the device during use or process steps in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptions used herein may be similarly interpreted accordingly.

As used herein, the term "substrate" refers to the material to which subsequent layers of material are applied. The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, so semiconductor devices are formed on the top side of the substrate unless otherwise stated. The bottom surface is opposite the top surface, so the bottom side of the substrate is opposite the top side of the substrate. The substrate itself may be patterned. The material added over the substrate may be patterned or left unpatterned. Further, substrates can include a wide variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be formed from a non-conductive material such as glass, plastic, or a sapphire wafer.

As used herein, the term "layer" refers to a portion of material that includes regions of thickness. The layer has a top side and a bottom side, the bottom side of the layer being relatively close to the substrate and the top side being relatively far from the substrate. A layer may extend over the entirety of an underlying or overlying structure or may have an extent less than that of an underlying or overlying structure. Further, a layer can be a region of homogeneous or non-homogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can be positioned between any set of horizontal planes between or in the top and bottom surfaces of a continuous structure. The layers can extend horizontally, vertically and/or along tapered surfaces. A substrate can be a layer, can include one or more layers, and/or can have one or more layers on, above, and/or below. A layer may include multiple layers. For example, interconnect layers include one or more conductive and contact layers (where contacts, interconnect lines, and/or vertical interconnect accesses (VIAs) are formed), and one or more dielectric layers. can contain.

In this disclosure, for ease of description, "hierarchy" is used to refer to elements of substantially the same height along the vertical direction. For example, a word line and an underlying gate dielectric layer can be referred to as a "level," and a word line and an underlying insulating layer can both be referred to as a "level," with words of substantially the same height. A line may be referred to as a "hierarchy of word lines" or similar, and so on.

As used herein, the term "nominal/nominally" refers to a value above and/or below a desired value during an aspect of designing a product or during a process. It refers to the desired or target value of a property or parameter for a component or process step, set together with the range of . The range of values may be due to slight variations or tolerances in the manufacturing process. As used herein, the term "about" indicates the value of a given quantity that can vary based on the particular technology node associated with the subject semiconductor device. . Based on a particular technology node, the term "about" refers to a given amount of A value can be indicated.

In this disclosure, the terms "horizontal/horizontally/transverse/laterally" mean nominally parallel to the lateral surface of the substrate, and the terms "vertical" or "vertically" refer to the lateral surface of the substrate. means nominally perpendicular to

As used herein, the term "3D memory" refers to vertically oriented memory cell transistors in a laterally oriented substrate such that memory strings extend vertically with respect to the substrate. We refer to a three-dimensional (3D) semiconductor device having strings (herein referred to as “memory strings”, such as NAND strings).

Various embodiments according to the present disclosure provide circuits and methods for current measurement in 3D memory devices. In a 3D memory device, memory cell current can be measured using existing circuits or using structures made with existing fabrication processes. Manufacturing costs can be reduced by not relying on circuits designed solely for measurement purposes.

FIG. 1 illustrates a top-down view of an exemplary three-dimensional (3D) memory device 100, according to some embodiments of the present disclosure. The 3D memory device 100 may comprise one or more memory planes 101 , which may be memory chips (packages), memory dies, or any portion of a memory die, and which may each comprise multiple memory blocks 103 . The same or simultaneous steps can be performed on each memory plane 101 . A memory block 103, which can be megabytes (MB) in size, is the minimum size for performing the deletion process. As shown in FIG. 1, an exemplary 3D memory device 100 comprises four memory planes 101, each memory plane 101 comprising six memory blocks 103. As shown in FIG. Each memory block 103 may comprise a plurality of memory cells, each addressable through interconnects such as bitlines and wordlines. Bit lines and word lines can be arranged vertically (eg, in rows and columns, respectively) to form an array of metal lines. The direction of the bit lines and the direction of the word lines are marked "BL" and "WL" in FIG. In this disclosure, memory block 103 is also referred to as a "memory array" or "array." A memory array is the core area in a memory device and implements the storage function.

The 3D memory device 100 also comprises a peripheral region 105, which is the region surrounding the memory plane 101. As shown in FIG. Peripheral area 105 contains many digital, analog, and/or mixed-signal circuits to support the function of the memory array, such as page buffers, row decoders, column decoders, and sense amplifiers. Peripheral circuits use active and/or passive semiconductor devices such as transistors, diodes, capacitors, resistors, etc., as will be apparent to those skilled in the art.

It should be noted that the arrangement of memory planes 101 in 3D memory device 100 and the arrangement of memory blocks 103 in each memory plane 101 shown in FIG. not something to do.

Referring to FIG. 2, an enlarged top down view of region 108 in FIG. 1 is shown according to some embodiments of the present disclosure. Region 108 of 3D memory device 100 may include staircase region 210 and channel structure region 211 . Channel structure region 211 may comprise an array of memory strings 212 each including a plurality of stacked memory cells. The staircase region 210 may comprise a staircase structure and an array of contact structures 214 formed in the staircase structure. In some embodiments, multiple slit structures 216 extending in the WL direction across channel structure region 211 and staircase region 210 can divide the memory block into multiple memory fingers 218 . At least some of the slit structures 216 can serve as common source contacts (eg, array common source) for the array of memory strings 212 in the channel structure region 211 . A top select gate break 220 can be placed in the middle of each memory finger 218, for example, to divide the top select gate (TSG) of the memory finger 218 into two parts, thereby A memory finger can be divided into two memory slices 224, and memory cells in memory slices 224 that share the same word line form programmable (read/write) memory pages. While the erase process of 3D NAND memory may be performed at the level of memory blocks, read and write operations may be performed at the level of memory pages. A memory page can be kilobytes (KB) in size. In some embodiments, region 108 also includes dummy memory strings 222 for process variation control during fabrication and/or for additional mechanical support.

FIG. 3 illustrates a perspective view of a portion of an exemplary three-dimensional (3D) memory array structure 300, according to some embodiments of the present disclosure. The memory array structure 300 forms a hierarchy of a substrate 330, an insulating film 331 over the substrate 330, a Lower Select Gate (LSG) 332 over the insulating film 331, and a stack 335 of alternating conductive and dielectric layers. and multiple hierarchies of control gates 333, also referred to as "word lines (WL)", stacked above the LSGs 332 to enable the Dielectric layers adjacent to the control gate level are not shown in FIG. 3 for clarity.

The control gates of each layer are separated by slit structures 216-1 and 216-2 through laminated film 335. FIG. Memory array structure 300 also includes a hierarchy of top select gates (TSG) 334 across the stack of control gates 333 . The stack of TSGs 334, control gates 333, and LSGs 332 are also referred to as "gate electrodes." Memory array structure 300 further comprises memory strings 212 and doped source line regions 344 in portions of substrate 330 between adjacent LSGs 332 . Each memory string 212 includes a channel hole 336 extending through an insulating film 331 and a stack 335 of alternating conductive and dielectric layers. The memory string 212 also comprises a memory film 337 on the sidewalls of the channel hole 336 , a channel layer 338 spanning the memory film 337 , and a core fill film 339 surrounded by the channel layer 338 . A memory cell 340 can be formed at the intersection of the control gate 333 and the memory string 212 . Memory array structure 300 further comprises a plurality of bit lines (BL) 341 coupled with memory strings 212 across TSG 334 . The memory array structure 300 also includes a plurality of metal interconnect lines 343 coupled with the gate electrodes through a plurality of contact structures 214. FIG. The edges of the film stack 335 are configured in a stepped fashion to allow electrical connection to each layer of gate electrodes.

In FIG. 3, three hierarchies of control gates 333-1, 333-2, and 333-3 are shown along with one hierarchy of TSGs 334 and one hierarchy of LSGs 332 for purposes of illustration. In this example, each memory string 212 may comprise three memory cells 340-1, 340-2 and 340-3 corresponding to control gates 333-1, 333-2 and 333-3 respectively. In some embodiments, the number of control gates and the number of memory cells may be greater than three to increase storage capacity. Memory array structure 300 may include other structures such as TSG cuts, common source contacts (ie, array common source), and dummy memory strings, for example. These structures are not shown in FIG. 3 for simplicity.

In order to achieve greater storage densities, the number of vertical WL stacks or the number of memory cells per memory string in 3D memory can be significantly increased, for example from 24 stacked WL layers (i.e. 24L) to 128 or more layers. It has increased. To further reduce the size of 3D memory, memory arrays can be stacked on top of peripheral circuits and vice versa. For example, peripheral circuits can be fabricated on a first wafer and memory arrays can be fabricated on a second wafer. The memory arrays and peripheral circuits can then be connected through various interconnects by bonding the first and second wafers together. Thereby, not only can 3D memory density be increased, but communication between the peripheral circuits and the memory array can be made with greater bandwidth and higher efficiency because interconnect lengths can be shorter through substrate (wafer) bonding. A small power consumption can be achieved. A detailed structure and method for forming a 3D memory device, in which the peripheral circuitry is coupled with the memory array through wafer bonding, is described in "Embedded Pad Structures of Three-Dimensional Memory Devices and Fabrication Methods Thereof" (U.S. patent application Ser. 163,274, filed Oct. 17, 2018), which is incorporated herein by reference in its entirety.

FIG. 4 illustrates a cross-section of an exemplary peripheral circuit 400 of a 3D memory device, according to some embodiments of the present disclosure. Peripheral circuitry 400 may comprise a first substrate 430 . In some embodiments, the first substrate 430 has surfaces on top and bottom sides (first side 430-1 and second side 430-2, respectively, or front and back sides). include.

Peripheral circuit 400 may comprise one or more peripherals 450 (eg, 450-1 and 450-2) on first side 430-1 of first substrate 430. As shown in FIG. Peripheral devices 450 may include any suitable semiconductor devices such as, for example, metal oxide semiconductor field effect transistors (MOSFETs), bipolar junction transistors (BJTs), diodes, resistors, capacitors, inductors. Among other semiconductor devices, p-type and/or n-type MOSFETs (ie, CMOS) are widely implemented in logic circuit design and are used as examples for peripheral device 450 in this disclosure. Peripheral circuitry 400 is also referred to as CMOS wafer 400 in this example.

Peripherals 450 can be either p-channel MOSFETs (eg, 450-1) or n-channel MOSFETs (eg, 450-2) by, but not limited to, shallow trench isolation (STI) 452. Wells 454 (eg, n-well 454-1, p-well 454-2, deep n-well 454-3, etc.) formed in the surrounded active device area, n-type or p-type doped active device area, gate A gate stack 451 may include a dielectric, gate conductor, and/or gate hard mask. Peripheral device 450 may also include source/drains 453 (eg, 453-1, 453-2, etc.) located on each side of the gate stack. In some embodiments, peripheral device 450 can be a high voltage MOSFET (eg, 450-3) with a lightly doped drain 453-3. The structure and method of fabrication of peripheral device 450 are known to those skilled in the art and are incorporated herein in their entirety.

In some embodiments, peripheral circuitry 400 includes peripheral circuits 450 to provide electrical connections between different peripheral devices 450 and external devices (eg, power supplies, other chips, I/O devices, etc.). A peripheral interconnect layer 455 (or first interconnect layer) and an insulating layer 460 may be provided on the first side 430-1 above the device 450. FIG. Peripheral interconnect layer 455 includes one or more interconnects, such as one or more vertical contact structures 456 and one or more horizontal conductive lines 458 (eg, 458-1, 458-2, etc.). It may comprise an interlocking structure. Contact structures 456 and conductive lines 458 may broadly comprise any suitable type of interconnect, such as middle-of-line (MOL) interconnects and back-end-of-line (BEOL) interconnects. In some embodiments, peripheral circuit 400 also includes one or more substrate contacts 462 that provide electrical coupling to first substrate 430 .

In some embodiments, multiple peripherals 450 may be used to form any digital, analog, and/or mixed-signal circuits for operation of peripheral circuit 400 . Peripheral circuitry 400 may perform, for example, row/column decoding, timing and control, and reading, writing, and deleting data from the memory array.

FIG. 5 illustrates a cross-sectional view of an exemplary 3D memory array 500, according to some embodiments of the present disclosure. The 3D memory array 500 can be a 3D NAND memory array and can comprise a second substrate 530 (with a first surface 530-1 and a second surface 530-2), memory cells 340 and array interconnects. A layer 555 (or a second interconnect layer) is formed on the first surface 530-1 of the second substrate 530. As shown in FIG. Array interconnect layer 555 may be similar to peripheral interconnect layer 455 . For example, the interconnect structures (e.g., contact structures 556 and conductive lines 558) of array interconnect layer 555 and insulating layer 560 correspond to the interconnect structures (e.g., contact structures 456, conductive lines 458) of peripheral interconnect layer 455 and the insulating layers 560, respectively. Similar to insulating layer 460 .

In some embodiments, 3D memory array 500 may be a memory array for 3D NAND flash memory in which memory cells 340 may be vertically stacked as memory strings 212 . Memory string 212 extends through an alternating conductive/dielectric stack 568 including a plurality of conductive layers 564 and dielectric layers 566 .

In some embodiments, the array device further comprises a plurality of contact structures 214 for wordlines (also called wordline contacts) in the staircase region. Each wordline contact structure 214 can form electrical contact with a corresponding conductive layer 564 in alternating conductive/dielectric stack 568 to individually control memory cell 340 .

As shown in FIG. 5, 3D memory array 500 also includes bitline contacts 570 formed over memory strings 212 to provide individual access to the channel layers of memory strings 212 . Conductive lines coupled to wordline contact structures 214 and bitline contacts 570 connect wordlines (WL) and bitlines (BL) of 3D memory array 500 (eg, WL333 and BL341 shown in FIG. 3). ) respectively. Typically, word lines (WL) and bit lines (BL) are laid perpendicular to each other (eg, in rows and columns, respectively) to form an "array" of memory.

In some embodiments, the 3D memory array 500 also comprises substrate contacts 562 of the second substrate 530. FIG. Substrate contacts 562 can provide electrical connections to the second substrate 530 of the 3D memory array 500 .

FIG. 6 illustrates a cross-sectional view of an exemplary 3D memory device 600, according to some embodiments of the present disclosure. The 3D memory device 600 comprises a peripheral circuit 400 fabricated on a first substrate 430 and a 3D memory array 500 fabricated on a second substrate 530 . In this example, 3D memory array 500 is flipped upside down and bonded to peripheral circuitry 400 with direct or hybrid bonding. At coupling interface 674, peripheral circuitry 400 and 3D memory array 500 are electrically coupled through a plurality of interconnect VIA's 472/572. Any conductive line 458 or contact structure 456 in the peripheral interconnect layer 455 can thereby be electrically coupled with any conductive line 558 or contact structure 556 in the array interconnect layer 555 . In other words, the peripheral circuit 400 and the 3D memory array 500 can be electrically coupled.

Through combination, the 3D memory device 600 can function like a 3D memory, with the peripheral circuits and memory array fabricated on the same substrate (as shown in FIG. 1). By stacking the 3D memory array 500 and the peripheral circuitry 400 on top of each other, the density of the 3D memory device 600 can be increased. On the other hand, the bandwidth of the 3D memory device 600 can be increased because the interconnection distance between the peripheral circuit 400 and the 3D memory array 500 can be reduced using a stacked design.

FIG. 7 is a cross-sectional view of a 3D memory device 700 according to some embodiments of the present disclosure. The 3D memory device 700 includes through array contacts (TAC) 770 and input/output (I/O) pads 772 formed on the second side 530-2 of the second substrate 530 of the 3D memory device 600 in FIG. and In some embodiments, second substrate 530 may be thinned prior to forming TAC 770 and I/O pads 772 . Note that the structure and number of TAC 770 and I/O pads 772 are not limited to the example shown in FIG.

In some embodiments, the TAC 770 can be electrically coupled to any of the contact structures 556 or any of the conductive lines 558 of the array interconnect layer 555, thereby allowing the second side 530- 2, electrical connections can be made with either the wordlines or bitlines of the 3D memory array 500 . In some embodiments, TAC 770 may be electrically coupled to either contact structure 456 or conductive line 458 of peripheral interconnect layer 455 through one or more of interconnect vias 472 or 572. good. Thereby, from the second side 530 - 2 of the second substrate 530 , an electrical connection can be made between the I/O pads 772 , the TAC 770 and any of the peripherals 450 of the peripheral circuit 400 . In some embodiments, TAC 770 and I/O pads 772 may be electrically coupled with substrate contacts 462 or 562 .

For 3D memory devices, accurate measurement of memory cell current is important for optimized memory design and operation, estimating memory cell sensing time, noise level, and memory cell device performance, for example. Previously, the memory cell current was measured indirectly using a current mirror circuit. However, accurate measurement of memory cell current through indirect methods can be difficult in circuit design. Inserting a current mirror circuit with a large area into a memory product chip introduces an area penalty in memory storage capacity and can also increase the manufacturing cost of the memory. Memory cell current may be measured directly through an external I/O pad with connections designed to bypass the page buffer circuitry. Therefore, to accurately measure memory cell current in three-dimensional (3D) memories without adding extra circuitry designed solely for this measurement purpose, thereby avoiding any area or performance penalties. There is a need for a method of

FIG. 8 shows a schematic circuit diagram of a 3D memory device 800 configured to provide cell current measurements, according to some embodiments of the present disclosure. 3D memory device 800 comprises a memory array wafer (eg, 3D memory array 500) bonded with a CMOS wafer (eg, peripheral circuitry 400) at bonding layer 676 and bonding interface 674. FIG. As previously described, the 3D memory array 500 comprises a plurality of memory strings 212, each memory string 212 having a plurality of memory cells 340 stacked together. Memory string 212 also includes at least one field effect transistor (MOSFET) at each end. For example, the field effect transistor closest to the second substrate 530 can be controlled by the lower select gate (LSG) 332, and is therefore referred to as the lower select transistor 332-T. The field effect transistor at the other end far away from the second substrate 530 can be controlled by a top select gate (TSG) 334 and is referred to as top select transistor 334-T. The stacked memory cells 340 can be controlled by control gates 333, which are coupled to word lines (not shown in FIG. 8) of the 3D memory device 800. FIG. The drain of top select transistor 334-T can be coupled to bit line 341, which can be made up of one or more conductive lines 558 and/or conductive structures 556 (as shown in FIG. 7). . The sources of lower select transistors 332-T can be coupled to wells (eg, doped source line regions 344) in second substrate 530 from which multiple array common sources (ACS) 880 are in electrical coupling with ACS mesh 882. Form. ACS mesh 882 can be shared by memory strings 212 throughout the memory block, also referred to as a common source line. ACS880 can be made from slit structure 216 (shown in FIGS. 2 and 3) with an additional conductive core, or can be made from substrate contacts 562 shown in FIG. It should be noted that the formation and configuration of wordlines, bitlines, ACSs, and ACS meshes are not limited to the configurations described above and may include other interconnect structures.

In some embodiments, the 3D memory device 800 further comprises a plurality of through array contacts (eg, TAC 770) coupling bitlines 341 with bitline (BL) pads 872-1. Bit line pad 872-1 may be similar to I/O pad 772 in FIG. In some embodiments, each bit line 341 may be electrically coupled to one BL pad 872-1. In some embodiments, TAC 770 may be coupled with bit line 341 through one or more of contact line 558 and contact structure 556 . In some embodiments, TAC 770 may also be coupled to one or more of interconnecting VIA 572 at coupling interface 674 . In some embodiments, interconnect VIA 572 of 3D memory array 500 may also be coupled to interconnect VIA 472 of peripheral circuit 400 . In some embodiments, the bitlines 341, wordlines (control gates 333), TSGs 334, LSGs 332, ACS meshes 882, and other structures in the 3D memory array 500 are the interconnection VIA 472 of the peripheral circuitry 400 and the 3D memory array 500. /572, one or more of contact structures 556, 456, and/or one or more of contact lines 558/458 to any circuit of peripheral circuit 400.

In NAND flash memory, read and write operations can be performed in memory pages, which contain memory cells that share the same word line. An exemplary memory page 886 is shown in FIG. During read and write operations, memory cells 340 in the same memory page 886 can be accessed simultaneously and cell data can be sent to the page buffer for temporary storage. In some embodiments, one page buffer may be tied to one bitline. In some embodiments, one page buffer may be shared between two adjacent bitlines. Cell data in the page buffer can be decoded using a column decoder (not shown).

A simplified schematic circuit diagram of page buffer 888 of 3D memory device 800 is shown in FIG. 8, according to some embodiments of the present disclosure. In this example, page buffer 888 may be formed in CMOS wafer 400 and coupled to bit line 341 across bonding interface 674 through interconnect VIA 472/572. In some embodiments, page buffer 888 comprises a sense latch 878 and a sense transistor (not shown) coupled at sensing node 884 . Page buffer 888 further comprises a power source pad 872-2 (also referred to as a Vdd pad) that provides electrical connection to page buffer 888 to a power source. The page buffer also comprises multiple transistors, eg n-channel MOSFETs 850-N3 through 850-N6 and p-channel MOSFETs 850-P1 through 850-P3.

およびDにおいて第1の出力部および第2の出力部を有する。各々のインバータの対はpチャネルMOSFETおよびnチャネルMOSFET(例えば、878-P1および878-N1)を備える。2つのpチャネルMOSFET878-P1および878-P2のソース端子はノード890-1において内部パワーソースに連結され、2つのnチャネルMOSFET878-N1および878-N2のソース端子は内部接地892-1に連結される。2つのインバータの第1および第2の出力部は、ノード

およびDと記され、反対(または相補的)のデータ信号を含む。例えば、ノードDが高い電位にあるとき、ノード

は低い電位とでき、逆もまた同様となる。センスラッチを形成するために、インバータの一方の対の出力部は、他方の対のトランジスタのゲートに連結され得る。例えば、ノードDにおける第2の出力部は、nチャネルMOSFET878-N1およびpチャネルMOSFET878-P1のゲートと連結され、ノード

における第1の出力部は、nチャネルMOSFET878-N2およびpチャネルMOSFET878-P2のゲートと連結される。 In some embodiments, sense latch 878 comprises two n-channel MOSFETs 878-N1 and 878-N2 and two p-channel MOSFETs 878-P1 and 878-P2, forming two pairs of inverters and node

and at D have a first output and a second output. Each inverter pair includes a p-channel MOSFET and an n-channel MOSFET (eg, 878-P1 and 878-N1). The source terminals of the two p-channel MOSFETs 878-P1 and 878-P2 are tied to the internal power source at node 890-1 and the source terminals of the two n-channel MOSFETs 878-N1 and 878-N2 are tied to the internal ground 892-1. be. The first and second outputs of the two inverters are connected to node

and D, containing opposite (or complementary) data signals. For example, when node D is at a high potential, node

can be at a lower potential and vice versa. The outputs of one pair of inverters may be coupled to the gates of the other pair of transistors to form a sense latch. For example, a second output at node D is coupled to the gates of n-channel MOSFET 878-N1 and p-channel MOSFET 878-P1, node

A first output at is coupled to the gates of n-channel MOSFET 878-N2 and p-channel MOSFET 878-P2.

に連結される。ノードDにおけるセンスラッチ878の他方の出力部はトランジスタ850-N6のゲートに連結され、一方、トランジスタ850-N6のドレイン端子はトランジスタ850-N5(周辺回路の第4のトランジスタとも称される)のソースと共有される。トランジスタ850-N6のソースは内部接地892-3に連結される。周辺回路の第5のトランジスタとも称される2つのnチャネルMOSFET850-N3および850-N4のソース/ドレイン端子は、ページバッファと、対応するビット線341との間の通信の制御において直列に連結される。 In some embodiments, the source of transistor 850-P1 is coupled to Vdd pad 872-2, and the drain is connected to transistors 850-P2 and 850-P3 (also referred to as the sixth and third transistors of the peripheral circuitry, respectively). is connected to node 883 shared with The other terminal (source) of transistor 850-P2 is coupled to the internal power source at node 890-2. In some embodiments, the internal power sources at nodes 890-1 and 890-2 may have the same voltage (eg, referred to as Vdd). The drain terminal of transistor 850-P3 is coupled to the source/drain terminals of transistors 850-N4 and 850-N5 at node 885, which is at the same potential as sensing node 884, also referred to as the sensing node. The gate of transistor 850-P3 is connected to one node of the output of sense latch 878.

connected to The other output of sense latch 878 at node D is coupled to the gate of transistor 850-N6, while the drain terminal of transistor 850-N6 is the drain terminal of transistor 850-N5 (also referred to as the fourth transistor of the peripheral circuitry). Shared with Source. The source of transistor 850-N6 is tied to internal ground 892-3. The source/drain terminals of two n-channel MOSFETs 850-N3 and 850-N4, also called the fifth transistor of the peripheral circuitry, are serially coupled in controlling communication between the page buffer and the corresponding bit line 341. be.

In some embodiments, the 3D memory device 800 also includes a source line (SL) pad 872-3 and two transistors (eg, n-channel MOSFETs 850-N1 and 850-N2) in the peripheral circuitry 400 to provide an n-channel The source terminals of MOSFETs 850-N1 (also referred to as peripheral circuitry first transistor) and 850-N2 (also referred to as peripheral circuitry second transistor) are connected to internal ground 892-2 and SL pad 872-3, respectively. connected to In some embodiments, internal grounds 892-1, 892-2, and 892-3 are electrically coupled to maintain the same potential. The drain terminals of n-channel MOSFETs 850-N1 and 850-N2 are coupled at node 887, which may be coupled to ACS mesh 882 of 3D memory array 500 through interconnect VIA472/572. In some embodiments, SL pad 872-3 can be used to couple to source line driver circuitry (not shown in FIG. 8). In this example, ACS mesh 882 can be tied to either internal ground 892-2 or the source line driver circuit by switching on or off transistors 850-N1 and 850-N2.

In some embodiments, Vdd pad 872-2 and SL pad 872-3 are connected via TAC 770, interconnect VIA 572/472, and/or contact structures 556/456 and/or conductive lines 558/458. 2 can be formed on the second surface 530-2 of the substrate 530; In some embodiments, Vdd pad 872-2 and SL pad 872-3 are through array contacts to first substrate 430, similar to the method used to form BL pad 872-1 and TAC770. It can be formed on the second surface 430-2 of the first substrate 430 (as shown in FIG. 7) in a penetrating manner.

In some embodiments, a memory cell after being programmed or erased can be verified by measuring the current flowing through the memory cell. According to this disclosure, the memory cell current of 3D memory device 800 can be measured using three methods.

In a first method, according to some embodiments of the present disclosure, memory cell current is reduced by applying a first test voltage (eg, external ground) to SL pad 872-3 and at BL pad 872-1. It can be measured directly by sweeping a second test voltage (eg, 0-10V). Switching SL pad 872-3 from the source line driver circuit (not shown) to external ground can be accomplished in many ways, such as by adding an additional switching transistor known to those skilled in the art. can be implemented.

In some embodiments, a bias (eg, between 1V and 5V) switches transistor 850-N2 so that memory cell current can flow between BL pad 872-1 and SL pad 872-3. can be applied to the gate of transistor 850-N2 to turn it on. A method is to apply another bias (eg, 0V) to the gate of transistor 850-N1 to turn off transistor 850-N1 so that the memory cell current can be disconnected from internal ground 892-2. Including further. By switching off transistor 850-N1, noise from peripheral circuitry 400 is avoided during memory cell current measurements.

In a first method, an operating voltage (eg, 0.5 V to 5 V) can be applied to the selected word line of the memory cell 340 of interest among the word lines 333, and an operating voltage (eg, 0 V to 5 V) can be applied to the unselected word lines. A pass voltage (V _pass ) high enough to switch on other memory cells in the same memory string 212 above the threshold voltage of a memory cell, such as 10V, can be applied. A high switching voltage (eg, 0.5V to 5V) can also be applied to TSG 334 and LSG 332 to switch on lower select transistor 334-T and upper select transistor 332-T. In this example, current flows from BL pad 872-1 through TAC770, corresponding BL341, corresponding memory string 212, ACS880, ACS mesh 882, node 887, transistor 850-N2, to SL pad 872-3 (or , Vdd and in opposite directions depending on the applied voltages at the SL pads). Current may also flow through one or more of contact structures 456/556 and/or contact lines 458/558. In some embodiments, the parasitic resistance of the current paths described herein is much smaller than the intrinsic resistance of the memory cell 340 under consideration and can be ignored. In some embodiments, the parasitic resistance of the current path can be derived by curve fitting. Thereby, the device parameters of the memory cell of interest can be obtained and the programmed state can be verified.

In some embodiments, the current of multiple memory cells (in various rows and columns) can be measured by adding multiplexer and decoder circuits, which are known to those skilled in the art.

In the second and third methods, memory cell current may be indirectly measured through Vdd pad 872-2 or SL pad 872-3, according to some embodiments of the present disclosure. In this method, the memory cell current is obtained by calculating the difference between the measured currents before and after switching on the memory cell of interest.

In some embodiments, a second test voltage (eg, 0-10V) may be applied to Vdd pad 872-2. In this example, SL pad 872-3 may be disconnected from the source line driver and tied to external ground. In some embodiments, SL pad 872-3 may be coupled to another external power source with a first test voltage (eg, 0-10V) unlike Vdd pad 872-2. In some embodiments, current may be measured at Vdd pad 872-2. In some embodiments, current may be measured at SL pad 872-3.

As in the first method, transistor 850-N1 can be switched off to disconnect the ACS mesh from internal ground 892-2, and transistor 850-N2 can be switched between the ACS mesh and SL pad 872-3. It can be switched on to form an electrical path.

およびDにおけるセンスラッチ878の出力部の各々に連結され得る。この例では、ノードDには、低い電圧から高い電圧へとデータ信号が供給され得る一方で、その相補的なノード

には、高い電圧から低い電圧へとデータ信号が供給され得る。例えば、ノード

は3Vから0Vへと切り替えることができ、ノードDは0Vから3Vへと切り替えることができる。それによって、pチャネルMOSFET850-P3は、ゲートにおいて0Vを受けた後に切り替えられ得る。一部の実施形態では、2つのトランジスタ850-N4および850-N3は、ノード885から結合境界面674を横切って(相互連結VIA472/572を通じて)ビット線341へと導電性経路を許容するために、スイッチオンされ得る。一部の実施形態では、トランジスタ850-N5は、電流がセンスラッチ878を通じて流れることができないようにスイッチオフされ得る。 In some embodiments, transistor 850-P1 may be switched on to couple Vdd pad 872-2 to node 883. FIG. Transistor 850-P2 can be switched off to disconnect the other devices and circuits of page buffer 888 from the internal power source at node 890-2. In some embodiments, a data line (not shown) is a node

and to each of the outputs of sense latch 878 at D. In this example, node D may be fed a data signal from a lower voltage to a higher voltage, while its complementary node

can be supplied with a data signal from a high voltage to a low voltage. For example, node

can be switched from 3V to 0V and node D can be switched from 0V to 3V. Thereby, p-channel MOSFET 850-P3 can be switched after receiving 0V at the gate. In some embodiments, two transistors 850-N4 and 850-N3 are used to allow a conductive path from node 885 across coupling interface 674 (through interconnect VIA 472/572) to bit line 341. , can be switched on. In some embodiments, transistor 850-N5 may be switched off such that current cannot flow through sense latch 878. FIG.

As a result, the current path is from Vdd pad 872-2, transistor 850-P1, node 883, transistor 850-P3, node 885, transistor 850-N4/850-N3, interconnect VIA 472/572, corresponding bit line 341. , through the corresponding memory string 212, ACS 880, ACS mesh 882, interconnect VIA 572/472, node 887 to SL pad 872-3. Current can also flow in opposite directions depending on the applied voltages at Vdd pad 872-2 and SL pad 872-3.

In the second and third methods, the memory cells of interest and the corresponding wordlines and bitlines may be selected in the same manner as in the first method. However, only in the second and third methods the measurement current flows through additional transistors and current paths. Therefore, in order to accurately determine the current through the memory cell of interest, the current flowing from Vdd pad 872-2 to SL pad 872-3 is measured twice, i.e. with the memory cell of interest switched on. It can be measured with and without (or selected and not selected). The difference between these two measurements can eliminate parasitic (or leakage) current paths through non-ideal transistors that are supposed to be switched off.

In summary, this disclosure describes various embodiments of methods for measuring memory cell current in a three-dimensional memory. The direct and indirect measurement methods disclosed herein can be performed at the wafer level utilizing existing circuits and/or structures requiring no additional design or processing steps. As such, programming and erasing can be verified for memory cells through in-line testing. Memory die yield can be tested at the wafer level prior to dicing and packaging. Manufacturing costs can thereby be reduced.

One aspect of the present disclosure provides a method for measuring memory cell current in a three-dimensional (3D) memory device. The method comprises applying a first test voltage to a source line pad of a peripheral circuit of the 3D memory device, the source line pad being electrically coupled to a common source line of a 3D memory array of the 3D memory device; A step is included in which the peripheral circuitry formed on the first substrate and the 3D memory array formed on the second substrate are electrically coupled through direct coupling. The method includes applying a second test voltage to bitline pads of a 3D memory array, the bitline pads and the 3D memory array being formed on opposite sides of a second substrate, the bitline pads passing through A step is also included in which the array contacts are used to electrically couple the bit lines of the memory cells. The method further includes applying an operating voltage to a word line of the memory cell, the word line electrically coupled to a control gate of the memory cell. The method also includes applying a pass voltage to the wordlines of the unselected memory cells and measuring the current flowing through the bitline or sourceline pads.

Another aspect of the present disclosure provides a method of measuring memory cell current in a three-dimensional (3D) memory device. The method comprises applying a first test voltage to a source line pad of a peripheral circuit of the 3D memory device, the source line pad being electrically coupled to a common source line of a 3D memory array of the 3D memory device; A step is included in which the peripheral circuitry formed on the first substrate and the 3D memory array formed on the second substrate are electrically coupled through direct coupling. The method includes applying a second test voltage to a power source pad, the power source pad electrically coupled to a page buffer of the peripheral circuit, the page buffer providing temporary storage for the memory cell. Also includes a step comprising: The method further includes applying an operating voltage to a word line of the memory cell, the word line electrically coupled to a control gate of the memory cell. The method also includes applying a pass voltage to the word lines of the unselected memory cells and sensing current flowing through the power source or source line pads.

The foregoing descriptions of specific embodiments may enable others, applying the knowledge of those of ordinary skill in the art, to implement such specific embodiments without undue experimentation and without departing from the general concepts of this disclosure. The general nature of the disclosure has been made sufficiently clear so that it can be readily modified and/or adapted for various uses. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the disclosure and guidance provided herein. that the phrases and terminology herein are for the purpose of description and not of limitation, such that they should be interpreted by those of ordinary skill in the art in light of the present disclosure and guidance; is understood.

Embodiments of the present disclosure are described above with the aid of functional building blocks that illustrate the performance of the specified functions and their relationships. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries may be defined so long as the functions specified and their relationships are appropriately performed.

The summary and abstract may describe one or more exemplary embodiments of the disclosure, but may not describe all exemplary embodiments of the disclosure as contemplated by the inventors. , and therefore are not intended to limit the scope of this disclosure and the appended claims in any way.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined solely in accordance with the following claims and their equivalents.

100 three-dimensional (3D) memory device
101 memory plane
103 memory blocks
105 Peripheral Area
108 areas
210 Stair area
211 channel structure region
212 memory strings
214 contact structure
216, 216-1, 216-2 slit structure
218 memory fingers
222 dummy memory string
224 memory slices
300 three-dimensional (3D) memory array structure
330 Substrate
331 insulating film
332 Lower Select Gate, LSG
332-T Bottom Select Transistor
333, 333-1, 333-2, 333-3 Control Gate, Word Line
334 Upper Select Gate, TSG
334-T Top Select Transistor
335 laminated film
336 Channel Hall
337 Memory Membrane
338 channel layer
339 core filling membrane
340, 340-1, 340-2, 340-3 memory cells
341 bit lines
343 metal interconnection lines
344 doped source line region
400 peripheral circuits, CMOS wafers
430 First substrate
430-1 First Side
430-2 second side
450 Peripherals
450-1 Peripherals, p-channel MOSFETs
450-2 Peripherals, n-channel MOSFETs
450-3 High Voltage MOSFET
451 Gate Stack
452 Shallow Trench Isolation, STI
453, 453-1, 453-2 Source/Drain
453-3 Lightly Doped Drain
454 wells
454-1 n-well
454-2 pwell
454-3 Deep n Well
455 peripheral interconnection layer
456 contact structure
458, 458-1, 458-2 conductive wire
462 Substrate Contact
472 INTERCONNECT VIA
500 3D memory array
530 Second substrate
530-1 first surface
530-2 Second surface
555 array interconnect layer
556 contact structure
558 Conductive wire, contact wire
560 insulating layer
562 Substrate Contact
564 conductive layer
566 dielectric layer
568 Alternating Conductive/Dielectric Stack
570 bit line contact
572 INTERCONNECT VIA
600 3D memory device
674 bonding interface
676 Bonding Layer
700 3D memory device
770 Through Array Contact, TAC
772 Input/Output (I/O) Pads
800 3D memory device
850-N1, 850-N2, 850-N3, 850-N4, 850-N5, 850-N6 n-Channel MOSFETs, Transistors
850-P1, 850-P2, 850-P3 p-channel MOSFETs, transistors
872-1 Bit Line (BL) Pad
872-2 Power source pad, Vdd pad
872-3 Source line (SL) pad
878 Sense Latch
878-N1, 878-N2 n-channel MOSFETs
878-P1, 878-P2 p-channel MOSFETs
880 Array Common Source (ACS)
882 ACS Mesh
883 nodes
884 Sensing Node
886 memory pages
887 nodes
888 page buffers
890-1, 890-2 nodes
892-1 Internal ground
892-2 Internal ground
892-3 Internal ground
BL bit line
WL word line

Claims (20)

A method of measuring current in a memory cell in a three-dimensional (3D) memory device, comprising:
applying a first test voltage to a source line pad of a peripheral circuit of the 3D memory device, comprising:
the source line pad is electrically connected to a common source line of a 3D memory array of the 3D memory device;
the peripheral circuit formed on a first substrate and the 3D memory array formed on a second substrate are electrically coupled through direct coupling;
a step;
applying a second test voltage to bit line pads of said 3D memory array, said bit line pads and said 3D memory array being formed on opposite sides of said second substrate, said bit line pads being , electrically coupled to bit lines of the memory cells using through array contacts;
applying an operating voltage to a word line of the memory cell, the word line being electrically coupled to a control gate of the memory cell;
applying a pass voltage to word lines of unselected memory cells;
measuring current flowing through the bit line pad or the source line pad. 2. The method of claim 1, wherein said step of applying said second test voltage comprises applying a voltage between 0V and 10V. 2. The method of claim 1, wherein said step of applying said first test voltage comprises applying a voltage of 0V. 2. The method of claim 1, wherein said step of applying said operating voltage comprises applying a voltage between 0.5V and 5V. 2. The method of claim 1, wherein said step of applying said pass voltage comprises applying a voltage between 0V and 10V. electrically disconnecting the common source line from an internal ground by a first transistor of the peripheral circuit;
2. The method of claim 1, further comprising: electrically coupling the common source line and the source line pad by a second transistor of the peripheral circuit. 2. The method of claim 1, further comprising applying a switching voltage to lower select gates and upper select gates corresponding to a memory string of said memory cells. 8. The method of claim 7, wherein said step of applying said switching voltage comprises applying a voltage between 0.5V and 5V. 2. The method of claim 1, further comprising electrically coupling said common source line and source terminals of memory strings of said memory cells through a doped source line region and an array common source. 2. The method of claim 1, wherein the through array contact through the second substrate is configured to form electrical contact between the bitline pad and the bitline. 2. The method of claim 1, further comprising electrically coupling said source line pad with said common source line of said 3D memory array through one or more interconnect VIA at a bonding interface. A method of measuring current in a memory cell in a three-dimensional (3D) memory device, comprising:
applying a first test voltage to a source line pad of a peripheral circuit of the 3D memory device, comprising:
the source line pad is electrically connected to a common source line of a 3D memory array of the 3D memory device;
the peripheral circuit formed on a first substrate and the 3D memory array formed on a second substrate are electrically coupled through direct coupling;
a step;
applying a second test voltage to a power source pad, said power source pad being electrically coupled to a page buffer of said peripheral circuit, said page buffer providing temporary storage for said memory cell; a step configured to:
applying an operating voltage to a word line of the memory cell, the word line being electrically coupled to a control gate of the memory cell;
applying a pass voltage to word lines of unselected memory cells;
and detecting a current flowing through said power source pad or said source line pad. 13. The method of claim 12, wherein said step of applying said first test voltage comprises applying a voltage between 0V and 10V. 13. The method of claim 12, wherein said step of applying said second test voltage comprises applying a voltage between 0V and 10V. 13. The method of claim 12, wherein said step of applying said operating voltage comprises applying a voltage between 0.5V and 5V. 13. The method of claim 12, wherein said step of applying said pass voltage comprises applying a voltage between 0V and 10V. electrically disconnecting the common source line from an internal ground by a first transistor of the peripheral circuit;
13. The method of claim 12, further comprising electrically coupling said common source line and said source line pad by a second transistor of said peripheral circuitry. providing a data signal to a first output of a sense latch of said page buffer, said data signal being for electrical coupling between said power source pad and a sense node of said peripheral circuit; a step configured to switch on the third transistor;
13. The method of claim 12, further comprising: switching off a fourth transistor of the peripheral circuit to electrically disconnect a second output of the sense latch and the sense node. 19. The method of claim 18, further comprising electrically coupling said sense node and a bitline of said memory cell by a fifth transistor of said peripheral circuitry. 13. The method of claim 12, further comprising electrically decoupling the page buffer and an internal power source by a sixth transistor of the peripheral circuitry.

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