TWI708329B - 記憶體元件及其製作方法 - Google Patents

記憶體元件及其製作方法 Download PDF

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TWI708329B
TWI708329B TW106109135A TW106109135A TWI708329B TW I708329 B TWI708329 B TW I708329B TW 106109135 A TW106109135 A TW 106109135A TW 106109135 A TW106109135 A TW 106109135A TW I708329 B TWI708329 B TW I708329B
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gate
back gate
dielectric layer
substrate
insulating layer
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TW201836076A (zh
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萬迅 何
溯 邢
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聯華電子股份有限公司
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Priority to US15/491,939 priority patent/US10177156B2/en
Publication of TW201836076A publication Critical patent/TW201836076A/zh
Priority to US16/207,171 priority patent/US10347645B2/en
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Abstract

本發明揭露一種製作記憶體元件的方法。首先提供一基底，該基底包含一第一區域以及一第二區域，其中該基底又包含一半導體層設於一絕緣層上，然後形成一第一前閘極於基底之第一區域上以及一第二前閘極於基底之第二區域上。接著去除第一前閘極下方之部分絕緣層，形成一第一後閘極於絕緣層上並位於第一前閘極下方，再形成一第二後閘極於第二前閘極下方。

Description

記憶體元件及其製作方法
本發明是關於一種記憶體元件，尤指一種靜態隨機存取記憶體(static random access memory,SRAM)及其製作方法。
在一嵌入式靜態隨機存取記憶體(embedded static random access memory,embedded SRAM)中，包含有邏輯電路(logic circuit)和與邏輯電路連接之靜態隨機存取記憶體。靜態隨機存取記憶體本身屬於一種揮發性(volatile)的記憶單元(memory cell)，亦即當供給靜態隨機存取記憶體之電力消失之後，所儲存之資料會同時抹除。靜態隨機存取記憶體儲存資料之方式是利用記憶單元內電晶體的導電狀態來達成，靜態隨機存取記憶體的設計是採用互耦合電晶體為基礎，沒有電容器放電的問題，不需要不斷充電以保持資料不流失，也就是不需作記憶體更新的動作，這與同屬揮發性記憶體的動態隨機存取記憶體(Dynamic Random Access Memory,DRAM)利用電容器帶電狀態儲存資 料的方式並不相同。靜態隨機存取記憶體之存取速度相當快，因此有在電腦系統中當作快取記憶體(cache memory)等之應用。
然而隨著製程線寬與曝光間距的縮減，現今SRAM元件的製作難以利用現有的架構曝出所要的圖案。因此如何改良現有SRAM元件的架構來提升曝光的品質即為現今一重要課題。
本發明一實施例揭露一種製作記憶體元件的方法。首先提供一基底，該基底包含一第一區域以及一第二區域，其中該基底又包含一半導體層設於一絕緣層上，然後形成一第一前閘極於基底之第一區域上以及一第二前閘極於基底之第二區域上。接著去除第一前閘極下方之部分絕緣層，形成一第一後閘極於絕緣層上並位於第一前閘極下方，再形成一第二後閘極於第二前閘極下方。
本發明另一實施例揭露一種記憶體元件，其主要包含：一基底包含一第一區域以及一第二區域，該基底包含一半導體層設於一絕緣層上且該第一區域之該絕緣層厚度不同於該第二區域之該絕緣層厚度；一第一前閘極於基底之第一區域上以及一第二前閘極於基底之第二區域上；一第一後閘極設於絕緣層上並位於第一前閘極下方；以及一第二後閘極設於絕緣層上並位於第二前閘極下方。
10:6T-SRAM記憶單元
12:上拉電晶體
14:上拉電晶體
16:下拉電晶體
18:下拉電晶體
20:傳送電晶體
22:傳送電晶體
24:儲存節點
26:儲存節點
28:串接電路
30:串接電路
32:電壓源
34:電壓源
36:字元線
38:位元線
52:基底
54:第一區域
56:第二區域
58:底矽層
60:絕緣層
62:上矽層
64:第一前閘極
66:第二前閘極
68:源極/汲極區域
70:第一介電層
72:接觸插塞
74:金屬內連線
76:第二介電層
78:凹槽
80:第一後閘極
82:高介電常數介電層
84:第三介電層
86:第二後閘極
88:第三後閘極
90:第四介電層
92:接觸插塞
94:第四後閘極
第1圖至第3圖為本發明較佳實施例製作一SRAM元件之方法示意圖。
第4圖為本發明較佳實施例之一SRAM元件之電路圖。
第5圖為本發明較佳實施例之一SRAM元件之佈局圖。
第6圖為第3圖之第一後閘極於SRAM元件中所覆蓋區域之上視圖。
第7圖為第3圖之第二後閘極於SRAM元件中所覆蓋區域之上視圖。
第8圖為第3圖之第四後閘極於SRAM元件中所覆蓋區域之上視圖。
請參照第1圖至第3圖，第1圖至第3圖為本發明較佳實施例製作一SRAM元件之方法示意圖。如第1圖所示，首先提供一基底52，並於基底52上定義出一第一區域54以及一第二區域56。在本實施例中，基底52較佳包含一矽覆絕緣(silicon-on-insulator,SOI)基板，其主要細部包含一底矽層(base silicon)58、一絕緣層60設於底矽層58上以及一上矽層(top silicon)62設於絕緣層60上，其中絕緣層60較佳由氧化矽所構成，但不侷限於此。
然後形成一第一前閘極64於基底52的第一區域54上以及一第二前閘極66於基底52的第二區域56上。在本實施例中，第一前閘極64與第二前閘極66的製作可先沉積一閘極介電層(圖未示)與一閘極材料層(圖未示)於基底52上，接著再以微影暨蝕刻製程去除部分閘極介電層與部分閘極材料層，以於基底52上之第一區域54與第二區域56中分別形成由圖案化之閘極材料層所構成的第一前閘極64與第二前閘極 66。其中閘極介電層可包含二氧化矽(SiO2)、氮化矽(SiN)或高介電常數(high dielectric constant,high-k)材料，閘極材料層或第一前閘極64與第二前閘極66可包含多晶矽或例如金屬等導電材料。若第一前閘極64與第二前閘極66由金屬所構成，其又可細部包含一高介電常數介電層、一U型功函數金屬層以及一低阻抗金屬層。
在本實施例中，高介電常數介電層包含介電常數大於4的介電材料，例如選自氧化鉿(hafnium oxide，HfO2)、矽酸鉿氧化合物(hafnium silicon oxide,HfSiO4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化鋁(aluminum oxide,Al2O3)、氧化鑭(lanthanum oxide,La2O3)、氧化鉭(tantalum oxide,Ta2O5)、氧化釔(yttrium oxide,Y2O3)、氧化鋯(zirconium oxide,ZrO2)、鈦酸鍶(strontium titanate oxide,SrTiO3)、矽酸鋯氧化合物(zirconium silicon oxide,ZrSiO4)、鋯酸鉿(hafnium zirconium oxide,HfZrO4)、鍶鉍鉭氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、鋯鈦酸鉛(lead zirconate titanate,PbZrxTi1-xO3,PZT)、鈦酸鋇鍶(barium strontium titanate,BaxSr1-xTiO3,BST)、或其組合所組成之群組。
功函數金屬層較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層可選用功函數為3.9電子伏特(eV)~4.3eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC(碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層可選用功函數為4.8eV~5.2eV的金屬材料，如氮 化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層與低阻抗金屬層之間可包含另一阻障層(圖未示)，其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層48則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。
隨後可於各第一前閘極64與第二前閘極66側壁選擇性形成至少一側壁子(圖未示)，並於側壁子兩側的基底52中形成一源極/汲極區域68。在本實施例中，側壁子可為單一側壁子或複合式側壁子，例如可細部包含一偏位側壁子以及一主側壁子。其中偏位側壁子與主側壁子可包含相同或不同材料，且兩者均可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組。源極/汲極區域68則可依據所置備電晶體的導電型式而包含不同摻質，例如可包含P型摻質或N型摻質。在本實施例中，第一前閘極64與第二前閘極66較佳包含相同導電型式，例如均為N型金氧半導體電晶體，但不侷限於此。
接著形成一第一介電層70，例如一層間介電層(interlayer dielectric,ILD)於基底52上並覆蓋第一前閘極64與第二前閘極66，然後進行接觸插塞與金屬內連線製程，以於第一介電層70內形成複數個接觸插塞72接觸源極/汲極區域68並電連接第一前閘極64與第二前閘極66以及金屬內連線74連接接觸插塞72。在本實施例中，第一介電層70可包含氧化物，例如四乙氧基矽烷(Tetraethyl orthosilicate,TEOS)，金屬內連線74可包含鋁、鉻、銅、鉭、鉬、鎢或其組合且最佳為銅，接觸插塞72則較佳由鎢所構成，但均不侷限於此。
以上較佳為本發明SRAM元件於基底52上半部的製作，迨上半部的製程，包括連接第一前閘極64與第二前閘極66的金屬內連線74完成後，如第2圖所示，可先將整個基底52翻轉使底矽層58下表面朝上，然後利用蝕刻完全去除SOI基板最下層的底矽層58並暴露出絕緣層60表面，之後再進行後續SRAM元件下半部包括後閘極的製作。
值得注意的是，為了更清楚顯示所製備記憶體元件的整體結構，以下說明仍以未將基底52翻轉前的態樣來進行後續製程的描述，因此製作後續後閘極等元件時的順序較佳由第2圖中絕緣層60底部開始往下依序進行。另外由於製程順序實際上是由絕緣層60底部開始往下進行，因此後續描述某元件設置或形成於基底52上的時候所使用之"上"的敘述僅代表設置元件的動作，而非指元件實際上所設置的位置。例如第2圖所示，迨去除底部矽層58並暴露出絕緣層60下表面後先利用微影暨蝕刻製程去除第一區域54中第一前閘極64下方的部分絕緣層60，使第一區域54的絕緣層60厚度不同於第二區域56的絕緣層60厚度，或更具體而言第一區域54的絕緣層60厚度低於第二區域56的絕緣層60厚度。
然後全面性形成一第二介電層76於絕緣層60上或以圖中所示形成第二介電層76於絕緣層60下表面，並利用微影暨蝕刻製程去除第一區域的部分第二介電層形成凹槽78以暴露出第一區域54的絕緣層60底部。
接著如第3圖所示，形成一第一後閘極80於凹槽78內或第一前閘極64下方的絕緣層60底部，其中第二介電層76下表面較佳切齊所形成的第一後閘極80下表面。在本實施例中，第二介電層76可與第一介電層70包含相同或不同材料，其中第二介電層76較佳包含氧化矽或TEOS，第一後閘極80可包含鋁、鉻、銅、鉭、鉬、鎢或其組合且最佳由銅所構成，但不侷限於此。
需注意的是，雖然上述實施例是先去除第一區域54中的部分絕緣層60底部才形成第二介電層76於絕緣層60上，但不侷限於此，依據本發明一實施例又可選擇在不去除任何絕緣層60底部的情況下先直接覆蓋第二介電層76於絕緣層60上，然後再利用微影暨蝕刻方式同時去除設於第一區域54內或第一前閘極64下方的部分第二介電層76與部分絕緣層60形成第2圖中的凹槽78並使第一區域54的絕緣層60厚度略低於第二區域56的絕緣層60厚度。
換句話說，相較於上述實施例需進行兩道微影暨蝕刻製程分別去除第一區域54中的部分絕緣層60與部分第二介電層76，本實施例僅需進行一道微影暨蝕刻製程便可形成第2圖中的凹槽78，這兩種變化型均屬本發明所涵蓋的範圍。之後可以利用相同方式形成第一後閘極80於凹槽78內，且第一後閘極80底部同樣切齊第二介電層76底部。
接著形成一高介電常數介電層82於第二介電層與第一後閘極表面。依據本發明一實施例，高介電常數介電層82包含介電常數大於4的介電材料，例如可選自氧化鉿(hafnium oxide，HfO2)、矽酸鉿氧 化合物(hafnium silicon oxide,HfSiO4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化鋁(aluminum oxide,Al2O3)、氧化鑭(lanthanum oxide,La2O3)、氧化鉭(tantalum oxide,Ta2O5)、氧化釔(yttrium oxide,Y2O3)、氧化鋯(zirconium oxide,ZrO2)、鈦酸鍶(strontium titanate oxide,SrTiO3)、矽酸鋯氧化合物(zirconium silicon oxide,ZrSiO4)、鋯酸鉿(hafnium zirconium oxide,HfZrO4)、鍶鉍鉭氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、鋯鈦酸鉛(lead zirconate titanate,PbZrxTi1-xO3,PZT)、鈦酸鋇鍶(barium strontium titanate,BaxSr1-xTiO3,BST)、或其組合所組成之群組。
隨後可選擇性去除第一區域54的部分高介電常數介電層82暴露出部分第一後閘極80下表面，形成一第三介電層84於高介電常數介電層82下表面，去除部分第三介電層84形成開口(圖未示)暴露出部分位於第一區域54與第二區域56的高介電常數介電層82下表面，再同時形成第二後閘極86於第二區域56的開口內與高介電常數介電層82下表面以及第三後閘極88於第一區域54的開口內或第一後閘極80下方。由於第一區域54的部分高介電常數介電層82已被先行去除，所形成的第三後閘極88較佳直接接觸第一後閘極80且第三後閘極88下表面同時切齊第二後閘極86下表面。
需注意的是，雖然本實施例較佳於形成第二後閘極86與第三後閘極88之前先去除第一區域54的部分高介電常數介電層82使第三後閘極88可直接接觸第一後閘極80，但不侷限於此，依據本發明一實施例，又可選擇在不去除任何高介電常數介電層82的情況下直接形成第 二後閘極86與第三後閘極88，如此第二後閘極86的上下表面均切齊第三後閘極88的上下表面，此實施例也屬本發明所涵蓋的範圍。
接著可再搭配進行接觸插塞與金屬內連線製程，以於第三介電層84上形成第四介電層90、形成接觸插塞92於第四介電層90內連接第二後閘極86以及第四後閘極94連接接觸插塞92。在本實施例中，第三介電層84與第四介電層90可與第二介電層76包含相同或不同材料，例如三者均可包含氧化矽或TEOS。第一後閘極80、第二後閘極86、第三後閘極88、第四後閘極94以及接觸插塞92也可由相同或不同材料所構成，例如第一後閘極80、第二後閘極86、第三後閘極88、第四後閘極94以及接觸插塞92均可包含鋁、鉻、銅、鉭、鉬、鎢或其組合且最佳為銅，但均不侷限於此。至此即完成本發明較佳實施例之一記憶體元件的製作。
值得注意的是，依據前述製程本發明所製備之SRAM元件的精神主要如第2圖所示先去除第一區域54中第一前閘極64下方的部分絕緣層60並使兩個區域中的絕緣層60具有不同厚度，然後分別於基底52背面的第一區域54與第二區56域形成後閘極對應基底54正面的前閘極，如此便可在運作時由第一區域54與第二區域56的後閘極分別提供不同臨界電壓至前閘極，除了可調整整個記憶體元件的貝塔比例值(beta ratio)之外又可同時達到更加的讀取範圍(read margin)。
請繼續參照第4圖至第5圖，第4圖為本發明SRAM元件之電路圖，第5圖為本發明較佳實施例之一SRAM元件之佈局圖。如第4圖 與第5圖所示，本發明之SRAM元件較佳包含一六電晶體靜態隨機存取記憶體(six-transistor SRAM,6T-SRAM)10。在本實施例中，6T-SRAM記憶單元10較佳由上拉電晶體(Pull-Up transistor)12和14、下拉電晶體(Pull-Down transistor)16和18以及存取電晶體(Access transistor)或傳送電晶體(Pass transistor)或20和22構成正反器(flip-flop)，其中上拉電晶體12和14及下拉電晶體16和18構成栓鎖電路(latch)，使資料可以栓鎖在儲存節點(Storage Node)24或26。另外，上拉電晶體12和14是作為主動負載之用，其亦可以一般之電阻來取代做為上拉元件，在此情況下即為四電晶體靜態隨機存取記憶體(four-transistor SRAM,4T-SRAM)。另外在本實施例中，各上拉電晶體12和14較佳共用一源極/汲極區域並電連接至一電壓源32(例如Vcc)，各下拉電晶體16和18共用一源極/汲極區域並電連接至一電壓源34(例如Vss)，且第一靜態隨機存取記憶體單元40與第二靜態隨機存取記憶體單元42呈上下對稱佈局設置，使第一靜態隨機存取記憶體單元40中下拉電晶體16和18所共用的源極/汲極區域較佳電連接第二靜態隨機存取記憶體單元42中上拉電晶體12和14所共用的源極/汲極區域並電連接至電壓源34(例如Vss)。
一般而言，6T-SRAM記憶單元10的上拉電晶體12、14是由P型金氧半導體(P-type metal oxide semiconductor,PMOS)電晶體所組成，而下拉電晶體16、18和傳送電晶體20、22則是由N型金氧半導體(N-type metal oxide semiconductor,NMOS)電晶體所組成。其中，上拉電晶體12和下拉電晶體16一同構成一反向器(inverter)，且這兩者所構成的串接電路28其兩端點分別耦接於一電壓源32與一電壓源34；同樣地，上拉電晶體14與下拉電晶體18構成另一反向器，而這兩者所構成 的串接電路30其兩端點亦分別耦接於電壓源32與電壓源34。
此外，在儲存節點24處，係分別電連接有下拉電晶體18和上拉電晶體14之閘極(gate)、及下拉電晶體16、上拉電晶體12和傳送電晶體20的汲極(Drain)；同樣地，在儲存節點26上，亦分別電連接有下拉電晶體16和上拉電晶體12之閘極、及下拉電晶體18、上拉電晶體14和存取電晶體22的汲極。至於傳送電晶體20和22的閘極則耦接至字元線(Word Line)36，而傳送電晶體20和22的源極(Source)則分別耦接至相對應之位元線(Data Line)38。
在本實施例中，第2圖中所揭露之第一前閘極64即為下拉電晶體16、18中的其中一者，第二前閘極66為傳送電晶體20、22中的其中一者，且兩者均較佳由NMOS電晶體所構成。如第4圖所示，本發明可同時藉由第一後閘極80與第二後閘極86分別傳送不同臨界電壓至所對應的第一前閘極64(或下拉電晶體)與第二前閘極66(或傳送電晶體)。
請接著參照第6圖至第8圖，第6圖至第8圖為前述實施例中所製備之後閘極相對於整個SRAM元件所覆蓋之區域之上視圖，其中第6圖為第3圖之第一後閘極於SRAM元件中所覆蓋區域之上視圖，第7圖為第3圖之第二後閘極於SRAM元件中所覆蓋區域之上視圖，第8圖為第3圖之第四後閘極於SRAM元件中所覆蓋區域之上視圖。
如第6圖所示，第3圖之第一後閘極80較佳覆蓋第5圖SRAM元件中右上角與左下角的電晶體，亦即兩顆下拉電晶體16、18。
如第7圖所示，第3圖之第二後閘極86較佳覆蓋第5圖SRAM元件中左上角與右下角的電晶體，亦即兩顆傳送電晶體20、22。
如第8圖所示，第3圖之第四後閘極94可選擇性覆蓋第5圖SRAM元件設於中間部分的兩個上拉電晶體12、14但不覆蓋任何下拉電晶體16、18與任何傳送電晶體20、22。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
52:基底
54:第一區域
56:第二區域
60:絕緣層
62:上矽層
64:第一前閘極
66:第二前閘極
68:源極/汲極區域
70:第一介電層
72:接觸插塞
74:金屬內連線
76:第二介電層
80:第一後閘極
82:高介電常數介電層
84:第三介電層
86:第二後閘極
88:第三後閘極
90:第四介電層
92:接觸插塞
94:第四後閘極

Claims (19)

  1. 一種製作記憶體元件的方法，包含：提供一基底，該基底包含一第一區域以及一第二區域，其中該基底包含一半導體層設於一絕緣層上；形成一第一前閘極於該基底之該第一區域上以及一第二前閘極於該基底之該第二區域上；去除該第一前閘極下方之部分該絕緣層；形成一第一後閘極於該絕緣層上並位於該第一前閘極下方；以及形成一第二後閘極於該第二前閘極下方。
  2. 如申請專利範圍第1項所述之方法，另包含：形成一第一介電層於該基底上並覆蓋該第一前閘極及該第二前閘極；以及形成複數個第一接觸插塞於該第一介電層內並電連接該第一前閘極及該第二前閘極。
  3. 如申請專利範圍第2項所述之方法，另包含：形成一第二介電層於該絕緣層上；形成該第一後閘極於該第二介電層旁；以及形成該第二後閘極於該第二介電層上。
  4. 如申請專利範圍第3項所述之方法，其中該第二介電層下表面切齊該第一後閘極下表面。
  5. 如申請專利範圍第3項所述之方法，另包含於形成該第二後閘極之前形成一高介電常數介電層於該第二介電層及該第一後閘極上。
  6. 如申請專利範圍第3項所述之方法，另包含同時形成該第二後閘極於該第二前閘極下方以及一第三後閘極於該第一後閘極下方。
  7. 如申請專利範圍第6項所述之方法，其中該第一後閘極及該第三後閘極係設於該第一區域之該第一前閘極下方。
  8. 如申請專利範圍第6項所述之方法，其中該第一後閘極直接接觸該第三後閘極。
  9. 如申請專利範圍第6項所述之方法，另包含：形成一第三介電層於該絕緣層上；形成該第二後閘極及該第三後閘極於該第三介電層內；形成一第二接觸插塞於該第二後閘極上；以及形成一第四後閘極於該第二接觸插塞上。
  10. 如申請專利範圍第9項所述之方法，其中該第二後閘極及該第四後閘極係設於該第二區域之該第二前閘極下方。
  11. 一種記憶體元件，包含： 一基底包含一第一區域以及一第二區域，該基底包含一半導體層設於一絕緣層上且該第一區域之該絕緣層厚度不同於該第二區域之該絕緣層厚度；一第一前閘極於該基底之該第一區域上以及一第二前閘極於該基底之該第二區域上；一第一後閘極設於該絕緣層上並位於該第一前閘極下方；一第二後閘極設於該絕緣層上並位於該第二前閘極下方；以及一第三後閘極設於該第一後閘極下方，其中該第二後閘極下表面切齊該第三後閘極下表面。
  12. 如申請專利範圍第11項所述之記憶體元件，另包含：一第一介電層於該基底上並覆蓋該第一前閘極及該第二前閘極；以及複數個第一接觸插塞於該第一介電層內並電連接該第一前閘極及該第二前閘極。
  13. 如申請專利範圍第12項所述之記憶體元件，另包含一第二介電層設於該絕緣層上並位於該第一後閘極旁。
  14. 如申請專利範圍第13項所述之記憶體元件，其中該第二介電層下表面切齊該第一後閘極下表面。
  15. 如申請專利範圍第13項所述之記憶體元件，另包含一高介電常數介電層設於該第二介電層及該第一後閘極上。
  16. 如申請專利範圍第11項所述之記憶體元件，其中該第一後閘極及該第三後閘極係設於該第一區域之該第一前閘極下方。
  17. 如申請專利範圍第11項所述之記憶體元件，其中該第一後閘極直接接觸該第三後閘極。
  18. 如申請專利範圍第11項所述之記憶體元件，另包含：一第三介電層設於該第二後閘極及該第三後閘極周圍；一第二接觸插塞設於該第二後閘極上；以及一第四後閘極設於該第二接觸插塞上。
  19. 如申請專利範圍第18項所述之記憶體元件，其中該第二後閘極及該第四後閘極係設於該第二區域之該第二前閘極下方。
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