TWI708107B - Pixel array substrate - Google Patents

Pixel array substrate Download PDF

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TWI708107B
TWI708107B TW108106138A TW108106138A TWI708107B TW I708107 B TWI708107 B TW I708107B TW 108106138 A TW108106138 A TW 108106138A TW 108106138 A TW108106138 A TW 108106138A TW I708107 B TWI708107 B TW I708107B
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scan line
pixel
electrode
touch signal
array substrate
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TW108106138A
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TW202032241A (en
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張翔睿
丘兆仟
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友達光電股份有限公司
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Priority to CN201910837877.9A priority patent/CN110568962B/en
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412Digitisers structurally integrated in a display
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416Control or interface arrangements specially adapted for digitisers
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04112Electrode mesh in capacitive digitiser: electrode for touch sensing is formed of a mesh of very fine, normally metallic, interconnected lines that are almost invisible to see. This provides a quite large but transparent electrode surface, without need for ITO or similar transparent conductive material

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

A pixel array substrate including a substrate, scan line groups, data lines, touch sensing lines, and a common electrode is provided. Each scan line group includes a first and a second scan lines each having a pixel section and a transition section. The transition section of the first scan line spaces from the transition section of the second scan line by a first distance. The pixel section of the first scan line spaces from the pixel section of the second scan line by a second distance smaller than the first distance. The data lines and the touch sensing lines are arranged alternatively. The common electrode includes an electrode portion overlapping the pixel structures, a contact portion and a connection portion. The contact portion is located between the transition section of one first scan line and the transition section of one second scan line and electrically connected to one touch sensing line. The connection portion crosses over one transition section to connect between the electrode portion and the contact portion.

Description

畫素陣列基板Pixel array substrate

本發明是有關於一種電子裝置的基板,且特別是有關於一種畫素陣列基板。 The present invention relates to a substrate of an electronic device, and particularly relates to a pixel array substrate.

為了整合觸控功能於顯示面板中,大致上可採用外貼式與內嵌式(in-cell)兩種整合技術。以內嵌式技術實現觸控與顯示的整合可達到裝置整體厚度較薄與重量較輕的優點,因此被廣泛地應用。內嵌式觸控顯示面板可以利用畫素陣列基板中的導電層來構成觸控電極與觸控線路,或是將觸控用的電極與線路製作於畫素陣列基板上。此時,畫素陣列基板包括了顯示用的線路以及觸控用的線路,這可能導致不同線路增加彼此的負載。因此,避免線路負載影響到顯示或是觸控功能的表現是規劃與製作畫素陣列基板時需要考量的議題。 In order to integrate the touch function in the display panel, generally two integration technologies can be used, namely, an externally attached type and an in-cell type. The integration of touch and display with in-cell technology can achieve the advantages of thinner overall device thickness and lighter weight, so it is widely used. The in-cell touch display panel can use the conductive layer in the pixel array substrate to form touch electrodes and touch circuits, or fabricate touch electrodes and circuits on the pixel array substrate. At this time, the pixel array substrate includes lines for display and lines for touch, which may cause different lines to increase mutual load. Therefore, avoiding the line load from affecting the performance of the display or touch function is an issue that needs to be considered when planning and manufacturing the pixel array substrate.

本發明提供一種畫素陣列基板,可減小觸控相關線路對顯示相關線路造成的負載而提供良好的觸控與顯示性能。 The present invention provides a pixel array substrate, which can reduce the load caused by touch-related circuits to display-related circuits and provide good touch and display performance.

本發明的畫素陣列基板包括基板、多個掃描線組、多條資料線、多條觸控訊號線、多個畫素結構及共用電極。掃描線組配置於基板上。各掃描線組包括第一掃描線以及第二掃描線。第一掃描線及第二掃描線的每一者包括畫素段與接續畫素段的過度段。第一掃描線的過度段與第二掃描線的過度段之間至少隔開第一距離,第一掃描線的畫素段與第二掃描線的畫素段之間至少隔開第二距離,且第一距離大於第二距離。資料線配置於基板上,且各資料線延伸交錯掃描線組。觸控訊號線配置於基板上,各觸控訊號線延伸交錯掃描線組,且資料線與觸控訊號線交替排列。畫素結構配置於基板上,且排成陣列。各掃描線組位於相鄰兩列畫素結構之間。共用電極配置於基板上,且共用電極包括電極部、接觸部與連接部。電極部重疊畫素結構。接觸部位於其中一個掃描線組的第一掃描線的過度段與第二掃描線的過度段之間且電連接其中一條觸控訊號線。連接部橫越其中一個過度段以連接於電極部與接觸部之間。 The pixel array substrate of the present invention includes a substrate, multiple scan line groups, multiple data lines, multiple touch signal lines, multiple pixel structures, and common electrodes. The scan line group is arranged on the substrate. Each scan line group includes a first scan line and a second scan line. Each of the first scan line and the second scan line includes a pixel segment and a transitional segment of the subsequent pixel segment. The transition section of the first scan line and the transition section of the second scan line are separated by at least a first distance, and the pixel section of the first scan line and the pixel section of the second scan line are separated by at least a second distance, And the first distance is greater than the second distance. The data lines are arranged on the substrate, and each data line extends to the interlaced scan line group. The touch signal lines are arranged on the substrate, and each touch signal line extends the interlaced scanning line group, and the data lines and the touch signal lines are arranged alternately. The pixel structures are arranged on the substrate and arranged in an array. Each scan line group is located between two adjacent pixel structures. The common electrode is disposed on the substrate, and the common electrode includes an electrode part, a contact part and a connection part. The electrode portion overlaps the pixel structure. The contact portion is located between the transition section of the first scan line and the transition section of the second scan line in one of the scan line groups and is electrically connected to one of the touch signal lines. The connecting part traverses one of the transition sections to connect between the electrode part and the contact part.

基於上述,本發明實施例的畫素陣列基板可在半源極(half source driving)驅動畫素陣列的架構下,利用掃描線的圖案設計使得觸控電極與對應的觸控訊號線的接觸點位於緊鄰的掃描線之間且接觸點的面積不重疊掃描線。如此,可減小觸控電極對掃描線造成的負載,使得掃描線無須因應負載的增加而加寬,從而有助於縮減邊框寬度。 Based on the above, the pixel array substrate of the embodiment of the present invention can use the pattern design of the scan line to make the touch electrode and the corresponding touch signal line contact point under the structure of half source driving the pixel array. It is located between the adjacent scan lines and the area of the contact point does not overlap the scan line. In this way, the load caused by the touch electrode to the scan line can be reduced, so that the scan line does not need to be widened in response to the increase in the load, thereby helping to reduce the frame width.

為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。 In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

100、200:畫素陣列基板 100, 200: pixel array substrate

110:基板 110: substrate

120、120A、120B:掃描線組 120, 120A, 120B: scan line group

122:第一掃描線 122: first scan line

1222、1242:畫素段 1222, 1242: pixel segment

1222A、1242A:增寬部 1222A, 1242A: widened part

1224、1244:過度段 1224, 1244: Transition section

1226、1246:轉折段 1226, 1246: turning section

124:第二掃描線 124: second scan line

130:資料線 130: data line

140、140A、140B:觸控訊號線 140, 140A, 140B: touch signal cable

150、250:畫素結構 150, 250: Pixel structure

150A:第一畫素結構 150A: The first pixel structure

150B:第二畫素結構 150B: second pixel structure

152、152A、152B:主動元件 152, 152A, 152B: active components

154、254:畫素電極 154, 254: pixel electrode

154S、262S:狹縫 154S, 262S: slit

160、260:共用電極 160, 260: common electrode

162、262:電極部 162, 262: Electrode section

162A:開孔 162A: Hole

164、264:接觸部 164, 264: Contact part

166、266:連接部 166, 266: connecting part

170:導通電極 170: Conduction electrode

182:閘絕緣層 182: gate insulation

184:第一保護層 184: The first protective layer

186:第二保護層 186: The second protective layer

192、192A、192B:第一接觸孔 192, 192A, 192B: first contact hole

194:第二接觸孔 194: second contact hole

290:接觸孔 290: contact hole

A:區域 A: area

C:半導體層 C: semiconductor layer

D:汲極 D: Dip pole

D1:方向 D1: direction

DA:第一端 DA: first end

DB:第二端 DB: second end

DC:汲極接觸部 DC: Drain contact

D192A、D194、D290:尺寸 D192A, D194, D290: size

G:閘極 G: Gate

G1:第一距離 G1: first distance

G2:第二距離 G2: second distance

I-I’、II-II’、III-III’、IV-IV’:剖線 I-I’, II-II’, III-III’, IV-IV’: Sectional line

LO:重疊長度 LO: overlapping length

LS:間隔長度 LS: interval length

P1、P2:間隙 P1, P2: gap

W166:寬度 W166: width

圖1A為本發明一實施例的畫素陣列基板的上視圖。 FIG. 1A is a top view of a pixel array substrate according to an embodiment of the invention.

圖1B為圖1A中區域A的放大圖。 Fig. 1B is an enlarged view of area A in Fig. 1A.

圖2為依據本發明一實施例的掃描線組的示意圖。 FIG. 2 is a schematic diagram of a scan line group according to an embodiment of the invention.

圖3為依據本發明一實施例的掃描線組與半導體層的示意圖。 FIG. 3 is a schematic diagram of a scan line group and a semiconductor layer according to an embodiment of the invention.

圖4為根據本發明一實施例的資料線、觸控訊號線及主動元件配置於圖3的結構上的示意圖。 4 is a schematic diagram of data lines, touch signal lines, and active components arranged on the structure of FIG. 3 according to an embodiment of the present invention.

圖5為根據本發明一實施例的共用電極的示意圖。 FIG. 5 is a schematic diagram of a common electrode according to an embodiment of the invention.

圖6為圖1A的剖線I-I’、II-II’的剖面示意圖。 Fig. 6 is a schematic cross-sectional view taken along the line I-I' and II-II' of Fig. 1A.

圖7為本發明一實施例的畫素陣列基板的局部示意圖。 FIG. 7 is a partial schematic diagram of a pixel array substrate according to an embodiment of the invention.

圖8為沿圖7的剖線III-III’與IV-IV’的剖面圖。 Fig. 8 is a cross-sectional view taken along the line III-III' and IV-IV' of Fig. 7.

圖1A為本發明一實施例的畫素陣列基板的上視圖,而圖1B為圖1A中區域A的放大圖。請參照圖1A與1B,畫素陣列基板100包括基板110、多個掃描線組120、多條資料線130、多條觸控訊號線140、多個畫素結構150以及共用電極160。掃描線組 120、資料線130、觸控訊號線140、畫素結構150及共用電極160都配置於基板110上。多個畫素結構150以排列成陣列的方式配置於基板110上。設置有掃描線組120、資料線130、觸控訊號線140、畫素結構150、共用電極160及基板110整體構成畫素陣列基板100。在本實施例中,畫素結構150可在掃描線組120與資料線130的訊號控制之下提供顯示驅動電場以實現顯示操作。在本實施例中,畫素陣列基板100還包括導通電極170,且導通電極170將共用電極160與對應的觸控訊號線140電性連接。如此,共用電極160可在觸控訊號線140的訊號控制與傳遞之下實現觸控感測的操作。因此,畫素陣列基板100可應用於觸控顯示裝置中,以實現觸控與顯示的雙重功能。 FIG. 1A is a top view of a pixel array substrate according to an embodiment of the present invention, and FIG. 1B is an enlarged view of area A in FIG. 1A. 1A and 1B, the pixel array substrate 100 includes a substrate 110, a plurality of scan line groups 120, a plurality of data lines 130, a plurality of touch signal lines 140, a plurality of pixel structures 150, and a common electrode 160. Scan line group 120, the data line 130, the touch signal line 140, the pixel structure 150 and the common electrode 160 are all disposed on the substrate 110. The plurality of pixel structures 150 are arranged on the substrate 110 in an array. The scan line group 120, the data line 130, the touch signal line 140, the pixel structure 150, the common electrode 160 and the substrate 110 integrally constitute the pixel array substrate 100. In this embodiment, the pixel structure 150 can provide a display driving electric field under the signal control of the scan line group 120 and the data line 130 to realize the display operation. In this embodiment, the pixel array substrate 100 further includes a conductive electrode 170, and the conductive electrode 170 electrically connects the common electrode 160 and the corresponding touch signal line 140. In this way, the common electrode 160 can realize the touch sensing operation under the signal control and transmission of the touch signal line 140. Therefore, the pixel array substrate 100 can be applied to a touch display device to realize the dual functions of touch and display.

在本實施例中,掃描線組120各自包括成對的第一掃描線122與第二掃描線124,且各個掃描線組120位於相鄰兩列的畫素結構150之間。換言之,同一個掃描線組120中的第一掃描線122與第二掃描線124之間並未設置有任何畫素結構150。各條資料線130的延伸方向交錯於掃描線組120,且各條觸控訊號線140的延伸方向也交錯於掃描線組120。資料線130與觸控訊號線140交替排列。以圖1A與1B來看,兩相鄰資料線130之間即設置有一條觸控訊號線140,而兩相鄰觸控訊號線140之間即設置有一條資料線130。此外,各畫素結構150設置於相鄰兩組掃描線組120之間,且位於其中一條資料線130與其中一條觸控訊號線140之 間。各畫素結構150包括主動元件152以及畫素電極154,其中主動元件152包括閘極G、半導體層C、源極S與汲極D,且畫素電極154連接汲極D而電性連接主動元件152。 In this embodiment, the scan line groups 120 each include a pair of first scan lines 122 and second scan lines 124, and each scan line group 120 is located between the pixel structures 150 in two adjacent columns. In other words, there is no pixel structure 150 between the first scan line 122 and the second scan line 124 in the same scan line group 120. The extension direction of each data line 130 is staggered with the scan line group 120, and the extension direction of each touch signal line 140 is also staggered with the scan line group 120. The data lines 130 and the touch signal lines 140 are alternately arranged. 1A and 1B, a touch signal line 140 is provided between two adjacent data lines 130, and a data line 130 is provided between two adjacent touch signal lines 140. In addition, each pixel structure 150 is disposed between two adjacent scan line groups 120, and is located between one of the data lines 130 and one of the touch signal lines 140 between. Each pixel structure 150 includes an active device 152 and a pixel electrode 154. The active device 152 includes a gate G, a semiconductor layer C, a source S and a drain D, and the pixel electrode 154 is connected to the drain D and electrically connected to the active Component 152.

圖2為依據本發明一實施例的掃描線組的示意圖。請同時參照圖1A、1B與圖2,各掃描線組120包括第一掃描線122與第二掃描線124。第一掃描線122與第二掃描線124每一者由金屬或是導電性良好的替代材料製作,且可依據圖案設計而劃分成多個區段。各第一掃描線122包括交替連接的畫素段1222與過度段1224,各過度段1224接續其中一個畫素段1222,而各畫素段1222接續其中一個過度段1224。相似地,各第二掃描線124包括交替連接的畫素段1242與過度段1244,各過度段1244接續其中一個畫素段1242,而各畫素段1242接續其中一個過度段1244。此外,第一掃描線122還包括連接於畫素段1222與過度段1224之間的轉折段1226,且轉折段1226的延伸方向相交於畫素段1222與過度段1224。第二掃描線124還包括連接於畫素段1242與過度段1244之間的轉折段1246,且轉折段1246的延伸方向相交於畫素段1242與過度段1244。如此,第一掃描線122與第二掃描線124各自為折曲型的傳輸線路。 FIG. 2 is a schematic diagram of a scan line group according to an embodiment of the invention. 1A, 1B and FIG. 2 at the same time, each scan line group 120 includes a first scan line 122 and a second scan line 124. Each of the first scan line 122 and the second scan line 124 is made of metal or an alternative material with good conductivity, and can be divided into a plurality of sections according to the pattern design. Each first scan line 122 includes alternately connected pixel segments 1222 and transition segments 1224. Each transition segment 1224 is connected to one of the pixel segments 1222, and each pixel segment 1222 is connected to one of the transition segments 1224. Similarly, each second scan line 124 includes alternately connected pixel segments 1242 and transition segments 1244. Each transition segment 1244 is connected to one of the pixel segments 1242, and each pixel segment 1242 is connected to one of the transition segments 1244. In addition, the first scan line 122 further includes a turning section 1226 connected between the pixel section 1222 and the transition section 1224, and the extension direction of the turning section 1226 intersects the pixel section 1222 and the transition section 1224. The second scan line 124 further includes a turning section 1246 connected between the pixel section 1242 and the transition section 1244, and the extension direction of the turning section 1246 intersects the pixel section 1242 and the transition section 1244. In this way, the first scan line 122 and the second scan line 124 are respectively curved transmission lines.

在本實施例中,第一掃描線122的過度段1224與第二掃描線124的過度段1244之間至少隔開第一距離G1,第一掃描線122的畫素段1222與第二掃描線124的畫素段1242之間至少隔開 第二距離G2,且第一距離G1大於第二距離G2。也就是說,各第一掃描線122的畫素段1222相較於過度段1224更接近於同一個掃描線組120中第二掃描線124,而各第二掃描線124的畫素段1242相較於過度段1244更接近於同一個掃描線組120中第一掃描線122,以在過度段1224與過度段1244之間保留較大的空間。在部分實施例中,第一距離G1可由12μm至15μm,而第二距離G2可由3.5μm至4μm。 In this embodiment, the transition section 1224 of the first scan line 122 and the transition section 1244 of the second scan line 124 are at least separated by a first distance G1, and the pixel section 1222 of the first scan line 122 and the second scan line 124 pixel segments at least 1242 separated The second distance G2, and the first distance G1 is greater than the second distance G2. In other words, the pixel segment 1222 of each first scan line 122 is closer to the second scan line 124 in the same scan line group 120 than the transition segment 1224, and the pixel segment 1242 of each second scan line 124 is relatively It is closer to the first scan line 122 in the same scan line group 120 than the transition section 1244, so as to reserve a larger space between the transition section 1224 and the transition section 1244. In some embodiments, the first distance G1 may be 12 μm to 15 μm, and the second distance G2 may be 3.5 μm to 4 μm.

在圖1A、1B與圖2中,不同掃描線組120的區段布局可不須對齊。舉例而言,圖2所呈現的兩組掃描線組120中,各掃描線組120的畫素段相對於另一掃描線組120的畫素段橫移一段距離。如此,兩組掃描線組120的圖案設計呈現彼此錯位而非彼此對齊的設計。另外,在同一掃描線組120中,第一掃描線122與第二掃描線124可選擇地彼此呈鏡面對稱。 In FIGS. 1A, 1B, and 2, the segment layouts of different scan line groups 120 may not be aligned. For example, in the two scan line groups 120 shown in FIG. 2, the pixel segment of each scan line group 120 is shifted by a distance relative to the pixel segment of the other scan line group 120. In this way, the pattern designs of the two scan line groups 120 are misaligned rather than aligned with each other. In addition, in the same scan line group 120, the first scan line 122 and the second scan line 124 can optionally be mirror-symmetric to each other.

由圖1A、1B與圖2可知,第一掃描線122的畫素段1222具有增寬部1222A,且增寬部1222A與第一掃描線122的轉折段1226之間相隔一間隙P1。第二掃描線124的畫素段1242具有增寬部1242A,且增寬部1242A與第二掃描線124的轉折段1246之間相隔一間隙P2。在本實施例中,增寬部1222A以及增寬部1242A用以構成圖1A、1B的各畫素結構150中的主動元件152的閘極G。不過,在其他實施例中,閘極G與掃描線的布局方式可依照不同需求而有所調整,並不限定須包括增寬部1222A與增寬部 1224A。間隙P1與間隙P2各自可由12μm至14μm。 As can be seen from FIGS. 1A, 1B and FIG. 2, the pixel segment 1222 of the first scan line 122 has a widened portion 1222A, and there is a gap P1 between the widened portion 1222A and the turning section 1226 of the first scan line 122. The pixel section 1242 of the second scan line 124 has a widened portion 1242A, and the widened portion 1242A and the turning section 1246 of the second scan line 124 are separated by a gap P2. In this embodiment, the widened portion 1222A and the widened portion 1242A are used to form the gate G of the active device 152 in each pixel structure 150 of FIGS. 1A and 1B. However, in other embodiments, the layout of the gate G and the scan line can be adjusted according to different requirements, and it is not limited to include the widening portion 1222A and the widening portion. 1224A. The gap P1 and the gap P2 may each be 12 μm to 14 μm.

圖3為依據本發明一實施例的掃描線組與半導體層的示意圖。請同時參照圖1A、1B與圖3,第一掃描線122的增寬部1222A以及第二掃描線124的增寬部1242A用以定義圖1A、1B的各畫素結構150中的主動元件152的閘極G。因此,畫素陣列基板100中,部分的半導體層C分別配置於第一掃描線122的畫素段1222的增寬部1222A,另一部分半導體層C分別配置於第二掃描線124的畫素段1242的增寬部1242A。半導體層C由半導體材料製作,其在不同電場作用下可具有不同載子遷移率,以控制主動元件152的開啟與關閉。半導體材料可包括多晶矽、非晶矽、微晶矽、半導體氧化物、有機半導體材料等。 FIG. 3 is a schematic diagram of a scan line group and a semiconductor layer according to an embodiment of the invention. 1A, 1B and FIG. 3, the widening portion 1222A of the first scan line 122 and the widening portion 1242A of the second scan line 124 are used to define the active element 152 in each pixel structure 150 of FIGS. 1A and 1B The gate G. Therefore, in the pixel array substrate 100, part of the semiconductor layer C is respectively arranged on the widened portion 1222A of the pixel section 1222 of the first scan line 122, and another part of the semiconductor layer C is respectively arranged on the pixel section of the second scan line 124 The widening of 1242 1242A. The semiconductor layer C is made of semiconductor material, which can have different carrier mobility under different electric fields, so as to control the turning on and off of the active device 152. The semiconductor material may include polycrystalline silicon, amorphous silicon, microcrystalline silicon, semiconductor oxide, organic semiconductor materials, and the like.

圖4為根據本發明一實施例的資料線、觸控訊號線及主動元件配置於圖3的結構上的示意圖。請同時參照圖1A、1B與圖4,資料線130與觸控訊號線140沿著圖面的側向方向交替排列。各條資料線130的延伸方向相交於掃描線組120,且各條觸控訊號線140的延伸方向也相交於掃描線組120。另外,各資料線130例如橫越對應的掃描線組120的第一掃描線122的畫素段1222與第二掃描線124的畫素段1242,而各觸控訊號線140則橫越對應的掃描線組120的第一掃描線122的過度段1224與第二掃描線124的過度段1244。在部分實施例中,資料線130與觸控訊號線140之間的間隔距離可維持恆定以避免彼此訊號的干擾,因此,資 料線130與觸控訊號線140彼此平行。 4 is a schematic diagram of data lines, touch signal lines, and active components arranged on the structure of FIG. 3 according to an embodiment of the present invention. Referring to FIGS. 1A, 1B and 4 at the same time, the data lines 130 and the touch signal lines 140 are alternately arranged along the lateral direction of the figure. The extension direction of each data line 130 intersects the scan line group 120, and the extension direction of each touch signal line 140 also intersects the scan line group 120. In addition, each data line 130 traverses the pixel segment 1222 of the first scan line 122 and the pixel segment 1242 of the second scan line 124 of the corresponding scan line group 120, and each touch signal line 140 traverses the corresponding The transition section 1224 of the first scan line 122 and the transition section 1244 of the second scan line 124 of the scan line group 120. In some embodiments, the separation distance between the data line 130 and the touch signal line 140 can be kept constant to avoid interference with each other's signals. The material line 130 and the touch signal line 140 are parallel to each other.

各資料線130橫越對應的畫素段1222或1224上的閘極G以及對應的閘極G上的半導體層C。製作資料線130與觸控訊號線140時,也製作出各主動元件152的源極S與汲極D。因此,源極S、汲極D、資料線130與觸控訊號線140由相同膜層構成。在本實施例中,源極S可選擇由對應的資料線130橫越閘極G的一部分構成,以電性連接於對應的資料線130。不過,在其他實施例中,源極S可選擇地由資料線130所延伸出來的分支構成。汲極D則是由獨立於資料線130與源極S的導體圖案構成。源極S與汲極D都重疊於半導體層C且可都接觸半導體層C。 Each data line 130 traverses the gate G on the corresponding pixel segment 1222 or 1224 and the semiconductor layer C on the corresponding gate G. When the data line 130 and the touch signal line 140 are fabricated, the source S and the drain D of each active element 152 are also fabricated. Therefore, the source S, the drain D, the data line 130 and the touch signal line 140 are composed of the same film layer. In this embodiment, the source S may be formed by a part of the corresponding data line 130 that crosses the gate G, and is electrically connected to the corresponding data line 130. However, in other embodiments, the source S can optionally be formed by a branch extending from the data line 130. The drain D is composed of a conductor pattern independent of the data line 130 and the source S. The source electrode S and the drain electrode D both overlap the semiconductor layer C and may both contact the semiconductor layer C.

在圖1A、1B與圖4中,位於同一條資料線130相對兩側的兩個畫素結構150的主動元件152分別連接不同的掃描線組120。以圖4而言,主動元件152A連接於掃描線組120A的第一掃描線122,而主動元件152B連接於掃描線組120B的第二掃描線124。如此,對應於主動元件152A的畫素結構150位於其中一條資料線130的第一側而對應於主動元件152B的畫素結構150位於同一條資料線130的第二側,且第一側與第二側為相反側。在此,掃描線組120A的第一掃描線122的畫素段與第二掃描線124的畫素段位於其中一條資料線130與其中一條觸控訊號線140A之間,掃描線組120B的第一掃描線122的畫素段與第二掃描線124的畫素段位於同一條資料線130與另一條觸控訊號線140B之間, 且觸控訊號線140A與觸控訊號線140B位於這條資料線130的相反兩側。 In FIGS. 1A, 1B and 4, the active devices 152 of the two pixel structures 150 located on opposite sides of the same data line 130 are connected to different scan line groups 120, respectively. In FIG. 4, the active device 152A is connected to the first scan line 122 of the scan line group 120A, and the active device 152B is connected to the second scan line 124 of the scan line group 120B. As such, the pixel structure 150 corresponding to the active device 152A is located on the first side of one of the data lines 130 and the pixel structure 150 corresponding to the active device 152B is located on the second side of the same data line 130, and the first side and the second side The two sides are opposite sides. Here, the pixel segment of the first scan line 122 and the pixel segment of the second scan line 124 of the scan line group 120A are located between one of the data lines 130 and one of the touch signal lines 140A, and the first scan line group 120B The pixel segment of one scan line 122 and the pixel segment of the second scan line 124 are located between the same data line 130 and another touch signal line 140B, In addition, the touch signal line 140A and the touch signal line 140B are located on opposite sides of the data line 130.

為了方便描述,以下以第一畫素結構150A與第二畫素結構150B來說明位於其中一條資料線130的第一側的畫素結構150與位於同一條資料線130的第二側的畫素結構150。在本實施例中,第一畫素結構150A的主動元件152A與第二畫素結構150B的主動元件152B分別連接於緊接的兩個掃描線組120A與120B。第一畫素結構150A的主動元件152A的汲極D較閘極G更接近位於對應資料線130的第一側的觸控訊號線140A。第二畫素結構150B的主動元件152B的汲極D則較閘極G更接近位於對應的資料線130的第二側的觸控訊號線140B,且第一側與第二側為相反側。 For the convenience of description, the following uses the first pixel structure 150A and the second pixel structure 150B to illustrate the pixel structure 150 located on the first side of one of the data lines 130 and the pixel located on the second side of the same data line 130. Structure 150. In this embodiment, the active element 152A of the first pixel structure 150A and the active element 152B of the second pixel structure 150B are respectively connected to the next two scan line groups 120A and 120B. The drain D of the active device 152A of the first pixel structure 150A is closer to the touch signal line 140A on the first side of the corresponding data line 130 than the gate G. The drain D of the active device 152B of the second pixel structure 150B is closer to the touch signal line 140B on the second side of the corresponding data line 130 than the gate G, and the first side and the second side are opposite sides.

各主動元件152A或152B的汲極D可包括第一端DA、第二端DB與汲極接觸部DC,其中汲極接觸部DC位於第一端DA與第二端DB之間,而第一端DA重疊於閘極G且第二端DB重疊於對應的掃描線(122或124)的轉折段(1226或1246)。以圖4中標註的主動元件152B而言,其汲極D重疊閘極G,由閘極G朝向轉折段1246延伸而橫越閘極G與轉折段1246之間的間隙P2,且汲極接觸部DC位於間隙P2中。因此,汲極D暨重疊閘極G也重疊轉折段1246。在本實施例中,間隙P2(或是圖2中的間隙P1)的寬度可設置為足夠容納汲極接觸部DC,且汲極接觸部DC可具 有足夠的面積供後續元件接觸。 The drain D of each active element 152A or 152B may include a first terminal DA, a second terminal DB, and a drain contact part DC, wherein the drain contact part DC is located between the first terminal DA and the second terminal DB, and the first terminal The end DA overlaps the gate G and the second end DB overlaps the turning section (1226 or 1246) of the corresponding scan line (122 or 124). For the active device 152B marked in FIG. 4, its drain D overlaps the gate G, extends from the gate G toward the turning section 1246 and traverses the gap P2 between the gate G and the turning section 1246, and the drain contacts The part DC is located in the gap P2. Therefore, the drain D and the overlapping gate G also overlap the turning section 1246. In this embodiment, the width of the gap P2 (or the gap P1 in FIG. 2) can be set to be sufficient to accommodate the drain contact portion DC, and the drain contact portion DC can have There is enough area for subsequent components to contact.

這些資料線130、觸控訊號線140以及汲極D是由相同膜層(例如金屬層或是其他導電材料層)圖案化而成。在製作過程中,資料線130、觸控訊號線140以及汲極D可能在製作過程中因為對位誤差而相對預定設置位置橫向位移。假設資料線130、觸控訊號線140以及汲極D相對預定設置位置朝方向D1偏移,主動元件152A的汲極D與閘極G的重疊面積會減少,不過主動元件152A的汲極D與對應的第一掃描線122的轉折段1226的重疊面積會增加。如此,主動元件152A的汲極D與第一掃描線122因彼此重疊而構成的寄生電容(可稱之為閘極-汲極電容Cgd)可與預設大小相近,不因對位誤差而改變。 The data lines 130, the touch signal lines 140, and the drain electrode D are formed by patterning the same film layer (for example, a metal layer or other conductive material layer). During the manufacturing process, the data line 130, the touch signal line 140, and the drain electrode D may be laterally displaced relative to the predetermined setting position due to alignment errors during the manufacturing process. Assuming that the data line 130, the touch signal line 140, and the drain D are offset in the direction D1 relative to the predetermined position, the overlap area of the drain D and the gate G of the active device 152A will be reduced, but the drain D of the active device 152A and The overlapping area of the turning section 1226 of the corresponding first scan line 122 will increase. In this way, the parasitic capacitance (which can be referred to as the gate-drain capacitance Cgd) formed by the drain D of the active device 152A and the first scan line 122 overlapping each other can be close to the preset size, and will not change due to alignment errors .

另外,在同樣的位移情形下,主動元件152B的的汲極D與閘極G的重疊面積會增加,不過主動元件152B的汲極D與對應的第二掃描線124的轉折段1246的重疊面積會減少。如此,主動元件152B的汲極D與對應的第二掃描線124因彼此重疊而構成的寄生電容也可與預設大小相近,不因對位誤差而改變。整體來說,主動元件152A與主動元件152B雖位於對應的資料線130相對兩側,且主動元件152A的汲極D與主動元件152B的汲極D由對應的資料線130朝相反方向延伸。不過,主動元件152A的汲極D遠離對應的資料線130的一端重疊對應的第一掃描線122的轉折段1226而主動元件152B的汲極D遠離對應的資料線130的一 端重疊對應的第二掃描線124的轉折段1246,使得無論汲極D的膜層相對於預設位置朝方向D1橫移或是朝方向D1的相反向橫移,所有主動元件152的汲極D與對應的掃描線的重疊面積都可以大致維持恆定。如此,即使發生對位誤差,畫素陣列基板100中的所有主動元件152的閘極-汲極電容仍保持大致相近而提供一致的充電特性。 In addition, under the same displacement, the overlap area of the drain D of the active device 152B and the gate G will increase, but the overlap area of the drain D of the active device 152B and the corresponding turning section 1246 of the second scan line 124 Will decrease. In this way, the parasitic capacitance formed by the drain D of the active device 152B and the corresponding second scan line 124 due to overlap with each other can also be close to the preset size, and does not change due to alignment errors. In general, the active device 152A and the active device 152B are located on opposite sides of the corresponding data line 130, and the drain D of the active device 152A and the drain D of the active device 152B extend in opposite directions from the corresponding data line 130. However, one end of the drain D of the active device 152A away from the corresponding data line 130 overlaps the corresponding turning section 1226 of the first scan line 122, and the drain D of the active device 152B is away from one of the corresponding data lines 130. The end overlaps the corresponding turning section 1246 of the second scan line 124, so that no matter if the film layer of the drain D moves in the direction D1 relative to the preset position or moves in the opposite direction of the direction D1, the drains of all the active devices 152 The overlap area between D and the corresponding scan line can be maintained approximately constant. In this way, even if an alignment error occurs, the gate-drain capacitances of all active devices 152 in the pixel array substrate 100 still remain approximately similar to provide consistent charging characteristics.

圖5為根據本發明一實施例的共用電極的示意圖,其中圖5表示出共用電極配置於圖4的結構上。請同時參照圖1A、1B與圖5,共用電極160包括電極部162、接觸部164與連接部166。接觸部164位於其中一個掃描線組120的第一掃描線122的過度段1224與第二掃描線124的過度段1244之間。連接部166橫越對應的掃描線組120的第一掃描線122的過度段1224以連接於電極部162與接觸部164之間。電極部162實質上延伸於相鄰兩組掃描線組120之間。具體而言,共用電極160可劃分出多個電極部162、多個連接部166與多個接觸部164。部分的連接部166橫越對應的掃描線組120的第一掃描線122的過度段1224以將對應的電極部162與接觸部164連接在一起,而另一部分橫越對應的掃描線組120的第二掃描線124的過度段1244以將對應的電極部162與接觸部164連接在一起。 FIG. 5 is a schematic diagram of a common electrode according to an embodiment of the present invention, wherein FIG. 5 shows that the common electrode is arranged on the structure of FIG. 4. 1A, 1B and FIG. 5 at the same time, the common electrode 160 includes an electrode portion 162, a contact portion 164 and a connection portion 166. The contact portion 164 is located between the transition section 1224 of the first scan line 122 and the transition section 1244 of the second scan line 124 of one of the scan line groups 120. The connecting portion 166 crosses the transition section 1224 of the first scan line 122 of the corresponding scan line group 120 to be connected between the electrode portion 162 and the contact portion 164. The electrode portion 162 substantially extends between two adjacent scan line groups 120. Specifically, the common electrode 160 may be divided into a plurality of electrode portions 162, a plurality of connection portions 166, and a plurality of contact portions 164. A portion of the connecting portion 166 crosses the transition section 1224 of the first scan line 122 of the corresponding scan line group 120 to connect the corresponding electrode portion 162 and the contact portion 164 together, and another portion crosses the transition section 1224 of the corresponding scan line group 120 The transition section 1244 of the second scan line 124 connects the corresponding electrode portion 162 and the contact portion 164 together.

電極部162可具有開孔162A,且開孔162A對應地露出觸控訊號線140,這有助於減少共用電極160與觸控訊號線140 之間的耦合,從而有助於提升共用電極160的觸控感測靈敏性。另外,電極部162可以橫越且重疊這些資料線130,但不橫越這些第一掃描線122與第二掃描線124。在本實施例中,共用電極160的電極部162可選擇地重疊於閘極G(例如為圖2中的增寬部1222A或1242A)的一部分,而不重疊於閘極G所連接的掃描線的其餘部分。舉例來說,電極部162可不重疊於任何掃描線(122或124)的過度段(1224或1244)。在部分的實施例中,電極部162重疊於閘極G的重疊長度LO可由1μm至3.5μm,例如約為1.5微米,而電極部162與過度段1224或1244的間隔長度LS可由1μm至3μm,例如約為1.5微米。 The electrode portion 162 may have an opening 162A, and the opening 162A correspondingly exposes the touch signal line 140, which helps to reduce the common electrode 160 and the touch signal line 140 The coupling between them helps to improve the touch sensing sensitivity of the common electrode 160. In addition, the electrode portion 162 may traverse and overlap the data lines 130, but not traverse the first scan line 122 and the second scan line 124. In this embodiment, the electrode portion 162 of the common electrode 160 can optionally overlap a part of the gate G (for example, the widened portion 1222A or 1242A in FIG. 2), and not overlap the scan line connected to the gate G The rest. For example, the electrode portion 162 may not overlap the transition section (1224 or 1244) of any scan line (122 or 124). In some embodiments, the overlap length LO of the electrode portion 162 overlapping the gate electrode G may be 1 μm to 3.5 μm, for example, about 1.5 μm, and the interval length LS between the electrode portion 162 and the transition section 1224 or 1244 may be 1 μm to 3 μm. For example, it is about 1.5 microns.

此外,接觸部164與對應的掃描線組120的第一掃描線122或第二掃描線124之間隔開第三距離G3,且第三距離G3大於零以使得接觸部164不與對應的第一掃描線122或第二掃描線124重疊。連接部166重疊於對應的過度段1224或1244,且連接部166的寬度W166相對於接觸部164的寬度明顯縮減,舉例而言,寬度W166約為4微米至5微米。因此,連接部166與掃描線(122或124)重疊面積以及電極部162與掃描線(122或124)重疊面積都不大,而共用電極160的其他部位都不重疊掃描線(122或124),這有助於避免共用電極160與掃描線組120對彼此造成負載,因而可穩定掃描線(122或124)的訊號傳輸品質,也可確保共用電極160的觸控靈敏性。 In addition, the contact portion 164 is separated from the first scan line 122 or the second scan line 124 of the corresponding scan line group 120 by a third distance G3, and the third distance G3 is greater than zero so that the contact portion 164 is not connected to the corresponding first scan line. The scan line 122 or the second scan line 124 overlap. The connecting portion 166 overlaps the corresponding transition section 1224 or 1244, and the width W166 of the connecting portion 166 is significantly reduced relative to the width of the contact portion 164. For example, the width W166 is about 4 to 5 microns. Therefore, the overlapping area of the connecting portion 166 and the scan line (122 or 124) and the overlapping area of the electrode portion 162 and the scan line (122 or 124) are not large, and the other parts of the common electrode 160 do not overlap the scan line (122 or 124). This helps to prevent the common electrode 160 and the scan line group 120 from causing a load to each other, thereby stabilizing the signal transmission quality of the scan line (122 or 124), and ensuring the touch sensitivity of the common electrode 160.

請繼續參照圖1A、1B與圖5,其中圖1A、1B表示各畫素結構150的畫素電極154配置於圖5的結構上。畫素結構150的畫素電極154重疊於共用電極160的電極部162且具有多個狹縫154S。如此,畫素電極154的狹縫154S可露出共用電極160的電極部162的部分面積,而構成邊緣電場切換型(Fringe Field Switch,FFS)畫素結構。 Please continue to refer to FIGS. 1A, 1B and 5, where FIGS. 1A and 1B show that the pixel electrodes 154 of each pixel structure 150 are arranged on the structure of FIG. 5. The pixel electrode 154 of the pixel structure 150 overlaps the electrode portion 162 of the common electrode 160 and has a plurality of slits 154S. In this way, the slit 154S of the pixel electrode 154 can expose a partial area of the electrode portion 162 of the common electrode 160 to form a fringe field switch (FFS) pixel structure.

另外,如圖1A、1B所示,畫素陣列基板100還包括導通電極170。導通電極170配置於基板110上,且連接於共用電極160的接觸部164與其中一條觸控訊號線140之間,且導通電極170與畫素電極154為相同膜層。在此,接觸部164以及導通電極170可完全位於對應一個掃描線組120的第一掃描線122與第二掃描線124之間。在部分實施例中,接觸部164以及導通電極170並不重疊對應的掃描線組120的第一掃描線122與第二掃描線124,藉此可降低共用電極160對掃描線組120造成的負載而有助於穩定掃描線組120的傳輸品質。同時,共用電極160也可因此提供良好的觸控靈敏性。 In addition, as shown in FIGS. 1A and 1B, the pixel array substrate 100 further includes a conductive electrode 170. The conductive electrode 170 is disposed on the substrate 110 and connected between the contact portion 164 of the common electrode 160 and one of the touch signal lines 140, and the conductive electrode 170 and the pixel electrode 154 are the same film layer. Here, the contact portion 164 and the conductive electrode 170 may be completely located between the first scan line 122 and the second scan line 124 corresponding to one scan line group 120. In some embodiments, the contact portion 164 and the conductive electrode 170 do not overlap the first scan line 122 and the second scan line 124 of the corresponding scan line group 120, thereby reducing the load on the scan line group 120 caused by the common electrode 160 This helps stabilize the transmission quality of the scan line group 120. At the same time, the common electrode 160 can also provide good touch sensitivity.

圖6為圖1A的剖線I-I’、II-II’的剖面示意圖。請同時參照圖1A、1B與圖6,畫素陣列基板100包括基板110、多個掃描線組120、多條資料線130、多條觸控訊號線140、多個畫素結構150、共用電極160與導通電極170外,還包括閘絕緣層182、第一保護層184與第二保護層186。閘絕緣層182、第一保護層184 與第二保護層186是配置於基板110上的絕緣材料,以隔離不同導電層之用。 Fig. 6 is a schematic cross-sectional view taken along the line I-I' and II-II' of Fig. 1A. 1A, 1B and FIG. 6 at the same time, the pixel array substrate 100 includes a substrate 110, a plurality of scan line groups 120, a plurality of data lines 130, a plurality of touch signal lines 140, a plurality of pixel structures 150, a common electrode In addition to the conductive electrodes 160 and 170, the gate insulating layer 182, the first protective layer 184 and the second protective layer 186 are further included. Gate insulating layer 182, first protective layer 184 The second protective layer 186 is an insulating material disposed on the substrate 110 to isolate different conductive layers.

閘絕緣層182是在製作完圖2的結構後製作於基板110上的。因此,閘絕緣層182覆蓋掃描線組120,也覆蓋各主動元件152的閘極G。閘絕緣層182的材質包括氧化矽、氮化矽、氮氧化矽或是其他可替代的絕緣材料。於基板110上製作閘絕緣層182後,接著於基板110上依序製作圖3的半導體層C與圖4的結構。因此,半導體層C配置於閘絕緣層182上,而資料線130與觸控訊號線140也都配置於閘絕緣層182上。在製作完圖4的結構後,各畫素結構150的主動元件152即已製作完成。 The gate insulating layer 182 is fabricated on the substrate 110 after the structure of FIG. 2 is fabricated. Therefore, the gate insulating layer 182 covers the scan line group 120 and also covers the gate G of each active device 152. The material of the gate insulating layer 182 includes silicon oxide, silicon nitride, silicon oxynitride or other alternative insulating materials. After the gate insulating layer 182 is formed on the substrate 110, the semiconductor layer C of FIG. 3 and the structure of FIG. 4 are sequentially formed on the substrate 110. Therefore, the semiconductor layer C is disposed on the gate insulating layer 182, and the data line 130 and the touch signal line 140 are also disposed on the gate insulating layer 182. After the structure of FIG. 4 is completed, the active element 152 of each pixel structure 150 is completed.

接著於基板110上形成第一保護層184,第一保護層184覆蓋主動元件152、資料線130以及觸控訊號線140。第一保護層184的材質可為有機絕緣材料、無機絕緣材料或由多層絕緣材料堆疊而成。接著,於第一保護層184上製作圖5的共用電極160。第一保護層184可提供平坦化的作用,因此共用電極160可形成在第一保護層184所提供的相對平坦的表面上。之後,於共用電極160上形成第二保護層186以將共用電極160覆蓋。第二保護層186的材質包括氧化矽、氮化矽、氮氧化矽或其他可替代的絕緣材料。 Next, a first protection layer 184 is formed on the substrate 110, and the first protection layer 184 covers the active device 152, the data line 130 and the touch signal line 140. The material of the first protection layer 184 may be an organic insulating material, an inorganic insulating material, or a stack of multiple insulating materials. Next, the common electrode 160 of FIG. 5 is formed on the first protection layer 184. The first protection layer 184 can provide a planarization effect, and therefore the common electrode 160 can be formed on a relatively flat surface provided by the first protection layer 184. After that, a second protection layer 186 is formed on the common electrode 160 to cover the common electrode 160. The material of the second protection layer 186 includes silicon oxide, silicon nitride, silicon oxynitride or other alternative insulating materials.

為了實現構件之間的連接,可在第二保護層186形成之後進行圖案化製程,以在第一保護層184與第二保護層186中形 成對應的接觸孔。舉例而言,此圖案化步驟可形成貫穿第一保護層184與第二保護層186的第一接觸孔192以及貫穿第二保護層186的第二接觸孔194。在畫素陣列基板100中,貫穿第一保護層184與第二保護層186的第一接觸孔192有兩類,其中第一接觸孔192A對應於觸控訊號線140,而第一接觸孔192B對應於汲極D。搭配圖1A、1B與圖6可知,第一接觸孔192A位於掃描線組120的第一掃描線122與第二掃描線124之間,而第一接觸孔192B位於汲極D的汲極接觸部DC上。另外,第二接觸孔194位於共用電極160的接觸部164上。 In order to realize the connection between the components, a patterning process can be performed after the formation of the second protective layer 186, so as to form a shape in the first protective layer 184 and the second protective layer 186. Into the corresponding contact hole. For example, this patterning step can form a first contact hole 192 penetrating the first protection layer 184 and the second protection layer 186 and a second contact hole 194 penetrating the second protection layer 186. In the pixel array substrate 100, there are two types of first contact holes 192 penetrating the first protection layer 184 and the second protection layer 186. The first contact hole 192A corresponds to the touch signal line 140, and the first contact hole 192B Corresponds to drain D. 1A, 1B and FIG. 6, it can be seen that the first contact hole 192A is located between the first scan line 122 and the second scan line 124 of the scan line group 120, and the first contact hole 192B is located at the drain contact portion of the drain D On DC. In addition, the second contact hole 194 is located on the contact portion 164 of the common electrode 160.

製作第一接觸孔192A、192B與第二接觸孔194後,在基板110上形成畫素電極154與導通電極170,使畫素電極154與導通電極170配置於第二保護層186上即完成圖1A、1B與圖6的畫素陣列基板100。在此,導通電極170連續延伸於第一接觸孔192A與第二接觸孔194之間。由於第一接觸孔192A露出觸控訊號線140,而第二接觸孔194露出共用電極160的接觸部164,導通電極170可在第一接觸孔192A接觸觸控訊號線140且在第二接觸孔194接觸共用電極160的接觸部164。如此,共用電極160可通過導通電極170電性連接觸控訊號線140。 After making the first contact holes 192A, 192B and the second contact hole 194, the pixel electrode 154 and the conductive electrode 170 are formed on the substrate 110, and the pixel electrode 154 and the conductive electrode 170 are arranged on the second protective layer 186 to complete the picture. 1A, 1B and the pixel array substrate 100 of FIG. 6. Here, the conductive electrode 170 continuously extends between the first contact hole 192A and the second contact hole 194. Since the first contact hole 192A exposes the touch signal line 140 and the second contact hole 194 exposes the contact portion 164 of the common electrode 160, the conductive electrode 170 can contact the touch signal line 140 in the first contact hole 192A and in the second contact hole 194 contacts the contact portion 164 of the common electrode 160. In this way, the common electrode 160 can be electrically connected to the touch signal line 140 through the conductive electrode 170.

在圖1A與1B中,第一接觸孔192A、第二接觸孔194、導通電極170以及共用電極160的接觸部164都位在掃描線組120的第一掃描線122的過度段1224以及第二掃描線124的過度段 1244之間。共用電極160電性連接觸控訊號線140的連接結構完全位於第一掃描線122與第二掃描線124因此不需犧牲畫素電極154的配置面積來實現共用電極160與觸控訊號線140的電性連接。第一接觸孔192A在第一掃描線122與第二掃描線124之間的尺寸D192A以及第二接觸孔194在第一掃描線122與第二掃描線124之間的尺寸D194都小於第一掃描線122與第二掃描線124之間的第一距離G1。因此,第一接觸孔192A、第二接觸孔194、導通電極170以及共用電極160的接觸部164都不重疊掃描線組120。在部分的實施例中,尺寸D192A與尺寸D194可分別為10μm至11μm。如此,觸控訊號線140與共用電極160的訊號對掃描線組120造成的負載可被控制,掃描線組120不致因負載增加而降低傳輸品質,且共用電極160也可保有理想的觸控靈敏性。另外,畫素電極154則是延伸於第一接觸孔192B中而與汲極D的汲極接觸部DC接觸,以實現畫素電極154與主動元件152的電連接關係。 In FIGS. 1A and 1B, the first contact hole 192A, the second contact hole 194, the conductive electrode 170, and the contact portion 164 of the common electrode 160 are all located in the transition section 1224 and the second scan line 122 of the scan line group 120. Transition section of scan line 124 Between 1244. The connection structure of the common electrode 160 electrically connected to the touch signal line 140 is completely located in the first scan line 122 and the second scan line 124, so there is no need to sacrifice the area of the pixel electrode 154 to realize the connection between the common electrode 160 and the touch signal line 140. Electrical connection. The size D192A of the first contact hole 192A between the first scan line 122 and the second scan line 124 and the size D194 of the second contact hole 194 between the first scan line 122 and the second scan line 124 are both smaller than in the first scan The first distance G1 between the line 122 and the second scan line 124. Therefore, the first contact hole 192A, the second contact hole 194, the conductive electrode 170, and the contact portion 164 of the common electrode 160 do not overlap the scan line group 120. In some embodiments, the size D192A and the size D194 may be 10 μm to 11 μm, respectively. In this way, the load on the scan line group 120 caused by the signals of the touch signal line 140 and the common electrode 160 can be controlled, the scan line group 120 will not reduce the transmission quality due to the increase in load, and the common electrode 160 can also maintain ideal touch sensitivity. Sex. In addition, the pixel electrode 154 extends in the first contact hole 192B and contacts the drain contact portion DC of the drain D, so as to realize the electrical connection relationship between the pixel electrode 154 and the active device 152.

在部分實施例中,所有第一掃描線122與所有第二掃描線124延伸到基板110周邊之後會轉向而都朝基板110的接合區延伸。面臨到掃描線組120的負載較大的情況時,多數設計會將掃描線朝向接合區延伸的線段加寬,因而增加整個畫素陣列基板100的周邊區寬度,無法達到窄邊框設計的需求。不過,本實施例利用將同一掃描線組120的第一掃描線122與第二掃描線124設計成折曲狀,且將共用電極160與觸控訊號線140的接觸結構設 置於第一掃描線122與第二掃描線124間隔較大的區段之間。如此,共用電極160重疊於掃描線組120的重疊面積減少使掃描線組120不需增加線寬即可提供理想的傳輸品質。因此,畫素陣列基板100可應用於窄邊框設計的產品中。此外,共用電極160重疊於掃描線組120的重疊面積減少也有助於降低共用電極160的負載,因此共用電極160執行觸控功能時,可提供理想的觸控性能。 In some embodiments, all the first scan lines 122 and all the second scan lines 124 extend to the periphery of the substrate 110 and then turn to extend toward the bonding area of the substrate 110. When faced with a large load on the scan line group 120, most designs will widen the line segment extending the scan line toward the bonding area, thereby increasing the width of the peripheral area of the entire pixel array substrate 100, which cannot meet the requirements of a narrow frame design. However, in this embodiment, the first scan line 122 and the second scan line 124 of the same scan line group 120 are designed to be bent, and the contact structure between the common electrode 160 and the touch signal line 140 is set It is placed between the section where the first scan line 122 and the second scan line 124 have a larger interval. In this way, the overlapping area of the common electrode 160 overlapping the scan line group 120 is reduced, so that the scan line group 120 does not need to increase the line width to provide ideal transmission quality. Therefore, the pixel array substrate 100 can be applied to products with a narrow frame design. In addition, the reduction in the overlapping area of the common electrode 160 overlapping the scan line group 120 also helps to reduce the load of the common electrode 160. Therefore, when the common electrode 160 performs a touch function, it can provide ideal touch performance.

圖7為本發明一實施例的畫素陣列基板的局部示意圖,而圖8為沿圖7的剖線III-III’與IV-IV’的剖面圖。在圖7中,畫素陣列基板200相似於圖1A、1B的畫素陣列基板100,不過圖7僅表示出一組掃描線組120。圖1A、1B與圖7的實施例中以相同或相似的標號表示相同或相似的構件,且這些構件的具體結構、功能與設計可參照前述說明。在圖7與圖8中,畫素陣列基板200包括基板110、多個掃描線組120(圖7僅繪示一組)、多條資料線130、多條觸控訊號線140(圖7僅繪示一條)、多個畫素結構250(圖7僅繪示各畫素結構250的局部)與共用電極260,其中各畫素結構250包括主動元件152與畫素電極254。本實施例與圖1A、1B的實施例的差異主要在於共用電極260與畫素電極254的疊置順序。另外,畫素陣列基板200包括閘絕緣層182與第一保護層184,但不包括圖6所示的第二保護層。 FIG. 7 is a partial schematic diagram of a pixel array substrate according to an embodiment of the present invention, and FIG. 8 is a cross-sectional view along the line III-III' and IV-IV' of FIG. In FIG. 7, the pixel array substrate 200 is similar to the pixel array substrate 100 of FIGS. 1A and 1B, but FIG. 7 only shows a set of scan line groups 120. The same or similar reference numerals in the embodiments of FIGS. 1A, 1B and FIG. 7 indicate the same or similar components, and the specific structure, function and design of these components can be referred to the foregoing description. In FIGS. 7 and 8, the pixel array substrate 200 includes a substrate 110, a plurality of scan line groups 120 (only one group is shown in FIG. 7), a plurality of data lines 130, and a plurality of touch signal lines 140 (only in FIG. One is shown), a plurality of pixel structures 250 (only a part of each pixel structure 250 is shown in FIG. 7) and a common electrode 260, wherein each pixel structure 250 includes an active element 152 and a pixel electrode 254. The main difference between this embodiment and the embodiment of FIGS. 1A and 1B lies in the stacking sequence of the common electrode 260 and the pixel electrode 254. In addition, the pixel array substrate 200 includes a gate insulating layer 182 and a first protective layer 184, but does not include the second protective layer shown in FIG. 6.

在圖7與圖8中,掃描線組120、資料線130、觸控訊號 線140、主動元件152閘絕緣層182與第一保護層184的配置關係都可參照圖1A、1B的實施例。此外,畫素電極254配置在閘絕緣層182與第一保護層184之間,且接觸主動元件152的汲極D。共用電極260則配置於第一保護層184上。如此一來,畫素電極254所在膜層是位於共用電極260所在膜層與基板110之間。共用電極260包括重疊於畫素電極254的電極部262、位於掃描線組120的第一掃描線122與第二掃描線124之間的接觸部264以及延伸跨越掃描線組120的第一掃描線122或第二掃描線124的連接部266。連接部266連接於電極部262與接觸部264之間。在畫素陣列基板200中,電極部262可具有多個狹縫262S。電極部262的狹縫262S可露出畫素電極254的部分面積,而構成邊緣電場切換型(Fringe Field Switch,FFS)畫素結構。由圖8可知,第一保護層184中形成有接觸孔290,且接觸孔290位於觸控訊號線140上。接觸部264可延伸於接觸孔290中且直接接觸對應的一條觸控訊號線140。 In FIGS. 7 and 8, the scan line group 120, the data line 130, and the touch signal The configuration relationship of the wire 140, the gate insulating layer 182 of the active device 152, and the first protection layer 184 can refer to the embodiments of FIGS. 1A and 1B. In addition, the pixel electrode 254 is disposed between the gate insulating layer 182 and the first protection layer 184 and contacts the drain D of the active device 152. The common electrode 260 is disposed on the first protection layer 184. In this way, the film layer where the pixel electrode 254 is located is located between the film layer where the common electrode 260 is located and the substrate 110. The common electrode 260 includes an electrode portion 262 overlapping the pixel electrode 254, a contact portion 264 located between the first scan line 122 and the second scan line 124 of the scan line group 120, and a first scan line extending across the scan line group 120 122 or the connecting portion 266 of the second scan line 124. The connecting portion 266 is connected between the electrode portion 262 and the contact portion 264. In the pixel array substrate 200, the electrode part 262 may have a plurality of slits 262S. The slit 262S of the electrode portion 262 can expose a part of the area of the pixel electrode 254 to form a fringe field switch (FFS) pixel structure. It can be seen from FIG. 8 that a contact hole 290 is formed in the first protection layer 184, and the contact hole 290 is located on the touch signal line 140. The contact portion 264 may extend in the contact hole 290 and directly contact a corresponding touch signal line 140.

在本實施例中,第一掃描線122與第二掃描線124的圖案設計大致相同於圖1A、1B的實施例。第一掃描線122的過度段1224與第二掃描線124的過度段1244之間隔開第一距離G1,第一掃描線122的畫素段1222與第二掃描線124的畫素段1242之間隔開第二距離G2,且第一距離G1大於第二距離G2。接觸孔290位於第一掃描線122的過度段1224與第二掃描線124的過度段 1244之間,且接觸孔290的尺寸D290不大於第一掃描線122的過度段1224與第二掃描線124的過度段1244之間的第一距離G1。因此,接觸孔290不重疊第一掃描線122也不重疊第二掃描線124。另外,接觸部264可分別與第一掃描線122及第二掃描線124隔開第三距離G3以使接觸部264不重疊第一掃描線122與第二掃描線124。因此,共用電極260重疊於掃描線組120的面積可被控制而不致造成共用電極260與掃描線組120之間的負載增加,這有助於穩定掃描線組120的訊號傳輸品質以及確保共用電極的觸控靈敏性。 In this embodiment, the pattern design of the first scan line 122 and the second scan line 124 is substantially the same as the embodiment in FIGS. 1A and 1B. The transition section 1224 of the first scan line 122 and the transition section 1244 of the second scan line 124 are separated by a first distance G1, and the distance between the pixel section 1222 of the first scan line 122 and the pixel section 1242 of the second scan line 124 Open a second distance G2, and the first distance G1 is greater than the second distance G2. The contact hole 290 is located at the transition section 1224 of the first scan line 122 and the transition section of the second scan line 124 The size D290 of the contact hole 290 is not greater than the first distance G1 between the transition section 1224 of the first scan line 122 and the transition section 1244 of the second scan line 124. Therefore, the contact hole 290 does not overlap the first scan line 122 nor the second scan line 124. In addition, the contact portion 264 may be separated from the first scan line 122 and the second scan line 124 by a third distance G3 so that the contact portion 264 does not overlap the first scan line 122 and the second scan line 124. Therefore, the area where the common electrode 260 overlaps the scan line group 120 can be controlled without increasing the load between the common electrode 260 and the scan line group 120, which helps stabilize the signal transmission quality of the scan line group 120 and ensure the common electrode The touch sensitivity.

綜上所述,本發明實施例的畫素陣列基板採用折曲型的掃描線設計,使得掃描線組中的第一掃描線與第二掃描線的間隔距離並非恆定。如此一來,共用電極與觸控訊號線相接觸的結構可以設置於第一掃描線與第二掃描線的間隔距離較大的區段,以減小共用電極重疊於掃描線組的面積,從而降低共用電極與掃描線組對彼此造成的負載。因此,本發明實施例的畫素陣列基板的掃描線組不需刻意增加線寬就可具有理想的傳輸品質,藉此有助於縮減畫素陣列基板的邊框寬度。同時,也可確保共用電極的觸控靈敏性不因負載過大而降低。另外,本發明實施例的畫素陣列基板的主動元件中,汲極的兩端都與掃描線重疊。如此,在製作過程發生對位誤差導致汲極相對預定設置位置偏移時,汲極與掃描線的重疊面積可大致維持,而提升畫素陣列基板的良率。 In summary, the pixel array substrate of the embodiment of the present invention adopts a curved scan line design, so that the separation distance between the first scan line and the second scan line in the scan line group is not constant. In this way, the structure in which the common electrode is in contact with the touch signal line can be arranged in the section where the distance between the first scan line and the second scan line is relatively large, so as to reduce the area of the common electrode overlapping the scan line group. Reduce the load caused by the common electrode and the scan line group to each other. Therefore, the scan line group of the pixel array substrate of the embodiment of the present invention can have ideal transmission quality without deliberately increasing the line width, thereby helping to reduce the frame width of the pixel array substrate. At the same time, it can also ensure that the touch sensitivity of the common electrode is not reduced due to excessive load. In addition, in the active element of the pixel array substrate of the embodiment of the present invention, both ends of the drain electrode overlap the scan line. In this way, when an alignment error occurs in the manufacturing process and the drain is shifted from the predetermined position, the overlapping area of the drain and the scan line can be maintained approximately, thereby improving the yield of the pixel array substrate.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

122:第一掃描線 1222、1242:畫素段 1224、1244:過度段 124:第二掃描線 130:資料線 140:觸控訊號線 152:主動元件 160:共用電極 162:電極部 164:接觸部 166:連接部 170:導通電極 192、192A、192B:第一接觸孔 194:第二接觸孔 A:區域 C:半導體層 D:汲極 DA:第一端 DB:第二端 DC:汲極接觸部 D192A、D194:尺寸 G:閘極 G1:第一距離 G2:第二距離 G3:第三距離 LO:重疊長度 LS:間隔長度 S:源極 W166:寬度 122: the first scan line 1222, 1242: pixel segment 1224, 1244: Transition section 124: second scan line 130: data line 140: Touch signal line 152: Active component 160: Common electrode 162: Electrode 164: Contact 166: Connection part 170: Conduction electrode 192, 192A, 192B: first contact hole 194: Second contact hole A: area C: Semiconductor layer D: Dip pole DA: first end DB: second end DC: Drain contact D192A, D194: Dimensions G: Gate G1: the first distance G2: second distance G3: third distance LO: overlapping length LS: interval length S: Source W166: width

Claims (18)

一種畫素陣列基板,包括:基板;多個掃描線組,配置於該基板上,各該掃描線組包括第一掃描線以及第二掃描線,該第一掃描線及該第二掃描線的每一者包括畫素段與接續該畫素段的過度段,其中該第一掃描線的該過度段與該第二掃描線的該過度段之間至少隔開第一距離,該第一掃描線的該畫素段與該第二掃描線的該畫素段之間至少隔開第二距離,且該第一距離大於該第二距離;多條資料線,配置於該基板上,各該資料線延伸交錯該些掃描線組;多條觸控訊號線,配置於該基板上,各該觸控訊號線延伸交錯該些掃描線組,該些資料線與該些觸控訊號線交替排列;多個畫素結構,配置於該基板上,排成陣列,各該掃描線組位於相鄰兩列畫素結構之間;以及共用電極,配置於該基板上,且該共用電極包括電極部、接觸部與連接部,該電極部重疊該些畫素結構,該接觸部位於其中一個掃描線組的該第一掃描線的該過度段與該第二掃描線的該過度段之間且電連接其中一條觸控訊號線,且該連接部橫越其中一個過度段以連接於該電極部與該接觸部之間,其中各該資料線橫越對應的掃描線組的該第一掃描線的該畫素段 以及橫越該對應的掃描線組的該第二掃描線的該畫素段,並且各該觸控訊號線橫越對應的掃描線組的該第一掃描線的該過度段以及橫越該對應的掃描線組的該第二掃描線的該過度段。 A pixel array substrate includes: a substrate; a plurality of scan line groups are arranged on the substrate, each of the scan line groups includes a first scan line and a second scan line, the first scan line and the second scan line Each includes a pixel segment and a transition segment following the pixel segment, wherein the transition segment of the first scan line and the transition segment of the second scan line are separated by at least a first distance, and the first scan The pixel segment of the line and the pixel segment of the second scan line are separated by at least a second distance, and the first distance is greater than the second distance; a plurality of data lines are arranged on the substrate, and each The data lines extend to intersect the scan line groups; a plurality of touch signal lines are arranged on the substrate, each touch signal line extends to intersect the scan line groups, and the data lines and the touch signal lines are alternately arranged A plurality of pixel structures are arranged on the substrate and arranged in an array, each of the scan line groups is located between two adjacent columns of pixel structures; and a common electrode is arranged on the substrate, and the common electrode includes an electrode portion , A contact portion and a connection portion, the electrode portion overlaps the pixel structures, the contact portion is located between the transition section of the first scan line and the transition section of the second scan line in one of the scan line groups and is electrically connected One of the touch signal lines is connected, and the connecting portion traverses one of the transition sections to connect between the electrode portion and the contact portion, wherein each data line traverses the first scan line of the corresponding scan line group Pixel segment And traverse the pixel segment of the second scan line of the corresponding scan line group, and each touch signal line traverses the transition segment of the first scan line of the corresponding scan line group and traverses the corresponding The transition section of the second scan line of the scan line group. 如申請專利範圍第1項所述的畫素陣列基板,其中該共用電極的該連接部的寬度為4微米至5微米。 In the pixel array substrate described in the first item of the scope of patent application, the width of the connecting portion of the common electrode is 4 μm to 5 μm. 如申請專利範圍第1項所述的畫素陣列基板,其中該些畫素結構的每一者包括主動元件與連接於該主動元件的畫素電極,且該畫素電極與該共用電極的該電極部重疊。 The pixel array substrate according to claim 1, wherein each of the pixel structures includes an active device and a pixel electrode connected to the active device, and the pixel electrode and the common electrode The electrodes overlap. 如申請專利範圍第3項所述的畫素陣列基板,其中該主動元件包括閘極、半導體層、源極與汲極,該閘極連接於其中一個掃描線組的該第一掃描線與該第二掃描線的其中一者的該畫素段,該半導體層重疊於該閘極,該源極連接於其中一條資料線且接觸該半導體層,而該汲極連接該畫素電極且接觸該半導體層。 The pixel array substrate according to claim 3, wherein the active device includes a gate, a semiconductor layer, a source and a drain, and the gate is connected to the first scan line and the first scan line of one of the scan line groups For the pixel segment of one of the second scan lines, the semiconductor layer overlaps the gate, the source is connected to one of the data lines and contacts the semiconductor layer, and the drain is connected to the pixel electrode and contacts the Semiconductor layer. 如申請專利範圍第4項所述的畫素陣列基板,其中該第一掃描線及該第二掃描線的每一者更包括轉折段,該轉折段連接於該畫素段與該過度段之間,且該轉折段與該閘極位於該畫素段的兩端而間隔一間隙。 The pixel array substrate according to claim 4, wherein each of the first scan line and the second scan line further includes a turning section connected to the pixel section and the transition section The turning section and the gate are located at both ends of the pixel section with a gap. 如申請專利範圍第5項所述的畫素陣列基板,其中該汲極重疊該閘極,橫越該間隙且重疊該轉折段。 The pixel array substrate according to claim 5, wherein the drain electrode overlaps the gate electrode, crosses the gap and overlaps the turning section. 如申請專利範圍第6項所述的畫素陣列基板,其中該汲極包括與該畫素電極接觸的汲極接觸部,且該汲極接觸部位於該間隙中。 According to the pixel array substrate according to claim 6, wherein the drain includes a drain contact part in contact with the pixel electrode, and the drain contact part is located in the gap. 如申請專利範圍第4項所述的畫素陣列基板,其中該些畫素結構中的第一畫素結構與第二畫素結構位於其中一條資料線的兩側,該第一畫素結構的該主動元件與該第二畫素結構的該主動元件分別連接於緊接的兩個掃描線組。 According to the pixel array substrate described in item 4 of the scope of patent application, the first pixel structure and the second pixel structure in the pixel structures are located on both sides of one of the data lines, and the first pixel structure The active element and the active element of the second pixel structure are respectively connected to two scan line groups next to each other. 如申請專利範圍第8項所述的畫素陣列基板,其中該第一畫素結構的該主動元件的該汲極較該閘極更接近該些觸控訊號線的其中一條,該第二畫素結構的該主動元件的該汲極較該閘極更接近該些觸控訊號線的另一條,該些觸控訊號線的該其中一條與該些觸控訊號線的該另一條位於該其中一條資料線的相反側。 According to the pixel array substrate described in claim 8, wherein the drain of the active element of the first pixel structure is closer to one of the touch signal lines than the gate, and the second picture The drain of the active element of the element structure is closer to the other of the touch signal lines than the gate, and the one of the touch signal lines and the other of the touch signal lines are located in the one The opposite side of a data line. 如申請專利範圍第4項所述的畫素陣列基板,其中該閘極所連接的該第一掃描線與該第二掃描線的該其中一者具有增寬部而構成該閘極,該共用電極的該電極部重疊於該閘極。 The pixel array substrate according to claim 4, wherein the one of the first scan line and the second scan line connected to the gate has a widened portion to form the gate, and the common The electrode portion of the electrode overlaps the gate electrode. 如申請專利範圍第3項所述的畫素陣列基板,其中該共用電極位於該畫素電極與該基板之間,且該畫素電極具有多個狹縫。 According to the pixel array substrate described in item 3 of the scope of patent application, the common electrode is located between the pixel electrode and the substrate, and the pixel electrode has a plurality of slits. 如申請專利範圍第11項所述的畫素陣列基板,更包括導通電極,該導通電極配置於該基板上,連接於該接觸部與該其 中一條觸控訊號線之間,且該導通電極與該畫素電極為相同膜層。 As described in item 11 of the scope of the patent application, the pixel array substrate further includes a conductive electrode disposed on the substrate and connected to the contact portion and the other Between a touch signal line, and the conductive electrode and the pixel electrode are the same film layer. 如申請專利範圍第12項所述的畫素陣列基板,更包括第一保護層及第二保護層,該第一保護層覆蓋該些觸控訊號線,該共用電極配置於該第一保護層上,該第二保護層覆蓋該共用電極,而該畫素電極與該導通電極配置於該第二保護層上,其中該導通電極藉由貫穿該第一保護層與該第二保護層的第一接觸孔而接觸該其中一條觸控訊號線,且該導通電極藉由貫穿該第二保護層的第二接觸孔而接觸該共用電極。 The pixel array substrate described in item 12 of the scope of patent application further includes a first protective layer and a second protective layer, the first protective layer covers the touch signal lines, and the common electrode is disposed on the first protective layer Above, the second protective layer covers the common electrode, and the pixel electrode and the conductive electrode are disposed on the second protective layer, wherein the conductive electrode passes through the first protective layer and the second protective layer. A contact hole contacts the one of the touch signal lines, and the conductive electrode contacts the common electrode through a second contact hole penetrating the second protection layer. 如申請專利範圍第3項所述的畫素陣列基板,其中該畫素電極位於該共用電極與該基板之間,且該共用電極具有多個狹縫。 According to the pixel array substrate described in item 3 of the scope of patent application, the pixel electrode is located between the common electrode and the substrate, and the common electrode has a plurality of slits. 如申請專利範圍第14項所述的畫素陣列基板,其中該接觸部直接接觸該其中一條觸控訊號線。 In the pixel array substrate described in claim 14, wherein the contact portion directly contacts one of the touch signal lines. 如申請專利範圍第1項所述的畫素陣列基板,其中各該掃描線組的該第一掃描線與該第二掃描線呈鏡面對稱。 According to the pixel array substrate described in the first item of the scope of patent application, the first scan line and the second scan line of each scan line group are mirror-symmetrical. 如申請專利範圍第1項所述的畫素陣列基板,其中該些掃描線組的其中一個的該第一掃描線的該畫素段與該第二掃描線的該畫素段位於其中一條資料線與其中一條觸控訊號線之間,該些掃描線組另一個的該第一掃描線的該畫素段與該第二掃描線的該畫素段位於該其中一條資料線與另一條觸控訊號線之間,且 該其中一條觸控訊號線與該另一條觸控訊號線位於該其中一條資料線的相反兩側。 The pixel array substrate according to claim 1, wherein the pixel segment of the first scan line of one of the scan line groups and the pixel segment of the second scan line are located in one of the data Line and one of the touch signal lines, the pixel segment of the first scan line and the pixel segment of the second scan line of the other scan line group are located between one of the data lines and the other touch signal line Between control signal lines, and The one touch signal line and the other touch signal line are located on opposite sides of the one data line. 如申請專利範圍第1項所述的畫素陣列基板,其中該接觸部於該基板的正投影與該其中一個掃描線組於該基板的正投影之間隔開第三距離,且該第三距離大於零。 The pixel array substrate according to claim 1, wherein the orthographic projection of the contact portion on the substrate and the orthographic projection of one of the scan line groups on the substrate are separated by a third distance, and the third distance Greater than zero.
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