TWI707451B - Memory device and method for manufacturing the same - Google Patents

Abstract

A memory device and a method for manufacturing the same are provided. A memory device includes a drain pillar structure, a source pillar structure, a charge trapping structure, a vertical channel structure and a gate structure. The drain pillar structure is formed in a first opening. The source pillar structure is formed in a second opening. The vertical channel structure and the vertical channel structure are formed in a hole partially overlapping the first opening and the second opening. The vertical channel structure is divided into two arc channel parts by the drain pillar structure and the source pillar structure. The gate structure surrounds the drain pillar structure, the source pillar structure and the vertical channel structure.

Description

Memory device and manufacturing method thereof

The present disclosure relates to memory devices and methods of manufacturing them, and more particularly to memory devices with vertical channels and methods of manufacturing them.

In modern computer systems, a dynamic random-access memory (DRAM) type memory device and a NAND flash type memory device have been widely used for storage data. Generally speaking, the advantages of DRAM type memory devices are lower latency and higher access speed, but DRAM type memory devices have limited memory capacity and cost per bit. Higher. In contrast, the advantages of the NAND flash type memory device are high storage density and lower cost per bit. However, the NAND flash type memory device has higher latency and lower access speed. Due to the huge gap in access speed between DRAM type memory devices and NAND flash type memory devices, a bottleneck occurs in the data transfer process, which in turn causes the data processing speed of the computer system to drop. Although NOR flash memory devices have already appeared on the market, NOR flash memory devices have higher access speed and lower latency than NAND flash memory devices. However, the storage density of the existing NOR flash type memory device is limited and cannot meet the large-capacity storage requirements.

In recent years, a new memory technology-storage-class memory (SCM) has been proposed. In the storage architecture of computer systems, storage-class memory is considered to be between DRAM-type memory devices and NAND. Flash memory devices can fill the gap in access speed between DRAM memory devices and NAND flash memory devices. Storage-level memory has developed many types, such as 3D XPoint memory, magnetoresistive random access memory (MRAM), and phase change memory (PCM). However, these types of storage-class memory still cannot meet all the demands for storage-class memory in the market.

Therefore, there is a need to provide a three-dimensional memory technology with high storage density, high access speed and low latency.

The present disclosure relates to memory devices and methods of manufacturing them. According to an embodiment, the manufacturing method can provide a memory device, which includes a drain columnar structure, a source columnar structure, and two arc-shaped channel components, thereby improving the storage density and operating speed of the memory device.

According to an embodiment of the disclosure, a method for manufacturing a memory device is provided. The method for manufacturing the memory device includes the following multiple steps. Holes are formed in the oxide-nitride stack. A vertical channel structure and a charge trapping structure are formed on the inner wall of the hole. A first opening and a second opening are formed, the first opening and the second opening partially overlap the hole, and the first opening and the second opening penetrate the vertical channel structure. The vertical channel structure is divided into two arc-shaped channel parts by the first opening and the second opening. A drain columnar structure and a source columnar structure are formed in the first opening and the second opening, respectively. A gate structure is formed, and the gate structure surrounds the drain columnar structure, the source columnar structure and the vertical channel structure.

According to an embodiment of the disclosure, a memory device is provided. The memory device includes a drain columnar structure, a source columnar structure, a charge trapping structure, a vertical channel structure and a gate structure. The drain columnar structure is formed in the first opening. The source columnar structure is formed in the second opening. The vertical channel structure and the charge trapping structure are formed in the hole, and the hole partially overlaps the first opening and the second opening. The vertical channel structure is divided into two arc-shaped channel parts by the drain columnar structure and the source columnar structure. The gate structure surrounds the drain columnar structure, the source columnar structure and the vertical channel structure.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

In the embodiment of the present disclosure, a memory device and a method of manufacturing the memory device are provided. According to the embodiment of the manufacturing method, a memory device can be obtained, for example, a memory device including a drain columnar structure, a source columnar structure, and two arc-shaped channel members. The two arc-shaped channel members are drained by a drain columnar structure and a source column. The structure is separated to fill the gap in access speed between the DRAM type memory device and the NAND flash type memory device, and at the same time optimize the storage density and operating speed of the memory device.

In practical applications, the embodiments of the disclosure can be implemented as a variety of different memory devices. For example, the embodiment can be applied to a three-dimensional vertical channel type memory device, but the present disclosure is not limited to this application. The following are related embodiments, in conjunction with the drawings, to describe in detail the memory device and its manufacturing method proposed in this disclosure. However, this disclosure is not limited to this. The descriptions in the embodiments, such as the detailed structure, the steps of the manufacturing method, and the material application, are for illustrative purposes only, and the scope of the disclosure to be protected is not limited to the described aspects.

At the same time, it should be noted that this disclosure does not show all possible embodiments. Those in the relevant technical field can change and modify the structures and manufacturing methods of the embodiments without departing from the spirit and scope of the present disclosure to meet the needs of practical applications. Therefore, other implementation aspects not mentioned in this disclosure may also be applicable. Furthermore, the drawings are simplified to clearly illustrate the content of the embodiments, and the size ratios on the drawings are not drawn in proportion to the actual product. Therefore, the description and the drawings are only used to describe the embodiments, rather than to limit the protection scope of the disclosure.

Moreover, the ordinal numbers used in the specification and the scope of the patent application, such as the terms "first", "second", "third", etc., are used to modify the elements of the claim, and do not in itself imply or represent the requested item. The component has any previous ordinal number, which does not represent the order of a requested component and another requested component, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a request with a certain name The component can be clearly distinguished from another requested component with the same name.

Figures 1A-14B illustrate a method for manufacturing a memory device according to an embodiment of the disclosure. FIG. 1A is a top view of an exemplary structure in this processing stage, and FIG. 1B is a cross-sectional view of an exemplary structure in this processing stage. As shown in FIGS. 1A-1B, the bottom oxide layer 102 is formed on the substrate 101, and the oxide-nitride stack is formed on the bottom oxide layer 102. The oxide-nitride stack includes a plurality of nitride layers 103 and a plurality of oxide layers 104, and the plurality of nitride layers 103 and the plurality of oxide layers 104 are along a third direction D3 perpendicular to the substrate 101 (for example, the Z direction ) Stacked alternately. In an example, the plurality of nitride layers 103 may include silicon nitride (SiN). In an example, the oxide-nitride stack may only include a nitride layer 103 and an oxide layer 104 formed on the nitride layer 103.

Next, as shown in FIGS. 2A-2B, FIG. 2A is a top view of an exemplary structure in this processing stage, and FIG. 2B is a cross-sectional view of an exemplary structure in this processing stage. In this processing stage, the oxide-nitride stack is patterned to form a plurality of holes 110, for example, the oxide-nitride stack is patterned by a photolithography process. The hole 110 may have a cylindrical shape or a conical shape, but the disclosure is not limited thereto. The hole 110 exposes the sidewall of the oxide-nitride stack. In one example, the etching process for the hole 110 can be stopped at the bottom oxide layer 102, that is, the hole 110 extends downward in the third direction D3 to penetrate the oxide-nitride stack and the bottom oxide layer 102 to The bottom oxide layer 102 is exposed. Then, the charge trapping structure 105 is formed on the oxide-nitride stack and is lined in the hole 110. In the hole 110, the charge trapping structure 105 is formed on the inner wall and bottom of the hole 110. The charge trapping structure 105 can be formed by a deposition process, such as a chemical vapor deposition (CVD) process. In one example, the charge trapping structure 105 is formed in a furnace. Next, the vertical channel structure 106 is formed on the charge trapping structure 105, and the charge trapping structure 105 is exposed at the bottom of the hole 110.

The charge trapping structure 105 described above may include a multilayer structure, such as ONO (oxide-nitride-oxide), ONONO (oxide-nitride-oxide-nitride- Oxide), ONONONO (oxide-nitride-oxide-nitride-oxide-nitride-oxide), SONOS (silicon-oxide-nitride-oxide-silicon), BE-SONOS (energy band Gap engineered silicon-oxide-nitride-oxide-silicon (bandgap engineered silicon-oxide-nitride-oxide-silicon), TANOS (tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, tantalum nitride) , aluminum oxide, silicon nitride, silicon oxide, silicon), and MA BE-SONOS (metal-high-k bandgap-silicon-oxide-nitride-oxide-silicon) engineered silicon-oxide-nitride-oxide-silicon)), or other types of charge trapping layers, or a combination of these layers. In an example, the vertical channel structure 106 may include polysilicon.

Next, as shown in FIGS. 3A-3B, FIG. 3A is a top view of an exemplary structure in this processing stage, and FIG. 3B is a cross-sectional view of an exemplary structure in this processing stage. The dielectric material 107 is formed on the vertical channel structure 106 and fills the hole 110. The dielectric material 107 may include oxide.

FIG. 4A is a top view of an exemplary structure in this processing stage, and FIG. 4B is a cross-sectional view of an exemplary structure in this processing stage. In this processing stage, the charge trapping structure 105, the vertical channel structure 106 and the dielectric material 107 above the oxide-nitride stack are removed to expose the top of the oxide-nitride stack and move in the first direction D1 (For example: X direction) to form a flat top surface of the structure. In one example, a planarization process may be applied to the structure. The planarization process stops at the vertical channel structure 106 on the oxide-nitride stack. The planarization process may be chemical-mechanical planarization (chemical-mechanical planarization; CMP). )deal with. Next, an etching process is applied to the structure, and the etching process stops at the top of the oxide-nitride stack. In an example, as shown in FIG. 4B, the charge trapping structure 105 has a hollow columnar shape and one end is closed, while the vertical channel structure 106 has a hollow columnar shape and both ends are open.

FIG. 5A is a top view of the exemplary structure after the processing stage shown in FIG. 4A-4B, and FIG. 5B is a cross-sectional view of the exemplary structure along the line P5 of FIG. 5A. The first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517 are formed to partially overlap with the hole 110. The first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517 can be formed by a dry etching process, but the present disclosure is not limited thereto. The first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517 extend downward in the third direction D3 to penetrate the oxide-nitride stack, the charge trapping structure 105, the vertical channel structure 106 and the dielectric Material 107. In an example, in the third direction D3, the first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517 stop at the bottom oxide layer 102. In an example, in the third direction D3, the depths of the first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517 are greater than the depth of the hole 110 in the third direction D3. In an example, the first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517 may have a cylindrical shape or a conical shape, but the present disclosure is not limited thereto.

The first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517 are formed on both sides of the hole 110. In an example, the first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517 are formed on opposite sides of the hole 110.

After the first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517 are formed, the vertical channel structure 106 in the hole 110 is divided by the first openings 510, 512, 514, and 516 and the second openings 511, 513, 515 and 517 are divided into two arc-shaped channel parts. In an example, the arc-shaped channel members are respectively disposed on the inner walls of the opposite side of the hole 110. In addition, the charge trapping structure 105 is divided into two arc-shaped charge trapping parts by the first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517.

FIG. 6A is a top view of the exemplary structure after the processing stage shown in FIG. 5A-5B, and FIG. 6B is a cross-sectional view of the exemplary structure along the line P6 of FIG. 6A. In this processing stage, the drain columnar structure 601 and the source columnar structure 602 are formed in the first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517, respectively. Specifically, conductive material is deposited in the first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517, and then the top surface of the structure is planarized to form the drain column structure 601 and Source columnar structure 602. The drain columnar structure 601 and the source columnar structure 602 directly contact the charge trapping structure 105 and the vertical channel structure 106. The charge trapping structure 105 in the hole 110 is divided into two arc-shaped charge trapping components by the drain columnar structure 601 and the source columnar structure 602. The vertical channel structure 106 in the hole 110 is divided into two arc-shaped channel parts by the drain columnar structure 601 and the source columnar structure 602. Two ends of the arc-shaped channel component are respectively connected to the drain columnar structure 601 and the source columnar structure 602.

In one example, the conductive material may include N+ polysilicon (N+ polysilicon). In an example, the planarization process may be a chemical mechanical planarization process. In an example, when the first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517 partially overlap the hole 110, the drain columnar structure 601 and the source columnar structure 602 are partially located in the hole 110 In the middle, and partly outside the hole 110. In one example, the drain columnar structure 601 and the source columnar structure 602 are both partially located in the hole 110 and partially located outside the hole 110. In an example, one of the drain columnar structure 601 and the source columnar structure 602 is partly located in the hole 110 and partly outside the hole 110, and the drain columnar structure 601 and the source columnar structure 602 The other one is completely disposed in the hole 110. On a plane including the first direction D1 and the second direction D2 (that is, on the D1-D2 plane), the cross-sectional area of the drain columnar structure 601 and the source columnar structure 602 can be smaller than that of the hole 110 on the D1-D2 plane Sectional area, but this disclosure does not limit this.

As shown in FIG. 6A, on the D1-D2 plane, the hole 110 has a center point C1, and the distance between the edge of the hole 110 and the center point C1 is defined as the distance R1 (ie the radius of the hole 110). The maximum distance between the edge of the drain columnar structure 601 and the center point C1 is defined as the distance R2. The maximum distance between the edge of the source columnar structure 602 and the center point C1 is defined as the distance R3. The distance R2 and the distance R3 are greater than the distance R1. In an example, the distance R2 and the distance R3 are both greater than the distance R1.

In one example, on the D1-D2 plane, at least one of the drain columnar structure 601 and the source columnar structure 602 may be intersected with the edge of the hole 110 to generate more than two dissimilar points. For example, on the D1-D2 plane, the edge of the drain columnar structure 601 and the edge of the hole 110 are staggered to produce two dissimilar points. For example, on the D1-D2 plane, the edge of the source columnar structure 602 is staggered with the edge of the hole 110 to generate two dissimilar points. For example, on the D1-D2 plane, the edge of the drain columnar structure 601 and the edge of the source columnar structure 602 and the edge of the hole 110 are respectively staggered at two dissimilar points, resulting in four dissimilar points.

FIG. 7A is a top view of the exemplary structure after the processing stage shown in FIG. 6A-6B, and FIG. 7B is a cross-sectional view of the exemplary structure along the line P7 of FIG. 7A. In this processing stage, the oxide-nitride stack is patterned to form slits 710 and 712 and stops at the bottom oxide layer 102, for example, by patterning the oxide-nitride stack by photolithography. The slits 710 and 712 extend downward in the third direction D3 to penetrate the oxide-nitride stack and the bottom oxide layer 102 to expose the bottom oxide layer 102.

FIG. 8A is a top view of the exemplary structure after the processing stage shown in FIG. 7A-7B, and FIG. 8B is a cross-sectional view of the exemplary structure along the line P8 of FIG. 8A. Next, as shown in FIGS. 8A-8B, the plurality of nitride layers 103 in the oxide-nitride stack are removed through the slits 710 and 712 to form a cavity 103x. The cavity 103x is originally the plurality of nitride layers 103 Where it is generated. The plurality of nitride layers 103 can be removed by an etching process. The cavity 103x exposes part of the sidewalls of the drain columnar structure 601, the source columnar structure 602, and the charge trapping layer 105, and these exposed sidewalls are originally in contact with the plurality of nitride layers 103.

FIG. 9A is a top view of the exemplary structure after the processing stage shown in FIG. 8A-8B, and FIG. 9B is a cross-sectional view of the exemplary structure along the line P9 of FIG. 9A. Next, as shown in FIGS. 9A-9B, a plurality of dielectric portions 601s are disposed on the sidewalls of the drain columnar structure 601 and the source columnar structure 602 exposed by the cavity 103x. In an example, the dielectric portion 601s can be formed by applying oxidation treatment to the sidewalls of the drain columnar structure 601 and the source columnar structure 602 exposed by the cavity 103x. In an example, the dielectric portion 601s may include polysilicon oxide. The width of the dielectric portion 601s in the second direction D2 is about 200 angstroms (angstrom; Å), more preferably greater than 200 angstroms, but the present disclosure does not limit this value. The dielectric portion 601s can avoid or improve the short-circuit problem caused by the contact between the word line and the drain columnar structure 601 or the contact between the word line and the source columnar structure 602.

FIG. 10A is a top view of the exemplary structure after the processing stage shown in FIG. 9A-9B, and FIG. 10B is a cross-sectional view of the exemplary structure along the line P10 of FIG. 10A. In this processing stage, a high dielectric constant (high-k) material layer 108 is formed on the sidewalls and bottoms of the slits 710 and 712, and on the walls where the plurality of oxide layers 104 are exposed by the void 103x , Formed on the sidewall of the charge trapping structure 105 exposed by the cavity 103x, and formed on the sidewall of the exposed dielectric portion 601s. In other words, the high dielectric constant material layer 108 is lined and formed in the slits 710 and 712 and the cavity 103x. The high dielectric constant material layer 108 may include high dielectric constant materials, such as aluminum oxide (Al ₂ O ₃ ), hafnium dioxide (HfO ₂ ), silicon nitride (Si ₃ N ₄ ), zirconium dioxide (ZrO ₂₎ ), titanium dioxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), lanthanum oxide (La ₂ O) or other suitable materials. The high dielectric constant material layer 108 can be formed by a deposition process or a wet etching process with a phosphoric acid (H ₃ PO ₄ ) solution.

FIG. 11A is a top view of the exemplary structure after the processing stage shown in FIG. 10A-10B, and FIG. 11B is a cross-sectional view of the exemplary structure along the line P11 of FIG. 11A. In this processing stage, the gate material 103g is formed in the remaining space between the cavity 103x and the slits 710 and 712. In an example, the gate material 103g is deposited in the remaining space between the cavity 103x and the slits 710 and 712. The gate material 103g may include metal, such as titanium nitride (TiN), tantalum nitride (TaN), and the like.

FIG. 12A is a top view of the exemplary structure after the processing stage shown in FIG. 11A-11B, and FIG. 12B is a cross-sectional view of the exemplary structure along the line P12 of FIG. 12A. Next, an etching back process is applied to the structure to remove part of the gate material 103g through the slits 710 and 712, thereby forming a plurality of recesses 710r and 712r, as shown in FIG. 12B. In an example, each of the plurality of recesses 710r and 712r is a lateral recess, extending from the slits 710 and 712 (along the second direction D2) into the gate material 103g. Therefore, each of the alcoves 710r connects the slit 710, and each of the alcoves 712r connects the slit 712. Each of the recesses 710r can be defined as a space formed by two adjacent oxide layers 104, the gate material 103g between the two adjacent oxide layers 104, and the slit 710. Each of the recesses 712r can be defined as a space formed by two adjacent oxide layers 104, the gate material 103g between the two adjacent oxide layers 104, and the slit 712. After the etch-back process, the remaining gate material 103g can be regarded as a gate structure, and the gate structure surrounds the drain columnar structure 601, the source columnar structure 602, and the vertical channel structure 106. The dielectric portion 601s is formed between the drain column structure 601 and the gate structure, or between the source column structure 602 and the gate structure.

Thus, a plurality of memory cells are formed in the structure. Each memory cell includes a drain columnar structure 601, a source columnar structure 602, two arc-shaped channel members and 103g of gate material (ie, gate structure), the two arc-shaped channel members are formed in a hole 110 Between the drain column structure 601 and the source column structure 602. Each memory unit is a dual channel type.

In an embodiment of the present disclosure, after the processing stage shown in FIGS. 12A-12B, the processing stage shown in FIGS. 13A-14B may be applied to the exemplary structure.

FIG. 13A is a top view of the exemplary structure after the processing stage shown in FIG. 12A-12B, and FIG. 13B is a cross-sectional view of the exemplary structure along the line P13 of FIG. 13A. In this processing stage, a low temperature oxide (LTO) layer 109 is formed in the slits 710 and 712, and then a trench 115 is formed. The trench 115 extends downward in the third direction D3 to penetrate the low temperature oxide layer 109. The trench 115 exposes the low-temperature oxide layer 109, but the gate material 103g (that is, the gate structure) and the high dielectric constant material layer 108 are not exposed by the trench 115. In one example, the low temperature oxide layer 109 is formed in the slits 710 and 712 by a deposition process, and then the low temperature oxide layer 109 is etched to form the trench 115.

Next, as shown in FIGS. 14A-14B, a conductive film 116 is formed in the trench 115. FIG. 14A is a top view of the exemplary structure after the processing stage shown in FIG. 13A-13B, and FIG. 14B is a cross-sectional view of the exemplary structure along the line P14 of FIG. 14A. In one example, the conductive film 116 is deposited in the trench 115 and fills the trench 115, and then chemical mechanical planarization is applied to the structure. In an example, the conductive film 116 may include the same material as the gate material 103g. In the slits 710 and 712, the low-temperature oxide layer 109 separates the conductive film 116 and the gate material 103g.

Next, the external circuit 120 is connected to the conductive film 116 to apply current to the conductive film 116. The current passing through the conductive film 116 can generate heat, which is also known as Joule heating. The heat generated by this process helps to repair the memory cell.

According to the disclosure, the drain columnar structure and the source columnar structure of the memory device partially overlap the holes formed in the vertical channel structure, so that the size of the holes can be reduced. Therefore, the benefits of the present invention are that the size of each memory cell in the memory device is reduced, the storage density and memory capacity of the memory device are increased, and the size of the memory device is reduced. In addition, the architecture of the memory device proposed in the present invention can perform random access, that is, regardless of the memory address to be read or written, it can be completed in the same time. Therefore, compared to only the serial type For block access NAND flash type memory devices, the memory device proposed in the present invention has a higher access speed. Furthermore, compared with the traditional planar (2D) structure memory device, the memory device proposed in the present invention has a three-dimensional stacked structure, so the storage density and memory capacity of the memory device can be significantly improved.

It should be noted that the above-mentioned drawings, structures and steps are used to describe some embodiments or application examples of the present disclosure, and the present disclosure is not limited to the scope and application of the above-mentioned structures and steps. Other embodiments with different structural aspects, such as known components of different internal components, can be applied, and the structure and steps of the examples can be adjusted according to actual application requirements. Therefore, the structure of the drawings is only used for illustration, not for limiting the present invention. Generally, the knowledgeable person should know that the relevant structures and steps of the application of the present disclosure, such as the arrangement or configuration of the relevant elements and layers in the memory device, or the details of the manufacturing steps, etc., may be as required by the actual application. There are corresponding adjustments and changes.

To sum up, although the present invention has been disclosed as above by embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

101: substrate 102: bottom oxide layer 103: Nitride layer 103g: Gate material 103x: Hollow 104: oxide layer 105: charge trapping structure 106: vertical channel structure 107: Dielectric materials 108: high dielectric constant material layer 109: low temperature oxide layer 110: Hole 115: groove 116: conductive film 120: external circuit 510, 512, 514, 516: first opening 511, 513, 515, 517: second opening 601: Drain columnar structure 601s: Dielectric Department 602: source columnar structure 710, 712: slit 710r, 712r: Alcove C1: Center point D1: First direction D2: second direction D3: Third party P5-P14: line R1, R2, R3: distance

Figures 1A-14B illustrate a method for manufacturing a memory device according to an embodiment of the disclosure.

103g: Gate material

108: high dielectric constant material layer

710, 712: slit

710r, 712r: Alcove

D1: First direction

D2: second direction

D3: Third party

Claims (10)

A manufacturing method of a memory device includes: Forming a hole in an oxide-nitride stack; Forming a vertical channel structure and a charge trapping structure on an inner wall of the hole; A first opening and a second opening are formed, the first opening and the second opening partially overlap the hole, and the first opening and the second opening penetrate the vertical channel structure, wherein the vertical channel structure is covered by the second opening. One opening and the second opening are separated into two arc-shaped channel parts; Forming a drain columnar structure and a source columnar structure in the first opening and the second opening respectively; and A gate structure is formed, and the gate structure surrounds the drain columnar structure, the source columnar structure and the vertical channel structure. According to the manufacturing method described in claim 1, wherein in the step of forming the drain columnar structure and the source columnar structure in the first opening and the second opening, respectively, the drain columnar The structure or the source columnar structure is partially located in the hole and partially located outside the hole. According to the manufacturing method described in claim 1, wherein in the step of forming the drain columnar structure and the source columnar structure in the first opening and the second opening, each of the arcs The two ends of the channel component are respectively connected to the drain columnar structure and the source columnar structure. The manufacturing method described in claim 1, wherein in the step of forming the first opening and the second opening, the charge trapping structure is divided into two arcs by the first opening and the second opening Charge trapping components. A memory device includes: A drain columnar structure formed in a first opening; A source columnar structure formed in a second opening; A charge trapping structure; A vertical channel structure, the vertical channel structure and the charge trapping structure are formed in a hole, the hole partially overlaps the first opening and the second opening, wherein the vertical channel structure is formed by the drain column structure and the source The pole-shaped structure is divided into two arc-shaped channel parts; and A gate structure surrounds the drain columnar structure, the source columnar structure and the vertical channel structure. The memory device according to claim 5, wherein the drain columnar structure or the source columnar structure is partly located in the hole, and the drain columnar structure or the source columnar structure is partly Located outside the hole. In the memory device described in claim 5, in a plane, a maximum distance between an edge of the drain columnar structure and a center point of the hole is greater than a radius of the hole. As for the memory device described in item 5 of the scope of patent application, the two ends of each arc-shaped channel member are respectively connected to the drain columnar structure and the source columnar structure. The memory device described in item 5 of the scope of patent application further includes a dielectric portion formed between the drain columnar structure and the gate structure. In the memory device described in item 5 of the scope of patent application, the charge trapping structure is divided into two arc-shaped charge trapping components by the drain columnar structure and the source columnar structure.

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