TWI705326B - Adapt to data output device - Google Patents

Abstract

A technology for realizing an adaptive data output device is proposed. The adaptive data output device has a highly reliable structure and a structure that is easy to quantitatively evaluate its reliability.

The first arithmetic processing unit (10) memorizes the first part of the adaptation data that is partly missing the adaptation data, and selects the first part of the adaptation data corresponding to the combination of the input condition signal (CS) and outputs it to the synthesis The output unit (30) is used as the first part to adapt to the data signal (PS1). The second arithmetic processing unit (20) memorizes the missing part and the second part adaptation data which is different from the first part adaptation data, and selects and outputs the second part adaptation data corresponding to the combination of the input condition signal (CS) To the composite output part (30) as the second part adapted to the data signal (PS2). The synthesis output unit (30) synthesizes the first part of the adaptive data signal (PS1) and the second part of the adaptive data signal (PS2), generates an adaptive data signal (AS) carrying the complete adaptive data, and transmits and outputs.

Description

Adapt to data output device

The present invention relates to a device for inputting a condition signal indicating the operation status or detection condition of a plurality of devices in a railway travel security system, and outputting a combination of adaptation data adapted to the condition signal.

Railways require high security, so various security measures are imposed and various systems for security are constructed. One of them is a driving security system that ensures safety when the train is running to avoid accidents. The driving security system includes a device to ensure blocking, a signal aspect device, a device to interlock signals, a device to automatically decelerate or stop a train, and a device to automatically travel , Devices used to detect trains, devices used to ensure the safety of level crossings, and various devices.

For each device of the driving security system, high reliability is required as much as possible. In terms of security devices, it is reasonable. For example, in the case of an electronically controlled device, a dual-system configuration of arithmetic processing units such as a CPU (Central Processing Unit) is adopted (refer to Patent Document 1).

[Prior Technical Literature] [Patent Literature]

[Patent Document 1] JP 2013-161354 A

In a railway travel security system, an adaptive data output device is used to input a condition signal that indicates the operation status of a plurality of devices or detect a situation, and output a combination of adaptation data that adapts to the condition signal. For example, an above-ground device that inputs signals indicating the respective time phases of a plurality of signals, and outputs data indicating the position or distance the train can enter for the combination of these signals is one of them. Since this adaptive data output device operates under electronic control, it also adopts a dual system configuration with the arithmetic processing unit.

However, in the conventional adaptive data output device, the calculation processing unit of each system performs the same processing, and the failure judgment unit judges the calculation processing unit of each system by comparing the data output from the calculation processing unit of each system Faults, and output the final adaptation data. Therefore, it is difficult to quantitatively evaluate reliability.

Specifically, quantitative reliability can be expressed in numerical values such as failure rate. In order to calculate the failure rate, it is necessary to assume the possibility of any failure and to search for the cause or location of the failure that may occur. However, the previous adaptive data output device, due to the processing unit The mutual relationship or actions are complicatedly involved. Therefore, even if one type of failure possibility is cited, it is sometimes difficult to divide the processing unit one by one and calculate the failure rate for the failure possibility. In addition, there are mechanisms for detecting faults everywhere. Although a mechanism is designed to detect faults in other places even if a missed fault detection occurs in one place, the mechanism is complicated and therefore sometimes difficult to quantify. To evaluate the reliability of the entire device. In addition, in the method of comparing the data from the calculation processing unit of each system, the common circuit, that is, the failure judgment unit, becomes complicated, and it is difficult to reduce the failure rate of the device.

The present invention was developed in order to solve the above problems, and its purpose is to propose a technology for realizing an adaptive data output device, which has a highly reliable structure and a structure that is easy to quantitatively evaluate its reliability. .

The first invention to solve the above-mentioned problems is an adaptive data output device, in a railway travel security system, which inputs in parallel status signals indicating the operation status or detection status of a plurality of devices, and adapts the The adaptive data output device for transmitting and outputting the adaptive data signal of the combination of the status signals of each device is provided with: a first calculation processing unit with a memory command and a part of the adaptive data that can be obtained as the combination of the aforementioned status signals is missing The first part of the adaptation data is the first storage part, and the first part of the adaptation data corresponding to the combination of the actual input of the situation signal is read from the first storage part and output as the first part of the adaptation data signal; The second arithmetic processing unit has a memory missing part that is different from the adaptation data of the first part. By combining with the adaptation data of the first part, a second memory of the second adaptation data of the complete adaptation data can be created. And read out the second partial adaptation data corresponding to the combination of the actual input status signal from the second storage unit and output it as the second partial adaptation data signal; the synthesis output unit will be received from the first arithmetic processing unit The outputted first partial adaptation data signal and the second partial adaptation data signal output from the second arithmetic processing unit are combined to generate the aforementioned adaptation data signal carrying the complete adaptation data, which is transmitted and output.

According to this first invention, the first arithmetic processing unit has a memory command and a first memory unit that can obtain the first part of the adaptation data corresponding to the combination of the status signal. The combination of the input status signals corresponds to the first part adaptation data and is output as the first part adaptation data signal. On the other hand, the second arithmetic processing unit has a memory missing part that is different from the adaptation data of the first part. By combining with the adaptation data of the first part, a second memory of the second adaptation data of the complete adaptation data can be made. Part, and read out the second part adaptation data corresponding to the combination of the actual input status signal and output it as the second part adaptation data signal. Therefore, the first arithmetic processing unit and the second arithmetic processing unit do not carry the data of the other party's system, so the independence between the systems can be improved. In addition, the synthesis output unit synthesizes the first part of the adaptation data signal and the second part of the adaptation data signal, generates an adaptation data signal carrying the complete adaptation data, and transmits and outputs it.

In this way, neither the first partial adaptation data signal output from the first calculation processing unit nor the second partial adaptation data signal output from the second calculation processing unit carry complete adaptation data. , The content of the information contained is different. Therefore, when the reliability of the entire device is quantitatively evaluated, it can be relatively simple by dividing the first calculation processing unit, the second calculation processing unit, and the synthesis output unit to calculate the failure rate individually and independently. Calculate the failure rate of the entire device. In other words, it is possible to facilitate quantitative evaluation of reliability. In addition, when calculating the failure rate, it is possible to easily determine the occurrence of an assumed failure, so the calculation of the failure rate of the entire device can be facilitated.

In addition, a second invention is an adaptive data output device as in the first invention, wherein the first calculation processing unit, the second calculation processing unit, and the composite output unit operate using separate power and clock signals , And the input and output interfaces of each other's signals are insulated.

According to this second invention, the power supply and even the clock signal of the first arithmetic processing unit, the second arithmetic processing unit, and the combined output unit are individually independent, and the input and output interfaces of each other's signals are insulated. Therefore, the independence of the operations of the first arithmetic processing unit, the second arithmetic processing unit, and the composite output unit is improved, and the quantitative evaluation of the reliability of the entire device becomes easier.

In addition, the third invention is an adaptive data output device as in the first or second invention, wherein the first memory section and the data of the adaptive data carried in the adaptive data signal The data format has the same data format, and the memory sets the missing part of the data as the aforementioned first part of the adaptation data of the prescribed data, and the aforementioned second memory part has the same data format as the data format of the adaptation data carried in the aforementioned adaptation data signal , And the memory sets the missing part of the data as the aforementioned second part of the specified data, and the aforementioned synthesis output unit combines the aforementioned first part of the adaptive data signal and the aforementioned second part of the adaptive data signal one by one, thereby Generate the aforementioned adaptation data signal.

According to this third invention, the first part of the adaptation data and the second part of the adaptation data and the adaptation data are in the same data format, and the missing part becomes the data storing the prescribed data, so the synthesis processing in the synthesis output unit can be simplified. Therefore, the reliability can be improved.

In addition, a fourth invention is an adaptive data output device according to any one of the first to third inventions, wherein the first calculation processing unit obtains the status input by the second calculation processing unit from the second calculation processing unit Combination of signals, compare the obtained combination with the combination of the status signal input to the first arithmetic processing unit, if they are different, set the input status signal combination as undetermined, and when they match In this case, the combination of the input status signals is determined as definite, and the aforementioned first part adaptation data corresponding to the determined status signal combination is read out and the aforementioned first part adaptation data signal is output. The aforementioned second calculation processing unit, Obtain the combination of the status signal input from the first arithmetic processing unit from the first arithmetic processing unit, and compare the obtained combination with the combination of the status signal input to the second arithmetic processing unit, and the result is different In the case of, set the combination of the input status signals as undetermined, when they are consistent, set the combination of the input status signals as confirmed, and read out the above part 2 corresponding to the combination of the confirmed status signals Adapt to the data and output the aforementioned Part 1 Adapted Data signal.

According to this fourth invention, the first arithmetic processing unit and the second arithmetic processing unit can exchange the combination of the input status signals with each other, and confirm the consistency with the combination of the status signals input to themselves. Therefore, when the input status signal changes, it is possible to prevent the acquisition error of the status signal caused by the error in the time point of the acquisition of the first arithmetic processing unit and the second arithmetic processing unit, and to improve the reliability.

In addition, the fifth invention is an adaptive data output device according to any one of the first to fourth inventions, wherein the aforementioned adaptive data is configured to include a data body and an error detection symbol, the aforementioned first part of the adaptive data and the aforementioned second part of the adaptive data The data is structured to include the complete error detection symbols described above, and part of the data body is lacking in different ways.

According to this fifth invention, the first part of the adaptation data and the second part of the adaptation data, the data in the adaptation data is partly lacking in this system, but the error detection symbol contains complete data.

In addition, the sixth invention is the adaptive data output device according to the fifth invention, wherein the first calculation processing unit inputs the feedback signal of the adaptive data signal and executes the first memory stored in the first storage unit. The error detection symbol in the partial adaptation data is used to check the adaptation data carried in the aforementioned adaptation data signal The second arithmetic processing unit inputs the request signal of the adaptation data signal, and executes checking the adaptation data signal by the error detection symbol in the second part adaptation data stored in the second memory unit The processing of the submitted adaptation data.

According to this sixth invention, each of the first arithmetic processing unit and the second arithmetic processing unit can check whether the adaptation data transmitted and output including the processing result of the dual system is correct. Therefore, the ability to detect failures is improved, and the reliability is improved.

In addition, a seventh invention is an adaptive data output device according to the sixth invention, wherein the synthesis output unit has a switching circuit for cutting off the transmission output, and the first arithmetic processing unit, when the result of the inspection is bad In case, the switching circuit is turned off, and the second arithmetic processing unit turns off the switching circuit when the result of the inspection is bad.

According to this seventh invention, each of the first arithmetic processing unit and the second arithmetic processing unit checks whether the adaptive data signal is correct or not, and when the result of any one of the inspections becomes bad, the transmission and output of the adaptive data signal Be stopped.

In addition, the eighth invention is the adaptive data output device according to any one of the first to seventh inventions, wherein the aforementioned status signal indicates the time phase of a signal that is in advance of a predetermined position and is greater than the aforementioned The signal of any one of the route selected by the turnout that is within the specified position and the position of the train that is within the specified position. The aforementioned adaptation data is for signals located at the aforementioned specified position or outside the aforementioned specified position. The aforementioned composite output unit transmits and outputs the aforementioned adaptive data signal to the ground transmitter, which is used for the driving support or driving control data of the train in the rear of. The train sends the aforementioned adaptation data.

According to this eighth invention, it is possible to set any of the time phase of a signal that is within a predetermined position, a route selected by a switch that is within a predetermined position, and the position of a train that is located within a predetermined position. The signal input of the other is used as the status signal, and the transmission output sets the data for the travel support or travel control of the train at the specified location or at the specified location as the adaptation data signal of the adaptation data.

1‧‧‧Adapt to data output device

10‧‧‧The first calculation processing unit

12‧‧‧Calculation Circuit Section 1

14‧‧‧First memory

20‧‧‧The second calculation processing unit

22‧‧‧Calculation Circuit Section 2

24‧‧‧Second Memory Department

30‧‧‧Synthetic output

32‧‧‧Composition Department

34‧‧‧Modulation circuit

36‧‧‧Demodulation circuit

38‧‧‧Clock generator for synthesis

CS‧‧‧Status signal

AS‧‧‧Adapt to data signal

[Figure 1] A configuration diagram of an adaptive data output device.

[Figure 2] A schematic diagram of an example of the structure of the first part of the adaptation data stored in the first storage unit.

[Figure 3] A schematic diagram of an example of the structure of the second part of the adaptation data stored in the second storage unit.

[Figure 4] A schematic diagram of the relationship between the adaptation data, the first part adaptation data, and the second part adaptation data.

[Figure 5] A schematic flowchart of the processing flow executed by the first arithmetic processing unit and the second arithmetic processing unit.

Hereinafter, an example of an embodiment to which the present invention is applied will be described.

The adaptive data output device 1 of this embodiment is an on-ground device that transmits and outputs a signal carrying data for traveling support or traveling control to an on-ground signal for a train traveling on a track. The data used for driving support or driving control is the adaptation data, and the signal transmitted and output to the ground transmitter is the adaptation data signal AS. The ground transmitter sends the adaptation data carried in the received adaptation data signal AS to the train.

In addition, the adaptive data output device 1 of the present embodiment inputs in parallel signals indicating the respective operating status or detection status of a plurality of devices in the railway travel security system as the status signal CS. Specifically, it indicates the time phase of a signal that is within a predetermined position of the track, a route selected by a turnout that is within a predetermined position (also referred to as the opening direction), and is located at a predetermined position. The signal of any one of the positions of the trains on the inside is input as the status signal CS. The status signal CS is a bundle of multiple signals input in parallel. Each signal is a signal indicating the time phase of one signal, or the opening direction of one switch (the currently selected route), and the position of each train.

The status indicated by the status signal CS indicates the railway line The operation status or detection status signal of multiple devices in the driving security system. Therefore, the time interval of change depends on the time interval of the train. The shortest one is several seconds to tens of seconds, depending on the situation, it can reach several minutes to tens of minutes. . Therefore, compared with the internal operation cycle of the adaptive data output device 1 operated by electronic control, it can be said that the signal changes at a very long time interval.

FIG. 1 is a schematic diagram of the circuit configuration of the adaptive data output device 1.

Applicable to the data output device 1, there are roughly 3 circuit blocks. The first calculation processing unit 10, the second calculation processing unit 20, and the composite output unit 30. The first arithmetic processing unit 10 and the second arithmetic processing unit 20 are circuit blocks for realizing the arithmetic processing of the dual system, and the composite output unit 30 is a combination of the first arithmetic processing unit 10 and the second arithmetic processing unit 20 The output signal of is synthesized to generate the adaptive data signal AS, and the output circuit block is transmitted to the outside (the ground transmitter in this embodiment).

In addition, the first arithmetic processing unit 10, the second arithmetic processing unit 20, and the composite output unit 30 each operate using independent power and clock signals. In other words, the first arithmetic processing unit 10 operates based on the first clock generated by the first clock generating unit 61 by the power supply power supplied from the first power supply unit 51. The second arithmetic processing unit 20 operates based on the second clock generated by the second clock generating unit 62 by the power supply power supplied from the second power supply unit 52. The composite output unit 30 operates based on the third clock generated by the third clock generation unit 63 by the power supply power supplied from the third power supply unit 53.

In addition, the first calculation processing unit 10 and the second calculation processing unit 20 and the composite output unit 30 are insulated from each other's signal input and output interfaces. In this embodiment, a photocoupler is used as the circuit for insulation, but it may be designed to use a circuit other than a photocoupler such as a pulse transformer to insulate the output and input of each other's signals.

Therefore, the operation independence of the first arithmetic processing unit 10, the second arithmetic processing unit 20, and the synthesis output unit 30 is improved, and therefore, the quantitative evaluation of the reliability of the entire data output device 1 can be easily performed. In other words, when calculating the failure rate, the range of possible failures can be divided into the first arithmetic processing unit 10, the second arithmetic processing unit 20, and the composite output unit 30 to consider each, so it adapts to the failure rate of the entire data output device 1 The calculation will become easier.

The first calculation processing unit 10 includes a first calculation circuit unit 12, a transmission output cut-off driver 16, and a relay QR1.

The first arithmetic circuit unit 12 is configured to have a calculation device such as a CPU (Central Processing Unit) or an integrated circuit such as an ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), etc., as a memory of the first memory unit 14, etc. . The first arithmetic circuit unit 12 reads out the first partial adaptation data corresponding to the combination of the input status signal CS from the first storage unit 14 based on the program or data stored in the first storage unit 14, and outputs it to the synthesis The output unit 30 adapts to the data signal PS1 as the first part.

In addition to the programs executed by the first calculation circuit unit 12, the first storage unit 14 also stores first part adaptation data corresponding to various combinations that can be obtained as the status signal CS as shown in FIG. part 1 Adaptation data is information that is partially lacking in adaptation data.

4 is a schematic diagram of the relationship between the adaptation data, the first partial adaptation data, and the second partial adaptation data stored in the second storage unit 24 of the second arithmetic processing unit 20, schematically showing the data format. Adaptation data is the data that adapts to the input status signal CS, and is also the data that should be transmitted to the train through the ground communication machine, and is used for driving support or running control of the train corresponding to the situation indicated by the status signal CS. Adaptation data is roughly divided into data body, and error detection symbols. The error detection symbol is the data used to check the content (ie, bit value) of the data body. Of course, it can also be set to check the data of the entire adaptation data including the data body and error detection symbols.

The first part of the adaptation data and the second part of the adaptation data, in order to make the adaptation data part of the lack of data, the missing parts of each other are different. Therefore, the first part of the adaptation data and the second part of the adaptation data are combined to form a complete adaptation data. To be more specific, the first part of the adaptation data and the second part of the adaptation data are the data that are missing every predetermined bit in the body of the adaptation data, and they contain complete data in terms of error detection symbols. The unit of the specified bit that is lacking may be every 1 bit or every digit. In the missing part, data indicating the missing state (for example, Low bit value, or NULL value) is stored. In addition, in the examples of Fig. 2 and Fig. 3, it is designed to set the number of bits that make the interaction missing to 4 bits, and store the Low bit value (="0") in the missing part.

Therefore, the first part of the adaptation data and the second part of the adaptation data The data is the same as the adapted data in terms of data format, and the error detection symbol contains complete data.

The first arithmetic circuit unit 12 reads out the first partial adaptation data corresponding to the combination of the input status signal CS from the first storage unit 14, and outputs it as the first partial adaptation data signal PS1. 1 Part of the adaptation data will be in the same data format as the adaptation data carried in the adaptation data signal AS sent and output by the synthesis output unit 30.

In addition, the first arithmetic circuit unit 12 inputs a feedback signal FS adapted to the data signal AS from the synthesis output unit 30. In the feedback signal FS, adaptation data are carried. The first arithmetic circuit unit 12 checks the adaptation data by the complete error detection symbol of the first adaptation data. As a result of the inspection, when it is judged that there is an error in the adaptive data, it can be regarded as a failure of the adaptive data output device 1, so the first arithmetic circuit unit 12 will cut off the transmission and output of the adaptive data signal AS.

Specifically, a cut-off instruction signal (Low signal) is output to the transmission output cut-off driver 16. The transmission output cut-off driver 16 is composed of a charge pump circuit. It is a circuit that controls the action (loading)/falling of the relay QR1. The relay QR1 is in charge of the switching circuit, which is the construction of the action contact HR1/ Open switching. When it is normal, the first arithmetic circuit unit 12 outputs an alternating signal that repeats Low/High in a certain cycle to the transmission output cutoff driver 16. In the transmission output cut-off driver 16, the charge pump circuit thus operates by repeating the input of the Low/High alternating signal in a certain period, and applies a predetermined voltage to the relay QR1. As a result, the relay QR1 becomes an action (push up) state, The two ends of the action contact HR1 become a state of construction.

On the other hand, when it is judged that the adaptation data has an error, the first arithmetic circuit unit 12 outputs a cut-off instruction signal (Low signal) to the transmission cut-off driver 16. In this case, the transmission output cut-off driver 16 stops the charge pump circuit, thereby stopping the voltage application to the relay QR1. As a result, the relay QR1 falls, and the two ends of the operating contact HR1 become open.

In other words, if the transmission output cut-off driver 16 maintains the input of an alternating signal that repeats Low/High in a certain cycle, the predetermined voltage is continuously applied to the relay QR1, and when the input of the alternating signal stops, a cut-off instruction is input In the case of a signal (Low signal), the voltage application is immediately stopped and the relay QR1 falls. In this way, the action contact HR1 becomes an open circuit. The action contact HR1 is inserted with a signal line for outputting the adaptive data signal AS. Therefore, when the action contact HR1 becomes an open circuit, the output of the adaptive data signal AS will be cut off immediately.

Although the first calculation processing unit 10 has been described, the second calculation processing unit 20, which is the other processing unit of the dual system, also has the same configuration.

That is, the second calculation processing unit 20 includes the second calculation circuit unit 22, the transmission output cutoff driver 26, and the relay QR2.

The second arithmetic circuit unit 22 is configured to have a calculation device such as a CPU or an integrated circuit such as an ASIC or FPGA as a memory of the second storage unit 24. The second arithmetic circuit unit 22 reads and inputs from the second storage unit 24 based on the program or data stored in the second storage unit 24 The combination of the signal CS corresponds to the second part adaptive data, and is output to the synthesis output unit 30 as the second part adaptive data signal PS2.

The second storage unit 24, in addition to the program executed by the second calculation circuit unit 22, as shown in FIG. 3, also stores second part adaptation data corresponding to various combinations that can be obtained as the status signal CS. The second part of the adaptation data, referring to Figure 4, has the above-mentioned structure. In addition, the second part of the adaptation data carried in the second part of the adaptation data signal PS2 output by the second arithmetic circuit unit 22 is also the same as the adaptation data carried in the adaptation data signal AS sent and output by the synthesis output unit 30 Data format.

In addition, the second arithmetic circuit section 22 inputs a feedback signal FS adapted to the data signal AS from the synthesis output section 30. In the feedback signal FS, adaptation data are carried. The second arithmetic circuit unit 22 checks the adaptation data by the complete error detection symbol of the second adaptation data. As a result of the inspection, when it is judged that there is an error in the adaptive data, it can be regarded as a failure of the adaptive data output device 1, so the second arithmetic circuit unit 22 cuts off the transmission and output of the adaptive data signal AS. Specifically, a cut-off instruction signal (Low signal) is output to the transmission output cut-off driver 26. The transmission output cut-off driver 26 is a circuit that controls the action (loading)/dropping of the relay QR2. The relay QR2 is in charge of the switching circuit, that is, the switching of the construction/opening of the action contact HR2. The transmission output cutoff driver 26, the relay QR2, and the action contact HR2 have the same configuration as the transmission output cutoff driver 16, the relay QR1, and the action contact HR1, respectively. Action contact HR2, together with action contact HR1, is inserted for input A signal line that adapts to the data signal AS. Therefore, even if the operating contact HR1 does not become an open circuit state, the output of the adaptive data signal AS will be cut off immediately by the operating contact HR2 becoming an open circuit state.

As mentioned above, the first calculation processing unit 10, the second calculation processing unit 20, and the composite output unit 30 operate based on independent clock signals. Therefore, the actions of each other may be wrong. As a countermeasure, the adaptive data output device 1 has various configurations.

First, the first arithmetic circuit unit 12 and the second arithmetic circuit unit 22 mutually output and input data indicating the combination of the captured status signal CS. Then, the first calculation circuit unit 12 and the second calculation circuit unit 22 compare the combination of the status signal CS captured by the first calculation circuit unit 12 and the status signal CS captured by the second calculation circuit unit 22. Whether the combination is consistent. Since the first arithmetic circuit unit 12 and the second arithmetic circuit unit 22 are different in operating clock signals, there will be an error in the time when the condition signal CS is taken in, so they must be compared. If the comparison result is inconsistent, the first arithmetic circuit unit 12 and the second arithmetic circuit unit 22 will ignore the condition signal CS captured this time, and output the previously captured condition signal CS corresponding to the condition signal CS. The first part is adapted to the data signal PS1 and the second part is adapted to the data signal PS2. In addition, when the inconsistency of the comparison result continues for a predetermined number of times, it is regarded as a failure, and a cut-off instruction signal (Low signal) is output to the transmission output cut-off drivers 16, 26.

When one of the first arithmetic circuit unit 12 and the second arithmetic circuit unit 22 is taken in at the time before the status signal CS changes, and the other is taken at the time immediately after the status signal CS changes If the status signal CS is taken in, it will be inconsistent. However, at the next acquisition time, the possibility of acquiring the same status signal CS is extremely high. This is because the time interval during which the status signal CS changes is extremely long compared to the period of the operating clock signal.

With this configuration, it is prevented that the status signal CS referred to by the first arithmetic processing unit 10 differs from the status signal CS referenced by the second arithmetic processing unit 20 due to an error in the time point of entry, and the first part adapts to the data signal PS1 and the second partial adaptation data signal PS2 become signals that do not match each other.

In addition, in order to prevent the time point when the first partially adapted data signal PS1 is output from the first calculation circuit section 12 and the time point when the second partially adapted data signal PS2 is output from the second calculation circuit section 22, the first The calculation circuit unit 12 and the second calculation circuit unit 22 commonly use the clock signal CC generated by the synthesis clock generation unit 38 included in the synthesis output unit 30. In other words, the first arithmetic circuit unit 12 and the second arithmetic circuit unit 22 output the first partially adapted data signal PS1 and the second partially adapted data signal PS2 based on the common clock signal CC. More specifically, based on the rise or fall of the clock signal CC, the first part adaptive data signal PS1 and the second part adaptive data signal PS2 are outputted one bit by one bit. In this way, for the synthesis output unit 30, the first partially adapted data signal PS1 and the second partially adapted data signal PS2 will be input at the same time point in the same bit sequence.

Next, explain another circuit block that is the composite output unit 30. The synthesis output unit 30 includes a synthesis unit 32, a modulation circuit 34, a demodulation circuit 36, a synthesis clock generation unit 38, a contact HR1, and a contact HR2; it is the first output from the first arithmetic processing unit 10 The first part of the adaptive data signal PS1 and the second part of the adaptive data signal PS2 output from the second arithmetic processing unit 20 are combined to generate the adaptive data signal AS carrying the complete adaptive data and transmit the output circuit block.

The synthesis unit 32 is a circuit unit that synthesizes the first partial adaptation data signal PS1 and the second partial adaptation data signal PS2 based on the clock signal CC generated by the synthesis clock generation unit 38 to generate and output complete adaptation data . As mentioned above, the first part of the adaptation data and the second part of the adaptation data are in the same data format as the adaptation data (see Figure 4). The first part of the adaptation data signal PS1 and the second part of the adaptation data signal PS2 are based on the same bit. The sequence is input to the synthesis unit 32 at the same time. Therefore, based on the clock signal CC, the synthesis unit 32 can adapt the first part to the bit value indicated by the data signal PS1 and the second part to the bit value indicated by the data signal PS2 by a logic circuit. The logic calculus is synthesized. For example, if the bit value of the missing part of the signal data is set to Low, the logic circuit can be constructed using an OR circuit.

The signal (adaptation data) synthesized by the synthesis unit 32 is output to the modulation circuit 34 through the contact HR1 and the contact HR2 connected in series. The modulation circuit 34 modulates in accordance with the communication protocol for the transmission of the ground transmitter, thereby generating and transmitting the adaptive data signal AS carrying the signal (adaptive data) synthesized by the synthesis unit 32 The output circuit.

The adaptation data signal AS transmitted and output is fed back to the first calculation processing unit 10 and the second calculation processing unit 20 as the feedback signal FS. However, since the adaptive data signal AS is modulated, it is fed back to the first arithmetic processing unit 10 and the second arithmetic processing unit 20 as the feedback signal FS through the demodulation circuit 36 to remove it.

Next, referring to FIG. 5, the flow of processing executed by the first arithmetic processing unit 10 and the second arithmetic processing unit 20 will be described. FIG. 5 is a schematic flowchart showing the flow of processing executed by the first calculation processing unit 10 and the second calculation processing unit 20.

First, the first arithmetic processing unit 10 and the second arithmetic processing unit 20 take in the status signal CS (step A2), output the combined data of the received status signal CS to the counterpart system (step A4), and input the counterpart from the counterpart system Combination data of the status signal CS captured by the system (step A6). Then, it is compared whether the condition signals CS acquired by each other match (step A8). When they match (step A10: YES), the counter value is reset (step A11), and if it is the first arithmetic processing unit 10, the combination of the status signal CS read from the first memory unit 14 and fetched corresponds to it If the first part of the adaptation data is the second arithmetic processing unit 20, the second part of the adaptation data corresponding to the combination of the condition signal CS read and retrieved from the second memory unit 24 is selected/updated as the latest partial adaptation Data (step A12).

If the comparison result is inconsistent (step A10: NO), the counter value is incremented by "1" (step A13), if the counter value is a predetermined value (for example, a value above "2" is appropriate, but "1" "Also) Up (step A14: YES), cut off the transmission and output of the adaptive data signal AS (step A22) and end the process. If the counter value is not greater than the predetermined value (step A14: NO), skip step A12, do not update the partial adaptation data, and proceed to the processing of step A15 or lower.

In step A15, the latest partial adaptation data is output to the synthesis output unit 30 as a partial adaptation data signal (step A15). If it is the first arithmetic processing unit 10, it outputs as the first partial adaptation data signal PS1, and if it is the second arithmetic processing unit 20, it outputs as the second partial adaptation data signal PS2.

Next, the first calculation processing unit 10 and the second calculation processing unit 20 input the feedback signal FS adapted to the data signal AS (step A16). Then, the adaptive data carried in the adaptive data signal AS is checked by the complete error detection symbol in the partial adaptive data (step A18). In the case of the first arithmetic processing unit 10, the check is performed by the error detection symbol of the first partial adaptation data, and in the case of the second arithmetic processing unit 20, the check is performed by the error detection symbol of the second partial adaptation data.

As a result of the check, when the adapted data is correct and there is no error (step A20: YES), the process returns to step A2, and the process of steps A2~A20 is repeated. When it is judged that there is an error in the adaptive data and it is bad (step A20: NO), the transmission and output of the adaptive data signal AS is cut off (step A22). If it is the first arithmetic processing unit 10, it outputs a cut-off instruction signal (Low signal) to the transmission output cut-off driver 16. If it is the second arithmetic processing unit 20, it outputs a cut-off instruction signal (Low signal) to the transmission output cut-off driver 26. ).

〔Effect〕

According to the above embodiment, the first arithmetic processing unit 10 has a memory command and a first memory unit 14 that can obtain the first partial adaptation data corresponding to the combination of the status signal CS, which is partially missing, and The first partial adaptation data corresponding to the combination of the actual input status signal CS is read out and output as the first partial adaptation data signal PS1. On the other hand, the second arithmetic processing unit 20 has a memory missing part that is different from the first part of the adaptation data. By combining with the first part of the adaptation data, the second part of the second part of the complete adaptation data can be created. The storage unit 24 reads out the second partial adaptation data corresponding to the combination of the actual input status signal and outputs it as the second partial adaptation data signal PS2. Therefore, the first arithmetic processing unit and the second arithmetic processing unit do not carry the data of the other party's system, so the independence between the systems can be improved. In addition, the synthesis output unit 30 synthesizes the first part of the adaptation data signal and the second part of the adaptation data signal to generate and output the adaptation data signal AS carrying the complete adaptation data.

Neither the first partial adaptation data signal PS1 output from the first arithmetic processing unit 10 nor the second partial adaptation data signal PS2 output from the second arithmetic processing unit 20 carries the complete adaptation data , In addition, the content of the materials carried is different. Therefore, when the reliability of the entire device is quantitatively evaluated, by dividing each of the first arithmetic processing unit 10, the second arithmetic processing unit 20, and the synthesis output unit 30, and separately and independently calculate the failure rate, it is possible to It’s relatively easy to calculate the overall failure rate. In other words, it is possible to facilitate quantitative evaluation of reliability. In addition, when calculating the failure rate, it is possible to easily limit the occurrence of the assumed failure to any one of the first arithmetic processing unit 10, the second arithmetic processing unit 20, and the composite output unit 30, thereby enabling the entire device to fail Rate calculation becomes easy.

In addition, the power and clock signals of the first arithmetic processing unit 10, the second arithmetic processing unit 20, and the combined output unit 30 are individually independent, and the input/output interfaces of each other's signals are insulated by, for example, an optical coupler. Therefore, the independence of the operations of the first arithmetic processing unit 10, the second arithmetic processing unit 20, and the composite output unit 30 is improved, and the quantitative evaluation of the reliability of the entire device becomes easier.

[Modifications]

Although an example of the embodiment in which the present invention is applied has been described, the mode in which the present invention can be applied is not limited to the above-mentioned embodiment.

For example, the signal used to control the signal phase of a signal machine installed at a predetermined position is output as a device that adapts to the data signal AS, or an action instruction signal for a crossing barrier of a level crossing is output as The device that adapts to the data signal AS, the device that outputs the switching instruction signal of a certain switch machine as a device that adapts to the data signal AS, etc., can also use the adaptive data output device of the present invention. In addition, as a linkage device in a small-scale traveling section, the adaptive data output device of the present invention can also be used.

In addition, it can be used not only as an on-ground device, but also as an on-vehicle device. use.

1‧‧‧Adapt to data output device

10‧‧‧The first calculation processing unit

12‧‧‧Calculation Circuit Section 1

14‧‧‧First memory

16‧‧‧Transmission output cut-off driver

20‧‧‧The second calculation processing unit

22‧‧‧Calculation Circuit Section 2

24‧‧‧Second Memory Department

26‧‧‧Transmission output cut-off driver

30‧‧‧Synthetic output

32‧‧‧Composition Department

34‧‧‧Modulation circuit

36‧‧‧Demodulation circuit

38‧‧‧Clock generator for synthesis

51‧‧‧The first power supply unit

52‧‧‧Second Power Supply Unit

53‧‧‧The third power supply section

61‧‧‧The first clock generation part

62‧‧‧The second clock generation part

63‧‧‧The third clock generation part

AS‧‧‧Adapt to data signal

CC‧‧‧Clock signal

CS‧‧‧Status signal

FS‧‧‧Feedback signal

HR1, HR2‧‧‧action contact

PS1‧‧‧Part 1 Adaptation to Data Signal

PS2‧‧‧Part 2 Adaptation to Data Signal

QR1, QR2‧‧‧Relay

Claims (8)

An adaptive data output device, in the railway driving security system, input in parallel status signals indicating the operation status or detection status of a plurality of devices, and adapt the combined data signal of the combination of the status signals of each device An adaptive data output device for transmission and output, including: a first calculation processing unit, a first memory unit that has a memory command and a first part of the adaptive data that is partly missing from the combination of the aforementioned status signals. , And read out the first partial adaptation data corresponding to the combination of the actual input status signal from the first storage unit and output it as the first partial adaptation data signal; the second arithmetic processing unit has memory missing parts and The aforementioned first part of the adaptation data is different. By combining with the aforementioned first part of the adaptation data, the second part of the second part of the complete adaptation data can be made, and the second part of the second part of the adaptation data can be read and actually input from the aforementioned second memory part. The combination of the aforementioned condition signals corresponds to the aforementioned second partial adaptation data and outputs it as a second partial adaptation data signal; the synthesis output unit is to output the aforementioned first partial adaptation data signal from the aforementioned first arithmetic processing unit, and from The second partial adaptation data signal output by the second arithmetic processing unit is synthesized to generate the adaptation data signal carrying the complete adaptation data, which is transmitted and output. The adaptive data output device described in claim 1, wherein the first arithmetic processing unit, the second arithmetic processing unit, and the composite output unit operate using individual power and clock signals, and The input and output interfaces of each other's signals are insulated. For example, the adaptive data output device described in item 1 or 2 of the scope of patent application, wherein the first memory section and the data format of the adaptive data carried in the adaptive data signal have the same data format, and the memory will be missing part of the data format The data is defined as the aforementioned first part of the adaptation data of the prescribed data, the aforementioned second memory section has the same data format as the data format of the adaptation data carried in the aforementioned adaptation data signal, and the memory sets the missing part of the data as the prescribed data For the second part of the adaptive data, the synthesis output unit sequentially synthesizes the first part of the adaptive data signal and the second part of the adaptive data signal one by one, thereby generating the aforementioned adaptive data signal. The adaptive data output device described in item 1 or 2 of the scope of patent application, wherein the first arithmetic processing unit obtains the combination of the status signals input by the second arithmetic processing unit from the second arithmetic processing unit, and The obtained combination is compared with the combination of the status signal input to the first arithmetic processing unit. If they are different, the input status signal combination is set as undetermined, and if they match, it will be input The combination of the status signal is determined as determined, and the aforementioned first partial adaptation data corresponding to the combination of the confirmed status signal is read out and the aforementioned first partial adaptation data signal is output. The aforementioned second arithmetic processing unit performs the aforementioned first calculation The processing unit obtains the combination of the status signal input from the first arithmetic processing unit, and combines the obtained combination with the status signal input to the second arithmetic processing unit Combine the combinations, set the combination of the input status signals as undetermined when they are different, and set the combination of the input status signals as definite when they are the same, and read the combination of the status signals that are confirmed Output the aforementioned first part adaptive data signal corresponding to the aforementioned second part adaptation data. For the adaptation data output device described in item 1 or 2 of the scope of patent application, wherein the aforementioned adaptation data is constituted to include the data body and error detection symbols, and the aforementioned part 1 adaptation data and the aforementioned part 2 adaptation data are constituted to include Complete the aforementioned error detection symbols, and make the aforementioned data body partly lacking in different ways. The adaptive data output device described in item 5 of the scope of patent application, wherein the first arithmetic processing unit inputs the feedback signal of the adaptive data signal, and executes the first partial adaptation stored in the first memory unit The error detection symbol in the data is used to check the processing of the adaptive data carried in the adaptive data signal. The second arithmetic processing unit inputs the feedback signal of the adaptive data signal, and executes the foregoing stored in the second memory unit The second part is to adapt the error detection symbol in the data to check the processing of the adaptive data carried in the aforementioned adaptive data signal. The adaptive data output device described in item 6 of the scope of patent application, wherein the synthesis output unit has a switch whether to cut off the transmission output The circuit, the first arithmetic processing unit, if the result of the inspection is bad, the switching circuit is cut off, and the second arithmetic processing unit, if the result of the inspection is bad, the switching circuit is cut off. The adaptive data output device described in item 1 or 2 of the scope of patent application, wherein the aforementioned status signal is selected to indicate the time phase of a signal that is within a predetermined position, and a switch that is within a predetermined position. Signals of any one of the route and the position of the train located inside than the aforementioned predetermined position. The aforementioned adaptation data is used for driving support or running control of the train located at the aforementioned predetermined position or outside the aforementioned predetermined position The aforementioned composite output unit sends and outputs the aforementioned adaptation data signal to the ground transmitter, which transmits the aforementioned adaptation data to the train located outside the predetermined position.

Images