JP2017081449A - Adaptive data output device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for realizing an adaptive data output device having a configuration that facilitates quantitative evaluation of reliability even while the configuration is highly reliable.SOLUTION: A first arithmetic processing unit 10 stores first part adaptive data in which adaptive data is partially omitted, selects the first part adaptive data corresponding to the combination of inputted status signals CS, and outputs the selected first part adaptive data as a first part adaptive data signal PS1 to a synthetic output unit 30. A second arithmetic processing unit 20 stores second part adaptive data which is different in omission part from the first part adaptive data, selects the second part adaptive data corresponding to the combination of the inputted status signals CS, and outputs the selected second part adaptive data as a second part adaptive data signal PS2 to the synthetic output unit 30. The synthetic output unit 30 synthesizes the first part adaptive data signal PS1 and the second part adaptive data signal PS2 to generate an adaptive data signal AS for carrying complete adaptive data, and transmits and outputs the adaptive data signal AS.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a device for inputting status signals indicating operation statuses or detection statuses of a plurality of devices and outputting adaptive data adapted to the combination of the status signals in a railway driving security system.

  Since high safety is required for railways, various safety measures have been taken and various systems for safety have been established. One of them is a driving security system that ensures driving safety so that an accident does not occur when driving a train. The operation and security system includes a device for securing a block, a device for indicating a traffic light, a device for linking signals, a device for automatically decelerating or stopping a train, a device for operating automatically, and detecting a train And various devices such as a device for ensuring the safety of a railroad crossing.

  Each device related to the operation security system is required to have the highest possible reliability. Since it is a security device, it is natural. For example, in the case of a device that operates by electronic control, a configuration is adopted in which an arithmetic processing unit such as a CPU (Central Processing Unit) is made into two systems (see Patent Document 1).

JP 2013-161354 A

  In the railway driving security system, an adaptive data output device is used which inputs status signals indicating the operating status or detection status of a plurality of devices and outputs adaptive data adapted to the combination of the status signals. For example, a ground device that inputs a signal indicating the current status of each of a plurality of traffic lights and outputs data indicating a position or distance at which the train can enter for a combination of these signals. Since this adaptive data output device also operates by electronic control, a configuration having two systems of arithmetic processing units is employed.

  However, in the conventional adaptive data output device, the arithmetic processing units of each system perform the same processing, and the failure determination unit compares the data output from the arithmetic processing units of each system, thereby comparing each system. The failure of the arithmetic processing unit is judged and final adaptive data is output. For this reason, it has been difficult to quantitatively evaluate the reliability.

  Specifically, quantitative reliability can be indicated by a numerical value called a failure rate. In order to calculate the failure rate, it is necessary to identify the cause of failure that may occur and the location of the failure, assuming the possibility of occurrence of any failure. However, in the conventional adaptive data output apparatus, since the relationship and operation between the processing units are complicatedly entangled, even if one failure possibility is taken, the processing unit is separated one by one and the failure rate with respect to the failure possibility It was sometimes difficult to calculate In addition, a mechanism for detecting a failure is provided everywhere, and even if a failure detection is missed at one location, a mechanism that can detect a failure at another location is provided, but the mechanism is complicated. Therefore, it may be difficult to quantitatively evaluate the reliability of the entire apparatus. Further, in the method of comparing data from the arithmetic processing units of each system, the failure determination unit that is a common circuit becomes complicated, and it is difficult to reduce the failure rate of the apparatus.

  The present invention has been devised in order to solve the above-described problems, and the object of the present invention is an adaptation having a configuration in which it is easy to quantitatively evaluate the reliability while having a highly reliable configuration. It is to propose a technique for realizing a data output device.

The first invention for solving the above-described problems is
In a railway driving security system, an adaptive data output device (in which a situation signal indicating the operation status or detection status of a plurality of devices is input in parallel and an adaptive data signal adapted to the combination of the status signals of the devices is transmitted and output ( For example, the adaptive data output device 1) of FIG.
A first storage unit (for example, the first storage unit 14 in FIG. 1) that stores first partial adaptation data in which adaptation data corresponding to combinations that can be taken as the status signal is partially lost is actually input. A first arithmetic processing unit (for example, the first arithmetic processing of FIG. 1) that reads out the first partial adaptive data corresponding to the combination of the status signals that has been read from the first storage unit and outputs the first partial adaptive data signal Part 10),
A second storage unit that stores second partial adaptation data (for example, FIG. 5) that is different from the first partial adaptation data and has a missing portion and can be made into complete adaptation data by combining with the first partial adaptation data. The second partial adaptive data corresponding to the actually inputted combination of the status signals is read from the second storage unit and output as a second partial adaptive data signal. A second arithmetic processing unit (for example, the second arithmetic processing unit 20 in FIG. 1),
The first partial adaptive data signal output from the first arithmetic processing unit and the second partial adaptive data signal output from the second arithmetic processing unit are combined to carry complete adaptive data. A combined output unit (for example, combined output unit 30 in FIG. 1) that generates the adaptive data signal and performs transmission output;
Is an adaptive data output device.

  According to the first invention, the first arithmetic processing unit has the first storage unit that stores the first partial adaptive data in which the adaptive data corresponding to the combinations that can be taken as the situation signal is partially lost. The first partial adaptive data corresponding to the combination of the actually input status signals is read out and output as the first partial adaptive data signal. On the other hand, the second arithmetic processing unit stores second partial adaptation data that is different from the first partial adaptation data and can be made into complete adaptation data by combining with the first partial adaptation data. A second storage unit is provided for reading out the second partial adaptive data corresponding to the combination of the actually input status signals and outputting it as a second partial adaptive data signal. For this reason, since the 1st arithmetic processing part and the 2nd arithmetic processing part do not have the data of an other party mutually, the independence between systems can be raised. Then, the combined output unit combines the first partial adaptive data signal and the second partial adaptive data signal, generates an adaptive data signal carrying the complete adaptive data, and transmits and transmits it.

  However, neither the first partial adaptive data signal output from the first arithmetic processing unit nor the second partial adaptive data signal output from the second arithmetic processing unit carries complete adaptive data. Also, the contents of the data being conveyed are different. Therefore, when quantitatively evaluating the reliability of the entire device, the failure rate is calculated independently by separating each of the first arithmetic processing unit, the second arithmetic processing unit, and the combined output unit, and thus the entire device. The failure rate can be calculated relatively easily. That is, quantitative evaluation of reliability can be facilitated. In addition, since it is possible to easily determine the location of the expected failure when calculating the failure rate, it is possible to easily calculate the failure rate of the entire apparatus.

In addition, the second invention,
The first arithmetic processing unit, the second arithmetic processing unit, and the combined output unit operate using different power sources and clock signals, and input / output interfaces of the signals are isolated from each other.
It is the adaptive data output device of the first invention.

  According to the second aspect of the invention, the power supply and the clock signal of the first arithmetic processing unit, the second arithmetic processing unit, and the combined output unit are also independent, and the input / output interfaces of the signals are isolated from each other. . For this reason, the operation independence of the first arithmetic processing unit, the second arithmetic processing unit, and the combined output unit is increased, and quantitative evaluation of the reliability of the entire apparatus is further facilitated.

In addition, the third invention,
The first storage unit has the same data format as the data format of the adaptive data carried by the adaptive data signal, and stores the first partial adaptive data with the missing data as predetermined data;
The second storage unit has the same data format as the data format of the adaptive data carried by the adaptive data signal, and stores the second partial adaptive data with the missing portion data as predetermined data,
The combined output unit generates the adaptive data signal by sequentially combining the first partial adaptive data signal and the second partial adaptive data signal;
It is an adaptive data output device of the 1st or 2nd invention.

  According to the third aspect of the invention, the first partial adaptive data and the second partial adaptive data have the same data format as the adaptive data, and the missing portion is data in which predetermined data is stored. Can be simplified. Therefore, reliability can be improved.

In addition, the fourth invention is
The first calculation processing unit acquires the combination of the status signals input by the second calculation processing unit from the second calculation processing unit, and the acquired combination and the status input to the first calculation processing unit. The combination of the signals is compared. If they are different, the combination of the input status signals is unconfirmed. Reading first partial adaptation data and outputting the first partial adaptation data signal;
The second calculation processing unit acquires the combination of the status signals input by the first calculation processing unit from the first calculation processing unit, and the acquired combination and the status input to the second calculation processing unit. The combination of the signals is compared. If they are different, the combination of the input status signals is unconfirmed. Reading second partial adaptation data and outputting the first partial adaptation data signal;
An adaptive data output apparatus according to any one of the first to third aspects of the invention.

  According to the fourth aspect of the invention, the first arithmetic processing unit and the second arithmetic processing unit exchange the combination of the status signals input to each other, and confirm the coincidence with the combination of the status signals input to itself. be able to. Therefore, it is possible to prevent the difference in acquisition of the status signal due to the shift in the capture timing of the first arithmetic processing unit and the second arithmetic processing unit when the input status signal changes, and to improve the reliability.

In addition, the fifth invention,
The adaptive data includes a data body and an error detection code (see, for example, FIG. 4),
The first partial adaptation data and the second partial adaptation data include the complete error detection code, and are configured by partially missing the data body so that the missing portions are different from each other (for example, (See Fig. 4)
An adaptive data output apparatus according to any one of the first to fourth inventions.

  According to the fifth aspect of the present invention, the first partial adaptive data and the second partial adaptive data are partially missing the data body of the adaptive data, but the error detection code has complete data. included.

In addition, the sixth invention,
The first arithmetic processing unit inputs a feedback signal of the adaptive data signal, and the adaptive data carried by the adaptive data signal is included in the first partial adaptive data stored in the first storage unit. Execute processing to check with error detection code,
The second arithmetic processing unit inputs a feedback signal of the adaptive data signal, and the adaptive data carried by the adaptive data signal is included in the second partial adaptive data stored in the second storage unit. Execute processing to check with error detection code,
It is an adaptive data output device of the 5th invention.

  According to the sixth aspect, each of the first arithmetic processing unit and the second arithmetic processing unit can check the correctness of the adaptive data transmitted and output including the processing results of the two systems. Therefore, it is possible to improve the failure detection capability and improve the reliability.

In addition, the seventh invention,
The combined output unit has a switch circuit (for example, the operation contacts HR1 and HR2 in FIG. 1) as to whether or not to interrupt the transmission output
The first arithmetic processing unit shuts off the switch circuit when the result of the inspection is defective;
The second arithmetic processing unit shuts off the switch circuit when the result of the inspection is defective;
It is an adaptive data output device of the 6th invention.

  According to the seventh aspect, each of the first arithmetic processing unit and the second arithmetic processing unit inspects whether the adaptive data signal is correct, and if any of the inspection results is defective, the adaptive data signal Transmission output is stopped.

Further, the eighth invention is
The status signal is any one of the indication of the traffic signal inward from the predetermined position, the route selected by the branching device inward from the predetermined position, and the position of the train located inward from the predetermined position. Is a signal indicating
The adaptive data is data for driving support or travel control for a train located at the predetermined position or outside the predetermined position,
The combined output unit transmits and outputs the adaptive data signal to a ground transmitter that transmits the adaptive data toward a train located outside the predetermined position.
An adaptive data output apparatus according to any one of the first to seventh inventions.

  According to the eighth aspect of the present invention, among the indication of the traffic signal inward from the predetermined position, the route selected by the branching unit inward from the predetermined position, and the position of the train located inward from the predetermined position A signal indicating any one of the above is input as a status signal, and an adaptive data signal is transmitted using data for driving support or traveling control for a train located at a predetermined position or outside a predetermined position as adaptive data Can be output.

The block diagram of an adaptive data output device. The figure which shows the structural example of the 1st partial adaptation data which a 1st memory | storage part memorize | stores. The figure which shows the structural example of the 2nd partial adaptation data which a 2nd memory | storage part memorize | stores. The figure which shows the relationship between adaptation data, 1st partial adaptation data, and 2nd partial adaptation data. The flowchart which shows the flow of the process which a 1st arithmetic processing part and a 2nd arithmetic processing part perform.

Hereinafter, an example of an embodiment to which the present invention is applied will be described.
The adaptive data output device 1 of the present embodiment is a ground device that transmits and outputs a signal carrying data for driving support or travel control to a ground transmitter for a train traveling on a track. Data for driving support or driving control is adaptive data, and a signal transmitted and output to the ground transmitter is an adaptive data signal AS. The ground transmitter transmits the adaptive data carried by the received adaptive data signal AS toward the train.

  Moreover, the adaptive data output device 1 of the present embodiment inputs a signal indicating the operation status or detection status of each of a plurality of devices in the railway driving security system in parallel as the status signal CS. Specifically, the traffic signal inward from the predetermined position on the track, the route selected by the branching device inward from the predetermined position (also referred to as the opening direction), and the train located inward from the predetermined position A signal indicating one of the positions is input as the status signal CS. The status signal CS is a bundle of a plurality of signals input in parallel. Each signal is a signal indicating the current indication of each traffic light, the opening direction of each branching device (selected route), and the position of each train.

  The status indicated by the status signal CS is a signal indicating the operation status or detection status of each of a plurality of devices in the railway operation and security system. Therefore, the changing time interval depends on the time interval of the train, and is a few seconds to several tens of times. Seconds, in some cases minutes to tens of minutes. Therefore, it can be said that the signal changes at an extremely long time interval compared to the internal operation cycle of the adaptive data output device 1 that operates by electronic control.

FIG. 1 is a diagram schematically showing a circuit configuration of the adaptive data output apparatus 1.
The adaptive data output device 1 includes roughly three circuit blocks. The first arithmetic processing unit 10, the second arithmetic processing unit 20, and the composite output unit 30. The first arithmetic processing unit 10 and the second arithmetic processing unit 20 are circuit blocks for realizing two systems of arithmetic processing, and the combined output unit 30 includes the first arithmetic processing unit 10 and the second arithmetic processing unit 20. This is a circuit block that generates an adaptive data signal AS by synthesizing output signals from each of them, and transmits and outputs the data to the outside (in this embodiment, a terrestrial transmitter).

  The first arithmetic processing unit 10, the second arithmetic processing unit 20, and the combined output unit 30 operate using separate power supplies and clock signals that are independent of each other. That is, the first arithmetic processing unit 10 operates based on the first clock generated by the first clock generation unit 61 with the power source power supplied from the first power source unit 51. The second arithmetic processing unit 20 operates based on the second clock generated by the second clock generation unit 62 with the power supplied from the second power supply unit 52. The combined output unit 30 operates based on the third clock generated by the third clock generation unit 63 with the power supplied from the third power supply unit 53.

  The first arithmetic processing unit 10, the second arithmetic processing unit 20, and the combined output unit 30 are insulated from each other in input / output interfaces of signals. In this embodiment, a photocoupler is used as an insulating circuit. However, a circuit other than a photocoupler, such as a pulse transformer, may be used to insulate the input / output of signals from each other.

  For this reason, since the operation independence of the first arithmetic processing unit 10, the second arithmetic processing unit 20, and the combined output unit 30 is increased, quantitative evaluation of the reliability of the entire adaptive data output device 1 is facilitated. That is, in calculating the failure rate, the possible failure range can be considered separately for each of the first arithmetic processing unit 10, the second arithmetic processing unit 20, and the combined output unit 30, so that the failure rate of the entire adaptive data output device 1 can be considered. It becomes easy to calculate.

The first arithmetic processing unit 10 includes a first arithmetic circuit unit 12, a transmission output cutoff driver 16, and a relay QR1.
The first arithmetic circuit unit 12 includes an arithmetic device such as a CPU (Central Processing Unit), an integrated circuit such as an ASIC (Application Specific Integrated Circuit) and an FPGA (Field Programmable Gate Array), a memory serving as the first storage unit 14, and the like. Configured. The first arithmetic circuit unit 12 reads the first partial adaptive data corresponding to the combination of the input status signals CS from the first storage unit 14 based on the program, data, etc. stored in the first storage unit 14. And output to the combined output unit 30 as the first partial adaptive data signal PS1.

  In addition to the program executed by the first arithmetic circuit unit 12, the first storage unit 14 stores first partial adaptation data corresponding to each possible combination as the status signal CS as shown in FIG. The first partial adaptation data is data obtained by partially missing the adaptation data.

  FIG. 4 is a diagram illustrating the relationship between the adaptive data, the first partial adaptive data, and the second partial adaptive data stored in the second storage unit 24 of the second arithmetic processing unit 20. Shown schematically. The adaptation data is data that is adapted to the input situation signal CS, and is data that should be transmitted to the train through the ground communication device for driving support or traveling control corresponding to the situation indicated by the situation signal CS. is there. The adaptive data is roughly divided into a data body and an error detection code. The error detection code is data for inspecting the content (bit value) of the transmitted data body. Of course, it may be data for inspecting the entire adaptive data including the data body and the error detection code.

  The first partial adaptation data and the second partial adaptation data are data in which the adaptation data is partially missing, and the missing portions are different from each other. For this reason, perfect adaptive data can be created by combining and combining the first partial adaptive data and the second partial adaptive data. More specifically, the first partial adaptive data and the second partial adaptive data are data in which the data body of the adaptive data is alternately deleted by predetermined bits. Contains complete data. The unit of the predetermined bits to be deleted may be one bit or several bits. In the missing part, data indicating that it is missing (for example, a Low bit value or a NULL value) is stored. In the example of FIGS. 2 and 3, the number of bits to be alternately deleted is 4 bits, and the low bit value (= “0”) is stored in the missing part.

  Therefore, the first partial adaptive data and the second partial adaptive data have the same data format as the adaptive data, and the error detection code includes complete data.

  The first arithmetic circuit unit 12 reads out the first partial adaptive data corresponding to the combination of the input status signals CS from the first storage unit 14 and outputs it as the first partial adaptive data signal PS1. The output first partial adaptive data has the same data format as the adaptive data carried by the adaptive data signal AS transmitted and output by the combined output unit 30.

  Further, the first arithmetic circuit unit 12 receives the feedback signal FS of the adaptive data signal AS from the combined output unit 30. Adaptive data is carried in the feedback signal FS. The first arithmetic circuit unit 12 checks the adaptive data with the complete error detection code of the first partial adaptive data. As a result of the inspection, if it is determined that there is an error in the adaptive data, the adaptive data output device 1 may be out of order, so the first arithmetic circuit unit 12 blocks the transmission output of the adaptive data signal AS.

  Specifically, a cutoff instruction signal (Low signal) is output to the transmission output cutoff driver 16. The transmission output cutoff driver 16 is configured by a charge pump circuit, and is a circuit that controls the operation (upward) / falling of the relay QR1 that controls switching of the configuration / opening of the operation contact HR1 that is a switch circuit. When normal, the first arithmetic circuit unit 12 outputs an alternating signal that repeats Low / High at a constant cycle to the transmission output cutoff driver 16. In the transmission output cut-off driver 16, the charge pump circuit operates in response to an alternating signal that repeats Low / High at a constant cycle, and applies a predetermined voltage to the relay QR1. As a result, the relay QR1 is in an activated state (upward), and a state is formed between both ends of the operating contact HR1.

  On the other hand, when it is determined that there is an error in the adaptive data, the first arithmetic circuit unit 12 outputs a cutoff instruction signal (Low signal) to the transmission cutoff driver 16. In this case, the transmission output cutoff driver 16 stops the voltage application to the relay QR1 when the charge pump circuit stops. As a result, the relay QR1 is dropped, and the operation contact HR1 is opened at both ends.

  That is, the transmission output cut-off driver 16 continues to apply a predetermined voltage to the relay QR1 when an alternating signal that repeats Low / High at a constant cycle is input, the input of the alternating signal stops, and a cut-off instruction signal (Low signal) is generated. When it is input, the voltage application is immediately stopped and the relay QR1 is dropped. As a result, the operating contact HR1 is opened. Since the operating contact HR1 is inserted in the signal line for outputting the adaptive data signal AS, the output of the adaptive data signal AS is immediately cut off when the operating contact HR1 is opened.

Although the 1st arithmetic processing part 10 was demonstrated, the 2nd arithmetic processing part 20 which is the other process part of two systems is also provided with the same structure.
That is, the second arithmetic processing unit 20 includes a second arithmetic circuit unit 22, a transmission output cutoff driver 26, and a relay QR2.

  The second arithmetic circuit unit 22 includes an arithmetic device such as a CPU, an integrated circuit such as an ASIC or FPGA, a memory serving as the second storage unit 24, and the like. The second arithmetic circuit unit 22 reads out the second partial adaptation data corresponding to the combination of the input status signals CS from the second storage unit 24 based on the program, data, etc. stored in the second storage unit 24. And output to the combined output unit 30 as the second partial adaptive data signal PS2.

  In addition to the program executed by the second arithmetic circuit unit 22, the second storage unit 24 stores second partial adaptation data corresponding to each possible combination as the status signal CS as shown in FIG. The second partial adaptation data has a configuration as described above with reference to FIG. Further, the second partial adaptive data carried by the second partial adaptive data signal PS2 output by the second arithmetic circuit unit 22 is also the adaptive data carried by the adaptive data signal AS transmitted and output by the combined output unit 30. The same data format is used.

  The second arithmetic circuit unit 22 receives the feedback signal FS of the adaptive data signal AS from the combined output unit 30. Adaptive data is carried in the feedback signal FS. The second arithmetic circuit unit 22 checks the adaptive data with the complete error detection code of the second partial adaptive data. As a result of the inspection, if it is determined that there is an error in the adaptive data, the adaptive data output device 1 may be out of order, so the second arithmetic circuit unit 22 cuts off the transmission output of the adaptive data signal AS. Specifically, a cutoff instruction signal (Low signal) is output to the transmission output cutoff driver 26. The transmission output cut-off driver 26 is a circuit that controls the operation (upward) / falling of the relay QR2 that controls switching of the configuration / opening of the operation contact HR2 that is a switch circuit. The transmission output cutoff driver 26, the relay QR2, and the operating contact HR2 have the same configuration as the transmission output cutoff driver 16, the relay QR1, and the operating contact HR1, respectively. The operating contact HR2 is inserted in series with a signal line for outputting the adaptive data signal AS together with the operating contact HR1. For this reason, even if the operation contact HR1 is not in the open state, the output of the adaptive data signal AS is immediately cut off by the operation contact HR2 being in the open state.

  As described above, the first arithmetic processing unit 10, the second arithmetic processing unit 20, and the composite output unit 30 operate based on independent clock signals. For this reason, there is a possibility that a deviation occurs between the operations. As a countermeasure for this, the adaptive data output device 1 has various configurations.

  First, the first arithmetic circuit unit 12 and the second arithmetic circuit unit 22 input and output data indicating a combination of the captured status signals CS. The first arithmetic circuit unit 12 and the second arithmetic circuit determine whether the combination of the status signal CS captured by the first arithmetic circuit unit 12 and the combination of the status signal CS captured by the second arithmetic circuit unit 22 match. Units 22 collate with each other. Since the operation clock signals of the first arithmetic circuit unit 12 and the second arithmetic circuit unit 22 are different, the first arithmetic circuit unit 12 and the second arithmetic circuit unit 22 collate because there is a deviation in the timing of capturing the status signal CS. If the collation results do not match, the first arithmetic circuit unit 12 and the second arithmetic circuit unit 22 ignore the status signal CS captured this time, and the first part corresponding to the status signal CS previously captured The adaptive data signal PS1 and the second partial adaptive data signal PS2 are output. Further, when the mismatch of the collation results continues for a predetermined number of times, a cutoff instruction signal (Low signal) is output to the transmission output cutoff drivers 16 and 26 as a failure.

  One of the first arithmetic circuit unit 12 and the second arithmetic circuit unit 22 takes in at the timing immediately before the situation signal CS changes, and the other takes in the timing immediately after the situation signal CS changes. A mismatch occurs in the status signal CS. However, at the next capture timing, the possibility of capturing the same status signal CS is very high. This is because the time interval at which the status signal CS changes is extremely longer than the period of the operation clock signal.

  With this configuration, the situation signal CS referred to by the first arithmetic processing unit 10 and the situation signal CS referred to by the second arithmetic processing unit 20 are different depending on the shift in the capture timing, and the first partial adaptive data signal PS1 and the second The partial adaptive data signal PS2 is prevented from becoming incompatible signals.

  Further, the timing at which the first partial adaptive data signal PS1 is output from the first arithmetic circuit unit 12 and the timing at which the second partial adaptive data signal PS2 is output from the second arithmetic circuit unit 22 are prevented. Therefore, the first arithmetic circuit unit 12 and the second arithmetic circuit unit 22 commonly use the clock signal CC generated by the synthesis clock generation unit 38 included in the synthesis output unit 30. That is, the first arithmetic circuit unit 12 and the second arithmetic circuit unit 22 output the first partial adaptive data signal PS1 and the second partial adaptive data signal PS2 based on the common clock signal CC. More specifically, the first partial adaptive data signal PS1 and the second partial adaptive data signal PS2 are output bit by bit based on the rising or falling edge of the clock signal CC. As a result, for the combined output unit 30, the first partial adaptive data signal PS1 and the second partial adaptive data signal PS2 are input at the same timing in the same bit order.

  Next, the synthesis output unit 30 that is another circuit block will be described. The synthesis output unit 30 includes a synthesis unit 32, a modulation circuit 34, a demodulation circuit 36, a synthesis clock generation unit 38, a contact HR1 and a contact HR2, and is output from the first arithmetic processing unit 10. The first partial adaptive data signal PS1 and the second partial adaptive data signal PS2 output from the second arithmetic processing unit 20 are combined to generate an adaptive data signal AS carrying complete adaptive data, and transmit it. It is a circuit block.

  The synthesizing unit 32 synthesizes the first partial adaptive data signal PS1 and the second partial adaptive data signal PS2 based on the clock signal CC generated by the synthesizing clock generator 38 to generate complete adaptive data. Circuit section for output. As described above, the first partial adaptive data and the second partial adaptive data have the same data format as the adaptive data (see FIG. 4), and the first partial adaptive data signal PS1 and the second partial adaptive data signal PS2 is input to the combining unit 32 at the same timing in the same bit order. Therefore, based on the clock signal CC, the synthesizer 32 synthesizes the bit value indicated by the first partial adaptive data signal PS1 and the bit value indicated by the second partial adaptive data signal PS2 by a logical operation by a logic circuit. can do. For example, if the bit value indicating the missing portion of data is set to Low, the logic circuit can be configured using an OR circuit.

  The signal (adaptive data) synthesized by the synthesis unit 32 is output to the modulation circuit 34 via the contact HR1 and the contact HR2 connected in series. The modulation circuit 34 generates an adaptive data signal AS that carries the signal (adaptive data) synthesized by the synthesis unit 32 by performing modulation in accordance with a communication protocol related to transmission to the terrestrial transmitter, and transmits the adaptive data signal AS. Circuit.

  The transmitted adaptive data signal AS is fed back to the first arithmetic processing unit 10 and the second arithmetic processing unit 20 as a feedback signal FS. However, since the adaptive data signal AS is modulated, it is fed back to the first arithmetic processing unit 10 and the second arithmetic processing unit 20 as the feedback signal FS through the demodulation circuit 36 for removing the adaptive data signal AS.

  Next, with reference to FIG. 5, the flow of processing executed by the first arithmetic processing unit 10 and the second arithmetic processing unit 20 will be described. FIG. 5 is a flowchart showing a flow of processing executed by the first arithmetic processing unit 10 and the second arithmetic processing unit 20.

  First, the first arithmetic processing unit 10 and the second arithmetic processing unit 20 take in the status signal CS (step A2), and output the combination data of the fetched status signal CS to the counterpart system (step A4). The combination data of the status signal CS taken in by the partner system is input (step A6). Then, it is verified whether or not the status signals CS taken in each other match (step A8). If they match (step A10: YES), the counter value is reset (step A11), and if it is the first arithmetic processing unit 10, the first partial adaptive data corresponding to the combination of the captured status signals CS is the first If the second arithmetic processing unit 20 reads from the first storage unit 14, the second partial adaptive data corresponding to the acquired combination of the status signals CS is read from the second storage unit 24 and selected as the latest partial adaptive data Update (step A12).

  If the result of collation does not match (step A10: NO), the counter value is incremented by “1” (step A13), and the counter value is preferably a predetermined value (for example, “2” or more). If “1” is acceptable) (step A14: YES), the transmission output of the adaptive data signal AS is cut off (step A22), and the process is terminated. If the counter value is not equal to or greater than the predetermined value (step A14: NO), step A12 is skipped, and the processes after step A15 are advanced without updating the partial adaptive data.

  In step A15, the latest partial adaptive data is output to the synthesis output unit 30 as a partial adaptive data signal (step A15). If it is the first arithmetic processing unit 10, the first partial adaptive data signal PS1 is output, and if it is the second arithmetic processing unit 20, the second partial adaptive data signal PS2 is output.

  Next, the first arithmetic processing unit 10 and the second arithmetic processing unit 20 receive the feedback signal FS of the adaptive data signal AS (step A16). Then, the adaptive data carried by the adaptive data signal AS is checked with a complete error detection code in the partial adaptive data (step A18). In the case of the first arithmetic processing unit 10, the error detection code of the first partial adaptive data is inspected, and in the case of the second arithmetic processing unit 20, the error detection code of the second partial adaptive data is inspected.

  As a result of the inspection, if there is no error in the adaptive data and the data is appropriate (step A20: YES), the process returns to step A2, and the processes in steps A2 to A20 are repeated. If there is an error in the adaptive data and it is determined that it is defective (step A20: NO), the transmission output of the adaptive data signal AS is cut off (step A22). If it is the first arithmetic processing unit 10, a cutoff instruction signal (Low signal) is output to the transmission output cutoff driver 16, and if it is the second arithmetic processing unit 20, a cutoff instruction signal (Low signal) to the transmission output cutoff driver 26. Is output.

[Function and effect]
According to the present embodiment described above, the first arithmetic processing unit 10 stores the first partial adaptive data 14 in which the adaptive data corresponding to combinations that can be taken as the situation signal CS are partially lost. The first partial adaptive data corresponding to the combination of the actually input status signals CS is read and output as the first partial adaptive data signal PS1. On the other hand, the second arithmetic processing unit 20 stores the second partial adaptive data that is different from the first partial adaptive data and can be made into complete adaptive data by being combined with the first partial adaptive data. A second storage unit 24 that reads out the second partial adaptive data corresponding to the combination of the actually input status signals and outputs it as a second partial adaptive data signal PS2. For this reason, since the 1st arithmetic processing part and the 2nd arithmetic processing part do not have the data of an other party mutually, the independence between systems can be raised. Then, the synthesis output unit 30 synthesizes the first partial adaptive data signal and the second partial adaptive data signal, generates an adaptive data signal AS carrying complete adaptive data, and transmits it.

  Both the first partial adaptive data signal PS1 output from the first arithmetic processing unit 10 and the second partial adaptive data signal PS2 output from the second arithmetic processing unit 20 carry complete adaptive data. In addition, the contents of the data being conveyed are different. Therefore, when the reliability of the entire apparatus is quantitatively evaluated, the failure rate is calculated independently by separating each of the first calculation processing unit 10, the second calculation processing unit 20, and the combined output unit 30. The failure rate of the entire device can be calculated relatively easily. That is, quantitative evaluation of reliability can be facilitated. Further, in calculating the failure rate, it is possible to easily narrow down the assumed failure occurrence location to any one of the first arithmetic processing unit 10, the second arithmetic processing unit 20, and the combined output unit 30, so that the failure rate of the entire apparatus Can be easily calculated.

  Further, the power supply and the clock signal of the first arithmetic processing unit 10, the second arithmetic processing unit 20, and the combined output unit 30 are independent and independent, and the input / output interface of each signal is insulated by, for example, a photocoupler. For this reason, the operation independence of the first arithmetic processing unit 10, the second arithmetic processing unit 20, and the combined output unit 30 is increased, and quantitative evaluation of the reliability of the entire apparatus is further facilitated.

[Modification]
Although an example of the embodiment to which the present invention is applied has been described, the form to which the present invention can be applied is not limited to the above-described embodiment.
For example, a device that outputs a signal for controlling the signal display of a traffic light installed at a predetermined position as an adaptive data signal AS, a device that outputs an operation instruction signal to a certain level crossing breaker as an adaptive data signal AS, The adaptive data output device of the present invention can also be applied to a device that outputs a conversion instruction signal to a certain switch as the adaptive data signal AS. Further, the adaptive data output device of the present invention can be used as an interlocking device in a small travel section.
Further, it can be used not only as a ground device but also as an on-vehicle device.

DESCRIPTION OF SYMBOLS 1 Adaptive data output device 10 1st arithmetic processing part 12 1st arithmetic circuit part 14 1st memory | storage part 20 2nd arithmetic processing part 22 2nd arithmetic circuit part 24 2nd memory | storage part 30 Synthesis | combination output part 32 Synthesis | combination part 34 Modulation circuit 36 Demodulator 38 Synthesizing clock generator CS Status signal AS Adaptive data signal

Claims (8)

In a railway operation security system, an adaptive data output device that inputs status signals indicating the operating status or detection status of a plurality of devices in parallel and transmits and outputs adaptive data signals adapted to the status signal combinations of the devices. There,
A first storage unit that stores first partial adaptation data in which adaptation data corresponding to combinations that can be taken as the situation signals are partially lost, and that corresponds to a combination of the actually inputted situation signals; A first arithmetic processing unit that reads first partial adaptive data from the first storage unit and outputs the first partial adaptive data as a first partial adaptive data signal;
A second storage unit that stores second partial adaptation data that is different from the first partial adaptation data and that can be made into complete adaptation data when combined with the first partial adaptation data. A second arithmetic processing unit that reads out the second partial adaptive data corresponding to the actually inputted combination of the situation signals from the second storage unit and outputs the second partial adaptive data signal as a second partial adaptive data signal;
The first partial adaptive data signal output from the first arithmetic processing unit and the second partial adaptive data signal output from the second arithmetic processing unit are combined to carry complete adaptive data. A combined output unit for generating and transmitting the adaptive data signal; and
An adaptive data output device. The first arithmetic processing unit, the second arithmetic processing unit, and the combined output unit operate using different power sources and clock signals, and input / output interfaces of the signals are isolated from each other.
The adaptive data output device according to claim 1. The first storage unit has the same data format as the data format of the adaptive data carried by the adaptive data signal, and stores the first partial adaptive data with the missing portion data as predetermined data,
The second storage unit has the same data format as the data format of the adaptive data carried by the adaptive data signal, stores the second partial adaptive data with the missing portion data as predetermined data,
The combined output unit generates the adaptive data signal by sequentially combining the first partial adaptive data signal and the second partial adaptive data signal;
The adaptive data output device according to claim 1 or 2. The first calculation processing unit acquires the combination of the status signals input by the second calculation processing unit from the second calculation processing unit, and the acquired combination and the status input to the first calculation processing unit. The combination of the signals is compared. If they are different, the combination of the input status signals is unconfirmed. Reading first partial adaptation data and outputting the first partial adaptation data signal;
The second calculation processing unit acquires the combination of the status signals input by the first calculation processing unit from the first calculation processing unit, and the acquired combination and the status input to the second calculation processing unit. The combination of the signals is compared. If they are different, the combination of the input status signals is unconfirmed. Reading second partial adaptation data and outputting the first partial adaptation data signal;
The adaptive data output apparatus as described in any one of Claims 1-3. The adaptation data includes a data body and an error detection code,
The first partial adaptation data and the second partial adaptation data include the complete error detection code, and are configured by partially missing the data body so that the missing portions are different from each other.
The adaptive data output apparatus as described in any one of Claims 1-4. The first arithmetic processing unit receives a feedback signal of the adaptive data signal, and the adaptive data carried by the adaptive data signal is included in the first partial adaptive data stored in the first storage unit. Execute processing to check with error detection code,
The second arithmetic processing unit receives a feedback signal of the adaptive data signal, and the adaptive data carried by the adaptive data signal is included in the second partial adaptive data stored in the second storage unit. Execute processing to check with error detection code,
The adaptive data output device according to claim 5. The combined output unit includes a switch circuit for determining whether to interrupt the transmission output,
The first arithmetic processing unit shuts off the switch circuit when a result of the inspection is defective,
The second arithmetic processing unit shuts off the switch circuit when the result of the inspection is defective.
The adaptive data output device according to claim 6. The status signal may be any one of an indication of a traffic signal inward from a predetermined position, a route selected by a branching device inward from the predetermined position, and a train position positioned inward from the predetermined position. Is a signal indicating
The adaptive data is data for driving support or traveling control for a train located at the predetermined position or outside the predetermined position,
The combined output unit transmits and outputs the adaptive data signal to a ground transmitter that transmits the adaptive data toward a train located outside the predetermined position.
The adaptive data output apparatus as described in any one of Claims 1-7.

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