TWI704491B - Semiconductor devices - Google Patents

Abstract

A semiconductor device may include a data output circuit and a control signal output circuit. The data output circuit may compare a first input signal or a second input signal with a storage datum to generate a first comparison selection signal and may compare the first input signal with the second input signal to generate a second comparison selection signal. The control signal output circuit may detect logic levels of bits included in the first and second comparison selection signals to generate first and second detection signals, generate first and second flag signals from the first and second detection signals in response to a storage flag signal, and sequentially output the first and second flag signals as transmission control signals.

Description

Semiconductor device

This application claims the priority of the Korean application with the application number 10-2015-0045750 filed with the Korean Intellectual Property Office on March 31, 2015, the entire contents of which are incorporated herein by reference, as described in full.

The general system of the various embodiments relates to a semiconductor device, and more specifically, to a semiconductor device adopting a data inversion strategy.

Recently, a multi-bit prefetch strategy has been widely used in semiconductor devices. A semiconductor device using a multi-bit prefetch strategy can respond to a single command to generate multi-bit data from the memory cell in parallel, and can use a single data input/output (I/O, input/output) pin or multiple I/Os Pin to output multi-bit data synchronously with the clock signal. If a multi-bit prefetch strategy is used in the semiconductor device, the row path of the internal core of the semiconductor device can be driven at a low frequency. The low frequency is equal to or less than half of the frequency of the external clock signal. Therefore, if the semiconductor device adopts a multi-bit prefetch strategy, the internal core and row path of the semiconductor device can be easily designed.

At the same time, as the frequency of the external clock signal increases and the number of data pads through which data is output increases, the semiconductor device can be designed to have 32 or more data pads through which the data is simultaneously output Wide I/O structure. If 32 or more assets of semiconductor devices If the material is used to output data at the same time, a large amount of noise called "simultaneous switching noise (SSN)" can be generated in the output data, and the semiconductor device will suffer from SSN. SSN can distort the waveform of the output data and reduce the signal integrity of the semiconductor device. In this case, it may be difficult to obtain a high-performance semiconductor device with excellent I/O characteristics required for a high-frequency system.

According to an embodiment, a semiconductor device may include a data output circuit and a control signal output circuit. In the first burst sequence in which the first input signal and the second input signal are sequentially output as output data, the data output circuit can compare the first input signal with the stored data to generate a first comparison selection signal, and can The second input signal is compared with the first input signal to generate a second comparison selection signal. In the second burst sequence in which the second input signal and the first input signal are sequentially output as output data, the data output circuit can compare the second input signal with the stored data to generate the first comparison selection signal, and can The second input signal is compared with the first input signal to generate a second comparison selection signal. The control signal output circuit can detect the logic levels of the bits included in the first comparison selection signal and the second comparison selection signal to generate the first detection signal and the second detection signal, and can respond to the storage flag signal to detect the first The signal and the second detection signal generate a first flag signal and a second flag signal, and the first flag signal and the second flag signal can be sequentially output as the transmission control signal.

According to an embodiment, a semiconductor device may include a first pipe latch unit adapted to sequentially latch a first input signal and a second input signal in response to an input control signal, and adapted to respond to an output control signal To output the first input signal of the latch and the second input signal of the latch as the pipe latch data. Semiconductor devices can include data storage units, data storage The unit is suitable for storing the second input signal as storage data in the first burst sequence, and is suitable for storing the first input signal as storage data in the second burst sequence. The semiconductor device may include a data comparator, which is adapted to compare the first input signal with stored data to generate a first comparison signal, and is adapted to compare the second input signal with the first input signal to generate a second comparison signal And is suitable for comparing the second input signal with the stored data to generate a third comparison signal. The semiconductor device may include a comparison signal selector, which is suitable for outputting the first comparison signal as the first comparison selection signal and the second comparison signal as the second comparison selection signal in the first burst sequence, and is suitable for In the second burst sequence, the third comparison signal is output as the first comparison selection signal and the second comparison signal is output as the second comparison selection signal. The semiconductor device may include a control signal output circuit, and the control signal output circuit is adapted to detect the logic levels of the bits included in the first comparison selection signal and the second comparison selection signal to generate the first detection signal and the second detection signal. In response to storing the flag signal to generate the first flag signal and the second flag signal from the first detection signal and the second detection signal, and is suitable for sequentially outputting the first flag signal and the second flag signal as the transmission control signal .

According to an embodiment, a semiconductor device may include a data output circuit, a bit detector, a flag generator, a flag storage unit, a selection flag generator, a first pipe latch unit, and a control signal output unit. In the first burst sequence in which the first input signal and the second input signal are sequentially output as output data, the data output circuit can compare the first input signal with the stored data to generate a first comparison selection signal, and can The second input signal is compared with the first input signal to generate a second comparison selection signal. In the second burst sequence in which the second input signal and the first input signal are sequentially output as output data, the data output circuit can compare the second input signal with the stored data to generate the first comparison selection signal, and can The second input signal is compared with the first input signal to generate a second comparison selection signal. The bit detector can detect packets in the first comparison selection signal The logic level of the enclosed bit is used to generate a first detection signal, and the logic level of the bit included in the second comparison selection signal is detected to generate a second detection signal. The flag generator can compare the first detection signal with the stored flag signal to generate the first flag signal, and compare the first flag signal with the second detection signal to generate the second flag signal. The flag storage unit can respond to the delayed storage control signal to store the second flag signal as the storage flag signal. In the first burst sequence, the selection flag generator can output the first flag signal as the first selection flag signal and can output the second flag signal as the second selection flag signal. In the second burst sequence, the selection flag generator can output the second flag signal as the first selection flag signal and can output the first flag signal as the second selection flag signal. The first pipe latch unit can respond to the delayed input control signal to sequentially latch the first selection flag signal and the second selection flag signal, and can respond to the delayed output control signal to output the latched first selection flag signal and The second selection flag signal of the latch is used as an inverted control signal. The control signal output unit can be synchronized with the internal clock signal to generate the transmission control signal from the inverted control signal. The transmission control signal can be output via the control pad.

11: Data output circuit group

11_1~11_8: the first to eighth data output circuit

111: data selector

112: data storage unit

113: data comparator

114: Comparison signal selector

115: The first pipe latch unit

116: Phase Controller

117: data output unit

118: Data Pad

12: Control signal output circuit

121: bit detector

122: Flag Generator

123: Flag storage unit

124: Select Flag Generator

125: The second pipe latch unit

126: Control signal output unit

127: Control Pad

41~44: The first to the fourth selection/output unit

61~64: first to fourth detection signal generator

611~617: first to seventh level counter

81~84: first to fourth flag selector

1000: System

1100: processor

1150: Chipset

1200: Memory Controller

1250: input/output (I/O) bus

1300: Disk Drive Controller

1350: memory device

1410: Mouse

1420: Video display

1430: keyboard

1450: internal drive

COM<1>~COM<6>: the first to sixth comparison signals

C_SEL1<1: 8>: The first comparison selection signal

C_SEL2<1:8>: The second comparison selection signal

C_SEL3<1:8>: The third comparison selection signal

C_SEL4<1:8>: The fourth comparison selection signal

CNT1~CNT 22: the first to the twenty-second count signal

DIN1<1>~DIN4<1>: the first to fourth input signals

DIN1<2:8>~DIN4<2:8>: Input signal

DQ<1~8>: the first to eighth output data

DET1~DET4: the first to fourth detection signals

F_DT: Final data

FL_DT: Pipe latch data

FLAG_S: store flag signal

FLAG1~FLAG4: the first to fourth flag signals

ICLK: Internal clock signal

IV_CON: Inverting control signal

IV51~IV53: Inverter

nd51: node

PINSUM: Store control signal

PINSUMD: Delayed storage of control signals

POUT<1:4>: The first to fourth output control signals

POUTD<1:4>: The first to fourth delayed output control signals

PIN<1:4>: The first to fourth input control signals

PIND<1:4>: The first to fourth delayed input control signals

P_DT: Phase data

S_DT: save data

S_CON: select control signal

S_COND: Delay selection control signal

S_FLAG1~S_FLAG4: the first to fourth selection flag signals

T_CON: Transmission control signal

T51: Transmission gate

XOR31~XOR36: logic element

XOR71~XOR74: logic element

[FIG. 1] is a block diagram illustrating a representative example of the configuration of the semiconductor device according to the embodiment.

[FIG. 2] is a table illustrating examples of various combinations of the output sequence of data output through the data pad according to the burst sequence of the semiconductor device shown in FIG. 1.

[FIG. 3] is a logic circuit diagram illustrating an example of a data comparator included in the semiconductor device of FIG. 1.

[FIG. 4] is representative of an example of the comparison signal selector included in the semiconductor device of FIG. 1 Block diagram.

[FIG. 5] is a logic circuit diagram illustrating an example of a phase controller included in the semiconductor device of FIG. 1.

[FIG. 6] is a block diagram illustrating a representative example of a bit detector included in the semiconductor device of FIG. 1.

[FIG. 7] is a logic circuit diagram illustrating an example of a flag generator included in the semiconductor device of FIG. 1.

[FIG. 8] is a block diagram illustrating a representative example of the selection flag generator included in the semiconductor device of FIG. 1.

[FIG. 9, FIG. 10, and FIG. 11] are tables illustrating an example of the operation of the data inversion strategy adopted in the semiconductor device of FIG. 1.

[FIG. 12] is a block diagram illustrating a representative example of a system using a semiconductor device according to the various embodiments discussed above with respect to FIGS. 1 to 11.

Generally, a data inversion strategy can be used in semiconductor devices to improve the I/O characteristics of semiconductor devices used in high-frequency systems.

The data inversion strategy can be used to reduce the SSN of semiconductor devices. The semiconductor device using the data inversion strategy can compare the current output data (usually with 8 bits) with the previous output data to count the number of switching bits, and can actually output as-is based on the number of switching bits Current output data or output reverse data of current output data. If a data inversion strategy is used in a semiconductor device, the number of switching bits in the actual output data can always be smaller than the output data. Half of the number of all bits in the data. Therefore, the SSN can be reduced to improve the signal integrity of the semiconductor device. Therefore, the I/O characteristics of the semiconductor device can be enhanced to realize a high-performance semiconductor device.

Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. However, the embodiments described herein are for illustrative purposes only, and are not intended to limit the scope of the present invention. Various embodiments may be directed to semiconductor devices that adopt a data inversion strategy.

1, the semiconductor device according to the embodiment may include a data output circuit group 11 and a control signal output circuit 12. The data output circuit group 11 may include first to eighth data output circuits 11_1, 11_2,..., and 11_8. The first data output circuit 11_1 may include a data selector 111, a data storage unit 112, a data comparator 113, a comparison signal selector 114, a first pipe latch unit 115, a phase controller 116, a data output unit 117, and a data pad 118 . The control signal output circuit 12 may include a bit detector 121, a flag generator 122, a flag storage unit 123, a selection flag generator 124, a second pipe latch unit 125, a control signal output unit 126 and a control pad 127.

The data selector 111 can respond to the selection control signal S_CON to select any of the first input signal to the fourth input signal DIN1<1>, DIN2<1>, DIN3<1> and DIN4<1> sequentially input to it One is the final data F_DT. The selection control signal S_CON may have a logic level set according to a burst sequence, the burst sequence includes information about the first input signal to the fourth input signal DIN1<1>, DIN2<1>, DIN3<1> and DIN4<1> transmits the information of the sequence to the data pad 118 via the first pipe latch unit 115, the phase controller 116, and the data output unit 117.

The data storage unit 112 can respond to the storage control signal PINSUM to output the final data F_DT as the storage data S_DT. The storage control signal PINSUM can be set according to the first Input the control signal to the enabling state of the fourth input control signal PIN<1:4> to enable. For example, when the first input control signal to the fourth input control signal PIN<1:4> are all enabled, the storage control signal PINSUM can be used in the first input signal to the fourth input signal DIN1<1>, DIN2<1> , DIN3<1> and DIN4<1> are all input to the first pipe latch unit 115 and then enabled. The enabling logic level of the storage control signal PINSUM and the enabling logic level of the first input control signal to the fourth input control signal PIN<1:4> can be set to different according to various embodiments.

The data comparator 113 can select two signals from the storage data S_DT and the first input signal to the fourth input signal DIN1<1>, DIN2<1>, DIN3<1> and DIN4<1> according to the burst sequence The comparison is performed to generate the first comparison signal to the sixth comparison signal COM<1:6>. After that, the configuration and operation of the data comparator 113 will be more fully described with reference to FIGS. 2 and 3.

The comparison signal selector 114 can respond to the selection control signal S_CON to select some of the first comparison signal to the sixth comparison signal COM<1:6> to output the selected signal as the first comparison selection signal to the fourth comparison signal. Select the signals C_SEL1<1>, C_SEL2<1>, C_SEL3<1> and C_SEL4<1>. For example, the comparison signal selector 114 can select from the first comparison signal to the sixth comparison signal COM<1:6> and the first comparison selection signal to the fourth comparison selection signal C_SEL1<1>, C_SEL2<1 according to the burst sequence. >, C_SEL3<1> and C_SEL4<1> corresponding signals. After that, the configuration and operation of the comparison signal selector 114 will be described with reference to FIG. 4.

The first pipe latch unit 115 can respond to the first input control signal to the fourth input control signal PIN<1:4> and the first output control signal to the fourth output control signal POUT<1:4> to output the first input signal To the fourth input signal DIN1<1>, DIN2<1>, DIN3<1> and DIN4<1> as the pipe latch data FL_DT. If the first input control signal PIN<1> is enabled, the first pipe latch unit 115 can receive and latch the first input signal DIN1<1>. If the second input control signal When PIN<2> is enabled, the first pipe latch unit 115 can receive and latch the second input signal DIN2<1>. If the third input control signal PIN<3> is enabled, the first pipe latch unit 115 can receive and latch the third input signal DIN3<1>. If the fourth input control signal PIN<4> is enabled, the first pipe latch unit 115 can receive and latch the fourth input signal DIN4<1>. If the first output control signal POUT<1> is enabled, the first pipe latch unit 115 can output the latched first input signal DIN1<1> as the pipe latch data FL_DT. If the second output control signal POUT<2> is enabled, the first pipe latch unit 115 can output the latched second input signal DIN2<1> as the pipe latch data FL_DT. If the third output control signal POUT<3> is enabled, the first pipe latch unit 115 can output the latched third input signal DIN3<1> as the pipe latch data FL_DT. If the fourth output control signal POUT<4> is enabled, the first pipe latch unit 115 can output the latched fourth input signal DIN4<1> as the pipe latch data FL_DT. The enable logic level of the first input control signal to the fourth input control signal PIN<1:4> and the enable logic level of the first output control signal to the fourth output control signal POUT<1:4> can be It is set to be different according to various embodiments. The first pipe latch unit 115 can convert the first input signal to the fourth input signal DIN1<1>, DIN2<1>, DIN3<1>, and DIN4<1> inputted to it in parallel into serial output from it. Pipe latch data FL_DT. The sequence of the first input signal to the fourth input signal DIN1<1>, DIN2<1>, DIN3<1>, and DIN4<1> outputted as the pipe latch data FL_DT can be determined according to the burst sequence.

The phase controller 116 can respond to the inversion control signal IV_CON to determine the inversion of the pipe latch data FL_DT to generate the phase data P_DT. If the inverted control signal IV_CON is enabled, the phase controller 116 may invert the phase of the pipe latch data FL_DT to output the inverted signal of the pipe latch data FL_DT as the phase data P_DT. After that, the configuration and operation of the phase controller 116 will be described with reference to FIG. 5.

The data output unit 117 can synchronize the internal clock signal ICLK to output the phase data P_DT as the first output data DQ<1>. The first output data DQ<1> can be output from the semiconductor device through the data pad 118. The internal clock signal ICLK can be generated in the semiconductor device to output data. The internal clock signal ICLK can be generated from the external clock signal.

The second data output circuit to the eighth data output circuit 11_2,..., 11_8 can receive input signals DIN1<2:8>, DIN2<2:8>, DIN3<2:8> and DIN4<2:8>. Generate and output the first comparison selection signal to the fourth comparison selection signal C_SEL1<2:8>, C_SEL2<2:8>, C_SEL3<2:8> and C_SEL4<2:8> and the second output data to the eighth output Data DQ<2:8>. The configuration and operation of each of the second to eighth data output circuits 11_2,..., 11_8 may be substantially the same as the first data output circuit 11_1 described above. Therefore, detailed descriptions of the second to eighth data output circuits 11_2 to 11_8 will be omitted hereinafter to avoid repeated explanations.

The bit detector 121 can detect the logic level of the bit included in the first comparison selection signal C_SEL1<1:8> to generate the first detection signal DET1. For example, if the number of logic "high (also called'H')" levels among the logic levels of the bits included in the first comparison selection signal C_SEL1<1:8> is equal to or greater than 5, the bit The detector 121 can output the first detection signal DET1 that is enabled to have a logic “high” level. The bit detector 121 can detect the logic level of the bit included in the second comparison selection signal C_SEL2<1:8> to generate the second detection signal DET2. The bit detector 121 can detect the logic level of the bit included in the third comparison selection signal C_SEL3<1:8> to generate the third detection signal DET3. The bit detector 121 can detect the logic level of the bit included in the fourth comparison selection signal C_SEL4<1:8> to generate the fourth detection signal DET4. After that, the configuration and operation of the bit detector 121 will be described with reference to FIG. 6.

The flag generator 122 can compare the logic level of the first detection signal DET1 with the logic level of the stored flag signal FLAG_S to generate the first flag signal FLAG1. For example, if the logic level of the first detection signal DET1 is different from the logic level of the storage flag signal FLAG_S, the flag generator 122 may generate the first flag signal FLAG1 with a logic “high” level. If the logic level of the first detection signal DET1 is the same as the logic level of the storage flag signal FLAG_S, the flag generator 122 can generate the first flag signal FLAG1 with a logic “low” level. The flag generator 122 can compare the logic level of the second detection signal DET2 with the logic level of the first detection signal DET1 to generate the second flag signal FLAG2. The flag generator 122 can compare the logic level of the third detection signal DET3 with the logic level of the second detection signal DET2 to generate the third flag signal FLAG3. The flag generator 122 can compare the logic level of the fourth detection signal DET4 with the logic level of the third detection signal DET3 to generate the fourth flag signal FLAG4. After that, the configuration and operation of the flag generator 122 will be described with reference to FIG. 7.

The flag storage unit 123 can respond to the delayed storage control signal PINSUMD to store the fourth flag signal FLAG4 therein and can output the stored fourth flag signal FLAG4 as the storage flag signal FLAG_S. The delayed storage control signal PINSUMD can be generated by delaying the storage control signal PINSUM for a predetermined delay time. The predetermined delay time of the storage control signal PINSUM for generating the delayed storage control signal PINSUMD can be set as the operation of the data storage unit 112, the data comparator 113, the comparison signal selector 114, the bit detector 121, and the flag generator 122 Time period.

The selection flag generator 124 may respond to the delay selection control signal S_COND to output the first to fourth flag signals FLAG1, FLAG2, FLAG3, and FLAG4 sequentially input to it as the first selection flag signals to the fourth Select the flag signals S_FLAG1, S_FLAG2, S_FLAG3 and S_FLAG4. For example, the selection flag generator 124 may output each of the first flag signal to the fourth flag signal FLAG1, FLAG2, FLAG3, and FLAG4 as the first selection by delaying the burst sequence set by the selection control signal S_COND Any one of the flag signal to the fourth selection flag signal S_FLAG1, S_FLAG2, S_FLAG3, and S_FLAG4. The delayed selection control signal S_COND can be generated by delaying the selection control signal S_CON for a predetermined delay time. The predetermined delay time of the selection control signal S_CON for generating the delay selection control signal S_COND can be set to the data selector 111, the data storage unit 112, the data comparator 113, the comparison signal selector 114, the bit detector 121, and the flag The operating period of the generator 122. After that, the configuration and operation of the selection flag generator 124 will be described with reference to FIG. 8.

The second pipe latch unit 125 can respond to the first delayed input control signal to the fourth delayed input control signal PIND<1:4> and the first delayed output control signal to the fourth delayed output control signal POUTD<1:4> to output The first selection flag signal to the fourth selection flag signal S_FLAG1, S_FLAG2, S_FLAG3, and S_FLAG4 are used as inverted control signals IV_CON. If the first delayed input control signal PIND<1> is enabled, the second pipe latch unit 125 can receive and latch the first selection flag signal S_FLAG1. If the second delayed input control signal PIND<2> is enabled, the second pipe latch unit 125 can receive and latch the second selection flag signal S_FLAG2. If the third delayed input control signal PIND<3> is enabled, the second pipe latch unit 125 can receive and latch the third selection flag signal S_FLAG3. If the fourth delayed input control signal PIND<4> is enabled, the second pipe latch unit 125 can receive and latch the fourth selection flag signal S_FLAG4. If the first delayed output control signal POUTD<1> is enabled, the second pipe latch unit 125 can output the latched first selection flag signal S_FLAG1 as the inverted control signal IV_CON. If the second delayed output control signal POUTD<2> is enabled, the second pipe latch unit 125 can set the latched second selection flag The flag signal S_FLAG2 is output as the inverted control signal IV_CON. If the third delayed output control signal POUTD<3> is enabled, the second pipe latch unit 125 can output the latched third selection flag signal S_FLAG3 as the inverted control signal IV_CON. If the fourth delayed output control signal POUTD<4> is enabled, the second pipe latch unit 125 can output the latched fourth selection flag signal S_FLAG4 as the inverted control signal IV_CON. The first delayed input control signal to the fourth delayed input control signal PIND<1:4> can be generated by delaying the first input control signal to the fourth input control signal PIN<1:4> by a predetermined delay time. The first delayed output control signal to the fourth delayed output control signal POUTD<1:4> can be generated by delaying the first output control signal to the fourth output control signal POUT<1:4> by a predetermined delay time. The logic level of enabling from the first delayed input control signal to the fourth delayed input control signal PIND<1:4> and the enabling of the first delayed output control signal to the fourth delayed output control signal POUTD<1:4> The logic level may be set different according to various embodiments. The second pipe latch unit 125 may convert the first selection flag signals to the fourth selection flag signals S_FLAG1, S_FLAG2, S_FLAG3, and S_FLAG4 input in parallel to the inverted control signal IV_CON serially output from it. The order of the first selection flag signal to the fourth selection flag signal S_FLAG1, S_FLAG2, S_FLAG3, and S_FLAG4 outputted as the inverted control signal IV_CON can be determined according to the burst sequence.

The control signal output unit 126 can be synchronized with the internal clock signal ICLK to output the inverted control signal IV_CON as the transmission control signal T_CON. The transmission control signal T_CON may be output from the semiconductor device via the control pad 127.

2, the burst sequence is listed according to the level of the selection control signal S_CON, that is, the first input signal to the fourth input signal DIN1<1>, DIN2<1 that are sequentially input to the first data output circuit 11_1 >, DIN3<1> and DIN4<1> through the first pipe latch unit 115, phase The controller 116 and the data output unit 117 transmit information about the sequence to the data pad 118. For example, if the selection control signal S_CON has a logic "low" level (ie, L), the first input signal to the fourth input signal DIN1<1>, DIN2<1> are sequentially input to the first data output circuit 11_1 , DIN3<1> and DIN4<1> can be combined with the first input signal to the fourth input signal DIN1<1>, DIN2<1>, DIN3<1> and DIN4<1> to input to the first data output circuit 11_1 The same sequence is transmitted to the data pad 118. In this example, the fourth input signal DIN4<1> last input to the first data output circuit 11_1 can be stored as the storage data S_DT. After the fourth input signal DIN4<1> is stored as the storage data S_DT, the first input signal to the fourth input signal DIN1<1>, DIN2<1>, DIN3<1> and DIN4<1> can pass through the first pipe The latch unit 115, the phase controller 116 and the data output unit 117 are transmitted to the data pad 118. For example, if the control signal S_CON is selected to have a logic "high" level (ie, H), the first input signal to the fourth input signal DIN1<1>, DIN2<1> are sequentially input to the first data output circuit 11_1 , DIN3<1> and DIN4<1> can be transformed into a third input signal DIN3<1> and a fourth input signal DIN4 which are sequentially output from the first pipe latch unit 115 through the first pipe latch unit 115 <1>, the pipe latch data FL_DT of the first input signal DIN1<1> and the second input signal DIN2<1>. The pipe latch data FL_DT can be transmitted to the data pad 118 via the phase controller 116 and the data output unit 117. In this example, the second input signal DIN2<1> output from the first pipe latch unit 115 can be stored as the storage data S_DT. After the second input signal DIN2<1> is stored as the storage data S_DT, the first pipe latch unit 115 can sequentially input the first input signal to the fourth input signal DIN1<1>, DIN2<1> , DIN3<1> and DIN4<1> are transformed into a third input signal DIN3<1>, a fourth input signal DIN4<1>, a first input signal DIN1<1> and a second input signal that are sequentially output from them The pipe latch data FL_DT of DIN2<1>.

3, the data comparator 113 may include logic elements XOR31 to XOR36. The logic element XOR31 can perform an exclusive OR operation on the storage data S_DT and the first input signal DIN1<1> to generate and output the first comparison signal COM<1>. If the first input signal DIN1<1> is different from the stored data S_DT, the logic element XOR31 can output the first comparison signal COM<1> with a logic “high” level. If the first input signal DIN1<1> is the same as the stored data S_DT, the logic element XOR31 can output the first comparison signal COM<1> with a logic “low” level. The logic element XOR32 can perform an exclusive OR operation on the first input signal DIN1<1> and the second input signal DIN2<1> to generate and output the second comparison signal COM<2>. If the second input signal DIN2<1> is different from the first input signal DIN1<1>, the logic element XOR32 can output the second comparison signal COM<2> with a logic “high” level. If the second input signal DIN2<1> is the same as the first input signal DIN1<1>, the logic element XOR32 can output the second comparison signal COM<2> with a logic “low” level. The logic element XOR33 can perform an exclusive OR operation on the second input signal DIN2<1> and the third input signal DIN3<1> to generate and output the third comparison signal COM<3>. If the third input signal DIN3<1> is different from the second input signal DIN2<1>, the logic element XOR33 can output the third comparison signal COM<3> with a logic “high” level. If the third input signal DIN3<1> is the same as the second input signal DIN2<1>, the logic element XOR33 can output the third comparison signal COM<3> with a logic “low” level. The logic element XOR34 can perform mutually exclusive OR operation on the third input signal DIN3<1> and the fourth input signal DIN4<1> to generate and output the fourth comparison signal COM<4>. If the fourth input signal DIN4<1> is different from the third input signal DIN3<1>, the logic element XOR34 can output the fourth comparison signal COM<4> with a logic “high” level. If the fourth input signal DIN4<1> is the same as the third input signal DIN3<1>, the logic element XOR34 can output the fourth comparison signal COM<4> with a logic “low” level. The logic element XOR35 can respond to the third input signal DIN3<1> and the storage data S_DT perform mutually exclusive OR operation to generate and output the fifth comparison signal COM<5>. If the third input signal DIN3<1> is different from the stored data S_DT, the logic element XOR35 can output the fifth comparison signal COM<5> with a logic "high" level. If the third input signal DIN3<1> is the same as the stored data S_DT, the logic element XOR35 can output the fifth comparison signal COM<5> with a logic “low” level. The logic element XOR36 can perform an exclusive OR operation on the fourth input signal DIN4<1> and the first input signal DIN1<1> to generate and output the sixth comparison signal COM<6>. If the fourth input signal DIN4<1> is different from the first input signal DIN1<1>, the logic element XOR36 can output the sixth comparison signal COM<6> with a logic “high” level. If the fourth input signal DIN4<1> is the same as the first input signal DIN1<1>, the logic element XOR36 can output the sixth comparison signal COM<6> with a logic “low” level.

4, the comparison signal selector 114 may include a first selection/output unit 41, a second selection/output unit 42, a third selection/output unit 43, and a fourth selection/output unit 44. If the selection control signal S_CON has a logic “low” level, the first selection/output unit 41 can output the first comparison signal COM<1> as the first comparison selection signal C_SEL1<1>. If the selection control signal S_CON has a logic “high” level, the first selection/output unit 41 can output the fifth comparison signal COM<5> as the first comparison selection signal C_SEL1<1>. If the selection control signal S_CON has a logic “low” level, the second selection/output unit 42 can output the second comparison signal COM<2> as the second comparison selection signal C_SEL2<1>. If the selection control signal S_CON has a logic “high” level, the second selection/output unit 42 can output the fourth comparison signal COM<4> as the second comparison selection signal C_SEL2<1>. If the selection control signal S_CON has a logic “low” level, the third selection/output unit 43 can output the third comparison signal COM<3> as the third comparison selection signal C_SEL3<1>. If the selection control signal S_CON has a logic "high" level, the third selection/output unit 43 can output The sixth comparison signal COM<6> is used as the third comparison selection signal C_SEL3<1>. If the selection control signal S_CON has a logic “low” level, the fourth selection/output unit 44 can output the fourth comparison signal COM<4> as the fourth comparison selection signal C_SEL4<1>. If the selection control signal S_CON has a logic “high” level, the fourth selection/output unit 44 can output the second comparison signal COM<2> as the fourth comparison selection signal C_SEL4<1>.

5, the phase controller 116 may include inverters IV51, IV52, and IV53 and a transmission gate T51. The inverter IV51 can buffer the pipe latch data FL_DT in reverse. The inverter IV51 can output the inverted buffer data of the pipe latch data FL_DT to the node nd51. The inverter IV52 can buffer the inverted control signal IV_CON in an inverted manner. The inverter IV52 can output the inverted buffer signal of the inverted control signal IV_CON. If the inverted control signal IV_CON is disabled to have a logic “low” level, the inverter IV53 can invert the signal of the node nd51 to output the inverted buffer signal of the node nd51 as the phase data P_DT. If the inverted control signal IV_CON is enabled to have a logic "high" level, the transmission gate T51 can output the signal of the node nd51 as the phase data P_DT. If the inverted control signal IV_CON is disabled to have a logic "low" level, the phase controller 116 can use inverters IV51 and IV53 to buffer the pipeline latch data FL_DT to output the buffer data of the pipeline latch data FL_DT as phase data P_DT. If the inverted control signal IV_CON is enabled to have a logic "high" level, the phase controller 116 can use the inverter IV51 to invert the pipeline latch data FL_DT and use the transmission gate T51 to output the pipeline latch. The inverted buffer data of the data FL_DT is used as the phase data P_DT.

Referring to FIG. 6, the bit detector 121 may include a first detection signal generator 61, a second detection signal generator 62, a third detection signal generator 63 and a fourth detection signal generator 64. The first detection signal generator 61 may include a first level counter 611, a second level counter 612, The third level counter 613, the fourth level counter 614, the fifth level counter 615, the sixth level counter 616, and the seventh level counter 617. If neither the first bit nor the second bit C_SEL1<1:2> included in the first comparison selection signal C_SEL1<1:8> has a logic "high (H)" level, the first level counter 611 The first counting signal CNT1 that is enabled to have a logic "high" level can be generated. If any one of the first bit and the second bit C_SEL1<1:2> included in the first comparison selection signal C_SEL1<1:8> has a logic "high (H)" level, then the first level The counter 611 can generate a second counting signal CNT2 that is enabled to have a logic "high" level. If each of the first bit and the second bit C_SEL1<1:2> included in the first comparison selection signal C_SEL1<1:8> has a logic "high (H)" level, then the first bit The quasi-counter 611 can generate a third counting signal CNT3 that is enabled to have a logic “high” level. If neither the third bit nor the fourth bit C_SEL1<3:4> included in the first comparison selection signal C_SEL1<1:8> has a logic "high (H)" level, the second level counter 612 The fourth counting signal CNT4 that is enabled to have a logic "high" level can be generated. If any one of the third bit and the fourth bit C_SEL1<3:4> included in the first comparison selection signal C_SEL1<1:8> has a logic "high (H)" level, the second level The counter 612 can generate a fifth counting signal CNT5 that is enabled to have a logic "high" level. If each of the third and fourth bits included in the first comparison selection signal C_SEL1<1:8> has a logic "high (H)" level, the second bit The quasi-counter 612 can generate a sixth counting signal CNT6 that is enabled to have a logic “high” level. If neither the fifth bit nor the sixth bit C_SEL1<5:6> included in the first comparison selection signal C_SEL1<1:8> has a logic "high (H)" level, the third level counter 613 The seventh counting signal CNT7 that is enabled to have a logic "high" level can be generated. If any one of the fifth and sixth bits included in the first comparison selection signal C_SEL1<1:8> C_SEL1<5:6> has a logic "high (H)" level, then the third level The counter 613 can generate an eighth counting signal CNT8 that is enabled to have a logic "high" level. If the first A comparison selection signal C_SEL1<1:8> includes the fifth and sixth bits C_SEL1<5:6> each has a logic "high (H)" level, then the third level counter 613 can generate the ninth counting signal CNT9 that is enabled to have a logic "high" level. If neither the seventh bit nor the eighth bit C_SEL1<7:8> included in the first comparison selection signal C_SEL1<1:8> has a logic "high (H)" level, the fourth level counter 614 The tenth counting signal CNT10 which is enabled to have a logic "high" level can be generated. If any one of the seventh bit and the eighth bit included in the first comparison selection signal C_SEL1<1:8> has a logic "high (H)" level, then the fourth level The counter 614 can generate the eleventh counting signal CNT11 that is enabled to have a logic "high" level. If each of the seventh and eighth bits included in the first comparison selection signal C_SEL1<1:8> has a logic "high (H)" level, the fourth bit The quasi-counter 614 can generate the twelfth counting signal CNT12 that is enabled to have a logic "high" level.

The fifth level counter 615 can receive the first counting signal to the sixth counting signal CNT1, CNT2, CNT3, CNT4, CNT5, and CNT6 to generate the thirteenth counting signal CNT13. If the first comparison selection signal C_SEL1<1:8> The included first bit to fourth bit C_SEL1<1:4> do not have a logic "high (H)" level, and the thirteenth counting signal CNT13 is enabled to have a logic "high" level. The fifth level counter 615 can receive the first counting signal to the sixth counting signal CNT1, CNT2, CNT3, CNT4, CNT5 and CNT6 to generate the fourteenth counting signal CNT14. If the first comparison selection signal C_SEL1<1:8> If one of the included first to fourth bits C_SEL1<1:4> has a logic "high (H)" level, the fourteenth counting signal CNT14 is enabled to have a logic "high" level. The fifth level counter 615 can receive the first counting signal to the sixth counting signal CNT1, CNT2, CNT3, CNT4, CNT5, and CNT6 to generate the fifteenth counting signal CNT15. If the first comparison selection signal C_SEL1<1:8> Including the first to fourth bits Two of the C_SEL1<1:4> have a logic "high (H)" level, then the fifteenth counting signal CNT15 is enabled to have a logic "high" level. The fifth level counter 615 can receive the first counting signal to the sixth counting signal CNT1, CNT2, CNT3, CNT4, CNT5, and CNT6 to generate the sixteenth counting signal CNT16. If the first comparison selection signal C_SEL1<1:8> Three of the included first to fourth bits C_SEL1<1:4> have a logic "high (H)" level, then the sixteenth counting signal CNT16 is enabled to have a logic "high" level . The fifth level counter 615 can receive the first counting signal to the sixth counting signal CNT1, CNT2, CNT3, CNT4, CNT5, and CNT6 to generate the seventeenth counting signal CNT17. If the first comparison selection signal C_SEL1<1:8> Each of the included first bit to fourth bit C_SEL1<1:4> has a logic "high (H)" level, then the seventeenth counting signal CNT17 is enabled to have a logic "high" bit quasi.

The sixth level counter 616 can receive the seventh count signal to the twelfth count signal CNT7, CNT8, CNT9, CNT10, CNT11, and CNT12 to generate the eighteenth count signal CNT18. If the first comparison select signal C_SEL1<1:8> The fifth bit to the eighth bit included in C_SEL1<5:8> do not have a logic "high (H)" level, then the eighteenth counting signal CNT18 is enabled to have a logic "high" level. The sixth level counter 616 can receive the seventh count signal to the twelfth count signal CNT7, CNT8, CNT9, CNT10, CNT11, and CNT12 to generate the nineteenth count signal CNT19. If the first comparison select signal C_SEL1<1:8> If one of the fifth to eighth bits included in C_SEL1<5:8> has a logic "high (H)" level, the nineteenth counting signal CNT19 is enabled to have a logic "high" level . The sixth level counter 616 can receive the seventh count signal to the twelfth count signal CNT7, CNT8, CNT9, CNT10, CNT11, and CNT12 to generate the twentieth count signal CNT20, if the first comparison selection signal C_SEL1<1:8> Two of the fifth to eighth bits included in C_SEL1<5:8> have a logic "high (H)" level, then the twentieth counting signal CNT20 It is enabled to have a logical "high" level. The sixth level counter 616 can receive the seventh count signal to the twelfth count signal CNT7, CNT8, CNT9, CNT10, CNT11, and CNT12 to generate the twenty-first count signal CNT21, if the first comparison selection signal C_SEL1<1:8 > Three of the fifth to eighth bits included in C_SEL1<5:8> have logic "high (H)" levels, then the twenty-first counting signal CNT21 is enabled to have logic "high" "Level. The sixth level counter 616 can receive the seventh count signal to the twelfth count signal CNT7, CNT8, CNT9, CNT10, CNT11 and CNT12 to generate the twenty-second count signal CNT22. If the first comparison selection signal C_SEL1<1:8 > Each of the fifth to eighth bits included in C_SEL1<5:8> has a logic "high (H)" level, then the twenty-second count signal CNT22 is enabled to have a logic " High" level.

The seventh level counter 617 can receive the 13th count signal to the 22nd count signal CNT13, CNT14, CNT15, CNT16, CNT17, CNT18, CNT19, CNT20, CNT21 and CNT22 to generate the first detection signal DET1. At least five of the first to eighth bits included in the comparison selection signal C_SEL1<1:8> C_SEL1<1:8> have a logic "high (H)" level, then the first detection signal DET1 It is enabled to have a logical "high" level.

Hereinafter, the operation of the bit detector 121 will be described in conjunction with an example. In this example, the first to eighth bits of the first comparison selection signal C_SEL1<1:8> are respectively set to have logic "H ", "H", "L", "L", "H", "L", "H" and "H" levels. Since the first bit and the second bit C_SEL1<1:2> of the first comparison selection signal C_SEL1<1:8> all have the logic "H" level, so between the first counting signal and the third counting signal CNT1 Only the third counting signal CNT3 among CNT2 and CNT3 can be generated to have a logic "H" level. Since the third bit and the fourth bit C_SEL1<3:4> of the first comparison selection signal C_SEL1<1:8> do not have the logic "H" level, the fourth to sixth count signal CNT4 , CNT5 and CNT6 only the fourth counting signal CNT4 can be generated to have a logic "H" level. Since one of the fifth bit and the sixth bit C_SEL1<5:6> of the first comparison selection signal C_SEL1<1:8> has a logic "H" level, it is in the seventh to the ninth count signal Only the eighth counting signal CNT8 among CNT7, CNT8, and CNT9 can be generated with a logic "H" level. Since each of the seventh bit and the eighth bit C_SEL1<7:8> of the first comparison selection signal C_SEL1<1:8> has a logic "H" level, the count signals from the tenth to the tenth Among the two counting signals CNT10, CNT11, and CNT12, only the twelfth counting signal CNT12 can be generated with a logic "H" level. Since two bits from the first bit to the fourth bit C_SEL1<1:4> of the first comparison selection signal C_SEL1<1:8> (ie, the first bit and the second bit C_SEL1<1 : 2>) has a logic "H" level, so only the fifteenth count signal CNT15 can be generated as a logic "H" level among the thirteenth count signal to the seventeenth count signal CNT13, CNT14, CNT15, CNT16 and CNT17 H" level. Since the first comparison selection signal C_SEL1<1:8> has three bits from the fifth bit to the eighth bit C_SEL1<5:8> (ie, the fifth bit C_SEL1<5> and the seventh bit) C_SEL1<7> and the eighth bit C_SEL1<8>) have a logic "H" level, so only the eighteenth count signal to the twenty-second count signal CNT18, CNT19, CNT20, CNT21 and CNT22 The twenty-one count signal CNT21 can be generated to have a logic "H" level. Since the fifteenth counting signal CNT15 and the twenty-first counting signal CNT21 have a logic "H" level, five of the first to eighth bits of the first comparison selection signal C_SEL1<1:8> The bit can be considered to have a logical "H" level. Therefore, the first detection signal DET1 can be enabled to have a logic "H" level.

If at least five of the first to eighth bits included in the second comparison selection signal C_SEL2<1:8> C_SEL2<1:8> have a logic "H" level, the second detection The signal generator 62 can generate the second detection signal DET2 that is enabled to have a logic "H" level. If at least the first bit to the eighth bit included in the third comparison selection signal C_SEL3<1:8> C_SEL3<1:8> If the five bits have the logic "H" level, the third detection signal generator 63 can generate the third detection signal DET3 that is enabled to have the logic "H" level. If at least five of the first to eighth bits included in the fourth comparison selection signal C_SEL4<1:8> C_SEL4<1:8> have a logic "H" level, the fourth detection The signal generator 64 can generate the fourth detection signal DET4 that is enabled to have a logic "H" level. Each of the second detection signal generator 62, the third detection signal generator 63, and the fourth detection signal generator 64 may have substantially the same configuration as the first detection signal generator 61. Therefore, the detailed configuration and operation of the second detection signal generator 62, the third detection signal generator 63, and the fourth detection signal generator 64 will be omitted hereinafter.

Referring to FIG. 7, the flag generator 122 may include logic elements XOR71 to XOR74. The logic element XOR71 can perform an exclusive OR operation on the storage flag signal FLAG_S and the first detection signal DET1 to generate the first flag signal FLAG1. If the first detection signal DET1 and the storage flag signal FLAG_S have different logic levels, the logic element XOR71 can generate the first flag signal FLAG1 with a logic “high” level. If the first detection signal DET1 and the storage flag signal FLAG_S have the same logic level, the logic element XOR71 can generate the first flag signal FLAG1 with a logic “low” level. The logic element XOR72 can perform an exclusive OR operation on the first flag signal FLAG1 and the second detection signal DET2 to generate the second flag signal FLAG2. If the first flag signal FLAG1 and the second detection signal DET2 have different logic levels, the logic element XOR72 can generate the second flag signal FLAG2 with a logic “high” level. If the first flag signal FLAG1 and the second detection signal DET2 have the same logic level, the logic element XOR72 can generate the second flag signal FLAG2 with a logic “low” level. The logic element XOR73 can perform an exclusive OR operation on the second flag signal FLAG2 and the third detection signal DET3 to generate the third flag signal FLAG3. If the second flag signal FLAG2 and the third detection signal DET3 have different logic levels, the logic element XOR73 can To generate a third flag signal FLAG3 with a logic "high" level. If the second flag signal FLAG2 and the third detection signal DET3 have the same logic level, the logic element XOR73 can generate the third flag signal FLAG3 with a logic “low” level. The logic element XOR74 can perform an exclusive OR operation on the third flag signal FLAG3 and the fourth detection signal DET4 to generate the fourth flag signal FLAG4. If the third flag signal FLAG3 and the fourth detection signal DET4 have different logic levels, the logic element XOR74 can generate the fourth flag signal FLAG4 with a logic “high” level. If the third flag signal FLAG3 and the fourth detection signal DET4 have the same logic level, the logic element XOR74 can generate the fourth flag signal FLAG4 with a logic “low” level. The flag generator 122 can receive the storage flag signal FLAG_S, and can sequentially compare the first to fourth detection signals DET1, DET2, DET3, and DET4 with the storage flag signal FLAG_S to follow the logic of the transmission control signal T_CON Level and logic levels from the first output data output from the first data output circuit to the eighth data output circuits 11_1, 11_2,... and 11_8 to the eighth output data DQ<1:8> to perform the reverse of the data Operations related to the relevant strategy. For example, if the logic levels of at least five bits in the transmission control signal T_CON and the first output data to the eighth output data DQ<1:8> are changed, then the first output data to the eighth output data DQ< 1:8> All phases can be inverted, and the inverted data from the first output data to the eighth output data DQ<1:8> can be output. After that, the data inversion strategy will be described with reference to FIG. 9, FIG. 10, and FIG. 11.

Referring to FIG. 8, the selection flag generator 124 may include a first flag selector 81, a second flag selector 82, a third flag selector 83 and a fourth flag selector 84. If the delay selection control signal S_COND has a logic “low” level, the first flag selector 81 can output the first flag signal FLAG1 as the first selection flag signal S_FLAG1. If the delay selection control signal S_COND has a logic "high" level, the first flag selector 81 can output the third flag signal FLAG3 as The first selection flag signal S_FLAG1. If the delay selection control signal S_COND has a logic “low” level, the second flag selector 82 can output the second flag signal FLAG2 as the second selection flag signal S_FLAG2. If the delay selection control signal S_COND has a logic “high” level, the second flag selector 82 can output the fourth flag signal FLAG4 as the second selection flag signal S_FLAG2. If the delay selection control signal S_COND has a logic “low” level, the third flag selector 83 can output the third flag signal FLAG3 as the third selection flag signal S_FLAG3. If the delay selection control signal S_COND has a logic “high” level, the third flag selector 83 can output the first flag signal FLAG1 as the third selection flag signal S_FLAG3. If the delay selection control signal S_COND has a logic “low” level, the fourth flag selector 84 can output the fourth flag signal FLAG4 as the fourth selection flag signal S_FLAG4. If the delay selection control signal S_COND has a logic “high” level, the fourth flag selector 84 can output the second flag signal FLAG2 as the fourth selection flag signal S_FLAG4. In the semiconductor device of the embodiment, because the first flag FLAG1 to the fourth flag FLAG4 are selected from the first comparison selection signal to the fourth comparison selection signal C_SEL1<1>, C_SEL2<1>, C_SEL3<1>, and C_SEL4<1 > (It is output from the comparison signal selector 114 and its output order is changed according to the burst sequence), so the selection flag generator 124 can be used to change the output order of its output signal according to the burst sequence to restore the input to the first The input sequence of the first selection flag signal S_FLAG1 to the fourth selection flag signal S_FLAG4 of the second pipe latch unit 125.

9, from the first data output circuit to the eighth data output circuit 11_1, 11_2,... and 11_8 output first output data to the eighth output data DQ<1:8> logic level and transmission control signal The logic level of T_CON can be determined before the data inversion operation is performed. That is, FIG. 9 illustrates input signals DIN1<1:8>, DIN2<1:8>, DIN3< which are sequentially input to the first data output circuit to the eighth data output circuit 11_1, 11_2,..., and 11_8 1:8> and DIN4<1:8> are not inverted In the case of output as an example of the first output data to the eighth output data DQ<1:8>. In the first output data DQ<1>, the logic level "L" of "before output" means that the first input signal to the fourth input signal DIN1<1>, DIN2<1>, DIN3<1> and DIN4 <1>Before being input to the first data output circuit 11_1, the first input signal to the fourth input signal DIN1<1>, DIN2<1>, DIN3<1> and DIN4<1> all have logic "low" bits quasi. In the first output data DQ<1>, the logical level combination "H, H, H, L" of "first output", "second output", "third output" and "fourth output" means The first input signal DIN1<1> with logic "high" level, the second input signal DIN2<1> with logic "high" level, and the third input signal DIN3<1> with logic "high" level And the fourth input signal DIN4<1> with a logic "low" level is sequentially input to the first data output circuit 11_1. As shown in FIG. 9, the number of switching bits among the bits included in the first output data to the eighth output data DQ<1:8> at the "first output" stage is 5, and in the "first output" stage, The number of switching bits among the bits included in the first output data to the eighth output data DQ<1:8> at the "second output" stage is 4. In addition, the number of switching bits among the bits included in the first output data to the eighth output data DQ<1:8> at the "third output" stage is 4, and at the "fourth output" stage The number of switching bits among the bits included in the first output data to the eighth output data DQ<1:8> is 5. In addition, data inversion operation has not yet occurred. Therefore, all the transmission control signals T_CON can have a logic "low" level. Therefore, the number of switching bits among the bits included in the first output data to the eighth output data DQ<1:8> and the transmission control signal T_CON at the "first output" stage is 5, and in the "first output" The number of switching bits among the bits included in the transmission control signal T_CON from the first output data to the eighth output data DQ<1:8> and the transmission control signal T_CON is 4 (ie, the bits of “DQ+T_CON” Number of quasi-transitions). In addition, the number of switching bits among the bits included in the first output data to the eighth output data DQ<1:8> and the transmission control signal T_CON at the "third output" stage is 4, and in the "third output" The first output data to the eighth output data DQ<1:8> and the transmission control signal The number of switching bits among the bits included in the number T_CON is 5.

10, the data inversion operation performed according to the number of switching bits among the bits included in the first output data to the eighth output data DQ<1:8> can be determined. As described with reference to FIG. 9, the number of switching bits among the bits included in the first output data to the eighth output data DQ<1:8> at the "first output" stage is 5, while the The number of switching bits among the bits included in the first output data to the eighth output data DQ<1:8> at the "fourth output" stage is 5. Therefore, it is possible to invert all the logic levels of the first output data at the "first output" stage to the eighth output data DQ<1:8>, and it is also possible to invert the first output at the "fourth output" stage Data to all logic levels of the eighth output data DQ<1:8>. As a result of the above data inversion operation, the number of switching bits among the bits included in the first output data to the eighth output data DQ<1:8> at the "first output" stage is 3, and The number of switching bits among the bits included in the first output data to the eighth output data DQ<1:8> at the "second output" stage is 4. In addition, the number of switching bits among the bits included in the first output data to the eighth output data DQ<1:8> at the "third output" stage is 4, and at the "fourth output" stage The number of switching bits among the bits included in the first output data to the eighth output data DQ<1:8> is 3. In this example, because the data inversion operation is performed at the “first output” stage and the “fourth output” stage, the control signal T_CON is transmitted at the “first output” stage and the “fourth output” stage. The logic level can be changed to a logic "high" level. Therefore, the number of switching bits among the bits included in the first output data to the eighth output data DQ<1:8> and the transmission control signal T_CON at the "first output" stage is 4, while in the "first output" The number of switching bits among the bits included in the first output data to the eighth output data DQ<1:8> and the transmission control signal T_CON at the "second output" stage is 5. In addition, the number of switching bits among the bits included in the first output data to the eighth output data DQ<1:8> and the transmission control signal T_CON at the "third output" stage is 4, and in the "third output" The first output to the eighth output at the "four output" stage The number of switching bits among the bits included in the output data DQ<1:8> and the transmission control signal T_CON is 4. For example, when the number of switching bits among the bits included in the first output data to the eighth output data DQ<1:8> at the "second output" stage is 4, in the "second output" stage The number of switching bits among the bits included in the first output data to the eighth output data DQ<1:8> and the transmission control signal T_CON is 5.

Referring to FIG. 11, the data inversion operation performed according to the number of switching bits among the bits included in the first to eighth output data DQ<1:8> and the transmission control signal T_CON can be determined. As described with reference to FIG. 10, the number of switching bits among the bits included in the first output data to the eighth output data DQ<1:8> and the transmission control signal T_CON at the "second output" stage is 5. Therefore, the logic levels of the first output data to the eighth output data DQ<1:8> and the transmission control signal T_CON can all be inverted in the "second output" stage. As a result of the above data inversion operation, at the "third output" stage, the first output data to the eighth output data DQ<1:8> and the switching bit among the bits included in the transmission control signal T_CON The number can be 5. Therefore, the logic levels of the first output data to the eighth output data DQ<1:8> and the transmission control signal T_CON can all be inverted in the "third output" stage. As a result of the above data inversion operation, in the "fourth output" stage, the first output data to the eighth output data DQ<1:8> and the switching bit among the bits included in the transmission control signal T_CON The number can be 5. Therefore, the logic levels of the first output data to the eighth output data DQ<1:8> and the transmission control signal T_CON can all be inverted in the "fourth output" stage. Therefore, the number of switching bits among the bits included in the first output data to the eighth output data DQ<1:8> and the transmission control signal T_CON at the "first output" stage is 4, and at the "first output" stage The number of switching bits among the bits included in the first output data to the eighth output data DQ<1:8> and the transmission control signal T_CON at the "second output" stage is 4. In addition, in the "third output" The number of switching bits among the bits included in the first output data to the eighth output data DQ<1:8> and the transmission control signal T_CON is 4 at the stage, and the first output at the "fourth output" stage Data to the eighth output data DQ<1:8> and the number of switching bits among the bits included in the transmission control signal T_CON is 4. The above data inversion operation can be performed by the flag generator 122 shown in FIG. 7.

As described above, the semiconductor device according to the embodiment can perform data inversion according to the number of switching bits among the bits included in the first to eighth output data DQ<1:8> and the transmission control signal T_CON operating. These data inversion operations can remove the SSN generated through the first output data to the eighth output data DQ<1:8> and the transmission control signal T_CON, thereby improving the signal integrity of the semiconductor device.

In the following, the data inversion strategy of the semiconductor device according to the burst sequence will be described in conjunction with an example in which the selection control signal S_CON has a logic “low” level.

As described with reference to Figure 2, if the selection control signal S_CON has a logic "low" level, the first input signal DIN1<1>, the second input signal DIN2<1>, the third input signal DIN3<1> and the The four-input signal DIN4<1> can be sequentially transmitted to the data pad 118 via the first pipe latch unit 115, the phase controller 116, and the data output unit 117. The fourth input signal DIN4<1> can be selected as the final data F_DT, and the final data F_DT can be output as the storage data S_DT. The first comparison signal COM<1> generated by comparing the first input signal DIN1<1> with the stored data S_DT can be output as the first comparison selection signal C_SEL1<1>, and by comparing the second input signal DIN2< 1> The second comparison signal COM<2> generated by comparing with the first input signal DIN1<1> can be output as the second comparison selection signal C_SEL2<1>. The third comparison signal COM<3> generated by comparing the third input signal DIN3<1> with the second input signal DIN2<1> can be output as the third comparison selection signal C_SEL3<1>. By connecting the fourth input signal DIN4<1> with The fourth comparison signal COM<4> generated by the comparison of the third input signal DIN3<1> can be output as the fourth comparison selection signal C_SEL4<1>. Similarly, in the second data output circuit to the eighth data output circuit 11_2,..., and 11_8, the input signals DIN1<2:8>, DIN2<2:8>, DIN3<2:8> and DIN4<2:8> generates comparison selection signals C_SEL1<2:8>, C_SEL2<2:8>, C_SEL3<2:8> and C_SEL4<2:8>.

If the number of logic "H" levels among the logic levels of the bits included in the first comparison selection signal C_SEL1<1:8> is equal to or greater than 5, the enabled first detection signal DET1 can be generated, And if the number of logical "H" levels among the logical levels of the bits included in the second comparison selection signal C_SEL2<1:8> is equal to or greater than 5, the enabled second detection signal DET2 can be generated . Similarly, if the number of logic "H" levels among the logic levels of the bits included in the third comparison selection signal C_SEL3<1:8> is equal to or greater than 5, an enabled third detection can be generated Signal DET3, and if the number of logic "H" levels among the logic levels of the bits included in the fourth comparison selection signal C_SEL4<1:8> is equal to or greater than 5, then an enabled fourth Detection signal DET4.

The exclusive OR operation can be performed on the storage flag signal FLAG_S and the first detection signal DET1 to generate the first flag signal FLAG1, and the exclusive OR operation can be performed on the first flag signal FLAG1 and the second detection signal DET2 to generate the first flag signal FLAG_S and the second detection signal DET2. The second flag signal FLAG2. The second flag signal FLAG2 and the third detection signal DET3 can be subjected to exclusive OR operation to generate the third flag signal FLAG3, and the third flag signal FLAG3 and the fourth detection signal DET4 can be subjected to exclusive OR operation to generate The fourth flag signal FLAG4. The data inversion operation can be performed through the above exclusive OR operation according to the number of switching bits among the bits included in the first to eighth output data DQ<1:8> and the transmission control signal T_CON.

The first flag signal FLAG1 can be output as the first selection flag signal S_FLAG1 and the second flag signal FLAG2 can be output as the second selection flag signal S_FLAG2. The third flag signal FLAG3 may be output as the third selection flag signal S_FLAG3, and the fourth flag signal FLAG4 may be output as the fourth selection flag signal S_FLAG4. The first selection flag signal S_FLAG1, the second selection flag signal S_FLAG2, the third selection flag signal S_FLAG3, and the fourth selection flag signal S_FLAG4 corresponding to the parallel signals can be converted into the inverted control signal IV_CON for serial transmission. And the inverted control signal IV_CON can be output as the transmission control signal T_CON via the control pad 127.

In the following, the data inversion strategy of the semiconductor device according to the burst sequence will be described in conjunction with an example in which the selection control signal S_CON has a logic “high” level.

As described with reference to Figure 2, if the selection control signal S_CON has a logic "high" level, the third input signal DIN3<1>, the fourth input signal DIN4<1>, the first input signal DIN1<1> and the second The second input signal DIN2<1> can be sequentially transmitted to the data pad 118 via the first pipe latch unit 115, the phase controller 116, and the data output unit 117. The second input signal DIN2<1> can be selected as the final data F_DT, and the final data F_DT can be output as the storage data S_DT. The fifth comparison signal COM<5> generated by comparing the third input signal DIN3<1> with the stored data S_DT can be output as the first comparison selection signal C_SEL1<1>, and by comparing the fourth input signal DIN4< 1>The fourth comparison signal COM<4> generated by comparing with the third input signal DIN3<1> can be output as the second comparison selection signal C_SEL2<1>. The sixth comparison signal COM<6> generated by comparing the fourth input signal DIN4<1> with the first input signal DIN1<1> can be output as the third comparison selection signal C_SEL3<1>, and by The second comparison signal COM<2> generated by comparing the second input signal DIN2<1> with the first input signal DIN1<1> can be output as the fourth comparison selection signal C_SEL4<1>. Similarly, in the second data output circuit to In the eighth data output circuit 11_2... and 11_8, the comparison selection signal C_SEL1 can also be generated from the input signals DIN1<2:8>, DIN2<2:8>, DIN3<2:8> and DIN4<2:8> <2:8>, C_SEL2<2:8>, C_SEL3<2:8> and C_SEL4<2:8>.

If the number of logic "H" levels among the logic levels of the bits included in the first comparison selection signal C_SEL1<1:8> is equal to or greater than 5, the enabled first detection signal DET1 can be generated. If the number of logic “H” levels among the logic levels of the bits included in the second comparison selection signal C_SEL2<1:8> is equal to or greater than 5, the enabled second detection signal DET2 can be generated. Similarly, if the number of logic "H" levels among the logic levels of the bits included in the third comparison selection signal C_SEL3<1:8> is equal to or greater than 5, an enabled third detection can be generated Signal DET3. If the number of logic "H" levels among the logic levels of the bits included in the fourth comparison selection signal C_SEL4<1:8> is equal to or greater than 5, the enabled fourth detection signal DET4 can be generated.

The exclusive OR operation can be performed on the storage flag signal FLAG_S and the first detection signal DET1 to generate the first flag signal FLAG1, and the exclusive OR operation can be performed on the first flag signal FLAG1 and the second detection signal DET2 to generate the first flag signal FLAG_S and the second detection signal DET2. The second flag signal FLAG2. The second flag signal FLAG2 and the third detection signal DET3 can be subjected to exclusive OR operation to generate the third flag signal FLAG3, and the third flag signal FLAG3 and the fourth detection signal DET4 can be subjected to exclusive OR operation to generate The fourth flag signal FLAG4. The data inversion operation can be performed through the above exclusive OR operation according to the number of switching bits among the bits included in the first to eighth output data DQ<1:8> and the transmission control signal T_CON.

The third flag signal FLAG3 may be output as the first selection flag signal S_FLAG1, and the fourth flag signal FLAG4 may be output as the second selection flag signal S_FLAG2. The first flag signal FLAG1 can be output as the third selection flag signal S_FLAG3, And the second flag signal FLAG2 can be output as the fourth selection flag signal S_FLAG4. The first selection flag signal S_FLAG1, the second selection flag signal S_FLAG2, the third selection flag signal S_FLAG3, and the fourth selection flag signal S_FLAG4 corresponding to the parallel signals can be converted into the inverted control signal IV_CON for serial transmission. And the inverted control signal IV_CON can be output as the transmission control signal T_CON via the control pad 127.

As described above, the semiconductor device according to the embodiment may include performing the data inversion operation according to the burst sequence without changing the design.

The semiconductor device described above (see Figure 1 to Figure 11) is particularly useful in the design of memory devices, processors, and computer systems. For example, referring to FIG. 12, a block diagram of a system employing a semiconductor device according to various embodiments is illustrated and designated by reference numeral 1000 as a whole. The system 1000 may include one or more processors (ie, "processors") or, for example, but not limited to, a central processing unit (CPU) 1100. The processor (ie, CPU) 1100 may be used alone or in combination with other processors (ie, CPU). Although the processor (ie, CPU) 1100 is primarily referred to in the singular, those skilled in the art will understand that the system 1000 can be implemented with any number of physical or logical processors (ie, CPU).

The chipset 1150 may be operatively coupled to the processor (ie, CPU) 1100. The chipset 1150 is a communication path for signals between the processor (ie, CPU) 1100 and other components of the system 1000. Other components of the system 1000 may include a memory controller 1200, an input/output (I/O) bus 1250, and a disk drive controller 1300. According to the configuration of the system 1000, any one of several different signals can be transmitted via the chipset 1150, and those skilled in the art will recognize that the signals passing through the system 1000 can be easily adjusted without changing the basic properties of the system 1000 route.

As mentioned above, the memory controller 1200 may be operatively coupled to the chipset 1150. The memory controller 1200 may include at least one semiconductor device as discussed above with reference to FIGS. 1 to 11. Therefore, the memory controller 1200 can receive the request provided from the processor (ie, CPU) 1100 via the chipset 1150. In an alternative embodiment, the memory controller 1200 may be integrated in the chipset 1150. The memory controller 1200 may be operatively coupled to one or more memory devices 1350. In an embodiment, the memory device 1350 may include at least one semiconductor device as discussed above in relation to FIGS. 1 to 11, and the memory device 1350 may include multiple word lines and multiple bits for defining multiple storage cells. line. The memory device 1350 may be of several industry standard memory types (including but not limited to, single inline memory modules (SIMM, single inline memory modules) and dual inline memory modules (DIMM, dual inline memory modules) ) Any one of them. In addition, the memory device 1350 can assist the safe removal of the external data storage device by storing both commands and data.

The chipset 1150 can also be coupled to the I/O bus 1250. The I/O bus 1250 can be used as a communication path for signals from the chipset 1150 to the I/O devices 1410, 1420, and 1430. The I/O devices 1410, 1420, and 1430 may include, but are not limited to, for example, a mouse 1410, a video display 1420, or a keyboard 1430. The I/O bus 1250 can use any of several communication protocols to communicate with the I/O devices 1410, 1420, and 1430. In an embodiment, the I/O bus 1250 may be integrated in the chipset 1150.

The disk drive controller 1300 may be operatively coupled to the chipset 1150. The drive controller 1300 can be used as a communication path between the chipset 1150 and one internal drive 1450 or more than one internal drive 1450. The internal disk drive 1450 can assist the disconnection of the external data storage device by storing both commands and data. The disk drive controller 1300 and the internal disk drive 1450 can use almost any type of communication protocol (including but not limited to, all the communications mentioned above about the I/O bus Protocol) to communicate with each other or with the chipset 1150.

It is important that the system 1000 described above with respect to FIG. 12 is only an example of the system 1000 using the semiconductor device as discussed above with respect to FIGS. 1 to 11. In alternative embodiments (such as, for example, but not limited to, a cell phone or a digital camera), the elements may differ from the embodiment shown in FIG. 12.

11: Data output circuit group

11_1~11_8: the first to eighth data output circuit

111: data selector

112: data storage unit

113: data comparator

114: Comparison signal selector

115: The first pipe latch unit

116: Phase Controller

117: data output unit

118: Data Pad

12: Control signal output circuit

121: bit detector

122: Flag Generator

123: Flag storage unit

124: Select Flag Generator

125: The second pipe latch unit

126: Control signal output unit

127: Control Pad

COM<1:6>: the first to sixth comparison signal

C_SEL1<1:8>~C_SEL4<1:8>: first to fourth comparison selection signal

DQ<1>: First output data

DIN1<1>~DIN4<1>: the first to fourth input signals

DET1~DET4: the first to fourth detection signals

F_DT: Final data

FL_DT: Pipe latch data

FLAG1~FLAG4: the first to fourth flag signals

FLAG_S: store flag signal

ICLK: Internal clock signal

IV_CON: Inverting control signal

PINSUM: Store control signal

PINSUMD: Delayed storage of control signals

POUT<1:4>: The first to fourth output control signals

POUTD<1:4>: The first to fourth delayed output control signals

PIN<1:4>: The first to fourth input control signals

PIND<1:4>: The first to fourth delayed input control signals

P_DT: Phase data

S_DT: save data

S_CON: select control signal

S_COND: Delay selection control signal

S_FLAG1~S_FLAG4: the first to fourth selection flag signals

T_CON: Transmission control signal

Claims (30)

A semiconductor device, comprising: a data output circuit, adapted to compare the first input signal with stored data in a first burst sequence in which a first input signal and a second input signal are sequentially output as output data to generate a first A comparison selection signal, and the second input signal is compared with the first input signal to generate a second comparison selection signal, and is suitable for the second group of output data when the second input signal and the first input signal are sequentially output In the sending sequence, the second input signal is compared with the stored data to generate the first comparison selection signal, and the second input signal is compared with the first input signal to generate the second comparison selection signal; and the control signal output circuit is applicable For detecting the logic levels of the bits included in the first comparison selection signal and the second comparison selection signal to generate the first detection signal and the second detection signal, it is suitable for responding to the storage flag signal to obtain the first detection signal and the second detection signal The detection signal generates a first flag signal and a second flag signal, and is suitable for sequentially outputting the first flag signal and the second flag signal as the transmission control signal. The semiconductor device according to claim 1, wherein, in the first burst sequence, after the second input signal is stored as the storage data, the first input signal and the second input signal are sequentially input to the data output circuit again. The semiconductor device according to claim 1, wherein, in the second burst sequence, after the first input signal is stored as the storage data, the second input signal and the first input signal are sequentially input to the data output circuit again. The semiconductor device according to claim 1, wherein the data output circuit includes a data storage unit adapted to store the second input signal as storage data in the first burst sequence, and suitable for storing the second input signal in the second burst sequence. The first input signal is stored as storage data in the sending sequence. The semiconductor device according to claim 1, wherein the data output circuit includes a data comparator, and the data comparator is adapted to compare the first input signal with the stored data to generate a first comparison signal, and is adapted to compare the second input signal Compare with the first input signal to generate a second comparison signal, and is suitable for comparing the second input signal with stored data to generate a third comparison signal. The semiconductor device according to claim 5, wherein the data output circuit further includes a comparison signal selector adapted to output the first comparison signal as the first comparison selection signal in the first burst sequence and output the first comparison signal The second comparison signal is used as the second comparison selection signal, and is suitable for outputting the third comparison signal as the first comparison selection signal and the second comparison signal as the second comparison selection signal in the second burst sequence. The semiconductor device according to claim 1, wherein the data output circuit includes a pipe latch unit adapted to sequentially latch the first input signal and the second input signal in response to the input control signal, and to In response to the output control signal, the first input signal of the latch and the second input signal of the latch are output as pipe latch data. The semiconductor device according to claim 7, wherein, in the first burst sequence, the pipe latch unit outputs the latched second input signal after the latched first input signal is output as pipe latch data As the pipe latch data; and wherein, in the second input sequence mode, the pipe latch unit outputs the latched first input signal as the pipe latch after the second input signal of the latch is output as the pipe latch data Lock the data. The semiconductor device according to claim 7, wherein the data output circuit further includes: The phase controller is adapted to respond to the inverted control signal to determine the inversion of the pipe latch data to generate phase data; and the data output unit is adapted to synchronize the internal clock signal to generate output data from the phase data, where the output The data is output via the data pad. The semiconductor device according to claim 1, wherein the control signal output circuit includes a bit detector adapted to detect the logic level of the bit included in the first comparison selection signal to generate the first detection signal , And a logic level suitable for detecting the bits included in the second comparison selection signal to generate the second detection signal. The semiconductor device according to claim 1, wherein the control signal output circuit includes a flag generator adapted to compare the first detection signal with the stored flag signal to generate the first flag signal, and adapted to A flag signal is compared with the second detection signal to generate the second flag signal; and the flag storage unit is adapted to store the second flag signal as the storage flag signal in response to the delayed storage control signal. The semiconductor device according to claim 1, wherein the control signal output circuit includes a selection flag generator, the selection flag generator being adapted to output the first flag signal as the first selection flag in the first burst sequence Signal and output the second flag signal as the second selection flag signal, and is suitable for outputting the second flag signal as the first selection flag signal and outputting the first flag signal as the second selection in the second burst sequence Flag signal. The semiconductor device according to claim 12, wherein the control signal output circuit further includes a pipe latch unit adapted to sequentially latch the first selection flag in response to the delayed input control signal The flag signal and the second selection flag signal, as well as the first selection flag signal and the second selection flag signal that are suitable for outputting the latch in response to the delayed output control signal, are used as inverted control signals. The semiconductor device according to claim 13, wherein, in the first burst sequence, the pipe latch unit outputs the second selection of the latch after the first selection flag signal of the latch is output as the inverted control signal The flag signal is used as an inverted control signal; and wherein, in the second burst sequence, the pipe latch unit outputs the first option of the latch after the second selected flag signal of the latch is output as the inverted control signal The flag signal is used as an inverted control signal. The semiconductor device according to claim 13, wherein the control signal output circuit further includes a control signal output unit adapted to synchronize the internal clock signal to generate the transmission control signal from the inverted control signal; and wherein, the transmission The control signal is output through the control pad. A semiconductor device includes: a first pipe latch unit adapted to sequentially latch a first input signal and a second input signal in response to an input control signal, and a first input signal adapted to output a latch in response to an output control signal And the second input signal of the latch is used as the pipeline latch data; the data storage unit is suitable for storing the second input signal in the first burst sequence as storage data, and is suitable for storing the first input in the second burst sequence The signal is used as stored data; a data comparator is suitable for comparing the first input signal with the stored data to generate a first comparison signal, and is suitable for comparing the second input signal with the first input signal to generate a second comparison signal, and Suitable for comparing the second input signal with stored data to generate a third comparison signal; The comparison signal selector is suitable for outputting the first comparison signal as the first comparison selection signal and the second comparison signal as the second comparison selection signal in the first burst sequence, and is suitable for outputting the first comparison signal in the second burst sequence Three comparison signals are used as the first comparison selection signal and the second comparison signal is output as the second comparison selection signal; and the control signal output circuit is suitable for detecting the logic bits of the bits included in the first comparison selection signal and the second comparison selection signal Standard to generate the first detection signal and the second detection signal, suitable for responding to the stored flag signal to generate the first flag signal and the second flag signal from the first detection signal and the second detection signal, and suitable for sequential output The first flag signal and the second flag signal are used as transmission control signals. The semiconductor device according to claim 16, wherein, in the first burst sequence, the first pipe latch unit outputs the latched first input signal as pipe latch data, and then outputs the latched second input signal The signal is output as the pipe latch data; and wherein, in the second burst sequence, the first pipe latch unit outputs the latched first input signal after the latched second input signal is output as the pipe latch data Output as pipeline latch data. The semiconductor device according to claim 16, further comprising: a phase controller adapted to determine the inversion of the pipe latch data in response to an inverted control signal to generate phase data; and a data output unit adapted to synchronize the internal clock The signal is used to generate output data from the phase data, where the output data is output through the data pad. The semiconductor device according to claim 16, wherein the control signal output circuit includes a bit detector adapted to detect the logical level of the bit included in the first comparison selection signal to generate The first detection signal and the logic level suitable for detecting the bits included in the second comparison selection signal to generate the second detection signal. The semiconductor device according to claim 16, wherein the control signal output circuit includes: a flag generator adapted to compare the first detection signal with the stored flag signal to generate the first flag signal, and adapted to A flag signal is compared with the second detection signal to generate the second flag signal; and the flag storage unit is adapted to store the second flag signal as the storage flag signal in response to the delayed storage control signal. The semiconductor device according to claim 16, wherein the control signal output circuit includes a selection flag generator, the selection flag generator being adapted to output the first flag signal as the first selection flag in the first burst sequence Signal and output the second flag signal as the second selection flag signal, and is suitable for outputting the second flag signal as the first selection flag signal and outputting the first flag signal as the second selection in the second burst sequence Flag signal. The semiconductor device according to claim 21, wherein the control signal output circuit further comprises a second pipe latch unit adapted to sequentially latch the first selection flag signal in response to the delayed input control signal And the second selection flag signal, and the first selection flag signal adapted to output the latch in response to the delayed output control signal and the second selection flag signal of the latch as the inverted control signal. The semiconductor device according to claim 22, wherein, in the first burst sequence, the second pipe latch unit outputs the latched first selection flag signal as the inverted control signal after the latched first selection flag signal is output 2. Select the flag signal as the inverted control signal; and Wherein, in the second burst sequence, the second pipe latch unit outputs the latched first selection flag signal as the inverted control signal after the latched second selection flag signal is output as the inverted control signal . The semiconductor device according to claim 22, wherein the control signal output circuit further includes a control signal output unit adapted to synchronize with the internal clock signal to generate the transmission control signal from the inverted control signal; and wherein, The transmission control signal is output through the control pad. A semiconductor device, comprising: a data output circuit, adapted to compare the first input signal with stored data in a first burst sequence in which a first input signal and a second input signal are sequentially output as output data to generate a first A comparison selection signal, and the second input signal is compared with the first input signal to generate a second comparison selection signal, and is suitable for the second group of output data when the second input signal and the first input signal are sequentially output In the sending sequence, the second input signal is compared with the stored data to generate the first comparison selection signal, and the second input signal is compared with the first input signal to generate the second comparison selection signal; bit detector, suitable for The logic level of the bit included in the first comparison selection signal is detected to generate the first detection signal, and the logic level suitable for detecting the bit included in the second comparison selection signal is used to generate the second detection signal; flag generation The device is suitable for comparing the first detection signal with the stored flag signal to generate the first flag signal, and is suitable for comparing the first flag signal with the second detection signal to generate the second flag signal; The flag storage unit is suitable for responding to the delayed storage control signal to store the second flag signal as the storage flag signal; the selected flag generator is suitable for outputting the first flag signal in the first burst sequence as the first choice Flag signal and output the second flag signal as the second selection flag signal, and is suitable for outputting the second flag signal as the first selection flag signal in the second burst sequence and outputting the first flag signal as the second selection flag signal Second selection flag signal; the first pipe latch unit is suitable for responding to the delayed input control signal to sequentially latch the first selection flag signal and the second selection flag signal, and for responding to the delayed output control signal to output the latch The first selection flag signal of the lock and the second selection flag signal of the latch are used as the inverted control signal; and the control signal output unit is suitable for synchronizing the internal clock signal to generate the transmission control signal from the inverted control signal, wherein, The transmission control signal is output through the control pad. The semiconductor device according to claim 25, wherein the data output circuit includes a data comparator adapted to compare the first input signal with the stored data to generate a first comparison signal, and is adapted to compare the second input signal Compare with the first input signal to generate a second comparison signal, and is suitable for comparing the second input signal with stored data to generate a third comparison signal. The semiconductor device according to claim 26, wherein the data output circuit further includes a comparison signal selector adapted to output the first comparison signal as the first comparison selection signal in the first burst sequence and output the first comparison signal The second comparison signal is used as the second comparison selection signal, and is suitable for outputting the third comparison signal as the first comparison selection signal and the second comparison signal as the second comparison selection signal in the second burst sequence. The semiconductor device according to claim 25, wherein the data output circuit includes a second pipe latch unit adapted to sequentially latch the first input signal and the second input signal in response to the input control signal , And suitable for outputting the first input signal of the latch in response to the output control signal and the second input signal of the latch as the pipe latch data. The semiconductor device according to claim 28, wherein the data output circuit further includes: a phase controller adapted to determine the inversion of the pipe latch data in response to the inversion control signal to generate phase data; and a data output unit, applicable The output data is generated from the phase data by synchronizing the internal clock signal, wherein the output data is output through the data pad. The semiconductor device according to claim 25, wherein, in the first burst sequence, the first pipe latch unit outputs the latched first selection flag signal as the inverted control signal. The second selection flag signal is used as the inverted control signal; and wherein, in the second burst sequence, the first pipe latch unit outputs the latch after the second selected flag signal of the latch is output as the inverted control signal The first selection flag signal is used as the inverted control signal.

Images