TWI704482B - Display apparatus - Google Patents

Abstract

A display apparatus includes scan lines, data lines, pixel structures, a driver and a circuit board. The pixel structures are electrically connected to the scan lines and the data lines. The driver is electrically connected to the data lines. The driver includes a die, a second pad and a conductive shielding layer. The die has an integrated circuit and a first pad electrically connected to the integrated circuit, wherein the first pad has a first ground potential. The second pad is spaced apart from the first pad and the integrated circuit. The conductive shielding layer is electrically connected to the second pad and shields the die. The circuit board is electrically connected to the driver, wherein the second pad and the conductive shielding layer of the driver have a second ground potential of the circuit board.

Description

Display device

The present invention relates to an electronic device, and more particularly to a display device.

According to the relative position of the sensor pad for touch and the display panel, the architecture of the touch display device can be divided into Out-cell, On-cell and In-cell . Generally speaking, in a touch display device with an out-cell architecture, the outer surface of the substrate on the display panel is plated with a backside ITO to shield the display panel. Noise interference. However, in a touch display device with an in-cell structure, the sensing pad for touch is also a common electrode for display. In order to detect the change of capacitance, the outer surface of the substrate on the display panel It is not possible to plate a layer of indium tin oxide on the back side, and how to shield the noise of the display panel is a challenge.

The invention provides a display device with good performance.

A display device of the present invention includes a first substrate, a plurality of scan lines, a plurality of data lines, a plurality of pixel structures, a second substrate, a display medium, a driving element and a circuit board. A plurality of scan lines and a plurality of data lines are arranged on the first substrate. The pixel structures are arranged on the first substrate and are electrically connected to the scan lines and the data lines. The second substrate is disposed opposite to the first substrate. The display medium is disposed between the first substrate and the second substrate. The driving element is electrically connected to a plurality of data lines. The driving element includes a die, a second pad and a conductive shielding layer. The die has an integrated circuit and a first pad electrically connected to the integrated circuit, wherein the first pad has a first ground potential. The second pad is separated from the first pad and the integrated circuit. The conductive shielding layer is electrically connected to the second pad and shields the integrated circuit of the die. The circuit board is electrically connected to the driving element, wherein the second pad and the conductive shielding layer of the driving element have the second ground potential of the circuit board.

In an embodiment of the present invention, the above-mentioned display device further includes a gate driving circuit electrically connected to the scan line, wherein the first pad of the die is electrically connected to the gate driving circuit.

In an embodiment of the present invention, the above-mentioned die further has through silicon vias, and the second pad is electrically connected to the conductive shielding layer through a conductive object disposed in the through silicon vias.

In an embodiment of the present invention, the above-mentioned driving element further includes a package body that covers the die, and has a package through hole located outside the die, wherein the second pad is electrically conductive through a conductive object disposed in the package through hole. Connect to the conductive shield.

In an embodiment of the present invention, the aforementioned conductive shielding layer includes a metal sub-layer disposed on the crystal grain and a metal oxide sub-layer disposed on the metal sub-layer.

In an embodiment of the present invention, the aforementioned conductive shielding layer includes a metal sub-layer disposed on the die and an insulating sub-layer disposed on the metal sub-layer.

Reference will now be made in detail to the exemplary embodiments of the present invention, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and descriptions to indicate the same or similar parts.

It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected" to another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connected" can refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that there are other elements between two elements.

As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by a person of ordinary skill in the art, taking into account the measurement in question and the The specific amount of measurement-related error (ie, the limitation of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the "about", "approximately" or "substantially" used herein can select a more acceptable range of deviation or standard deviation based on optical properties, etching properties, or other properties, instead of using one standard deviation for all properties .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of related technologies and the present invention, and will not be interpreted as idealized or excessive The formal meaning, unless explicitly defined as such in this article.

FIG. 1 is a schematic top view of a display device 10 according to an embodiment of the invention.

2 is a schematic cross-sectional view of a display device 10 according to an embodiment of the invention.

Figure 2 corresponds to the section line Ι-Ι' of Figure 1. FIG. 1 omits the illustration of the display medium 300 and the sealant 400 of FIG. 2.

1 and 2, the display device 10 includes a first substrate 110, a second substrate 200 disposed opposite to the first substrate 110, and a display medium 300 disposed between the first substrate 110 and the second substrate 200. In this embodiment, the display device 10 further includes a sealant 400, and the display medium 300 is disposed in the space enclosed by the first substrate 110, the second substrate 200, and the sealant 400.

For example, in this embodiment, the materials of the first substrate 110 and the second substrate 200 can be selected from glass, quartz, organic polymers, or opaque/reflective materials (such as wafers, ceramics, etc.), Or other applicable materials.

In this embodiment, the display medium 300 may be liquid crystal. However, the present invention is not limited to this. According to other embodiments, the display medium 300 may also be an organic light emitting diode layer (OLED), a micro light emitting diode (micro-LED), or a sub-millimeter light emitting diode (mini-LED). , Quantum dot, or other types of display media.

Please refer to FIG. 1, the display device 10 further includes a plurality of scan lines SL and a plurality of data lines DL, which are disposed on the first substrate 110. The scan line SL and the data line DL are arranged alternately. In other words, the extension direction of the data line DL is not parallel to the extension direction of the scan line SL. Preferably, the extension direction of the data line DL is perpendicular to the extension direction of the scan line SL, but the invention is not limited thereto. In addition, the scan line SL and the data line DL belong to different layers. Based on the consideration of conductivity, the scan line SL and the data line DL generally use metal materials. However, the present invention is not limited to this. According to other embodiments, the scan line SL and the data line DL may also use other conductive materials. For example: alloys, nitrides of metallic materials, oxides of metallic materials, oxynitrides of metallic materials, or stacked layers of metallic materials and other conductive materials.

The display device 10 further includes a plurality of pixel structures PX, which are disposed on the first substrate 110. The pixel structures PX are electrically connected to the scan lines SL and the data lines DL. For example, in this embodiment, each pixel structure PX may include a thin film transistor (not shown) and a pixel electrode (not shown), wherein the source of the thin film transistor is electrically connected to the corresponding In a data line DL, the gate of the thin film transistor is electrically connected to a corresponding scan line SL, and the drain of the thin film transistor is electrically connected to the pixel electrode.

The display device 10 further includes a gate driving circuit 120, which is electrically connected to a plurality of scan lines SL. For example, in this embodiment, the gate driving circuit 120 may be disposed on the first substrate 110, and the manufacturing process of the gate driving circuit 120 may be integrated with the manufacturing process of the pixel structure PX. That is to say, in this embodiment, the gate driver circuit 120 can optionally be an integrated gate driver-on-array (GOA). However, the present invention is not limited to this. According to other embodiments, the gate driving circuit 120 may also be a separately manufactured chip.

In this embodiment, the display device 10 further includes a common electrode layer 130. The common electrode layer 130 can be selectively disposed on the first substrate 110, but the invention is not limited to this. In a display time interval, the common electrode layer 130 and a plurality of pixel structures PX jointly drive the display medium 300 (shown in FIG. 2), thereby enabling the display device 10 to display images. In this embodiment, the common electrode layer 130 may include a plurality of electrodes 132; in the touch time interval, the plurality of electrodes 132 of the common electrode layer 130 may be used as sensing pads for touch, so that the display device 10 has touch Control function. In other words, the display device 10 of this embodiment may be a touch display device with an in-cell structure. However, the present invention is not limited to this. According to other embodiments, the display device 10 may also adopt an out-cell or on-cell architecture.

1 and 2, the display device 10 further includes a driving element 500. The driving element 500 includes a source driving circuit. The source driving circuit of the driving element 500 is electrically connected to a plurality of data lines DL.

In this embodiment, the display device 10 further includes a plurality of pads 141, 142, 143 disposed in the peripheral area of the first substrate 110, wherein the plurality of pads 141 are electrically connected to the plurality of data lines DL, and the plurality of The pad 142 is electrically connected to the gate driving circuit 120, and the plurality of pads 143 are used to electrically connect to the circuit board 600.

For example, in this embodiment, the driving element 500 may be bonded to the plurality of pads 141, 142, and 143 on the first substrate 110 by using a chip-on-glass bonding process (COG), and the circuit board 600 For example, it is a flexible printed circuit board (Flexible Printed Circuit, FPC). However, the present invention is not limited to this. In another embodiment, the driving element 500 may also be formed by a chip-on-film (COF) process and multiple pads 141, 142 on the first substrate 110. Electrical connection.

The display device 10 further includes a circuit board 600 which is electrically connected to the driving element 500. For example, in this embodiment, the circuit board 600 may be a flexible printed circuit (Flexible Printed Circuit; FPC), and the circuit board 600 may be electrically connected to the driver through the pad 143 provided on the first substrate 110 The second pad 520 of the component 500.

The driving element 500 includes a die 510. The die 510 includes an integrated circuit 513 and a first pad 515 electrically connected to the integrated circuit 513. In this embodiment, the first pad 515 of the die 510 can be electrically connected to the gate driving circuit 120 through the pad 142 provided on the first substrate 110, but the invention is not limited thereto.

For example, in this embodiment, the die 510 includes a semiconductor substrate 511, such as but not limited to: doped or undoped silicon. The semiconductor substrate 511 and/or the semiconductor substrate 511 can be formed with components 511a such as transistors, diodes, capacitors, resistors, etc., and the components 511a can be interconnected by the interconnection structure 512 of the die 510 In order to form the integrated circuit 513, the interconnection structure 512 may be formed by conductive patterns in one or more dielectric layers 514 on the semiconductor substrate 511, for example.

The driving element 500 further includes a second pad 520 and a conductive shielding layer 530. The second pad 520 is separated from the first pad 515 and the integrated circuit 513. The second pad 520 is structurally separated from the first pad 515 and the integrated circuit 513. In other words, the second pad 520 is electrically independent of the first pad 515 and the integrated circuit 513. The conductive shielding layer 530 is electrically connected to the second pad 520 and shields the integrated circuit 513 of the die 510.

For example, in this embodiment, the semiconductor substrate 511 of the die 510 may also have a through silicon via (TSV) 511b, and the second pad 520 may conduct electricity through a through silicon via 511b. The object 540 is electrically connected to the conductive shielding layer 530, but the invention is not limited to this.

It is worth noting that the first pad 515 electrically connected to the integrated circuit 513 has the first ground potential of the die 510, and the second pad 520 and the conductive shielding layer 530 have the second ground potential of the circuit board 600. Potential. In other words, the conductive shielding layer 530 and the integrated circuit 513 of the die 510 are not grounded in common. Thereby, the conductive shielding layer 530 can more effectively shield the noise interference generated by the integrated circuit 513.

For example, in this embodiment, the conductive shielding layer 530 may include a metal sublayer 531 disposed on the die 510 and a metal oxide sublayer 532 disposed on the metal sublayer 531; the metal oxide sublayer 532 can The metal sub-layer 531 is protected against degradation by environmental factors (such as water, oxygen, etc.); the material of the metal sub-layer 531 can be aluminum, copper or other metals; the material of the metal oxide sub-layer 532 can be indium tin oxide , Indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide or other suitable metal oxides; but the present invention is not limited thereto.

It must be noted here that the following embodiments use the element numbers and part of the content of the foregoing embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, refer to the foregoing embodiment, and the following embodiments will not be repeated.

3 is a schematic cross-sectional view of a display device 10A according to another embodiment of the invention. The display device 10A in FIG. 3 is similar to the aforementioned display device 10, please refer to the foregoing description for the same or similarities, and the differences between the two are described below.

In the embodiment of FIG. 3, the driving element 500A includes a package body 550 covering the die 510, and the package body 550 has a through package via (TPV) 551 located outside the die 510, wherein the second pad 520 It is electrically connected to the conductive shielding layer 530 through the conductive object 540 disposed in the package through hole 551.

In addition, in the embodiment of FIG. 3, the conductive shielding layer 530 may include a metal sub-layer 531 disposed on the die 510 and an insulating sub-layer 533 disposed on the metal sub-layer 531. The insulating sub-layer 533 can protect the metal sub-layer 531. Deteriorated by environmental factors (such as water, oxygen, etc.).

Furthermore, in the embodiment of FIG. 3, the driving element 500A may include a plurality of dies 510; that is, the conductive shielding layer 530 that is not in the same ground with the integrated circuit 513 of the die 510 may also be applied to the polycrystalline Packaged driving element 500A.

10.10A: Display device 110: first substrate 120: Gate drive circuit 130: common electrode layer 132: Electrode 141, 142, 143: pad 200: second substrate 300: display medium 400: frame glue 500, 500A, 500B: drive components 510: Die 511: Semiconductor substrate 511a: component 511b: Through silicon via 512: interconnect structure 513: Integrated Circuit 514: Dielectric layer 515: first pad 520: second pad 530: conductive shielding layer 531: Metal Sublayer 532: metal oxide sublayer 533: Insulator layer 540: Conductive object 550: package body 551: Package perforation 600: circuit board DL: Data line SL: scan line PX: Pixel structure Ι-Ι’: Cut line

FIG. 1 is a schematic top view of a display device 10 according to an embodiment of the invention. 2 is a schematic cross-sectional view of a display device 10 according to an embodiment of the invention. 3 is a schematic cross-sectional view of a display device 10A according to another embodiment of the invention.

10: Display device

110: first substrate

142, 143: pads

200: second substrate

300: display medium

400: frame glue

500: drive element

510: Die

511: Semiconductor substrate

511a: component

511b: Through silicon via

512: interconnect structure

513: Integrated Circuit

514: Dielectric layer

515: first pad

520: second pad

530: conductive shielding layer

531: Metal Sublayer

532: metal oxide sublayer

540: Conductive object

600: circuit board

I-I’: Sectional line

Claims (6)

A display device includes: A first substrate; Multiple scan lines and multiple data lines are arranged on the first substrate; A plurality of pixel structures are disposed on the first substrate and are electrically connected to the scan lines and the data lines; A second substrate disposed on the opposite side of the first substrate; A display medium disposed between the first substrate and the second substrate; A driving element is electrically connected to the data lines, wherein the driving element includes: A die having an integrated circuit and a first pad electrically connected to the integrated circuit, wherein the first pad has a first ground potential; A second pad, separated from the first pad and the integrated circuit; and A conductive shielding layer electrically connected to the second pad and shielding the integrated circuit of the die; and A circuit board is electrically connected to the driving element, wherein the second pad and the conductive shielding layer of the driving element have a second ground potential of the circuit board. The display device described in item 1 of the scope of patent application further includes: A gate driving circuit is electrically connected to the scan lines, wherein the first pad of the die is electrically connected to the gate driving circuit. As for the display device described in claim 1, wherein the die also has a through silicon through hole, and the second pad is electrically connected to the conductive shield through a conductive object disposed in the through silicon through hole Floor. According to the display device described in item 1 of the scope of patent application, the driving element further includes: A package body encapsulates the die, and has a package through hole located outside the die, wherein the second pad is electrically connected to the conductive shielding layer through a conductive object disposed in the package through hole. According to the display device described in item 1 of the scope of patent application, the conductive shielding layer includes: A metal sub-layer disposed on the die; and A metal oxide sub-layer is disposed on the metal sub-layer. According to the display device described in item 1 of the scope of patent application, the conductive shielding layer includes: A metal sub-layer disposed on the die; and An insulating sub-layer is arranged on the metal sub-layer.

Images