TWI703686B - Chip on film package structure - Google Patents

Abstract

A chip on film package structure includes a flexible film, at least two conductive parts, an insulator, at least two first upper leads, at least two lower leads and a chip. The flexible film has a first surface and a second surface opposite to each other, and at least one through hole located in a chip mounting area of the first surface. The second surface has a projection area which overlaps the chip mounting area. The conductive parts and the insulator are disposed in the through hole, and the conductive parts are separated from each other by the insulator to be electrically isolated. The first upper leads are disposed in the chip mounting area and are respectively connected the conductive parts. The lower leads extend outward from the projection area and are electrically connected to the first upper leads through the conductive parts respectively. The chip is disposed in the chip mounting area and includes at least two first bumps. The first bumps are bonded to the first upper leads.

Description

Thin film flip chip package structure

The present invention relates to a packaging structure, and more particularly to a thin-film-on-chip packaging structure.

The chip on film (COF) package structure is a common package type of the driver chip of the liquid crystal display. With the increase in the number of bumps on the wafer, the increase in the number of pins, and the shrinking of the pin pitch, the layout of bumps and pins is increasingly restricted. If the layout of bumps and pins is improper, bridging is likely to occur in the flip chip bonding process.

At present, the technology of double-sided circuit film has been proposed, which uses a one-to-one configuration to electrically connect the upper pins on the upper surface of the film and the lower pins on the lower surface of the film through a corresponding number of conductive through holes. Accordingly, the layout flexibility of bumps and pins can be improved. The above-mentioned one-to-one configuration requires a large number of conductive through holes, which requires a large area of the film, and still poses a certain degree of restriction on the pin layout, so high pin count, high bump count and The need for fine pitch still needs to be further improved and designed.

The invention provides a thin film flip chip packaging structure, which can improve the layout flexibility of bumps and pins.

The chip-on-film package structure of the present invention includes a flexible film, at least two conductive elements, an insulator, at least two first upper leads, at least two lower leads, and a chip. The flexible film has a first surface, a second surface opposite to the first surface, and at least one through hole penetrating the first surface and the second surface. The first surface has a wafer setting area, and the through hole is located in the wafer setting area. The second surface has a projection area overlapping with the wafer setting area. The two conductive parts are arranged in the through hole. The insulator is arranged in the through hole to separate the two conductive parts and electrically separate the two conductive parts. The two first upper pins are arranged in the chip setting area and are respectively connected to the two conductive elements. The two lower pins are arranged on the second surface, wherein the two lower pins extend outward from the projection area, and are respectively electrically connected to the two first upper pins through the two conductive members. The chip is arranged in the chip arrangement area, wherein the chip includes at least two first bumps, and the two first bumps are connected to the two first upper pins.

Based on the above, the film-on-chip package structure of the present invention adopts a one-to-many configuration, and electrically connects at least two first upper pins on the first surface of the flexible film through a conductive through hole to the flexible film. At least two lower leads on the second surface of the film. Furthermore, the conductive through hole of the present invention is composed of at least two conductive members that are electrically separated, so that at least two sets of first upper pins and lower pins can be electrically connected with one hole position, and make this The first upper pin and the lower pin of the two groups are electrically separated. Therefore, the film-on-chip package structure of the present invention can not only improve the layout flexibility of bumps and pins, but also meet the design requirements of high pin count, high bump count, and fine pitch, so that the transmission is less in a limited area. A number of conductive through holes are electrically connected to a larger number of first upper pins and lower pins.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

FIG. 1A is a schematic top view of a chip-on-film package structure according to an embodiment of the invention. FIG. 1B is a schematic bottom view of the chip-on-film package structure of FIG. 1A. FIG. 1C is an enlarged schematic diagram of area A in FIG. 1A. FIG. 1D is an enlarged schematic diagram of area B in FIG. 1B. Fig. 1E is a schematic cross-sectional view of Fig. 1C along the section line E-E'. FIG. 1F is an enlarged schematic diagram of area F in FIG. 1A. In order to clearly show the connection relationship between the chip 160 and the first upper pin 140, the chip 160 in FIG. 1A is presented in perspective drawing.

1A to 1F, in this embodiment, the film-on-chip package structure 100 includes a flexible film 110, at least two conductive elements 120, an insulator 130, at least two first upper leads 140, and at least two lower leads 150 and wafer 160. The flexible film 110 has a first surface 110a and a second surface 110b opposite to each other. Furthermore, the first surface 110a of the flexible film 110 is provided with a wafer setting area R1, and the area overlapping the wafer setting area R1 on the second surface 110b of the flexible film 110 is the projection area R2. The flexible film 110 is made of, for example, polyimide (PI), polyethylene terephthalate (PET), polyethersulfone (PES), polycarbonate (PC) or Other suitable flexible materials.

In this embodiment, at least two first upper pins 140 (schematically show a plurality of) are arranged in the wafer setting area R1 of the first surface 110a, and at least two lower pins 150 (schematically show a plurality of ) Is disposed on the second surface 110b and extends from the projection area R2 to the outside. The chip 160 is disposed in the chip setting area R1 and is electrically connected to the first upper pin 140. Furthermore, the chip 160 faces the first surface 110a with its active surface, and is bonded to the at least two first upper pins 140 through at least two first bumps 161 (schematically show multiple) on the active surface.

On the other hand, the flexible film 110 also includes at least one conductive through hole (schematically shows a plurality) penetrating through the first surface 110a and the second surface 110b, wherein the conductive through hole is designed in the chip placement area. At least two conductive elements 120 and an insulator 130 are provided in the through holes 111 in R1 that penetrates the first surface 110a and the second surface 110b, and the at least two conductive elements 120 are separated by the insulator 130 and are electrically separated and have no structure. Of physical contact. The at least two first upper pins 140 are respectively connected to the conductive element 120, and the at least two lower pins 150 are respectively electrically connected to the corresponding at least two first upper pins 140 through the conductive element 120. Further, one of the at least two first upper pins 140 is electrically connected to one of the at least two lower pins 150 through one of the at least two conductive members 120, and the other of the at least two first upper pins 140 penetrates The other of the at least two conductive members 120 is electrically connected to the other of the at least two lower pins 150.

Since the conductive through hole is composed of at least two conductive members 120 that are electrically separated, at least two sets of the first upper pin 140 and the lower pin 150 can be electrically connected with one hole, and the at least two sets The first upper pin 140 and the lower pin 150 are electrically separated. Therefore, the film-on-chip package structure 100 can not only improve the layout flexibility of bumps and pins, but also meet the design requirements of high pin count, high bump count, and fine pitch, so that a smaller number of The conductive through holes electrically connect more groups of the first upper pins 140 and the lower pins 150.

In an embodiment, the insulator 130 may divide the through hole 111 into holes O1, O2 separated from each other, one of the at least two conductive members 120 is disposed in the hole O1, and the other of the at least two conductive members 120 Set in the hole O2. On the other hand, the two opposite wall surfaces 131 of each insulator 130 respectively face and abut the inner wall surface of the through hole 111 to separate the at least two conductive members 120 reliably.

In an embodiment, each first upper pin 140 may further include an upper pad 141, an extension portion 142, and a first inner connecting end 143, and at least two first upper pins 140 may have a symmetrical configuration, but the present invention Not limited to this. In each of the first upper pins 140, the extension portion 142 is located between the first inner connecting end 143 and the upper pad 141 and connects the first inner connecting end 143 and the upper pad 141. The first bump 161 is engaged with the first inner connecting end 143 of the corresponding first upper pin 140.

Among the corresponding at least two first upper pins 140 and at least two lower pins 150, each of the first upper pins 140 is connected to the corresponding conductive member 120 through the corresponding upper pad 141. On the other hand, at least two first upper pins 140 are symmetrically disposed on opposite sides of the through hole 111, and at least two lower pins 150 are symmetrically disposed on opposite sides of the through hole 111. Furthermore, each lower pin 150 includes a lower pad 151, a lower pin extension 152, and a lower pin body portion 153. In each of the lower pins 150, the lower pin extension 152 is located on the lower pin body. The portion 153 and the lower pad 151 are connected to the lower pin body portion 153 and the lower pad 151. Each lower pin 150 is connected to the corresponding conductive element 120 through the corresponding lower pad 151.

In a first upper pin 140 and a lower pin 150 connected to the same conductive member 120, from the perspective of the orthographic projection position, the lower pin body 153 is partially aligned and overlaps the first inner connecting end 143, and the lower lead The leg extension portion 152 is aligned and overlapped with the corresponding extension portion 142, and the lower pad 151 is aligned and overlapped with the upper pad 141. This layout method can simplify the circuit planning on the flexible film 110 and improve the efficiency of manufacturing the circuit. It can also make the upper and lower stress distribution of the flexible film 110 more even, and reduce the problem of local sag or bending of the flexible film 110 due to uneven stress, which may lead to pin fracture. The lower pin 150 located on the second surface 110b can also provide support when the chip 160 is thermally and compressed with the first upper pin 140 located on the first surface 110a, so that the bumps and the pins are evenly joined by force to achieve Good electrical bonding quality.

In an embodiment, the chip-on-film package structure 100 may further include a plurality of second upper pins 170, wherein the plurality of second upper pins 170 extend outward from the chip placement area R1, and the plurality of second upper pins 170 The layout of the second upper pins 170 is different from the layout of the at least two first upper pins 140. On the other hand, the chip 160 may further include a plurality of second bumps 162 electrically connected to a plurality of second upper pins 170. Furthermore, the chip 160 is bonded to the second inner terminals 171 of the plurality of second upper pins 170 located in the chip setting region R1 through the plurality of second bumps 162 on the active surface.

In this embodiment, the extension direction of each lower pin 150 may be the same as the extension direction of each second upper pin 170. In addition, from the perspective of the orthographic projection position, a second upper lead 170 is provided between any two adjacent lower leads 150, or a lower lead 170 is provided between any two adjacent second upper leads 170. Feet 150, but the present invention is not limited thereto. In other embodiments, from the perspective of the orthographic projection position, the lower pin body portion 153 of each lower pin 150 is partially aligned and overlapped with the corresponding first inner connecting end 143, and the rest can be connected to a second upper The pins 170 overlap and extend outward together. With such a aligning and overlapping configuration, the upper and lower stress distribution of the flexible film 110 can be made more even, and the problem of local sag or bending of the flexible film 110 due to uneven stresses can be reduced, which may lead to pin fracture. The lower pin 150 located on the second surface 110b can also provide support when the chip 160 is thermally and compressed with the first upper pin 140 and the second upper pin 170 located on the first surface 110a, so that the bumps and the pins can be The force is evenly bonded to achieve good electrical bonding quality.

In this embodiment, the wafer setting region R1 has a first edge E1 and a second edge E2 opposite to each other, and the wafer 160 has a first side 160a and a second side 160b opposite to each other. The first side 160a is adjacent to the first edge E1, and the second side 160b is adjacent to the second edge E2. With regard to the relative positions of the at least two first protrusions 161 and the plurality of second protrusions 162, the plurality of second protrusions 162 are closer to the first side 160a than the at least two first protrusions 161 . Furthermore, the at least two first bumps 161 may be arranged on a first straight line parallel to the first side 160a, and the plurality of second bumps 162 may be arranged in parallel to the first side 160a. The second straight line segment is adjacent to the first side 160a, and the first straight line segment is farther from the first side 160a than the second straight line segment.

It should be noted that the at least two first bumps 161 are not limited to being arranged on the first straight section, and the plurality of second bumps 162 are not limited to being arranged on the second straight section. For example, the at least The two first bumps 161 and the plurality of second bumps 162 may be arranged on two different curved segments, arc segments or irregular line segments, for example, it is satisfied that the plurality of second bumps 162 are larger than the plurality of pairs. The arrangement of the first bump 161 close to the first side 160a does not depart from the scope of the present invention.

The manufacturing process of the circuit film in the chip-on-film package structure 100 of this embodiment may be the following steps. First, a flexible film 110 is provided. Next, a drilling procedure (for example, laser drilling) is performed on the flexible film 110 to form the through hole 111. Then, the insulator 130 is formed in the through hole 111 to partition the through hole 111 into two hole portions O1 and O2, and the two hole portions O1 and O2 are not connected. For example, the insulator 130 may be a dielectric material, an insulating adhesive material or a photoresist material, and is connected to the inner wall surface of the through hole 111, that is, the insulator 130 is not a part of the flexible film 110. Then, metal layers are formed on the first surface 110a and the second surface 110b of the flexible film 110 by electroplating, electroless plating, chemical vapor deposition, physical vapor deposition or other suitable processes, and the two surfaces are filled at the same time. The holes O1 and O2 form two electrically separated conductive members 120. After that, a part of the metal layer on the first surface 110a and the second surface 110b is removed by the photolithography technique to produce the patterned circuit as shown in FIGS. 1A to 1F. In other words, the two conductive members 120 in the through hole 111 and the upper pad 141 and the lower pad 151 in the patterned circuit can be an integral structure.

On the other hand, the insulator 130 has a first end surface 130a adjacent to the first surface 110a and a second end surface 130b adjacent to the second surface 110b. The first end surface 130a may extend beyond the first surface 110a and face the upper pad 141 away from the The outer surface of one surface 110a is flush or coplanar, and the second end surface 130b may extend beyond the second surface 110b and be flush or coplanar with the outer surface of the lower pad 151 facing away from the second surface 110b.

2 is a schematic cross-sectional view of a chip-on-film package structure according to another embodiment of the invention. Please refer to FIG. 2, the chip-on-film package structure 100a of this embodiment is similar to the chip-on-film package structure 100 of the above embodiment, but the difference lies in: the first end surface 130a of the insulator 130 and the flexible film 110 of this embodiment The first surface 110a of the flexible film 110 is coplanar, and the second end surface 130b is coplanar with the second surface 110b of the flexible film 110. In other words, the first end surface 130a of the insulator 130 is concave relative to the upper pad 141, and the second end surface 130b is concave relative to the lower pad 151.

3A is a schematic top view of a chip-on-film package structure according to another embodiment of the invention. 3B is a schematic bottom view of a chip on film package structure according to another embodiment of the invention. FIG. 3C is an enlarged schematic diagram of area C in FIG. 3A. FIG. 3D is an enlarged schematic diagram of area D in FIG. 3B.

3A to 3D, the thin film on chip package structure 100b of this embodiment is similar to the thin film on chip package structure 100 of the above embodiment, but the difference is that the insulator 130 of this embodiment can divide the through holes 111 into each other The hole O11, the hole O12, the hole O13, and the hole O14 are separated, and the conductive member 120 is formed in the hole O11, the hole O12, the hole O13, and the hole O14, respectively. Furthermore, because the conductive through holes are composed of four conductive members 120 that are electrically separated, at least four groups of the first upper pins 140 and the lower pins 150 can be electrically connected with one hole position. The four groups of first upper pins 140 and lower pins 150 are electrically separated. Therefore, the film-on-chip package structure 100b can not only improve the layout flexibility of bumps and pins, but also further meet the design requirements of high pin count, high bump count, and fine pitch, so that less penetration in a limited area A larger number of conductive through holes electrically connect more groups of the first upper pins 140 and the second lower pins 150.

Specifically, the first bump 161 is not particularly limited to be disposed between the first side 160a and the conductive member 120. For example, the first bump 161 may also be disposed between the second side 160b and the conductive member 120. Correspondingly, part of the first upper pin 140 must extend toward the second side 160b so as to engage with the first bump 161 between the second side 160b and the conductive element 120, thereby increasing the circuit layout的flexibility.

In summary, the film-on-chip package structure of the present invention adopts a one-to-many configuration, and electrically connects at least two first upper pins on the first surface of the flexible film through a conductive through hole with At least two lower leads on the second surface of the flexible film. Furthermore, the conductive through hole of the present invention is composed of at least two conductive members that are electrically separated, so that at least two sets of first upper pins and lower pins can be electrically connected with one hole position, and make this The first upper pin and the lower pin of the two groups are electrically separated. Therefore, the film-on-chip package structure of the present invention can not only improve the layout flexibility of bumps and pins, but also meet the design requirements of high pin count, high bump count, and fine pitch, so that the transmission is less in a limited area. A number of conductive through holes are electrically connected to a larger number of first upper pins and lower pins.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make slight changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100, 100a, 100b: Thin film flip chip package structure

110: Flexible film

110a: first surface

110b: second surface

111: Through hole

120: conductive parts

130: Insulator

130a: first end face

130b: second end face

131: Wall

140: The first upper pin

141: upper pad

142: Extension

143: first inner connection end

150: lower pin

151: Lower pad

152: Lower pin extension

153: Lower pin body

160: chip

160a: first side

160b: second side

161: The first bump

162: second bump

170: second upper pin

171: second inner connection end

E1: First edge

E2: second edge

A, B, F: area

O1, O2, O11, O12, O13, O14: Hole

R1: Chip setting area

R2: projection area

FIG. 1A is a schematic top view of a chip-on-film package structure according to an embodiment of the invention. FIG. 1B is a schematic bottom view of the chip-on-film package structure of FIG. 1A. FIG. 1C is an enlarged schematic diagram of area A in FIG. 1A. FIG. 1D is an enlarged schematic diagram of area B in FIG. 1B. Fig. 1E is a schematic cross-sectional view of Fig. 1C along the section line E-E'. FIG. 1F is an enlarged schematic diagram of area F in FIG. 1A. 2 is a schematic cross-sectional view of a chip-on-film package structure according to another embodiment of the invention. 3A is a schematic top view of a chip-on-film package structure according to another embodiment of the invention. 3B is a schematic bottom view of a chip on film package structure according to another embodiment of the present invention. FIG. 3C is an enlarged schematic diagram of area C in FIG. 3A. FIG. 3D is an enlarged schematic diagram of area D in FIG. 3B.

100: Thin film flip chip package structure

110: Flexible film

110a: first surface

110b: second surface

111: Through hole

120: conductive parts

130: Insulator

130a: first end face

130b: second end face

141: upper pad

151: Lower pad

Claims (10)

A chip-on-film packaging structure includes: a flexible film having a first surface, a second surface opposite to the first surface, and at least one through hole penetrating the first surface and the second surface, wherein the first surface It has a wafer setting area, and the through hole is located in the wafer setting area, the second surface has a projection area overlapping with the wafer setting area; at least two conductive elements are arranged in the through hole; an insulator is arranged in the In the through hole, to separate the at least two conductive parts and electrically separate the at least two conductive parts; at least two first upper pins are arranged in the chip setting area and are connected to the at least two conductive parts respectively; The lower pins are disposed on the second surface, wherein the at least two lower pins extend outward from the projection area, and are electrically connected to the at least two first upper pins through the at least two conductive members, respectively, wherein the at least two The first upper pin and the at least two lower pins correspond to the through holes; and the chip is arranged in the chip setting area, wherein the chip includes at least two first bumps, and the at least two first bumps are bonded to the At least two first upper pins. According to the first item of the scope of patent application, the chip-on-film package structure, wherein the insulator divides the through hole into at least two hole portions separated from each other, and the at least two conductive members are respectively disposed in the at least two hole portions. As described in the first item of the scope of patent application, each of the first upper pins includes a first inner terminal, an extension portion, and an upper pad, and each of the extensions The parts are connected to the corresponding first inner connecting end and the upper pad, each of the first inner connecting ends is connected to the corresponding first bump, and each of the upper pads is connected to the corresponding conductive element. In the chip-on-film package structure described in item 3 of the scope of the patent application, each of the upper pads and the corresponding conductive element are integrally formed. As described in item 3 of the scope of patent application, each of the lower leads includes a lower lead body, a lower lead extension, and a lower pad, and each lower lead extension is connected to the corresponding The lower pin body part is connected to the lower pad, and each of the lower pads is connected to the corresponding conductive element. As described in the fifth item of the scope of patent application, the thin film flip chip package structure, wherein each of the lower lead body part is locally aligned and overlapped with the corresponding first inner terminal, and each of the lower lead extension parts is aligned and overlapped with the corresponding The extension part of the, and each of the lower pads overlaps the corresponding upper pad. According to the chip-on-film package structure described in item 5 of the scope of patent application, each of the bottom pads and the corresponding conductive element are integrally formed. As claimed in claim 5, the chip-on-film package structure, wherein the insulator has a first end surface adjacent to the first surface and a second end surface adjacent to the second surface, the first end surface and the first surface or The upper pad is coplanar, and the second end surface is coplanar with the second surface or the lower pad. As described in the first item of the scope of patent application, the chip-on-film package structure further includes a plurality of second upper pins extending outward from the chip setting area, wherein each of the second upper pins is located in the chip setting area The chip further includes a plurality of second bumps, and the second bumps are joined to the second inbound ends. The chip-on-film package structure according to claim 9, wherein the chip arrangement area has opposite first and second edges, and the chip has opposite first and second sides, and the first One side is adjacent to the first edge, and the second side is adjacent to the second edge, the second upper leads extend outward from the chip placement area through the first edge, and the second protrusions The block is adjacent to the first side, and the first bumps are farther away from the first side than the second bumps.

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