JP2012015469A - Tape carrier for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a tape carrier for a semiconductor device in which bonding area of a bonded material to be connected with an outer lead and interconnections can be ensured stably even if the cumulative size of the outer lead of the tape carrier for the semiconductor device varies.SOLUTION: In a tape carrier for a semiconductor device having an insulating film, and interconnections containing inner leads and outer leads on the insulating film, at least a part of a plurality of outer leads 51 provided contiguously to each other is arranged to incline against parallel arrangement where the outer leads 51 are parallel with a plurality of interconnects 52 provided contiguously to a bonded material to which the outer leads 51 are connected.

Description

  The present invention relates to a tape carrier for a semiconductor device, and more particularly to a tape carrier for a semiconductor device suitable for a COF (Chip On Film) tape having a fine outer lead.

In a semiconductor device tape carrier on which a semiconductor device such as an IC chip is mounted, wiring such as inner leads and outer leads is formed on an insulating film made of polyimide or the like. For example, in the case of a COF tape that is one of tape carriers for semiconductor devices, bumps of an IC chip are connected to inner leads on an insulating film by flip chip bonding, and anisotropic conductive films are connected to outer leads. (ACF: Anisotropic Conductive Film) or the like is connected to the wiring (terminal portion) of a material to be joined such as a wiring board or a display panel.

  In recent years, as electronic devices such as display panels have become smaller, lighter, and more precise, wiring of inner leads, outer leads, etc. has become finer and multi-wired, and the cumulative pitch of terminal groups such as outer leads has increased. Management is important.

  As a countermeasure against accumulated pitch fluctuation, outer leads are extended radially with respect to the IC chip mounted on the film carrier, and pads of the printed wiring board are provided at positions corresponding to these outer leads, A structure for connecting a pad of a printed wiring board has been proposed (see, for example, Patent Document 1). In this connection structure, even when the outer lead and the pad of the printed wiring board are connected by thermocompression bonding with a bonding tool, the outer lead is not affected even if the film carrier (support ring) supporting the outer lead is thermally expanded uniformly. Is only moved (displaced) in the radial direction, it is described that the bonding between the outer lead and the pad of the printed wiring board is maintained.

JP 7-211742 A

  By the way, an insulating film made of polyimide or the like used for providing flexibility tends to expand and contract due to changes in environmental temperature and humidity during storage. In addition, the insulating film expands and contracts more than desired due to heating and moisture absorption during the manufacturing process. When the insulating film expands and contracts, especially when the cumulative dimensional tolerance of the outer leads is small, the position of the outer leads on the insulating film shifts and the predetermined pitch cannot be secured, and the material to be joined (display panel, wiring board, etc.) There is a risk of inconsistency with the position of the wiring.

  The positional mismatch between the outer lead and the wiring of the material to be joined due to the expansion and contraction of the insulating film will be described with reference to FIG.

As shown in FIG. 4, the outer lead 41 and the wiring (terminal portion) 42 of the material to be joined to which the outer lead 41 is connected are both rectangular, and the width of the rectangular outer lead 41 is the width of the wiring 42. Narrower. The long side of the rectangular outer lead 41 is parallel to the long side of the rectangular wiring 42, and the outer lead 41 is parallel to the wiring 42. The outer leads 41 and the wirings 42 are provided at the same pitch in the rectangular width direction (left and right direction in FIG. 4), and in the desired state as designed as shown in FIG. 41 and wiring 42 all overlap, and a normal junction is obtained. In FIG. 4, outer leads 41 are provided on the wirings 42, and the joint portions where the wirings 42 and the outer leads 41 are joined to each other are grayed out so that they can be easily seen visually. Has been given.

FIG. 4B shows a state in which the outer lead 41 on the insulating film is displaced from a desired wiring position (state shown in FIG. 4A) due to expansion and contraction of the insulating film of the tape carrier for semiconductor devices. In FIG.4 (b), it is in the state which the insulating film extended by heating, moisture absorption, etc.
When the insulating film is stretched, as shown in FIG. 4B, the outer lead 41 located at the center portion in the arrangement direction (in FIG. 4B, the third outer lead 41 from the left is normal and the wiring 42 is normal. The outer leads 41 on both sides of the central outer lead 41 expand to the left and right sides, the position of the outer lead 41 shifts, and the cumulative pitch dimension changes. As described above, when the accumulated pitch dimension of the outer lead 41 changes, the joint area (the gray area in FIG. 4) between the outer lead 41 and the wiring 42 also changes for each outer lead 41, and the accumulated pitch dimension changes. In the large outer lead 41 (the outer leads 41 at the left and right ends in FIG. 4), the bonding area with the wiring 42 is reduced. If the joint area between the wiring 42 and the outer lead 41 is significantly reduced, it will affect the transmission and reception of signals and power.

  In order to solve such problems, it is conceivable to form wiring by predicting expansion and contraction of the insulating film, but since the expansion and contraction size of the cumulative dimension varies depending on the layout and shape of the wiring, it is uniformly ruled. It is difficult.

  An object of the present invention is to provide a tape carrier for a semiconductor device that can stably secure a bonding area with a wiring of a material to be joined to which the outer lead is connected even if the cumulative dimension of the outer lead of the tape carrier for a semiconductor device fluctuates. It is to provide.

  A first aspect of the present invention is a tape carrier for a semiconductor device having an insulating film and a wiring including an inner lead and an outer lead on the insulating film, and a plurality of the outer leads provided adjacent to each other. At least a part of them is a tape carrier for a semiconductor device that is arranged to be inclined from a parallel arrangement that is parallel to a plurality of wirings that are provided adjacent to a material to be joined to which the outer lead is connected. .

  According to a second aspect of the present invention, in the tape carrier for a semiconductor device according to the first aspect, the outer leads disposed at an inclination are inclined at an angle of a maximum of 10 ° from a parallel arrangement of the material to be bonded to the wiring. Has been placed.

  According to a third aspect of the present invention, in the tape carrier for a semiconductor device according to the first or second aspect, a plurality of the outer leads arranged at an angle are arranged at a maximum of 10 ° from a parallel arrangement of the material to be joined to the wiring. Up to several different angles are arranged.

  According to a fourth aspect of the present invention, in the tape carrier for a semiconductor device according to any one of the first to third aspects, a plurality of the outer leads arranged at an inclination are arranged in parallel to the wiring of the material to be joined. The distribution of the angle inclined from the center is symmetrical with respect to the central part in the arrangement direction of the outer leads provided adjacent to each other, and the outer leads on both sides of the central part are symmetrical.

According to a fifth aspect of the present invention, in the tape carrier for a semiconductor device according to any one of the first to fourth aspects, at least some of the plurality of outer leads arranged at an inclination are arranged in parallel to each other. .

  ADVANTAGE OF THE INVENTION According to this invention, even if the accumulation dimension of the outer lead of the tape carrier for semiconductor devices fluctuates, the joining area with the wiring of the to-be-joined material to which an outer lead is connected can be ensured stably.

It is sectional drawing which shows one Embodiment of the tape carrier for semiconductor devices which concerns on this invention. It is sectional drawing which shows an example which used the tape carrier for semiconductor devices which concerns on one Embodiment of this invention for the display panel connection. It is process drawing which shows an example of the manufacturing process which manufactures the tape carrier for semiconductor devices which concerns on this invention. It is the schematic explaining the joining state of the outer lead of the conventional tape carrier for semiconductor devices, and the wiring of a to-be-joined material. It is the schematic explaining the joining state of the outer lead of the tape carrier for semiconductor devices which concerns on one Embodiment of this invention, and the wiring of a to-be-joined material. It is explanatory drawing explaining the change of the joint area by the outer dimension of the outer lead of the outer lead of the tape carrier for semiconductor devices of a comparative example, and the wiring of a to-be-joined material by the accumulation dimension fluctuation | variation. It is explanatory drawing explaining the change of the joint area by the outer dimension of the outer lead of the outer lead of the tape carrier for semiconductor devices which concerns on one Embodiment of this invention, and the wiring of a to-be-joined material.

  Hereinafter, embodiments of a tape carrier for a semiconductor device according to the present invention will be described with reference to the drawings.

FIG. 1 shows a cross-sectional view of a COF tape that is a tape carrier for a semiconductor device according to this embodiment.
As shown in FIG. 1, the COF tape 10 has wirings 2 formed on an insulating film 1 made of polyimide or the like. The surface portion of the wiring 2 is plated with tin 3 or the like. The surface of the wiring 2 is covered and protected by a solder resist 6 except for the inner lead 4 and the outer lead 5.

FIG. 2 shows an example using the COF tape 10 of FIG.
An IC driver chip 20 is mounted at the center of the COF tape 10, and a display panel 22 and a wiring board 23 are connected to the ends of the COF tape 10. The IC driver chip 20 is bonded to the inner leads 4 of the COF tape 10 via bumps 21 made of gold or the like formed on the IC driver chip 20. The wiring (terminal part) 24 of the display panel 22 and the wiring (terminal part) 25 of the wiring board 23 are respectively connected to the outer leads 5 of the COF tape 10 through an anisotropic conductive film (ACF) 26.
An electrical signal from the wiring 25 of the wiring board 23 is input to the outer lead 5 on the input side and transmitted to the IC driver chip 20 or the like through the wiring 2 of the COF tape 10, and an output signal from the IC driver chip 20 or the wiring board 23. An electric signal or the like input from is supplied to the display panel 22 via a wiring 24 connected to the outer lead 5 on the output side.

An example of the manufacturing process of the COF tape 10 will be described with reference to FIG.
First, a tape base material in which a conductor layer 31 such as a copper foil is formed on the insulating film 1 is prepared (FIG. 3A), and a photosensitive resist 32 is applied on the conductor layer 31 (FIG. 3B). )), The photosensitive resist 32 is exposed and baked in a desired pattern, and the photosensitive resist 32 is developed to form a resist pattern 33 (FIG. 3C). Subsequently, after etching the conductor layer 31 exposed without being masked by the resist pattern 33 (FIG. 3D), the resist 32 on the conductor layer 31 is removed to form the wiring 2 having a predetermined pattern ( FIG. 3 (e)). Further, after plating 3 such as tin on the surface of the wiring 2 (FIG. 3 (f)), a desired area on the wiring 2 (area excluding the inner lead and outer lead portions) is coated with the solder resist 6. Produced.

  The COF tape 10 is characterized by the arrangement of the outer leads 5 with respect to the materials to be joined to which the outer leads 5 are connected, for example, the wirings 24 and 25 provided on the display panel 22 and the wiring board 23. That is, the conventional outer lead 41 such as a COF tape has a parallel arrangement parallel to the wiring 42 of the material to be joined as shown in FIG. The arrangement is inclined from a parallel arrangement parallel to the wirings 24 and 25 on the material.

FIG. 5 shows an example of the arrangement of the outer leads 5.
As shown in FIG. 5, the outer lead 51 and the wiring (terminal portion) 52 of the material to be joined are both rectangular, and the width of the rectangular outer lead 51 is narrower than the width of the wiring 52 of the material to be joined. (The width of the outer lead 51 may be the same as or wider than the width of the wiring 52). The outer leads 51 and the wirings 52 are provided at the same pitch in the width direction of the wirings 52 (left and right direction in FIG. 5). The long sides of the rectangular outer leads 51 are inclined so as to incline from the parallel arrangement parallel to the long sides of the rectangular wiring 52. In the example of FIG. 5, all six outer leads 51 are provided to be inclined with respect to the corresponding wirings 52. Specifically, the angle formed between the long side of the rectangular outer lead 51 and the long side of the rectangular wiring 52 is θ1, θ2,..., Respectively, in the outer lead 51 from the left end to the right end in FIG. θ6> 0. The distribution of the angle inclined from the parallel arrangement of the outer leads 51 with respect to the wiring 52 is the central portion in the arrangement direction of the outer leads 51 (in FIG. 5, the third outer lead 51 and the fourth outer lead 51 counting from the left end). The outer leads 51 on both sides of the central portion have a symmetrical angular distribution. That is, the inclination angles θ1 to θ3 of the three outer leads 51 on the left side of the center portion gradually increase from the center side toward the left end (θ1>θ2> θ3), and the three outer leads 51 on the right side of the center portion. Are gradually increased from the center side toward the right end (θ6>θ5> θ4), and θ1 and θ6, θ2 and θ5, and θ3 and θ4 are almost the same angle.
In FIG. 5, the three outer leads 51 on the left are tilted in a state where they are rotated at respective angles in the clockwise direction from the parallel arrangement parallel to the wiring 52, and the three outer leads 51 on the right are Although it is tilted from a parallel arrangement parallel to 52 in a state of being rotated counterclockwise at respective angles, it may be an inclined arrangement in which all outer leads 51 are rotated in the same direction.

  FIG. 5A shows a desired state in which all the outer leads 51 are arranged as designed. The outer leads 51 are located at the center of the corresponding wirings 52 and are substantially the same as the outer leads 51. The entire surface overlaps with the wiring 52 and is in a normal bonded state. In FIG. 5, the vertical relationship between the outer lead 51 and the wiring 52 is that the outer lead 51 is on the wiring 52, and the wiring 52 and the outer lead 51 are overlapped and joined so as to be visually easy to understand. The joints to be made are painted in gray.

FIG. 5 (b) shows that the insulating film expands from the desired state of FIG. 5 (a) to the left and right sides centering on the central portion in the arrangement direction of the outer leads 51 by heating and moisture absorption of the insulating film. It shows the state when As the insulating film is stretched, the position of the outer leads 51 is shifted to the left and right sides around the center in the arrangement direction, and the cumulative pitch dimension of the outer leads 51 is changed. As described above, when the cumulative pitch dimension of the outer leads 51 changes, the bonding area between the outer leads 51 and the wiring 52 (the area of the gray portion in FIG. 5) decreases.

  If the change in the cumulative pitch dimension becomes large, there is a possibility that a bonding failure between the wiring 52 and the outer lead 51 may occur. In this embodiment, as shown in FIG. 5, the outer lead 51 is replaced with the wiring 52 to be bonded. On the other hand, since the angle is inclined from the parallel arrangement, the reduction in the bonding area with the wiring 52 can be suppressed even if the accumulated pitch dimension of the outer leads 51 changes. Therefore, in the COF tape of this embodiment, even if the accumulated dimensional tolerance of the outer leads is small, the bonding area with the wiring of the material to be bonded can be obtained stably. In addition, the tolerance of the cumulative dimensional tolerance of the outer leads to be joined to the wiring substrate or the display panel that is the material to be joined can be increased.

As described above, the outer lead is tilted from the parallel arrangement of the material to be joined and has an angle, but if this angle is excessively increased, the outer lead is electrically connected to the wiring adjacent to the corresponding wiring. Therefore, it is necessary to set the angle in consideration of the shrinkage rate of the insulating film and the manufacturing process. Specifically, the angle at which the outer lead is inclined from the parallel arrangement is preferably up to 10 °.
As shown in FIG. 5, when the plurality of outer leads are inclined at a plurality of different angles, the angle at which the outer lead is tilted is increased as the position of the outer lead is greatly displaced due to expansion and contraction of the insulating film. Is effective. On the other hand, the outer lead may be provided in parallel with the wiring of the material to be joined at a place where the positional deviation of the outer lead is small.
If the outer leads have an angle with respect to the wiring of the material to be joined, as shown in FIG. 5, the plurality of outer leads (or some of them) are not inclined without tilting the plurality of outer leads at a plurality of different angles. Outer leads) may be arranged parallel to each other.
Furthermore, the shape of the wiring of the outer lead and the material to be joined is not limited to the rectangular shape as shown in FIG. 5, and the width and pitch of the wiring of the outer lead and the material to be joined are not constant and change. You may let them.

(Other embodiments)
In the above embodiment, the COF tape has been described as the semiconductor device tape carrier. However, the semiconductor device tape carrier of the present invention is not limited to the COF tape, and the semiconductor chip is connected to the inner lead exposed in the device hole. It can also be applied to TCP (Tape Carrier Package) tape carriers.
In the above embodiment, all the wirings of the materials to be bonded are arranged in parallel to each other, and the outer leads of the COF tape (semiconductor device tape carrier) are inclined with respect to the wirings of the materials to be bonded. Instead of tilting, the wiring of the material to be joined may be tilted with respect to the outer lead. Alternatively, if the outer lead and the wiring of the material to be bonded are inclined from the parallel arrangement, one or both of the outer lead and the wiring of the material to be bonded may be inclined to form an angle. Further, the inclination angle of the outer lead of the COF tape may be changed depending on the shape of the outer lead or the wiring of the material to be joined.

  Next, an example of the present invention and a comparative example for comparison with this will be described.

(Comparative example)
FIG. 6 shows an arrangement relationship between the outer leads 61 of the semiconductor device tape carrier and the wiring 62 of the material to be joined in the comparative example.
As shown in FIG. 6, the outer lead 61 and the wiring 62 have a rectangular shape having the same width W and length L, and the outer lead 61 is arranged in parallel to the wiring 62. Further, the outer lead 61 and the wiring 62 are provided with the same pitch P and the total cumulative pitch dimension A. FIG. 6A shows an initial state in which all the outer leads 61 and the wirings 62 coincide with each other and overlap each other. FIG. 6B shows a center C in the arrangement direction of the outer leads 61 on both sides thereof. In this state, the outer film 61 on the insulating film is displaced toward the center C due to the shrinkage of the insulating film. In FIG. 6, the vertical relationship between the outer lead 61 and the wiring 62 is that the outer lead 61 is on the wiring 62, and the wiring 62 and the outer lead 61 are overlapped and joined so as to be visually easy to understand. (The same applies to the embodiment of FIG. 7, and the joint portion where the outer lead 71 and the wiring 72 are overlapped and joined is applied with gray.) )
For example, when W = 0.01 mm, length L = 0.1 mm, pitch P = 0.03 mm, and total cumulative pitch dimension A = 40 mm, the joint area between the outer lead 61 and the wiring 62 (the gray portion in the figure) 6A is reduced to 50% from the initial state of FIG. 6A because the total accumulated pitch dimension A of the outer leads 61 is reduced by 0.025% (the length is reduced by 10 μm), and one side of the center C is reduced. When 0.005 mm = 5 μm.

(Example)
FIG. 7 shows the positional relationship between the outer leads 71 of the semiconductor device tape carrier and the wiring 72 of the material to be joined in the embodiment.
As shown in FIG. 7, the wiring 72 has a rectangular shape with a width W and a length L, and is provided with a pitch P and a total cumulative pitch dimension A in the width W direction. The outer lead 71 has a parallelogram shape in which two opposing short sides of the wiring 72 having a rectangular shape are slid in the width direction in opposite directions from the original position by a displacement dimension D. On the other hand, the long side of the outer lead 71 is inclined at an angle θ. The outer leads 71 are also provided with the same pitch P as the wiring 72 and the total cumulative pitch dimension A.
FIG. 7A shows an initial state in which all the outer leads 71 are positioned at the central portions of the corresponding wirings 72. FIG. 7B shows the center C in the arrangement direction of the outer leads 71 as a center. The insulating films on both sides contract, and the outer film 71 on the insulating film is displaced toward the center C due to the contraction of the insulating film.
For example, when W = 0.01 mm, length L = 0.1 mm, pitch P = 0.03 mm, total cumulative pitch dimension A = 40 mm, and D = 0.005 mm, the joint area between the outer lead 71 and the wiring 72 is 7A decreases from the initial state of FIG. 7A to 50% when the total cumulative pitch dimension A of the outer leads 71 shrinks by 0.0065 mm = 6.3 μm on one side of the center C. That is, the insulating film on which the outer lead 71 is formed has a dimensional change of about 0.032%.
From the comparison between the above example and the comparative example, it can be seen that when the same cumulative pitch dimension is changed, the reduction ratio of the joint area is smaller in the inclined arrangement example than in the parallel arrangement comparative example.

DESCRIPTION OF SYMBOLS 1 Insulation film 2 Wiring 3 Plating 4 Inner lead 5 Outer lead 6 Solder resist 10 COF tape (tape carrier for semiconductor devices)
20 IC driver chip 21 Bump 22 Display panel (material to be joined)
23 Wiring board (material to be joined)
24, 25 Wiring 26 Anisotropic conductive films 41, 51, 61, 71 Outer leads 42, 52, 62, 72 Wiring (bonded material side)
A Total cumulative pitch dimension P Pitch W Width L Length D Deviation dimension

Claims (5)

A tape carrier for a semiconductor device having an insulating film and a wiring including an inner lead and an outer lead on the insulating film,
At least a part of the plurality of outer leads provided adjacent to each other is inclined from a parallel arrangement parallel to the plurality of wirings provided adjacent to the material to be joined to which the outer leads are connected. A tape carrier for a semiconductor device, wherein   2. The tape carrier for a semiconductor device according to claim 1, wherein the outer leads arranged to be inclined are arranged to be inclined at a maximum angle of 10 ° from a parallel arrangement of the material to be joined to the wiring. 3.   The plurality of outer leads arranged at an angle are arranged at an angle of a plurality of different angles from a parallel arrangement of the material to be joined to the wiring to a maximum of 10 °. The tape carrier for semiconductor devices as described in 2.   The distribution of the angle of the plurality of outer leads arranged at an inclination from the parallel arrangement of the material to be joined with respect to the wiring is centered symmetrically at the central portion in the arrangement direction of the outer leads provided adjacent to each other. The tape carrier for a semiconductor device according to claim 1, wherein the outer leads on both sides of the central portion have a symmetrical angular distribution.   5. The tape carrier for a semiconductor device according to claim 1, wherein at least a part of the plurality of outer leads arranged in an inclined manner are arranged in parallel to each other.