TWI702700B - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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TWI702700B
TWI702700B TW107120179A TW107120179A TWI702700B TW I702700 B TWI702700 B TW I702700B TW 107120179 A TW107120179 A TW 107120179A TW 107120179 A TW107120179 A TW 107120179A TW I702700 B TWI702700 B TW I702700B
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substrate
circuit substrate
microelectromechanical
bonding
manufacturing
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TW107120179A
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TW202002207A (en
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江家緯
方立志
范文正
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力成科技股份有限公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Abstract

A semiconductor device including a microelectromechanical systems (MEMS) transducer die, a cover plate, a plurality of stud bumps, and an encapsulation layer is provided. The MEMS transducer die has a MEMS transducer and a plurality of conductive pads on the same side. The cover plate has a recess and a plurality of through holes. The cover is bonded to the MEMS transducer die. The MEMS transducer is accommodated in the recess. The through holes are correspond to conductive pads. The stud bumps are disposed within the openings and are connected to the conductive pads. The encapsulation layer is filled into the opening and laterally encapsulates the stud bumps and exposes a portion of the stud bumps. A method of manufacturing a semiconductor device is also provided.

Description

半導體元件及其製造方法Semiconductor element and its manufacturing method

本發明是有關於一種半導體元件及其製造方法,且特別是有關於一種具有微機電傳感器的半導體元件及其製造方法。The present invention relates to a semiconductor element and a manufacturing method thereof, and in particular to a semiconductor element with a microelectromechanical sensor and a manufacturing method thereof.

近年來由於智慧型手機、平板電腦、互動遊戲機等電子商品開始採用微機電慣性感測元件(如加速度計與陀螺儀),微機電慣性感測元件的市場需求呈現快速地成長。在加速度計的製程技術與相關產品已相對成熟的情況下,量產時的良率已成為微機電慣性感測元件市場中,下一個重要的競爭因素。In recent years, as electronic products such as smart phones, tablet computers, and interactive game consoles have begun to use MEMS inertial sensing devices (such as accelerometers and gyroscopes), the market demand for MEMS inertial sensing devices has shown rapid growth. As the process technology and related products of accelerometers are relatively mature, the yield rate during mass production has become the next important competitive factor in the MEMS inertial sensing component market.

在微機電裝置的製作上,目前遭遇的問題之一是現有的微機電系統構件並不像晶圓級構件一樣有具有一致製程及/或量產規格。因此,如何進一步提升微機電裝置的生產能力(throughput)及良率(yield),實已成目前亟欲解決的課題。In the manufacture of microelectromechanical devices, one of the problems currently encountered is that the existing microelectromechanical system components do not have the same manufacturing process and/or mass production specifications as the wafer-level components. Therefore, how to further improve the throughput and yield of MEMS devices has become an urgent issue to be solved at present.

本發明提供一種半導體元件及其製造方法,其具有較佳的生產能力及良率。The present invention provides a semiconductor element and a manufacturing method thereof, which has better production capacity and yield.

本發明提供一種半導體元件,其包括微機電感測晶粒、蓋板、多個柱形凸塊以及封裝層。微機電感測晶粒具有位於同側的微機電傳感器及多個導電接墊。蓋板具有凹陷以及多個貫孔。蓋板接合於微機電感測晶粒。微機電傳感器容納於凹陷內。貫孔對應於導電接墊。柱形凸塊位於開口內且連接於導電接墊。封裝層填充於開口內並側向包封柱形凸塊,且暴露出部分的柱形凸塊。The invention provides a semiconductor element, which includes a microcomputer inductive sensing crystal grain, a cover plate, a plurality of columnar bumps and an encapsulation layer. The microcomputer inductance measurement die has a microelectromechanical sensor and a plurality of conductive pads on the same side. The cover plate has a recess and a plurality of through holes. The cover plate is connected to the microcomputer inductive sensing die. The microelectromechanical sensor is contained in the recess. The through hole corresponds to the conductive pad. The stud bump is located in the opening and connected to the conductive pad. The encapsulation layer fills the opening and encapsulates the stud bump laterally, and exposes part of the stud bump.

本發明提供一種半導體元件的製造方法。本方法包括至少以下步驟。提供基板。基板具有多個凹陷。提供微機電元件晶圓。微機電元件晶圓具有多個微機電傳感器以及對應於這些微機電傳感器的多個導電接墊。接合基板與微機電元件晶圓,且使微機電傳感器容納於對應的凹陷內。於基板上形成的暴露出這些導電接墊的多個貫孔。形成多條焊線於這些開口內。形成封裝材料層於基材上,以包封引線。移除部分的封裝材料層及部分的引線,以分別形成封裝層及多個柱形凸塊。The invention provides a method for manufacturing a semiconductor element. The method includes at least the following steps. Provide substrate. The substrate has a plurality of depressions. Provide MEMS wafers. The microelectromechanical device wafer has a plurality of microelectromechanical sensors and a plurality of conductive pads corresponding to the microelectromechanical sensors. The substrate and the micro-electro-mechanical device wafer are joined, and the micro-electro-mechanical sensor is accommodated in the corresponding recess. A plurality of through holes formed on the substrate exposing the conductive pads. A plurality of welding wires are formed in these openings. A packaging material layer is formed on the substrate to encapsulate the leads. Part of the packaging material layer and part of the leads are removed to form the packaging layer and a plurality of stud bumps respectively.

基於上述,半導體元件的製造方法是藉由類似於晶圓至晶圓接合或晶圓至玻璃接合的方式將微機電元件晶圓與基板相結合。並且,是藉由打線機以打線接合的方式所形成的柱形凸塊與微機電元件晶圓上的導電接墊連接。另外,在半導體元件中,封裝層側向包封柱形凸塊的側壁。因此,可以提升半導體元件及其製造方法的生產能力及良率,也可以降低生產成本。Based on the above, the manufacturing method of the semiconductor device is to combine the MEMS device wafer and the substrate in a manner similar to wafer-to-wafer bonding or wafer-to-glass bonding. In addition, the stud bumps formed by wire bonding by the wire bonding machine are connected to the conductive pads on the microelectromechanical device wafer. In addition, in the semiconductor element, the encapsulation layer laterally encapsulates the sidewall of the stud bump. Therefore, the production capacity and yield of the semiconductor device and its manufacturing method can be improved, and the production cost can also be reduced.

為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

圖1A至圖1G繪示依照本發明第一實施例的一種半導體元件的製造方法的部分剖面示意圖。在本實施例中,半導體元件100的製造方法包括以下步驟。請參照圖1A,提供基板110,其中基板110的接合面110a上例如可以藉由雷射雕刻、蝕刻或研磨的方式,以形成自接合面110a向基板110內部延伸的多個凹陷111。在一些實施例中,基板110可以為素玻璃基板(bare glass)、素晶圓(bare wafer)或其他適宜的基板,因此,縱使在形成凹陷111的過程中在基板110上造成裂紋、破損或其他影響良率的狀況,也不會大幅地提升製造成本。1A to 1G show schematic partial cross-sectional views of a method of manufacturing a semiconductor device according to a first embodiment of the present invention. In this embodiment, the manufacturing method of the semiconductor element 100 includes the following steps. 1A, a substrate 110 is provided. The bonding surface 110a of the substrate 110 may be laser engraved, etched or polished to form a plurality of recesses 111 extending from the bonding surface 110a to the inside of the substrate 110, for example. In some embodiments, the substrate 110 may be a bare glass, a bare wafer, or other suitable substrates. Therefore, even if cracks, breakages or damages are caused on the substrate 110 during the process of forming the recess 111 Other conditions that affect yield will not significantly increase manufacturing costs.

請參照圖1A,提供一微機電元件晶圓(MEMS device wafer)120。舉例而言,微機電元件晶圓120例如包括矽底材122,以及位於矽底材122上且以陣列方式排列的多個元件區121。微機電元件晶圓120的晶圓表面120a位於元件區121,且微機電元件晶圓120的晶圓背面120b相對於晶圓表面120a。各個元件區121上具有對應的微機電傳感器123(MEMS Transducer)。微機電傳感器123可以與元件區121電性耦合(electrically coupled),以適於使元件區121可以直接或間接地接收到微機電傳感器123感測到的電子訊號。舉例而言,微機電傳感器123可以包括加速度計(accelerometer)、陀螺儀(gyroscope)、壓力感測器(pressure sensor)、熱電堆(thermopile)或其他類似的電子感測器(sensor),及/或微光閘、微投影器、微顯示器或其他類似的電控光學致動器(actuator)。1A, a MEMS device wafer (MEMS device wafer) 120 is provided. For example, the MEMS device wafer 120 includes a silicon substrate 122 and a plurality of device regions 121 arranged on the silicon substrate 122 and arranged in an array. The wafer surface 120a of the microelectromechanical device wafer 120 is located in the device area 121, and the wafer back surface 120b of the microelectromechanical device wafer 120 is opposite to the wafer surface 120a. Each element area 121 has a corresponding microelectromechanical sensor 123 (MEMS Transducer). The MEMS sensor 123 may be electrically coupled with the element area 121 so as to be suitable for the element area 121 to directly or indirectly receive the electronic signals sensed by the MEMS sensor 123. For example, the microelectromechanical sensor 123 may include an accelerometer, a gyroscope, a pressure sensor, a thermopile, or other similar electronic sensors, and/ Or micro-shutter, micro-projector, micro-display or other similar electronically controlled optical actuator (actuator).

在本實施例中,微機電傳感器123位於元件區121的所對應的晶圓表面120a上,但本發明不限於此。在其他實施例中,微機電傳感器123也可以嵌入於元件區121內。In this embodiment, the microelectromechanical sensor 123 is located on the corresponding wafer surface 120a of the element area 121, but the invention is not limited to this. In other embodiments, the microelectromechanical sensor 123 may also be embedded in the element area 121.

另外,各個元件區121上具有對應的多個導電接墊124。導電接墊124可以與元件區121電性連接,以使其他的電子元件550可以藉由對應的導電接墊124以與元件區121傳遞電訊號。In addition, each device area 121 has a corresponding plurality of conductive pads 124. The conductive pads 124 can be electrically connected to the device area 121 so that other electronic components 550 can transmit electrical signals to the device area 121 through the corresponding conductive pads 124.

請同時參照圖1A與圖1B,以將基板110的接合面110a與微機電元件晶圓120的晶圓表面120a互相面對面的方式,接合基板110與微機電元件晶圓120,且使微機電傳感器123容納於對應的凹陷111內。舉例而言,可以依據基板110的種類,或是基板110的接合面110a及/或微機電元件晶圓120的晶圓表面120a上的膜層,而藉由陽極接合(anodic bonding)、熔融接合(fusion bonding)、金屬熱壓接合(metal thermal compression bonding)、共晶接合(eutectic bonding)、聚合物黏著接合(polymer adhesive bonding)或其他適宜的接合方式,以使基板110與微機電元件晶圓120相結合。也就是說,可以藉由類似於晶圓至晶圓接合(wafer to wafer bonding)或晶圓至玻璃接合(wafer to glass bonding)的方式將微機電元件晶圓120與基板110相結合,而可以降低製程上的變異,以提升生產的生產能力及良率。1A and 1B at the same time, the substrate 110 and the MEMS wafer 120 are joined in such a way that the bonding surface 110a of the substrate 110 and the wafer surface 120a of the MEMS wafer 120 face each other, and the MEMS sensor 123 is accommodated in the corresponding recess 111. For example, according to the type of substrate 110, or the bonding surface 110a of the substrate 110 and/or the film on the wafer surface 120a of the MEMS wafer 120, anodic bonding or fusion bonding (Fusion bonding), metal thermal compression bonding (metal thermal compression bonding), eutectic bonding, polymer adhesive bonding (polymer adhesive bonding) or other suitable bonding methods to make the substrate 110 and the MEMS device wafer 120 combined. That is to say, the MEMS device wafer 120 and the substrate 110 can be combined in a manner similar to wafer to wafer bonding or wafer to glass bonding. Reduce the variation in the manufacturing process to improve the production capacity and yield.

微機電傳感器123與基板110並不相互接觸且彼此之間具有適宜的間距,以降低基板110在微機電傳感器123運作時可能造成的影響。以本實施例為例,由於微機電傳感器123位於元件區121的所對應的晶圓表面120a上,因此可以使凹陷111的深度111a大於微機電傳感器123的高度123a,以降低微機電傳感器123與基板110彼此觸碰的可能。如此一來,對應於不同類型的微機電傳感器123,可以在凹陷111的深度111a上機動性地作出對應的調整,而可以提升生產的生產能力及良率。The MEMS sensor 123 and the substrate 110 are not in contact with each other and have an appropriate distance between each other, so as to reduce the possible influence of the substrate 110 when the MEMS sensor 123 is operating. Taking this embodiment as an example, since the microelectromechanical sensor 123 is located on the wafer surface 120a corresponding to the element area 121, the depth 111a of the recess 111 can be greater than the height 123a of the microelectromechanical sensor 123 to reduce the microelectromechanical sensor 123 and the substrate. 110 may touch each other. In this way, corresponding to different types of microelectromechanical sensors 123, corresponding adjustments can be made flexibly on the depth 111a of the recess 111, and the production capacity and yield can be improved.

接著,請參照圖1C,例如可以藉由鑽孔製程或蝕刻製程,以在基板110’上形成多個貫孔112,且各個貫孔112暴露出晶圓表面120a上對應的導電接墊124的至少一部分。Next, referring to FIG. 1C, a plurality of through holes 112 may be formed on the substrate 110' by a drilling process or an etching process, and each through hole 112 exposes the corresponding conductive pad 124 on the wafer surface 120a. At least part of it.

在本實施例中,更可以藉由研磨製程或拋光製程,以薄化基板110’的厚度。一般而言,可以先將基板110(繪示於圖1B)薄化後,再於薄化後的基板110’上形成多個貫孔112,以提升製程上的良率,但本發明不限於此。在其他可行的實施例中,也可以先於基板110上形成多個貫孔112,再將基板110薄化為基板110’。或是,若使用已薄化的基板110’(如:薄玻璃),則可以在已薄化的基板110’上形成凹陷111,並將基板110’與微機電元件晶圓120接合之後,再於基板110’上形成多個貫孔112。In this embodiment, the thickness of the substrate 110' can be thinned by a grinding process or a polishing process. Generally speaking, the substrate 110 (shown in FIG. 1B) may be thinned first, and then a plurality of through holes 112 may be formed on the thinned substrate 110' to improve the yield in the process, but the present invention is not limited to this. In other feasible embodiments, a plurality of through holes 112 may be formed on the substrate 110 first, and then the substrate 110 is thinned into the substrate 110'. Or, if a thinned substrate 110' (such as thin glass) is used, a recess 111 can be formed on the thinned substrate 110', and after the substrate 110' is bonded to the MEMS wafer 120, then A plurality of through holes 112 are formed on the substrate 110'.

在本實施例中,基板110’的不暴露出微機電元件晶圓120上的元件區121及矽底材122。以藉由蝕刻製程所形成的貫孔112為例,貫孔112是以導電接墊124作為蝕刻停止層(etching stop layer;ESL)。以藉由鑽孔製程所形成的貫孔112為例,可以藉由偵測導電接墊124對應的訊號(如:導電接墊124材質的原子訊號或硬度梯度),以判斷鑽孔的深度。在一些實施例中,導電接墊124可以是於元件區121的半導體製造過程中,藉由金屬化製程(metallization process)所形成的內連線(interconnection)的一部份。也就是說,導電接墊124暴露外的表面可以為晶圓表面120a的一部份。In this embodiment, the substrate 110' does not expose the device area 121 and the silicon substrate 122 on the MEMS device wafer 120. Taking the through hole 112 formed by the etching process as an example, the through hole 112 uses the conductive pad 124 as an etching stop layer (ESL). Taking the through hole 112 formed by the drilling process as an example, the depth of the drilling can be determined by detecting the signal corresponding to the conductive pad 124 (for example, the atomic signal or the hardness gradient of the conductive pad 124 material). In some embodiments, the conductive pad 124 may be a part of an interconnection formed by a metallization process in the semiconductor manufacturing process of the device region 121. In other words, the exposed surface of the conductive pad 124 may be a part of the wafer surface 120a.

接著,請參照圖1D,於基板110’的貫孔112內形成焊線130。焊線130例如可以藉由打線接合(wire bonding)方式與導電接墊124連接,但本發明不限於此。Next, referring to FIG. 1D, a bonding wire 130 is formed in the through hole 112 of the substrate 110'. The bonding wire 130 may be connected to the conductive pad 124 by wire bonding, for example, but the invention is not limited thereto.

在本實施例中,相鄰的微機電傳感器123之間的其中兩個導電接墊124可以藉由一條焊線130而彼此連接,以提升形成焊線130的步驟的生產能力,但本發明不限於此。In this embodiment, two of the conductive pads 124 between adjacent MEMS sensors 123 can be connected to each other by a bonding wire 130 to improve the production capacity of the step of forming the bonding wire 130, but the present invention does not Limited to this.

接著,參照圖1E,在形成多個焊線130之後,於基板110’相對於接合面110a的表面110b上形成封裝材料層140。封裝材料層140覆蓋於基材的表面110b上且填入基材的貫孔112內,以包封這些焊線130。在一些實施例中,封裝材料層140例如是藉由模塑製程(molding process)或其他適宜的方法將熔融的模塑化合物(molding compound)形成於基材上。然後,使熔融的模塑化合物冷卻並且固化。Next, referring to FIG. 1E, after forming a plurality of bonding wires 130, a packaging material layer 140 is formed on the surface 110b of the substrate 110' opposite to the bonding surface 110a. The packaging material layer 140 covers the surface 110 b of the substrate and fills the through holes 112 of the substrate to encapsulate the bonding wires 130. In some embodiments, the packaging material layer 140 is formed by forming a molten molding compound on the substrate by a molding process or other suitable methods. Then, the molten molding compound is cooled and solidified.

參照圖1F,在形成封裝材料層140(繪示於圖1E)之後,可以藉由裁切、研磨、蝕刻或其他適宜的方式,以將封裝材料層140的一部分及焊線130(繪示於圖1E)的一部分移除,而分別形成封裝層141及多個彼此分離的柱形凸塊(stud bump)131。如此一來,可以使柱形凸塊131的頂面131a大致上與封裝層141的封裝表面141a共平面(coplaner)。也就是說,於各個貫孔112內,柱形凸塊131的體積小於貫孔112的容積,封裝層141的體積小於貫孔112的容積,且柱形凸塊131的體積與封裝層141的體積的總合基本上相同於貫孔112的容積。1F, after the packaging material layer 140 (shown in FIG. 1E) is formed, a part of the packaging material layer 140 and the bonding wires 130 (shown in A part of FIG. 1E) is removed to form an encapsulation layer 141 and a plurality of stud bumps 131 separated from each other. In this way, the top surface 131 a of the stud bump 131 can be substantially coplaner with the packaging surface 141 a of the packaging layer 141. That is, in each through hole 112, the volume of the stud bump 131 is smaller than the volume of the through hole 112, the volume of the encapsulation layer 141 is smaller than the volume of the through hole 112, and the volume of the stud bump 131 is equal to that of the encapsulation layer 141. The total volume is substantially the same as the volume of the through hole 112.

在本實施例中,由於柱形凸塊131可以為藉由打線機以打線接合(wire bonding)的方式所形成。因此,相較於柱形凸塊131於頂面131a上的徑寬,柱形凸塊131與導電接墊124連接的連接端點131b的具有較大的寬度。並且,由於柱形凸塊131以及封裝層141位於貫孔112內,封裝層141側向包封柱形凸塊131的側壁131c且暴露出柱形凸塊131的頂面131a,以使柱形凸塊131的側壁131c不與基板110’直接接觸。因此,位於貫孔112內的封裝層141可以在基板110’與柱形凸塊131之間提供良好的緩衝,以降低在後續的製程中,因基板110’與微機電元件晶圓120的熱膨脹係數(coefficient of thermal expansion;CTE)不匹配,而造成柱形凸塊131與微機電元件晶圓120上的導電接墊124分離的可能。也因此,在基板110’材質上可以具有較多的選擇,而可以降低製造成本。In this embodiment, the stud bump 131 may be formed by wire bonding by a wire bonding machine. Therefore, compared to the diameter of the pillar bump 131 on the top surface 131a, the connection terminal 131b connecting the pillar bump 131 and the conductive pad 124 has a larger width. In addition, since the stud bump 131 and the encapsulation layer 141 are located in the through hole 112, the encapsulation layer 141 laterally encapsulates the sidewall 131c of the stud bump 131 and exposes the top surface 131a of the stud bump 131, so that the pillar shape The sidewall 131c of the bump 131 does not directly contact the substrate 110'. Therefore, the packaging layer 141 located in the through hole 112 can provide a good buffer between the substrate 110' and the stud bump 131, so as to reduce the thermal expansion of the substrate 110' and the MEMS wafer 120 in the subsequent manufacturing process. The coefficient of thermal expansion (CTE) is not matched, which may cause the stud bump 131 to be separated from the conductive pad 124 on the MEMS wafer 120. Therefore, there are more choices in the material of the substrate 110', and the manufacturing cost can be reduced.

經過上述製程後即可大致上完成本實施例的半導體元件100的製作。上述的半導體元件100包括微機電元件晶圓120、基板110’、多個柱形凸塊131以及封裝層141。微機電元件晶圓120包括矽底材122、多個元件區121、多個微機電傳感器123以及多個導電接墊124。元件區121位於矽底材122上且以陣列方式排列。微機電傳感器123對應於元件區121配置且與元件區121電性耦合。導電接墊124對應於元件區121配置且與元件區121電性連接。基板110’具有多個凹陷111以及多個貫孔112。微機電元件晶圓120上的微機電傳感器123位於基板110’的凹陷111內。基板110’的貫孔112對應於導電接墊124設置。After the above-mentioned manufacturing process, the fabrication of the semiconductor device 100 of this embodiment can be substantially completed. The aforementioned semiconductor device 100 includes a microelectromechanical device wafer 120, a substrate 110', a plurality of stud bumps 131, and an encapsulation layer 141. The microelectromechanical device wafer 120 includes a silicon substrate 122, a plurality of device regions 121, a plurality of microelectromechanical sensors 123, and a plurality of conductive pads 124. The device regions 121 are located on the silicon substrate 122 and arranged in an array. The microelectromechanical sensor 123 is configured corresponding to the element area 121 and is electrically coupled with the element area 121. The conductive pad 124 is configured corresponding to the device area 121 and is electrically connected to the device area 121. The substrate 110' has a plurality of recesses 111 and a plurality of through holes 112. The MEMS sensor 123 on the MEMS wafer 120 is located in the recess 111 of the substrate 110'. The through holes 112 of the substrate 110' are provided corresponding to the conductive pads 124.

在本實施例中,由於柱形凸塊131可以為藉由打線機以打線接合的方式所形成,且構成柱形凸塊131的銲線(繪示於圖1E)可以是在形成封裝層141之前已與導電接墊124電性連接。在一般的穿塑孔技術(through mold via;TMV)、矽穿孔技術(through silicon via;TSV)或玻璃穿孔技術(through glass via;TGV)中,通常在模塑化合物、矽基板或玻璃基板上形成通孔(through via),而後再以電鍍、沉積或其他將導電物質填充的類似方式形成導電通孔(conductive via)。但是,上述的製程所使用的機台較為昂貴且在製程上需消耗較多的電能。除此之外,上述的穿塑孔技術常會因通孔內所留下的膠渣(smear),而使導電通孔的導電性降低。因此,在一般的穿塑孔技術中常需要使用額外的去膠渣製程(desmear process)。由於本實施例構成柱形凸塊131的焊線130(繪示於圖1D或圖1E)可以是在形成封裝層141之前已與導電接墊124電性連接,因此可以具有較佳的導電性,且可以省略模塑化合物的移除製程以及後續的導電物質填充製程,而可以提升生產率。除此之外,相較於預先成型(preformed)的導電柱,藉由打線機以打線接合所形成的柱形凸塊131可以具有較低的生產成本,且可以具有較佳的細間距(fine pitch),因此在配置上可以具有較大的彈性。In this embodiment, the stud bumps 131 can be formed by wire bonding by a wire bonding machine, and the bonding wires (shown in FIG. 1E) forming the stud bumps 131 can be used to form the packaging layer 141 It has been electrically connected to the conductive pad 124 before. In general through mold via (TMV), through silicon via (TSV) or through glass via (TGV), it is usually on the molding compound, silicon substrate or glass substrate A through via is formed, and then a conductive via is formed by electroplating, deposition or other similar methods of filling a conductive material. However, the machine used in the above-mentioned manufacturing process is relatively expensive and consumes more power in the manufacturing process. In addition, the aforementioned through-hole technology often reduces the conductivity of the conductive via due to smear left in the via. Therefore, an additional desmear process is often required in general piercing technology. Since the bonding wires 130 (shown in FIG. 1D or FIG. 1E) forming the stud bumps 131 in this embodiment may be electrically connected to the conductive pads 124 before the packaging layer 141 is formed, they may have better conductivity And the removal process of the molding compound and the subsequent filling process of the conductive material can be omitted, and the productivity can be improved. In addition, compared with preformed conductive pillars, the pillar bumps 131 formed by wire bonding by a wire bonding machine can have a lower production cost, and can have a better fine pitch. pitch), so the configuration can have greater flexibility.

圖2繪示依照本發明第二實施例的一種半導體元件的部分製造方法的部分剖面示意圖。在本實施例中,半導體元件200的製造方法與前述實施例的半導體元件100的製造方法相似,其類似的構件以相同的標號表示,且具有類似的功能、材質或形成方式,並省略描述。具體而言,圖2A至圖2B所繪示的步驟可以是接續圖1F的步驟的半導體元件的製造方法的剖面示意圖。2 is a schematic partial cross-sectional view of a partial manufacturing method of a semiconductor device according to a second embodiment of the present invention. In this embodiment, the manufacturing method of the semiconductor device 200 is similar to the manufacturing method of the semiconductor device 100 of the previous embodiment, and similar components are denoted by the same reference numerals, and have similar functions, materials, or formation methods, and description is omitted. Specifically, the steps depicted in FIGS. 2A to 2B may be cross-sectional schematic diagrams of the semiconductor device manufacturing method following the steps of FIG. 1F.

請參照圖2A,在本實施例中,可以對如圖1F所示的半導體元件100進行單體化製程(singulation process),以單一化微機電傳感器123而構成多個如圖2B所示的半導體元件100。單體化製程例如包括以旋轉刀片或雷射光束進行切割,但本發明不限於此。Please refer to FIG. 2A. In this embodiment, the semiconductor device 100 shown in FIG. 1F may be subjected to a singulation process to singulate the microelectromechanical sensor 123 to form a plurality of semiconductor devices as shown in FIG. 2B. Component 100. The singulation process includes, for example, cutting with a rotating blade or a laser beam, but the invention is not limited thereto.

值得注意的是,在進行單體化製程之後,相似的元件符號將用於單體化後的元件。舉例而言,單體化後的微機電元件晶圓120可以為多個微機電感測晶粒220,而單體化後微機電元件晶圓120的矽底材122、多個元件區121、多個微機電傳感器123以及多個導電接墊124可以對應地為微機電感測晶粒220的矽底材122、元件區121、微機電傳感器123以及多個導電接墊124,微機電元件晶圓120的晶圓表面120a在單體化後構成微機電感測晶粒220的感測面220a,單體化後的基板110可以為蓋板210,而單體化後基板110的凹陷111及多個貫孔112可以對應地為蓋板210的凹陷111及多個貫孔112,單體化後的柱形凸塊131被稱為柱形凸塊131,單體化後的封裝層141被稱為封裝層141,諸如此類。其他單體化後的元件將依循上述相同的元件符號規則,於此不加以贅述。It is worth noting that after the singulation process, similar component symbols will be used for singulated components. For example, the singulated MEMS device wafer 120 can be a plurality of microcomputer inductive sensing die 220, and the singulated MEMS device wafer 120 has a silicon substrate 122, a plurality of device regions 121, The plurality of microelectromechanical sensors 123 and the plurality of conductive pads 124 can correspondingly be the silicon substrate 122, the element area 121, the microelectromechanical sensor 123, and the plurality of conductive pads 124 of the microcomputer inductive sensing die 220. The wafer surface 120a of the circle 120 is singulated to form the sensing surface 220a of the microcomputer inductive sensing die 220. The singulated substrate 110 may be the cover 210, and the singulated substrate 110 has the recess 111 and The plurality of through holes 112 may correspond to the recesses 111 of the cover 210 and the plurality of through holes 112. The singulated stud bumps 131 are called stud bumps 131, and the singulated encapsulation layer 141 is It is called an encapsulation layer 141, and so on. Other singulated components will follow the same component symbol rules described above, and will not be repeated here.

經過上述製程後即可大致上完成本實施例的半導體元件200的製作。上述的半導體元件200包括微機電感測晶粒220、蓋板210、多個柱形凸塊131以及封裝層141。微機電感測晶粒220包括矽底材122、元件區121、微機電傳感器123以及多個導電接墊124。元件區121、微機電傳感器123及導電接墊124位於矽底材122的同一側。微機電傳感器123與元件區121電性耦合。導電接墊124與元件區121電性連接,且導電接墊124凸出於感測面220a。蓋板210具有凹陷111以及多個貫孔112。微機電感測晶粒220上的微機電傳感器123位於蓋板210的凹陷111內,且微機電傳感器123的高度123a小於凹陷111的深度111a。蓋板210的貫孔112對應於導電接墊124設置。柱形凸塊131以及封裝層141位於貫孔112內,封裝層141側向包封柱形凸塊131的側壁131c且暴露出柱形凸塊131的頂面131a。After the above-mentioned manufacturing process, the fabrication of the semiconductor device 200 of this embodiment can be substantially completed. The aforementioned semiconductor device 200 includes a microcomputer inductive sensing die 220, a cover 210, a plurality of stud bumps 131 and a packaging layer 141. The microcomputer inductive sensing die 220 includes a silicon substrate 122, a component area 121, a microelectromechanical sensor 123, and a plurality of conductive pads 124. The element area 121, the microelectromechanical sensor 123 and the conductive pad 124 are located on the same side of the silicon substrate 122. The microelectromechanical sensor 123 is electrically coupled with the element area 121. The conductive pad 124 is electrically connected to the device region 121, and the conductive pad 124 protrudes from the sensing surface 220a. The cover 210 has a recess 111 and a plurality of through holes 112. The microelectromechanical sensor 123 on the microcomputer inductive sensing die 220 is located in the recess 111 of the cover 210, and the height 123a of the microelectromechanical sensor 123 is smaller than the depth 111a of the recess 111. The through hole 112 of the cover 210 is provided corresponding to the conductive pad 124. The stud bump 131 and the encapsulation layer 141 are located in the through hole 112. The encapsulation layer 141 laterally encapsulates the sidewall 131 c of the stud bump 131 and exposes the top surface 131 a of the stud bump 131.

圖3繪示依照本發明第三實施例的一種半導體元件的部分製造方法的部分剖面示意圖。具體而言,圖3所繪示的步驟可以是接續圖1C的步驟的一種半導體元件的製造方法的剖面示意圖。3 is a schematic partial cross-sectional view of a partial manufacturing method of a semiconductor device according to a third embodiment of the present invention. Specifically, the step shown in FIG. 3 may be a schematic cross-sectional view of a method for manufacturing a semiconductor device following the step of FIG. 1C.

請參考圖1D與圖3,本實施例的製作流程與上述實施例的製作流程的差異在於:各個貫孔112內的各條焊線330彼此分離,且各條焊線330與對應的一個導電接墊124電性連接。在此之後的製作流程大致與圖1E至圖1F相同或相似,以形成類似於圖1F所示的半導體元件,故不贅述。Please refer to FIGS. 1D and 3, the difference between the manufacturing process of this embodiment and the manufacturing process of the above-mentioned embodiment is that the bonding wires 330 in each through hole 112 are separated from each other, and each bonding wire 330 is conductively connected to a corresponding one. The pad 124 is electrically connected. The manufacturing process after this is roughly the same as or similar to that of FIGS. 1E to 1F to form a semiconductor device similar to that shown in FIG. 1F, so it will not be repeated.

圖4繪示依照本發明第四實施例的一種半導體元件100的部分製造方法的部分剖面示意圖。請參考圖1A與圖4,本實施例的製作流程與上述實施例的製作流程的差異在於:基板110與微機電元件晶圓120可以藉由黏著層450而彼此接合,且黏著層450具有多個對應於基板110的凹陷111的開口451。4 is a schematic partial cross-sectional view of a partial manufacturing method of a semiconductor device 100 according to a fourth embodiment of the present invention. 1A and 4, the difference between the manufacturing process of this embodiment and the manufacturing process of the foregoing embodiment is that the substrate 110 and the microelectromechanical device wafer 120 can be bonded to each other through the adhesive layer 450, and the adhesive layer 450 has many One opening 451 corresponding to the recess 111 of the substrate 110.

在此之後的製作流程大致與圖1B至圖1F相同或相似,以形成類似於圖1F所示的半導體元件,故不贅述。The manufacturing process after this is roughly the same as or similar to that of FIG. 1B to FIG. 1F to form a semiconductor device similar to that shown in FIG. 1F, so it will not be repeated.

圖5A至圖5B繪示依照本發明第五實施例的一種半導體元件的部分製造方法的部分剖面示意圖。在本實施例中,半導體元件500的製造方法與前述實施例的半導體元件100的製造方法相似,其類似的構件以相同的標號表示,且具有類似的功能、材質或形成方式,並省略描述。具體而言,圖5A至圖5B所繪示的步驟可以是接續圖2B的步驟的半導體元件的製造方法的剖面示意圖。5A to 5B are schematic partial cross-sectional views of a part of a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention. In this embodiment, the manufacturing method of the semiconductor element 500 is similar to the manufacturing method of the semiconductor element 100 of the previous embodiment, and similar components are denoted by the same reference numerals and have similar functions, materials or formation methods, and descriptions are omitted. Specifically, the steps depicted in FIGS. 5A to 5B may be cross-sectional schematic diagrams of the semiconductor device manufacturing method following the steps of FIG. 2B.

請參照圖5A,在本實施例中,半導體元件500的製造方法更包括提供一電子元件550。電子元件550包括線路基板551、晶片552、多個連接端子553以及多個導電端子554。晶片552以覆晶接合的方式電性連接於線路基板551。連接端子553電性連接於線路基板551,且連接端子553與晶片552位於線路基板551的相同側。導電端子554電性連接於線路基板551,且導電端子554與晶片552位於線路基板551的相對側。晶片552可以是晶粒(die)、封裝後晶片(packaged chip)、堆疊式的晶片封裝件(stacked chip package)或是特殊應用積體電路(Application-Specific Integrated Circuit;ASIC),但本發明不限於此。Please refer to FIG. 5A. In this embodiment, the method of manufacturing the semiconductor device 500 further includes providing an electronic device 550. The electronic component 550 includes a circuit substrate 551, a chip 552, a plurality of connection terminals 553, and a plurality of conductive terminals 554. The chip 552 is electrically connected to the circuit substrate 551 by flip chip bonding. The connecting terminal 553 is electrically connected to the circuit substrate 551, and the connecting terminal 553 and the chip 552 are located on the same side of the circuit substrate 551. The conductive terminal 554 is electrically connected to the circuit substrate 551, and the conductive terminal 554 and the chip 552 are located on the opposite side of the circuit substrate 551. The chip 552 may be a die, a packaged chip, a stacked chip package, or an Application-Specific Integrated Circuit (ASIC), but the invention does not Limited to this.

請繼續參照圖5A,將電子元件550與柱形凸塊131電性連接,以形成如圖5B所示的半導體元件500。舉例而言,可以藉由回焊製程(reflow process)以使電子元件550的連接端子553與柱形凸塊131的頂面131a相接合。Please continue to refer to FIG. 5A to electrically connect the electronic component 550 and the stud bump 131 to form the semiconductor component 500 as shown in FIG. 5B. For example, a reflow process may be used to connect the connecting terminal 553 of the electronic component 550 with the top surface 131 a of the stud bump 131.

經過上述製程後即可大致上完成本實施例的半導體元件100的製作。本實施例的半導體元件100與上述實施例的半導體元件100類似,差異在於:半導體元件100更包括電子元件550。電子元件550包括線路基板551、晶片552多個連接端子553以及多個導電端子554。蓋板210位於線路基板551與感測晶粒之間。晶片552以覆晶接合的方式電性連接於線路基板551,且晶片552配置於線路基板551與蓋板210之間。連接端子553位於線路基板551與柱形凸塊131之間,且連接端子553電性連接於線路基板551110與柱形凸塊131。導電端子554與晶片552位於線路基板551的相對側,且導電端子554電性連接於線路基板551。After the above-mentioned manufacturing process, the fabrication of the semiconductor device 100 of this embodiment can be substantially completed. The semiconductor element 100 of this embodiment is similar to the semiconductor element 100 of the above-mentioned embodiment, and the difference is that the semiconductor element 100 further includes an electronic element 550. The electronic component 550 includes a circuit substrate 551, a chip 552, a plurality of connection terminals 553, and a plurality of conductive terminals 554. The cover 210 is located between the circuit substrate 551 and the sensing die. The chip 552 is electrically connected to the circuit substrate 551 by flip-chip bonding, and the chip 552 is disposed between the circuit substrate 551 and the cover 210. The connection terminal 553 is located between the circuit substrate 551 and the stud bump 131, and the connection terminal 553 is electrically connected to the circuit substrate 551110 and the stud bump 131. The conductive terminals 554 and the chip 552 are located on opposite sides of the circuit substrate 551, and the conductive terminals 554 are electrically connected to the circuit substrate 551.

綜上所述,本發明的半導體元件的製造方法,是藉由類似於晶圓至晶圓接合或晶圓至玻璃接合的方式將微機電元件晶圓與基板相結合。並且,是藉由打線機以打線接合的方式所形成的柱形凸塊與微機電元件晶圓上的導電接墊連接。另外,在半導體元件中,封裝層側向包封柱形凸塊的側壁。因此,可以提升半導體元件及其製造方法的生產能力及良率,也可以降低生產成本。In summary, the manufacturing method of the semiconductor device of the present invention combines the wafer of the microelectromechanical device with the substrate in a manner similar to wafer-to-wafer bonding or wafer-to-glass bonding. In addition, the stud bumps formed by wire bonding by the wire bonding machine are connected to the conductive pads on the microelectromechanical device wafer. In addition, in the semiconductor element, the encapsulation layer laterally encapsulates the sidewall of the stud bump. Therefore, the production capacity and yield of the semiconductor device and its manufacturing method can be improved, and the production cost can also be reduced.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100、200、500‧‧‧半導體元件110、110'‧‧‧基板110a‧‧‧接合面111‧‧‧凹陷111a‧‧‧凹陷的深度110b‧‧‧表面112‧‧‧貫孔210‧‧‧蓋板120‧‧‧微機電元件晶圓121‧‧‧元件區122‧‧‧矽底材120a‧‧‧晶圓表面120b‧‧‧晶圓背面123‧‧‧微機電傳感器123a‧‧‧感測器的高度124‧‧‧導電接墊220‧‧‧微機電感測晶粒220a‧‧‧感測面130、330‧‧‧焊線131‧‧‧柱形凸塊131a‧‧‧頂面131b‧‧‧連接端點131c‧‧‧側壁140‧‧‧封裝材料層141‧‧‧封裝層141a‧‧‧封裝表面450‧‧‧黏著層451‧‧‧開口550‧‧‧電子元件551‧‧‧線路基板552‧‧‧晶片553‧‧‧連接端子554‧‧‧導電端子100、200、500‧‧‧Semiconductor element 110,110'‧‧‧Substrate 110a‧‧‧Joint surface 111‧‧‧Concavity 111a‧‧‧Concavity depth 110b‧‧‧Surface 112‧‧‧Through hole 210‧‧ ‧Cover plate 120‧‧‧Microelectromechanical component wafer 121‧‧‧Component area 122‧‧‧Silicon substrate 120a‧‧‧wafer surface 120b‧‧‧wafer back 123‧‧‧MEMS sensor 123a‧‧‧ The height of the sensor 124‧‧‧Conductive pad 220‧‧‧Microcomputer inductive sensing die 220a‧‧‧Sensing surface 130,330‧‧‧Wire bonding 131‧‧‧Cylinder bump 131a‧‧Top Surface 131b‧‧‧Connecting terminal 131c‧‧‧Sidewall 140‧‧‧Packaging material layer 141‧‧‧Packaging layer 141a‧‧Packing surface 450‧‧‧Adhesive layer 451‧‧‧ Opening 550‧‧‧Electronic component 551 ‧‧‧Circuit board 552‧‧‧Chip 553‧‧‧Connecting terminal 554‧‧‧Conductive terminal

圖1A至圖1F繪示依照本發明第一實施例的一種半導體元件的製造方法的部分剖面示意圖。 圖2A至圖2B繪示依照本發明第二實施例的一種半導體元件的部分製造方法的部分剖面示意圖。 圖3繪示依照本發明第三實施例的一種半導體元件的部分製造方法的部分剖面示意圖。 圖4繪示依照本發明第四實施例的一種半導體元件的部分製造方法的部分剖面示意圖。 圖5A至圖5B繪示依照本發明第五實施例的一種半導體元件的部分製造方法的部分剖面示意圖。1A to 1F are schematic partial cross-sectional views of a method of manufacturing a semiconductor device according to a first embodiment of the present invention. 2A to 2B are schematic partial cross-sectional views of a part of a method for manufacturing a semiconductor device according to a second embodiment of the present invention. 3 is a schematic partial cross-sectional view of a partial manufacturing method of a semiconductor device according to a third embodiment of the present invention. 4 is a schematic partial cross-sectional view of a part of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention. 5A to 5B are schematic partial cross-sectional views of a part of a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

200‧‧‧半導體元件 200‧‧‧Semiconductor components

111‧‧‧凹陷 111‧‧‧Sag

111a‧‧‧深度 111a‧‧‧depth

112‧‧‧貫孔 112‧‧‧Through hole

210‧‧‧蓋板 210‧‧‧Cover plate

121‧‧‧元件區 121‧‧‧Component area

122‧‧‧矽底材 122‧‧‧Silicon substrate

123‧‧‧微機電傳感器 123‧‧‧Microelectromechanical sensor

123a‧‧‧高度 123a‧‧‧Height

124‧‧‧導電接墊 124‧‧‧Conductive pad

220‧‧‧微機電感測晶粒 220‧‧‧Microcomputer inductance measuring die

220a‧‧‧感測面 220a‧‧‧Sensing surface

131‧‧‧柱形凸塊 131‧‧‧Cylinder bump

131a‧‧‧頂面 131a‧‧‧Top surface

131c‧‧‧側壁 131c‧‧‧ side wall

141‧‧‧封裝層 141‧‧‧Packaging layer

Claims (9)

一種半導體元件,包括:一微機電感測晶粒,具有位於同側的一微機電傳感器及多個導電接墊;一蓋板,具有一凹陷以及多個貫孔,其中該蓋板接合於該微機電感測晶粒,該微機電傳感器容納於該凹陷內,且該些貫孔對應於該些導電接墊;多個柱形凸塊,位於該些貫孔內且連接於該些導電接墊;一線路基板,其中該蓋板位於該線路基板與該感測晶粒之間;一晶片,以覆晶接合的方式電性連接於該線路基板,且該晶片配置於該線路基板與該蓋板之間;多個連接端子,位於該線路基板與該些柱形凸塊之間且電性連接於該線路基板與該些柱形凸塊;多個導電端子,與該晶片位於該線路基板的相對側且電性連接於該線路基板;以及一封裝層,填充於該些貫孔內並側向包封該些柱形凸塊,且暴露出部分的該些柱形凸塊。 A semiconductor element includes: a microcomputer inductive sensing die with a microelectromechanical sensor and a plurality of conductive pads on the same side; a cover plate with a recess and a plurality of through holes, wherein the cover plate is connected to the The microcomputer inductance detects the die, the microelectromechanical sensor is accommodated in the recess, and the through holes correspond to the conductive pads; a plurality of columnar bumps are located in the through holes and connected to the conductive contacts Pad; a circuit substrate, wherein the cover plate is located between the circuit substrate and the sensing die; a chip is electrically connected to the circuit substrate by flip chip bonding, and the chip is disposed on the circuit substrate and the Between the cover plates; a plurality of connecting terminals located between the circuit substrate and the stud bumps and electrically connected to the circuit substrate and the stud bumps; a plurality of conductive terminals and the chip located in the circuit The opposite side of the substrate is electrically connected to the circuit substrate; and an encapsulation layer is filled in the through holes and laterally encapsulates the stud bumps, and exposes part of the stud bumps. 如申請專利範圍第1項所述的半導體元件,其中該微機電傳感器的高度小於該凹陷的深度。 According to the semiconductor device described in claim 1, wherein the height of the microelectromechanical sensor is smaller than the depth of the recess. 如申請專利範圍第1項所述的半導體元件,更包括:一黏著層,位於該感測晶粒與該蓋板之間。 The semiconductor device described in item 1 of the scope of patent application further includes an adhesive layer located between the sensing die and the cover plate. 如申請專利範圍第1項所述的半導體元件,其中該些柱形凸塊遠離於該微機電感測晶粒的一端不與該蓋板直接接觸。 As for the semiconductor device described in item 1 of the scope of patent application, one end of the pillar-shaped bumps away from the microcomputer inductive sensing die does not directly contact the cover plate. 一種半導體元件的製造方法,包括:提供一基板,具有多個凹陷;提供一微機電元件晶圓,該微機電元件晶圓具有多個微機電傳感器以及對應於該些微機電傳感器的多個導電接墊;接合該基板與該微機電元件晶圓,且使該些微機電傳感器容納於對應的該些凹陷內;於該基板上形成的暴露出該些導電接墊的多個貫孔;形成多條焊線於該些貫孔內;形成一封裝材料層於該基材上,以包封該些焊線;以及移除部分的該封裝材料層及部分的該些焊線,以分別形成一封裝層及多個柱形凸塊。 A method for manufacturing a semiconductor element includes: providing a substrate with a plurality of recesses; providing a microelectromechanical element wafer having a plurality of microelectromechanical sensors and a plurality of conductive contacts corresponding to the microelectromechanical sensors Pad; bonding the substrate and the microelectromechanical device wafer, and the microelectromechanical sensors are accommodated in the corresponding recesses; a plurality of through holes formed on the substrate exposing the conductive pads; forming a plurality of Bonding wires in the through holes; forming a packaging material layer on the substrate to encapsulate the bonding wires; and removing part of the packaging material layer and part of the bonding wires to form a package respectively Layers and multiple stud bumps. 如申請專利範圍第5項所述的半導體元件的製造方法,更包括:進行單體化製程以單一化該些微機電傳感器。 As described in item 5 of the scope of patent application, the method for manufacturing a semiconductor device further includes: performing a singulation process to singulate the MEMS sensors. 如申請專利範圍第5項所述的半導體元件的製造方法,其中接合該基板與該元件晶圓的步驟包括:形成一黏著層於該基板上或該微機電元件晶圓上,以接合該基板與該微機電元件晶圓。 The method for manufacturing a semiconductor device according to claim 5, wherein the step of bonding the substrate and the device wafer includes: forming an adhesive layer on the substrate or the microelectromechanical device wafer to bond the substrate Wafer with the MEMS element. 如申請專利範圍第5項所述的半導體元件的製造方法,其中相鄰的該些微機電傳感器之間的部分該些導電接墊藉由該些焊線而彼此電性連接,且在移除部分的該些焊線之後,相鄰的該些感測器之間的部分該些導電接墊彼此電性分離。 According to the method for manufacturing a semiconductor device as described in claim 5, the conductive pads between the adjacent MEMS sensors are electrically connected to each other by the bonding wires, and the portions are removed After the wire bonding, the conductive pads between the adjacent sensors are electrically separated from each other. 如申請專利範圍第5項所述的半導體元件的製造方法,更包括:提供一電子元件,包括:一線路基板;一晶片,以覆晶接合的方式電性連接於該線路基板;多個連接端子,電性連接於該線路基板且與該晶片位於該線路基板的相同側;以及多個導電端子,電性連接於該線路基板且與該晶片位於該線路基板的相對側;以及接合該電子元件的該些連接端子與該些柱形凸塊,以使該晶片配置於該線路基板與該蓋板之間。 As described in item 5 of the scope of patent application, the method for manufacturing a semiconductor element further includes: providing an electronic element, including: a circuit substrate; a chip electrically connected to the circuit substrate by flip chip bonding; and multiple connections Terminals electrically connected to the circuit substrate and located on the same side of the circuit substrate as the chip; and a plurality of conductive terminals electrically connected to the circuit substrate and located on the opposite side of the circuit substrate from the chip; and bonding the electronics The connecting terminals and the stud bumps of the device enable the chip to be arranged between the circuit substrate and the cover plate.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201322433A (en) * 2011-11-23 2013-06-01 Tong Hsing Electronic Ind Ltd A structure of image sensor package and manufacturing method thereof
TW201719130A (en) * 2015-11-26 2017-06-01 李美燕 Micro feedback-chamber sensor and method of manufacturing such sensor
TW201806140A (en) * 2016-05-31 2018-02-16 半導體組件工業公司 Image sensor semiconductor packages and related methods

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201322433A (en) * 2011-11-23 2013-06-01 Tong Hsing Electronic Ind Ltd A structure of image sensor package and manufacturing method thereof
TW201719130A (en) * 2015-11-26 2017-06-01 李美燕 Micro feedback-chamber sensor and method of manufacturing such sensor
TW201806140A (en) * 2016-05-31 2018-02-16 半導體組件工業公司 Image sensor semiconductor packages and related methods

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