TWI701677B - Ssd device and related data writing method - Google Patents

Abstract

A solid-state drive (SSD) device includes: a solid-state drive containing a target block having multiple word lines and multiple bit lines; and a SSD controller circuit comprising: an access circuit; and a flash memory control circuit configured to operably control the access circuit to write a first data into one or more pages connected with a first word line in the target back using a first program scheme, and to operably control the access circuit to write a second data into one or more pages connected with a second word line in the target back using a second program scheme, so that the first data and the second data are stored in the target block at the same time.

Description

Solid state hard disk device and related data writing method

The present invention relates to a solid-state drive (solid-state drive, SSD), in particular to a solid-state drive device capable of flexibly adjusting a data programming mode (program scheme) and a related data writing method.

A solid-state drive device contains many flash memory blocks, and these blocks are usually divided into over provision blocks (OP blocks) and data blocks. The number of reserved space blocks affects the operating performance of the solid state drive device, and the number of data blocks affects the data storage capacity of the solid state drive device. When the number of unusable physical pages in any block exceeds a certain number, the control circuit of the traditional solid-state drive device will mark the block as a bad block and no longer use any of the blocks in the block. Physical pages to store data.

On the other hand, the control circuit of the conventional solid-state hard disk device sets the data programming mode of each block in the unit of the entire block. Therefore, if some physical pages of a block are defective and do not apply this data programming mode, data errors are prone to occur, or the block may be judged as a bad block by traditional control circuits. Performance, thereby reducing the available storage space of the solid state drive device.

Obviously, the control mechanism of the traditional solid-state drive device cannot fully utilize the storage capacity of the flash memory block, and it is also inflexible in the use of the flash memory block, so it is difficult to effectively improve the performance of the solid-state drive device. Operational efficiency.

In view of this, how to reduce or eliminate the deficiency of the above-mentioned traditional solid-state hard disk device is a problem to be solved.

This specification provides an embodiment of a solid state drive device, which includes: a plurality of memory blocks, wherein the plurality of memory blocks include a target block, and the target block includes a plurality of character lines and A plurality of bit lines; and a solid state drive control circuit, the solid state drive control circuit includes: an access circuit coupled to the plurality of memory blocks; and a memory control circuit coupled to the memory The fetching circuit is configured to perform the following operations: at a first time point, a first programming mode is determined according to the classification of a first character line in the target block recorded by a character line classification record, and the access is controlled The circuit writes a first data into one or more physical pages coupled to the first word line in the first programming mode; and at a second time point according to the word line classification record in the target area The classification of a second word line in the block determines a second programming mode, and controls the access circuit to use the second programming mode to write a second data into a second word line coupled to the second word line Or multiple physical pages, so that the first data and the second data exist in the target block at the same time; wherein, the character line classification record records the individual character line types of the plurality of character lines; wherein , The first programming mode and the second programming mode are different programming modes.

This specification also provides an embodiment of a data writing method for a solid state drive device. The solid state disk device includes a plurality of memory blocks and a solid state disk control circuit, the plurality of memory blocks include a target block, and the target block includes a plurality of character lines and a plurality of bits Line, the data writing method includes: at a first point in time, using the solid-state drive control circuit to determine a first character line classification in the target block according to a character line classification record Programming mode, and writing a first data into one or more physical pages coupled to the first word line in the first programming mode; and at a second time point, using the solid-state drive control circuit according to The classification of a second character line in the target block of the character line classification record determines a second programming mode, and a second data is written into the second character line in the second programming mode One or more physical pages that are coupled, wherein the first data and the second data exist in the target block at the same time; wherein, the character line classification record records individual characters of the plurality of character lines Line type; wherein, the first programming mode and the second programming mode are different programming modes.

One of the advantages of the above-mentioned embodiment is that the flash memory control circuit sets the data programming mode for different parts of the individual flash memory blocks in units of word lines, which can greatly improve the writing of data to the flash memory. The flexibility of data programming mode selection during block is conducive to making full use of the storage capacity of the flash memory block, which can effectively increase the storage space of the solid state drive device without increasing the number of flash memory blocks.

Another advantage of the above embodiment is that the flash memory control circuit uses different data programming modes for different types of character lines in the same block to write data, so the reliability of the data in the block can be improved.

Other advantages of the present invention will be explained in more detail with the following description and drawings.

The embodiments of the present invention will be described below in conjunction with related drawings. In the drawings, the same reference numerals indicate the same or similar elements or method flows.

FIG. 1 is a simplified functional block diagram of a solid state drive device 100 according to the first embodiment of the present invention. The solid-state drive device 100 includes a solid-state drive 110, a transmission interface 140, a non-volatile storage circuit 150, and a solid-state drive control circuit 160.

The solid state drive 110 includes a plurality of flash memory blocks, such as the exemplary blocks 112, 114, and 116 in FIG. 1. As shown in FIG. 1, each flash memory block contains multiple word lines and multiple bit lines. For example, block 112 includes exemplary word lines 121, 122, and 123, and exemplary bit lines 131, 132, and 133; block 114 includes exemplary word lines 124, 125, and 126, and exemplary bit lines 134, 135, and 136; block 116 includes exemplary word lines 127, 128, and 129, and exemplary bit lines 137, 138, and 139.

In each flash memory block, a storage cell is provided at the intersection of each character line and each bit line, which can be used to store data. Therefore, each flash memory block contains many storage units. In order to reduce the complexity of the drawing, these storage units are not shown in FIG. 1.

Blocks 112, 114, and 116 in the aforementioned solid state drive 110 can all use single-level cell (SLC) chips, multi-level cell (MLC) chips, and third-level storage cells ( Triple-level cell (TLC) chips, quad-level cell (QLC) chips, or higher-level storage cell chips.

The transmission interface 140 is configured to perform data communication with a host device (not shown in FIG. 1). In practice, the transmission interface 140 can be compatible with various Serial Advanced Technology Attachment (SATA) series transmission standards, peripheral component interconnect express (PCIe) series transmission standards, and/or general purpose Serial bus (Universal Serial Bus, USB) series transmission standard interface circuit to achieve.

The storage circuit 150 is used to store the classification results of all the character lines in the individual blocks of the solid state drive 110.

The solid state drive control circuit 160 includes an access circuit 162 and a flash memory control circuit 164. The access circuit 162 is coupled to the solid state drive 110. The flash memory control circuit 164 is coupled to the transmission interface 140 and the storage circuit 150, and is configured to access the solid state drive 110 through the access circuit 162. When data needs to be written to the solid state drive 110, the flash memory control circuit 164 can select a suitable block from the solid state drive 110, and determine the selection according to the classification result of the character lines stored in the storage circuit 150 The data programming method of the storage unit connected to the individual character line in the block.

In practice, the storage circuit 150 can be independently provided outside the solid state drive control circuit 160, or can be integrated into the solid state drive control circuit 160. For the convenience of description, FIG. 1 does not show other components and related connections and implementations of the solid-state drive device 100.

During the manufacturing or assembling process of the solid state drive 110, the manufacturer can perform various circuit characteristic tests on all flash memory blocks in the solid state drive 110 to determine the degree of defect of the main array of individual blocks And/or defect distribution. The manufacturer of the solid state drive 110 can study the circuit characteristics of the hardware quality, data read reliability, long-term data retention, and/or durability of different parts in each block based on the aforementioned test results, and based on the study results The different parts in the block are classified in units of character lines.

For example, in an embodiment in which the blocks in the solid state drive 110 are implemented with four-level storage cell chips, the manufacturer can classify the different character lines in each block into Q type, T type, M type, and S type. Four types of classes. S-type (S-type) means that most storage cells connected by the character line are only suitable for one-bit-per-cell (1bpc) programming mode (hereinafter referred to as 1bpc scheme) ) To write data. M-type (M-type) means that most of the storage cells connected by the character line can use the two-bit-per-cell (2bpc) mode (hereinafter referred to as the two-bit mode, 2bpc scheme). Write data, you can also use one bit mode to write data. T-type (T-type) represents that most of the storage cells connected by the character line can use the three-bit-per-cell (3bpc) mode (hereinafter referred to as the three-bit-per-cell, 3bpc scheme). To write data, you can also use two-bit mode or one-bit mode to write data. Q-type (Q-type) means that most of the storage cells connected by the character line can use a four-bit-per-cell (4bpc) mode (hereinafter referred to as the four-bit-per-cell, 4bpc scheme). To write data, you can also use three-bit mode, two-bit mode, or one-bit mode to write data.

The foregoing classification method to some extent means that the overall defect of the storage unit connected to the M-type character line is less than that of the S-type character line, and the overall defect of the storage unit connected to the T-type character line is less than the M-type character. The overall defect of the storage unit connected to the Q-type character line is less than that of the T-type character line. In other words, the overall circuit quality of the storage cells connected to the Q-type word lines is better than other types of word lines.

For another example, in an embodiment in which the blocks in the solid state drive 110 are implemented by a three-level storage cell chip, the manufacturer can distinguish the character lines in each block into the aforementioned T type, M type, and S type. Three types.

For another example, in an embodiment in which the blocks in the solid state drive 110 are implemented by multi-level storage cell chips, the manufacturer can distinguish the character lines in each block into the aforementioned two types, M type and S type.

It can be seen from the foregoing description that the one-bit mode can be applied to storage cells connected to type S character lines, type M character lines, type T character lines, or type Q character lines. The two-bit mode is only applicable to storage units connected to M-type character lines, T-type character lines, or Q-type character lines, but not to storage units connected to S-type character lines. The three-bit mode is only applicable to the storage cells connected to the T-type character line or the Q-type character line, but not to the storage cells connected to the M-type character line and the S-type character line. The four-bit mode is only applicable to storage units connected to type Q character lines, and not to storage units connected to type T character lines, type M character lines, and type S character lines.

Please note that the aforementioned terms such as Q, T, M, and S are just for the convenience of distinguishing different types. In practice, any suitable name, code, number, or index value can be used to express different characters Line type.

The manufacturer can pre-store the character line classification results in each block of the solid state drive 110 in the solid state drive device 100. For example, in this embodiment, the character line classification results in each block of the solid state drive 110 may be pre-recorded in the aforementioned storage circuit 150 in a suitable form as a character line classification record.

For example, FIG. 2 shows a simplified schematic diagram of the character line classification record 152 according to an embodiment of the present invention. The character line classification record 152 includes character line classification results of multiple blocks in the solid state drive 110. For example, the data items 210, 220, and 230 in the character line classification record 152 respectively represent the word-line types of the character lines 121, 122, and 123 in the block 112; the data item 240 , 250, and 260 respectively represent the character line types of the character lines 124, 125, and 126 in the block 114; and the data items 270, 280, and 290 represent the character lines 127, 128 in the block 116, respectively , And 129 character line type.

From the content of the data items 210 to 290 in the embodiment of FIG. 2, it can be known that the character line 121 in the block 112 belongs to the type S character line; the character lines 122 and 123 in the block 112, and the block 114 The character line 126 in block 114 belongs to the type M character line; the character line 124 in the block 114 belongs to the type T character line; the character line 125 in the block 114 and the character line 127 in the block 116, 128, and 129 are all Q-type character lines.

As can be seen from the foregoing classification of character lines, the storage cells connected to the Q-type character lines have the greatest flexibility in the selection of the data programming mode, followed by the T-type character lines and the M-type character lines again.

Therefore, when data needs to be written to the solid state drive 110, the flash memory control circuit 164 can select a suitable block from the solid state drive 110 and select the corresponding programming mode according to the content of the character line classification record 152 , To write data into one or more physical pages connected by individual character lines in the selected block.

The following will further describe how the solid state drive control circuit 160 accesses the solid state drive 110. For the convenience of description, it is assumed that the flash memory control circuit 164 selects the block 114 as the block to write data.

When the flash memory control circuit 164 wants to write a data D1 into the physical location corresponding to the word line 124 in the block 114 at a certain time point T1, the flash memory control circuit 164 can read the word from FIG. 2 The cell line classification record 152 searches for the classification of the character line 124, and finds that the character line 124 belongs to the T-type character line.

As mentioned above, the T-type represents that the storage unit connected to the word line can use three-bit mode, two-bit mode, or one-bit mode to write data. The flash memory control circuit 164 can select an appropriate programming mode according to the block management strategy adopted at the time, and control the access circuit 162 to use the selected programming mode to write data D1 into one or more entities connected to the word line 124 page.

For example, assuming that the current block management strategy is the capacity-take-priority approach, the access circuit 162 can use the three-bit mode to write the data D1.

For another example, assuming that the current block management strategy is a performance-take-priority approach, the access circuit 162 can use a bit mode to write the data D1.

For another example, assuming that the current block management strategy is a balance approach, the access circuit 162 can use a three-bit mode or a two-bit mode to write the data D1.

When the flash memory control circuit 164 wants to write another data D2 into the physical location corresponding to the word line 125 in the block 114 at another time point T2, the flash memory control circuit 164 can read from In the character line classification record 152, the classification of the character line 125 is queried, and it is learned that the character line 125 belongs to the Q-type character line.

As mentioned above, the storage unit connected to the Q type represents the word line can use four-bit mode, three-bit mode, two-bit mode, or one-bit mode to write data. The flash memory control circuit 164 can select an appropriate programming mode according to the current block management strategy, and control the access circuit 162 to use the selected programming mode to write data D2 into one or more physical pages connected to the word line 125 .

For example, assuming that the current block management strategy is the capacity priority mode, the access circuit 162 can use the four-bit mode to write the data D2.

For another example, assuming that the current block management strategy is the performance priority mode, the access circuit 162 can use the bit mode to write the data D2.

For another example, assuming that the current block management strategy is a balanced mode, the access circuit 162 can use a three-bit mode or a two-bit mode to write the data D2.

When the flash memory control circuit 164 needs to write another data D3 into the physical location corresponding to the word line 126 in the block 114 at another time point T3, the flash memory control circuit 164 can start from The character line classification record 152 searches for the classification of the character line 126 and knows that the character line 126 belongs to the M-type character line.

As mentioned above, the storage unit connected to the M type represents the word line can use the two-bit mode or the one-bit mode to write data. The flash memory control circuit 164 can select an appropriate programming mode according to the current block management strategy, and control the access circuit 162 to use the selected programming mode to write data D3 into one or more physical pages connected to the word line 126 .

For example, assuming that the current block management strategy is the capacity priority mode, the access circuit 162 can use the two-bit mode to write the data D3.

For another example, assuming that the current block management strategy is the performance priority mode, the access circuit 162 can use the bit mode to write the data D3.

For another example, assuming that the current block management strategy is a balanced mode, the access circuit 162 can use a two-bit mode to write the data D3.

It can be seen from the foregoing description that the solid-state drive control circuit 160 can adopt different data programming modes for different word lines in the same block 114 according to the circuit characteristics of different word lines. Therefore, the data programming mode of the storage cells connected to different word lines in the block 114 may be different at the same time.

For example, as shown in FIG. 3, in the case where the flash memory control circuit 164 uses the capacity priority mode to manage the solid state drive 110, the access circuit 162 may use the three-bit mode to write the data D1 into the characters at the time point T1. The one or more physical pages connected by the line 124 use the four-bit mode to write the data D2 into the one or more physical pages connected by the character line 125 at the time point T2, and the two-bit mode at the time point T3 The data D3 is written into one or more physical pages connected by the word line 126. In this way, the data D1 written in the three-bit mode, the data D2 written in the four-bit mode, and the data D3 written in the two-bit mode simultaneously exist in the block 114.

For other blocks in the solid state drive 110, the solid state drive control circuit 160 can select the data programming mode of the storage unit connected to the individual character line according to the content of the character line classification record 152.

As time passes, the flash memory control circuit 164 can erase the data stored in the block 114 at an appropriate time, so that the block 114 can be used to store other data.

In addition, during operation, the flash memory control circuit 164 can be based on the remaining storage space of the solid state drive 110, the data attributes of the data to be written, the requirements of the host device, the user's settings, or the current solid state drive The operating environment of the device 100 dynamically adjusts the block management mode.

For example, data that is frequently accessed can generally be called hot data, and data that is less frequently accessed is called cold data. After the block 114 is erased, if the flash memory control circuit 164 needs to write the new data D4, D5, and D6 belonging to the hot data into the word lines 124, 125, and 126 in the block 114, respectively The flash memory control circuit 164 can use the performance priority mode to access the block 114. In this case, as shown in FIG. 4, the flash memory control circuit 164 can control the access circuit 162 to write data D4 into one or more entities connected to the word line 124 in a bit mode at time T4. Page. At time T5, the data D5 is written into one or more physical pages connected to the word line 125 in a bit mode, and at time T6, the data D6 is written in the word line 126 in a bit mode. One or more physical pages connected. In this way, the data D4, D5, and D6 stored in the block 114 will have the same programming mode, that is, the one-bit mode.

For another example, after the block 114 is erased, if the master control device or the user requests the flash memory control circuit 164 to change the block management strategy to a balanced mode, and the flash memory control circuit 164 needs to change the new data D7, D8, and D9 are written into the physical positions corresponding to the word lines 124, 125, and 126 in the block 114, respectively, and the flash memory control circuit 164 can use the balanced mode to access the block 114. In this case, as shown in FIG. 5, the flash memory control circuit 164 can control the access circuit 162 at time T7 to write data D7 into one or more entities connected to the word line 124 in a three-bit mode. Page. At time T8, use the three-bit mode to write data D8 into one or more physical pages connected to the word line 125, and at time T9, use the two-bit mode to write data D9 into the word line 126. One or more physical pages connected. In this way, the data D7 and D8 written in the three-bit mode and the data D9 written in the two-bit mode are simultaneously present in the block 114.

As can be seen from the foregoing description, for the physical pages connected by the same word line in the block 114, the solid-state drive control circuit 160 can use different data programming modes to write data at different time points. For example, in the aforementioned embodiment, the data programming mode corresponding to the word line 124 in the block 114 is sometimes a three-bit mode and sometimes a one-bit mode; the data programming mode corresponding to the word line 125 is The mode is sometimes four-bit mode, sometimes one-bit mode, and sometimes three-bit mode; the data programming mode corresponding to character line 126 is sometimes two-bit mode, and sometimes one-bit mode Meta mode.

It can be seen from the foregoing description that the flash memory control circuit 164 sets the data programming mode of the related physical page in units of word lines, so that the data programming mode selection flexibility when writing data to the flash memory block can be greatly improved .

The aforementioned block usage method is conducive to making full use of the storage capacity of each flash memory block, and can effectively increase the solid state drive device without increasing the number of flash memory blocks in the solid state drive 110 100 storage space.

On the other hand, since the flash memory control circuit 164 adapts different data programming modes for different types of character lines in the same block to write data, it can improve the reliability of data in individual blocks.

As the number of times of data writing or erasing increases, the circuit defects of the storage units connected to individual word lines may increase, or the reliability of data may decrease. Therefore, the flash memory control circuit 164 can dynamically adjust the corresponding data items in the aforementioned character line classification record 152 according to the number of data writing or erasing times of the physical page connected to each character line during operation. Content. The flash memory control circuit 164 can also use various suitable test methods to test the reliability of the physical pages connected by each character line, and dynamically adjust the value of the corresponding data items in the aforementioned character line classification record 152 according to the test results. content.

For example, as shown in FIG. 6, when the flash memory control circuit 164 determines that most of the storage cells connected to the word line 123 in the block 112 become only suitable for writing data in a bit mode, the flash memory The control circuit 164 can modify the original data item 230 in the character line classification record 152 to the new data item 630, so that the type of the character line 123 is changed from the M type to the S type.

For another example, when the flash memory control circuit 164 determines that most of the storage cells connected to the word line 125 in the block 114 become only suitable for writing in three-bit mode, two-bit mode, or one-bit mode When the data is no longer suitable for writing data in the four-bit mode, the flash memory control circuit 164 can modify the original data item 250 in the character line classification record 152 into a new data item 650, so that the character line The type of 125 changed from Q type to T type.

As we all know, the traditional flash memory control circuit uses the same data programming mode for all physical pages in the entire block, but this approach does not take into account the possible differences in circuit characteristics of different parts of the block. Therefore, when the traditional flash memory control circuit uses a higher-level data programming mode to write data to a block, but some physical locations in the block cannot support the higher-level data programming mode due to circuit defects , It is easy to cause data errors, or increase the possibility that the block is judged as a bad block by the traditional flash memory control circuit. Once the possibility of a block being marked as a bad block increases, it will reduce the available storage space of the solid state drive.

Different from the traditional bad block management mechanism, as long as there are enough physical pages connected by character lines in any block of the solid state drive 110 to support the lower-level data programming mode, the fast speed in this embodiment The flash memory control circuit 164 uses the block according to the aforementioned method, and does not mark the block as a bad block. Only when all the character lines in a block or the physical pages connected by more than a predetermined number of character lines are not suitable for storing data, the flash memory control circuit 164 will mark the block as Bad block. In this way, the possibility of a block being judged as a bad block can be reduced, thereby increasing the available storage space in the solid state drive 110 and prolonging the service life of the solid state drive 110.

In some embodiments, the aforementioned flash memory control circuit 164 can also flexibly adjust the usage of individual blocks in the solid state drive 110. In practical applications, some blocks of the solid state drive 110 can be divided into over provision blocks (OP blocks) and other blocks can be divided into data blocks (data blocks). As mentioned above, the number of reserved space blocks will affect the operating performance of the solid state drive device 100, and the number of data blocks will affect the data storage capacity of the solid state drive device 100.

Therefore, during operation, the flash memory control circuit 164 can follow a predetermined management strategy, the remaining storage space of the solid state drive 110, the requirements of the master control device, the user's settings, or the current solid state drive device 100 The operating environment can flexibly adjust the usage of some blocks in the solid state drive 110.

For example, the flash memory control circuit 164 can set the block 114 to be used as a data block during a first period P1 when the solid state drive 110 is required to provide more data storage space, and the flash memory control circuit 164 In a second period P2 in which the access performance of the solid state drive 110 needs to be improved, the block 114 can be set as a reserved space block for use. In other words, some blocks in the solid state drive 110 (for example, the aforementioned block 114) can serve different purposes in different periods.

In this way, the adjustment flexibility of the block usage in the solid state drive 110 can be greatly improved, and the operation flexibility and use flexibility of the solid state drive device 100 can be effectively increased.

Please note that the aforementioned circuit structure in FIG. 1 is only an exemplary embodiment, and does not limit the actual implementation of the present invention.

For example, FIG. 7 is a simplified functional block diagram of the solid state drive device according to the second embodiment of the present invention. In the embodiment of FIG. 7, the aforementioned character line classification record 152 is stored in a certain block of the solid state drive 110, for example, the block 112.

In some embodiments, the aforementioned character line classification record 152 may also be divided into a plurality of sections and stored in different sections of the solid state drive 110 respectively.

In the specification and the scope of the patent application, certain words are used to refer to specific elements, and those skilled in the art may use different terms to refer to the same elements. This specification and the scope of the patent application do not use differences in names as a way of distinguishing elements, but use differences in functions of elements as a basis for distinction. The "include" mentioned in the specification and the scope of the patent application is an open term and should be interpreted as "include but not limited to". In addition, the term "coupled" herein includes any direct and indirect connection means. Therefore, if it is described in the text that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection, wireless transmission, optical transmission, or other signal connections, or through other elements or connections. The means is indirectly connected to the second element electrically or signally.

The description method of "and/or" used in the description includes one of the listed items or any combination of multiple items. In addition, unless otherwise specified in the specification, any term in the singular case also includes the meaning of the plural case.

The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention should fall within the scope of the present invention.

100: solid state drive device (SSD device)

110: Solid State Drive (SSD)

112, 114, 116: flash memory block

121～129: word line

131～139: bit line

140: Transmission interface (communication interface)

150: non-volatile storage circuit (non-volatile storage circuit)

152: word-line category record

160: solid state drive control circuit (SSD controller circuit)

162: access circuit

164: flash memory control circuit (flash memory control circuit)

210～290, 630, 650: data entry

FIG. 1 is a simplified functional block diagram of the solid state drive device according to the first embodiment of the present invention.

2 is a simplified schematic diagram of a character line classification record according to an embodiment of the present invention.

3 to 5 are simplified schematic diagrams of an embodiment of data writing methods for a flash memory block in a solid state drive device under different scenarios.

6 is a simplified schematic diagram of a character line classification record according to another embodiment of the present invention.

FIG. 7 is a simplified functional block diagram of the solid state disk device according to the second embodiment of the present invention.

100: solid state drive device

110: Solid State Drive

112, 114, 116: Flash memory block

121~129: character line

131~139: bit line

140: Transmission interface

150: Non-volatile storage circuit

152: Character line classification record

160: solid state drive control circuit

162: Access circuit

164: Flash memory control circuit

Claims (10)

A solid state drive device (100), including: A plurality of memory blocks (112, 114, 116), wherein the plurality of memory blocks (112, 114, 116) includes a target block (114), and the target block includes a plurality of characters Lines (124, 125, 126) and multiple bit lines (134, 135, 136); and A solid state drive control circuit (160), the solid state drive control circuit (160) includes: An access circuit (162) coupled to the plurality of memory blocks (112, 114, 116); and A memory control circuit (164), coupled to the access circuit (162), is configured to perform the following operations: At a first time point (T1), a first programming mode is determined according to the classification of a first character line (124) in the target block (114) of a character line classification record (152), and control The access circuit (162) writes a first data (D1) into one or more physical pages coupled to the first word line (124) in the first programming mode; and At a second time point (T2), a second programming mode is determined according to the classification of a second character line (125) in the target block (114) of the character line classification record (152), and control The access circuit (162) writes a second data (D2) into one or more physical pages coupled to the second word line (125) in the second programming mode, so that the first data ( D1) Exist in the target block (114) simultaneously with the second data (D2); Wherein, the character line classification record (152) records the individual character line types of the multiple character lines (124, 125, 126); Wherein, the first programming mode and the second programming mode are different programming modes. The solid state disk device (100) according to claim 1, wherein the character line classification record (152) is stored in a non-volatile storage circuit other than the plurality of memory blocks (112, 114, 116) (150) In. The solid state drive device (100) according to claim 1, wherein the character line classification record (152) is stored in at least one of the plurality of flash memory blocks (112, 114, 116). The solid state drive device (100) according to claim 1, wherein the first programming mode is one of a plurality of programming modes corresponding to the first character line type, and is also corresponding to the second character line type The second programming mode is one of the programming modes corresponding to the second word line type, but not one of the programming modes corresponding to the first word line type. The solid state disk device (100) according to claim 1, wherein the memory control circuit (164) is further configured to perform the following operations: At a third time point (T5), the access circuit (162) is controlled to write a third data (D5) into the second programming mode of the target block (114) in a programming mode different from the second programming mode. One or more physical pages to which the two-character line (125) is coupled. The solid state drive device (100) according to claim 1, wherein the flash memory control circuit (164) is further configured to set the target block (114) as a data in a first period (P1) Block use, and set the target block (114) as a reserved space block for use in a different second period (P2). A data writing method for a solid state hard disk device (100), the solid state hard disk device (100) includes a plurality of memory blocks (112, 114, 116) and a solid state disk control circuit (160), The plurality of memory blocks (112, 114, 116) include a target block (114), and the target block (114) includes a plurality of character lines (124, 125, 126) and a plurality of bits Line (134, 135, 136), the data writing method includes: At a first time point (T1), the solid state drive control circuit (160) is used to classify records (152) according to a character line of a first character line (124) in the target block (114) Classification to determine a first programming mode, and write a first data (D1) in the first programming mode to one or more physical pages coupled to the first word line (124); and At a second time point (T2), the solid-state drive control circuit (160) is used according to the character line classification record (152) of a second character line (125) in the target block (114) A second programming mode is determined by classification, and a second data (D2) is written into one or more physical pages coupled to the second word line (125) in the second programming mode, where the first A data (D1) and the second data (D2) exist in the target block (114) at the same time; Wherein, the character line classification record (152) records the individual character line types of the multiple character lines (124, 125, 126); Wherein, the first programming mode and the second programming mode are different programming modes. The data writing method according to claim 7, wherein the character line classification record (152) is stored in a non-volatile storage circuit (150) other than the plurality of memory blocks (112, 114, 116) Or at least one of the plurality of flash memory blocks (112, 114, 116). The data writing method according to claim 7, wherein the first programming mode is one of a plurality of programming modes corresponding to the first word line type, and is also a plurality of programming modes corresponding to the second word line type One of the programming modes. The second programming mode is one of the programming modes corresponding to the second word line type, but not one of the programming modes corresponding to the first word line type. The data writing method according to claim 7, wherein the solid-state drive control circuit (160) is further configured to set the target block (114) as a data block for use in the first period (P1), And in the second time period (P2), the target block (114) is set as a reserved space block for use.

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