TWI537955B - Flash memory controller - Google Patents

Description

Flash memory controller

The invention relates to a flash memory technology, in particular to a flash memory controller capable of improving the wear resistance and data reliability of a flash memory module.

Flash memory is widely used in many applications, such as solid-state disks (SSDs), memory cards, digital cameras, digital cameras, multimedia players, mobile phones, computers, and many other electronic devices.

Flash memory can use single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC) or higher-order storage units. to realise. Single-stage memory cells are more efficient at access speed and data reliability. Multi-level storage units, third-order storage units, and higher-order storage units can provide higher storage capacity at lower cost, but endurance and wear capacity are not as good as single-stage storage units. .

Due to the aforementioned characteristics, the conventional flash memory device is difficult to achieve both low-cost and high-capacity targets in terms of both wear resistance and data reliability.

In view of this, how to effectively improve the loss-resisting capability of the flash memory realized by the multi-level storage unit, the third-order storage unit or the higher-order storage unit and improve the data reliability is a problem to be solved in the industry.

This specification provides an embodiment of a flash memory controller for controlling one a flash memory module, wherein the flash memory module includes a read/write circuit, a first data block, and a second data block, the flash memory controller includes: a communication interface, Receiving a first data and a second data; and a processing circuit coupled to the communication interface and the flash memory module for determining the amount of data stored at the time of the flash memory module. Dynamically adjusting a mode in which data is written into the flash memory module; wherein, if the communication interface receives the first data, the amount of data stored in the flash memory module at that time is lower than a first threshold The processing circuit controls the read/write circuit to write the first data into the first data block in a bit mode per storage unit, and if the communication interface receives the second data, the flash memory When the amount of data stored in the body module is higher than the first threshold, the processing circuit controls the read/write circuit to write the second data into the second data block in a two-dimensional mode per storage unit.

The present disclosure provides another embodiment of a flash memory controller for controlling a flash memory module, wherein the flash memory module includes a read/write circuit, a first data block, and a first a data block, the flash memory controller includes: a communication interface for receiving a first data; and a processing circuit coupled to the communication interface and the flash memory module for Dynamically adjusting a mode for writing data into the flash memory module according to the amount of data stored in the flash memory module at the time; wherein the flash memory is received when the communication interface receives the first data The amount of data stored in the module is lower than a first threshold, and the processing circuit controls the read/write circuit to write the first data into the first data block in a bit pattern per storage unit, and the After processing the circuit, the read/write circuit controls the at least one data in the first data block to be written into a second data block by using the two-dimensional mode of each storage unit.

The present disclosure provides another embodiment of a flash memory controller for controlling a flash memory module, wherein the flash memory module includes a read/write circuit, a first data block, and a first a data block, the flash memory controller includes: a communication interface for receiving at least one first data; and a processing circuit coupled to the communication interface and the flash memory a memory module for controlling the read/write circuit to write data to the flash memory module; wherein, if the communication interface receives the first data, the amount of data in the flash memory module is low At a first threshold, the processing circuit controls the read/write circuit to set a programming threshold voltage of at least one of the first data blocks to a first voltage range to write the first data The first data block.

The present disclosure provides another embodiment of a flash memory controller for controlling a flash memory module, wherein the flash memory module includes a read/write circuit, a first data block, and a first a data block, the flash memory controller includes: a communication interface for receiving a first data; and a processing circuit coupled to the communication interface and the flash memory module; If the communication device receives the first data, the amount of data in the flash memory module is lower than a first threshold, and the processing circuit controls the read/write circuit to at least the first data block. a programming threshold voltage of a storage unit is set in a first voltage range to write the first data into the first data block, and the processing circuit then controls the read/write circuit to the second data block The programming threshold voltage of the at least one storage unit is set in a third voltage range to write at least one data in the first data block into the second data block, wherein the first voltage range is less than The third voltage .

One of the advantages of the above flash memory controller is that it can not only reduce the power consumption required when writing data into the data block, but also effectively improve the loss resistance of the memory unit of the flash memory module. Improve the reliability of the data stored in the flash memory module.

Another advantage of the above flash memory controller is that the processing circuit can directly specify the read threshold voltage used by the read/write circuit during the data reading operation, thereby speeding up the reading of the flash memory module.

Another advantage of the above flash memory controller is that it can realize flash memory modules not only with MLC chips, TLC chips, or even higher order chips, but also for low cost and high capacity targets. Effectively improve the durability, wear resistance, and data reliability of flash memory modules.

100‧‧‧Data Storage System

110‧‧‧Master control unit

120‧‧‧Flash Memory Controller

122‧‧‧Recording media

124‧‧‧Processing Circuit

126‧‧‧Communication interface

130‧‧‧Flash Memory Module

132‧‧‧Reading and writing circuit

134‧‧‧Information block

1 is a simplified functional block diagram of an embodiment of a data storage system of the present invention.

2 is a simplified flow chart of the first embodiment of the flash memory writing method of the present invention.

3 is a simplified schematic diagram of an embodiment of a programming threshold voltage of a memory cell in the data block of FIG.

4 is a simplified flow chart of a second embodiment of the flash memory writing method of the present invention.

FIG. 5 is a simplified flowchart of a third embodiment of the flash memory writing method of the present invention.

Embodiments of the present invention will be described below in conjunction with the associated drawings. In the figures, the same reference numerals are used to refer to the same or similar elements or process steps.

Certain terms are used throughout the description and following claims to refer to particular elements. Those of ordinary skill in the art should understand that the same elements may be referred to by different nouns. The scope of this specification and the subsequent patent application does not use the difference in name as the way to distinguish the components, but the difference in function of the components as the basis for differentiation. The word "contains" mentioned in the entire specification and subsequent claims is an open term and should be interpreted as "including but not limited to...". In addition, the term "coupled" is used herein to include any direct and indirect means of attachment. Therefore, if a first device is coupled to a second device, the first device can be directly connected to the second device (including a signal connection through electrical connection or wireless transmission, optical transmission, etc.), or Electrically or signally connected to the second device indirectly through other devices or connection means.

FIG. 1 is a simplified functional block diagram of a data storage system 100 according to an embodiment of the present invention. The data storage system 100 includes a main control device 110, a flash memory controller 120, and a flash memory module 130. The main control device 110 accesses the flash memory module 130 through the flash memory controller 120. The main control device 110 can be a computer, a card reader, a digital camera, a digital camera, a mobile phone, a GPS positioning device, or any other electronic device that can use the flash memory module 130 as a storage medium. The flash memory controller 120 includes a recording medium 122, processing circuitry 124, and a communication interface 126. The communication interface 126 is coupled to the main control device 110 to enable the processing circuit 124 and the main control device 110 to transmit data through the communication interface 126.

The flash memory module 130 includes a read/write circuit 132 and a plurality of data blocks 134. In one embodiment, these data blocks 134 are implemented in one or more third-order storage unit (TLC) wafers to provide a lower cost, high storage capacity. The flash memory controller 120 and the flash memory module 130 can be integrated together into a single memory device, such as a solid state drive (SSD) or a memory card. The operation of the present invention for writing data to the flash memory module 130 will be further described below in conjunction with FIGS. 2 and 3.

2 is a simplified flow chart 200 of a first embodiment of a flash memory writing method of the present invention. 3 is a simplified schematic diagram 300 of an embodiment of a program threshold voltage for a memory cell in data block 134.

In the process 210, the flash memory controller 120 receives the data to be written from the master device 110 through the communication interface 126.

Then, the processing circuit 124 of the flash memory controller 120 determines the range of the programming threshold voltage of the target data block to be written according to the amount of data stored in the flash memory module 130 at that time.

For example, in the embodiment of FIG. 2, the processing circuit 124 performs a process 220 to determine whether the amount of data stored in the flash memory module 130 is higher than a first threshold TH1. If the amount of data of the flash memory module 130 at that time is lower than the first threshold TH1, the processing circuit 124 performs the process 230; otherwise, the process 240 is performed.

In the process 240, the processing circuit 124 further determines whether the amount of data stored by the flash memory module 130 at that time is higher than a second threshold TH2, where TH2 is greater than TH1. If the amount of data stored by the flash memory module 130 at that time is between the first threshold TH1 and the second threshold TH2, the processing circuit 124 proceeds to flow 250. If the amount of data that has been stored by the flash memory module 130 at that time is higher than the second threshold TH2, the processing circuit 124 proceeds to flow 260.

In practice, the aforementioned first threshold TH1 and second threshold TH2 may be expressed in the form of a data amount, such as an MB value or a GB value. Alternatively, it can also be expressed in the form of a percentage. For example, assuming that the flash memory module 130 has a nominal storage capacity of X GB, the first threshold TH1 and the second threshold TH2 can be set to 0.3X GB and 0.6X GB, respectively, or the first threshold TH1 can be set. And the second threshold TH2 is set to 30% and 60% of the nominal storage capacity of the flash memory module 130, respectively.

As shown in FIG. 2, the processing circuit 124 selects a first voltage range as the range of the programming threshold voltage of the target data block to be written in the process 230, and selects a third voltage range in the process 250. For the range of the programming threshold voltage of the target data block to be written, in the process 260, a second voltage range is selected as the range of the programming threshold voltage of the target data block of the data to be written.

The aforementioned first voltage range is less than 50% of the second voltage range, and the third voltage range is less than 60% of the second voltage range. Upper limit of the first voltage range for the first voltage range The value can be less than 80% of the upper limit of the second voltage range. For example, the upper limit of the first voltage range may be less than 60%, or even 30%, of the upper limit of the second voltage range. The lower the upper limit of the first voltage range, the lower the power consumption required to write data to the memory cells of the data block. For the third voltage range, the upper limit of the third voltage range may be less than 80%, or even 60%, of the upper limit of the second voltage range. Similarly, the lower the upper limit of the third voltage range, the lower the power consumption required to write data to the storage unit.

In flow 270, processing circuit 124 controls read/write circuit 132 to program a memory cell in target data block 134 with a programmed threshold voltage within a selected voltage range to write data to target data block 134. in.

In the embodiment of FIG. 3, each storage unit of the data block 134 has an erase threshold voltage interval EV and a plurality of program threshold voltage intervals V0 to V7. In practice, the processing circuit 124 can select the first voltage range VR1 as the range of the programming threshold voltage of the target data block of the data to be written in the process 230, and select the third voltage range VR3 as the wait in the process 250. The range of the programming threshold voltage of the target data block of the data is written. In the process 260, the second voltage range VR2 can be selected as the range of the programming threshold voltage of the target data block of the data to be written. In the present embodiment, the upper limit value of the first voltage range VR1 is lower than 30% of the upper limit value of the second voltage range VR2, and includes the lowest two programming threshold voltage intervals V0 and V1 of the second voltage range VR2. Further, the upper limit value of the third voltage range VR3 is lower than 60% of the upper limit value of the second voltage range VR2, and includes the lowest four programming threshold voltage intervals V0, V1, V2, and V3 in the second voltage range VR2.

For example, if the communication interface 126 receives the first data to be written D1 sent from the main control device 110, and the amount of data stored in the flash memory module 130 at that time is lower than the first threshold TH1, the processing circuit 124 may Selecting the first voltage range VR1 as a target data block (for example, the first data block) 134A) programming a range of threshold voltages, and controlling the read/write circuit 132 to program the memory cells in the first data block 134A with a programmed threshold voltage within the first voltage range VR1 to cause the first data D1 to be one per storage unit A one-bit-per-cell mode (abbreviated as 1bpc mode) is written in the first data block 134A.

If the communication interface 126 receives the second data to be written D2 from the main control unit 110, the amount of data stored in the flash memory module 130 at the time is between the first threshold TH1 and the second threshold TH2. The processing circuit 124 can select the third voltage range VR3 as the range of the programming threshold voltage of the target data block (for example, the second data block 134G), and control the read/write circuit 132 to be within the third voltage range VR3. The threshold voltage is programmed to program the storage unit in the second data block 134G to write the second data D2 into the second data area in a two-bit-per-cell mode (abbreviated as 2bpc mode). In block 134G.

Then, if the communication interface 126 receives the third data to be written D3 sent from the main control device 110, and the amount of data stored in the flash memory module 130 is higher than the second threshold TH2, the processing circuit 124 can The second voltage range VR2 is selected as the range of the programming threshold voltage of a target data block (eg, the third data block 134P), and the read/write circuit 132 is controlled to program the third by the programming threshold voltage in the second voltage range VR2. The storage unit in the data block 134P writes the third data D3 into the third data block 134P in a three-bit-per-cell mode (abbreviated as 3bpc mode).

In other words, at the same time point, the data storage mode of different data blocks 134 in the flash memory module 130 may be different. For example, in the foregoing embodiment, when the read/write circuit 132 has just completed the operation of writing the third data D3 into the third data block 134P, the data storage mode of the third data block 134P is the 3bpc mode. The data storage mode of the first data block 134A is 1bpc mode, and the data storage mode of the second data block 134G is 2bpc mode.

In addition, when the processing circuit 124 determines the range of the programming threshold voltage of the target data block, the attribute of the data to be written may also be taken into consideration. For example, FIG. 4 is a simplified flowchart 400 of the second embodiment of the data writing method of the present invention, and FIG. 5 is a simplified flowchart of the third embodiment of the data writing method of the present invention. 500.

In the embodiment of FIG. 4, when the communication interface 126 receives the fourth data to be written D4 from the master device 110, the processing circuit 124 first performs a flow 415 to determine whether the fourth data D4 is less likely to be Frequently accessed data (hereinafter referred to as cold data). The processing circuit 124 can determine whether it is cold data according to the file type, the auxiliary file name, the logical address or the other manner of the fourth data D4. If the processing circuit 124 determines the fourth data D4 as cold data, it will jump directly to the process 260; otherwise, it will proceed to the process 220.

In the embodiment of FIG. 5, when the communication interface 126 receives the fifth to-be-written data D5 from the main control device 110, the processing circuit 124 first performs a flow 515 to determine whether the fifth data D5 is likely to be frequently used. Accessed data (hereinafter referred to as hot data). The processing circuit 124 can determine whether it is hot data according to the file type, the auxiliary file name, the logical address or the other manner of the fifth data D5. If the processing circuit 124 determines the fifth data D5 as hot data, it will jump directly to the process 230; otherwise, it will proceed to the process 220.

In another embodiment, the processing circuit 124 first determines whether the fifth data D5 belongs to hot data or cold data. If the processing circuit 124 determines the fifth data D5 as the hot data, it will jump directly to the process 230; if the processing circuit 124 determines the fifth data D5 as the cold data, it will jump directly to the process 260; if the processing circuit 124 determines the first If the data D5 is neither hot nor cold, it will proceed to process 220.

In operation, the processing circuit 124 may also record the number of times each of the data blocks 134 is written in the 1bpc mode, the number of times written in the 2bpc mode, and/or the number of times written in the 3bpc mode, on the recording medium 122. To facilitate recording, processing circuitry 124 may record the number of erases of data block 134 in a particular mode (eg, 1bpc mode, 2bpc mode, 3bpc mode) as the number of times data block 134 is written in a particular mode. In the foregoing process 270, the processing circuit 124 can select the appropriate data block 134 as the target data block according to the content recorded in the recording medium 122, so that the number of times each data block is written in a specific mode can be More average, avoid overusing specific data blocks.

In addition, the processing circuit 124 can record the usage status of the data block 134 of the flash memory module 130 in the recording medium 122, and determine whether to merge the storage contents of the partial data block into a sufficient capacity. In the data block, more available data blocks are released for storing subsequent data.

For example, the processing circuit 124 can record the number of data blocks in use of the flash memory module 130 in the recording medium 122, and store the partial data blocks when the number is higher than a third threshold TH3. The content is merged into a target data block with sufficient capacity. Alternatively, the processing circuit 124 may also record the number of blank data blocks in the flash memory module 130 in the recording medium 122, and when the number is lower than a fourth threshold TH4, the partial data blocks are The stored content is merged into a target data block with sufficient capacity.

When merging the contents of the data block, the processing circuit 124 can control the read/write circuit 132 to change the valid data in one or more candidate data blocks (eg, the data blocks 134A and 134B) storing the data in the 1bpc mode to 2bpc. The mode or 3bpc mode is written to a target data block (eg, data block 134H or 134Q) and the candidate data blocks are erased. The processing circuit 124 can also control the read/write circuit 132 to write valid data in candidate data blocks (eg, data blocks 134G and 134H) of one or more 2bpc mode stored data into a target data block in a 3bpc mode (eg, Data block 134P Or 134Q) and erase the candidate data blocks. Alternatively, the processing circuit 124 can control the read/write circuit 132 to store the valid data in a first candidate data block (for example, the data block 134A or 134B) storing the data in the 1bpc mode, and write the target data block in the 3bpc mode ( For example, the data block 134P or 134Q) stores the valid data in a second candidate data block (for example, the data block 134G or 134H) of the data in the 2bpc mode, and writes the target data block in the 3bpc mode (for example, data). Block 134P or 134Q) and erase the first and second candidate data blocks.

The processing circuit 124 dynamically adjusts the range of the programming threshold voltage of the target data block 134 to be written according to the amount of data stored in the flash memory module 130. Therefore, the range of programming threshold voltages for the same data block 134 may vary at different points in time. For example, when the amount of data stored in the flash memory module 130 is lower than the first threshold TH1, if the data block 134Q is selected as the target data block, the processing circuit 124 can control the read/write circuit 132 to the foregoing A programming threshold voltage within a voltage range VR1 is programmed to store the target data block 134Q, and the data is written to the target data block 134Q in 1bpc mode.

After that, the data block 134Q may be erased for various operational reasons. When the amount of data stored in the flash memory module 130 increases between the first threshold TH1 and the second threshold TH2, if the data block 134Q is selected as the target data block, the processing circuit 124 The controllable read/write circuit 132 programs the storage unit of the target data block 134Q with the programming threshold voltage in the aforementioned third voltage range VR3, and writes the new data into the target data block 134Q in the 2bpc mode.

Similarly, data block 134Q may be erased after various operational reasons. When the amount of data stored in the flash memory module 130 increases above the second threshold TH2, if the data block 134Q is again selected as the target data block, the processing circuit 124 can control the read/write circuit 132 to The programming threshold voltage in the aforementioned second voltage range VR2 is programmed to store the storage unit of the target data block 134Q, and the new data is written into the target data block 134Q in the 3bpc mode.

It can be seen from the foregoing description that the processing circuit 124 dynamically adjusts the range of the programming threshold voltage of the target data block 134 to be written according to the amount of data stored in the flash memory module 130 at the time, and even directly specifies the read/write circuit. 132 The programming threshold voltage used to write data to the target data block 134. When the amount of data stored in the flash memory module 130 is low, the processing circuit 124 controls the read/write circuit 132 of the flash memory module 130 to have a lower programming threshold voltage (eg, within the voltage interval V0 of FIG. 3). The data block 134 is programmed with a threshold voltage or a threshold voltage within the voltage interval V1. This method can not only reduce the power consumption required when writing data into the data block, but also effectively improve the wear resistance of the storage unit of the flash memory module 130, thereby improving the flash memory module 130. The reliability of the stored data.

In addition, since the programming threshold voltage of the data block 134 can be specified by the processing circuit 124, the processing circuit 124 can also directly specify the read/write circuit 132 to use when reading the target data block 134 during the data reading operation. The read threshold voltage is read, thereby speeding up the reading of the flash memory module 130.

Therefore, in combination with the control method of the flash memory controller 120, the flash memory module 130 can be realized not only by the MLC chip, the TLC chip, or even the higher order chip, but also to meet the low cost and high capacity target. Moreover, the durability, the wear resistance, and the data reliability of the flash memory module 130 can be effectively improved. Such an architecture is very helpful for meeting the product specification requirements for energy saving and carbon reduction, and is also helpful for promoting the popularization and application of solid state hard disks.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

200‧‧‧flow chart

210~270‧‧‧ Method flow

Claims (10)

A flash memory controller for controlling a flash memory module, wherein the flash memory module includes a read/write circuit, a first data block, and a second data block, the flash The memory controller includes: a communication interface for receiving a first data and a second data; and a processing circuit coupled to the communication interface and the flash memory module for The amount of data stored in the flash memory module at that time, dynamically adjusting the data to be written into the flash memory module mode; wherein, if the communication interface receives the first data, the flash memory module is The amount of stored data is lower than a first threshold, and the processing circuit controls the flash memory module to cause the first data to be written into the first data block in a bit pattern per storage unit, and If the communication device receives the second data, the amount of data stored in the flash memory module at that time is higher than the first threshold, the processing circuit controls the flash memory module to make the first Two data with two yuan per storage unit The second type write data block. The flash memory controller of claim 1, wherein the processing circuit controls the flash memory module such that a programming threshold voltage of at least one of the first data blocks is at a first Writing, in the voltage range, the first data into the first data block, and controlling the flash memory module such that a programming threshold voltage of at least one of the second data blocks is located at a first level Within the three voltage range, the second data is written into the second data block; wherein the first voltage range is less than the third voltage range. A flash memory controller for controlling a flash memory module, wherein the flash memory module includes a read/write circuit, a first data block, and a second data block, the flash memory The body controller includes: a communication interface for receiving a first data; and a processing circuit coupled to the communication interface and the flash memory module for using the flash memory module at the time The amount of stored data is dynamically adjusted to write the data to the flash memory module mode; wherein, if the communication interface receives the first data, the flash memory module has a low amount of data stored at the time. At a first threshold, the processing circuit controls the flash memory module such that the first data is written into the first data block in a bit pattern per storage unit, and the processing circuit controls The flash memory module is configured to cause at least one of the first data blocks to be written into a second data block in a two-dimensional mode per storage unit. The flash memory controller of claim 3, wherein the processing circuit controls the flash memory module such that a programming threshold voltage of at least one of the first data blocks is at a first Writing, in the voltage range, the first data into the first data block, and controlling the flash memory module such that a programming threshold voltage of at least one of the second data blocks is located at a first level Within the three voltage range, the second data is written into the second data block; wherein the first voltage range is less than the third voltage range. A flash memory controller for controlling a flash memory module, wherein the flash memory module includes a read/write circuit, a first data block, and a second data block, the flash The memory controller includes: a communication interface for receiving at least one first data; and a processing circuit coupled to the communication interface and the flash memory module for controlling the data of the read/write circuit Writing to the flash memory module; wherein, if the communication interface receives the first data, the data in the flash memory module The processing circuit controls the flash memory module such that a programming threshold voltage of at least one of the first data blocks is within a first voltage range, so that the amount is lower than a first threshold. The first data is written into the first data block. The flash memory controller of claim 5, wherein if the communication interface receives a second data, the amount of data stored in the flash memory module at the time is higher than the first threshold, The processing circuit controls the flash memory module such that a programming threshold voltage of at least one of the second data blocks is within a third voltage range to write the second data to the second data In the block, wherein the third voltage range is greater than the first voltage range. The flash memory controller of claim 6, wherein if the communication interface receives a third data, the amount of data stored in the flash memory module at that time is higher than a second threshold, The processing circuit controls the flash memory module such that a programming threshold voltage of at least one of the memory cells in a third data block is within a second voltage range to write the third data into the third data In the block, wherein the second threshold is higher than the first threshold, and the second voltage range is greater than the third voltage range. The flash memory controller of claim 7, wherein the processing circuit controls the flash memory module to cause the first data to be written into the first data block in a bit pattern per storage unit. The second data is written into the second data block in a two-element mode per storage unit, and the third data is written into the third data block in a three-bit mode per storage unit. The flash memory controller of claim 7, wherein an upper limit value of the first voltage range is less than an upper limit value of the third voltage range, and an upper limit value of the third voltage range is smaller than the second The upper limit of the voltage range. A flash memory controller for controlling a flash memory module, wherein the flash memory module includes a read/write circuit, a first data block, and a second data block, the flash The memory controller includes: a communication interface for receiving a first data; and a processing circuit coupled to the communication interface and the flash memory module; wherein, if the communication interface receives the first In a data, the amount of data in the flash memory module is lower than a first threshold, and the processing circuit controls the flash memory module to make at least one of the first data blocks The programming threshold voltage is located in a first voltage range to write the first data into the first data block, and the processing circuit then controls the flash memory module to be in the second data block The programming threshold voltage of the at least one storage unit is located in a third voltage range to write at least one data in the first data block into the second data block, wherein the first voltage range is less than the first Three voltage ranges.