CN116719477A - Wear leveling method, memory storage device and memory controller - Google Patents
Wear leveling method, memory storage device and memory controller Download PDFInfo
- Publication number
- CN116719477A CN116719477A CN202310639730.5A CN202310639730A CN116719477A CN 116719477 A CN116719477 A CN 116719477A CN 202310639730 A CN202310639730 A CN 202310639730A CN 116719477 A CN116719477 A CN 116719477A
- Authority
- CN
- China
- Prior art keywords
- entity management
- management unit
- evaluation value
- entity
- units
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 title claims abstract description 177
- 230000005055 memory storage Effects 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000011156 evaluation Methods 0.000 claims abstract description 67
- 230000004044 response Effects 0.000 claims abstract description 21
- 230000010354 integration Effects 0.000 claims description 10
- 230000002035 prolonged effect Effects 0.000 abstract 1
- 238000007726 management method Methods 0.000 description 164
- 230000000875 corresponding effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000013507 mapping Methods 0.000 description 3
- 238000007596 consolidation process Methods 0.000 description 2
- 230000002596 correlated effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 1
- 238000013523 data management Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
- G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/0644—Management of space entities, e.g. partitions, extents, pools
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention provides a wear leveling method, a memory storage device and a memory controller. The method comprises the following steps: selecting a first entity management unit and executing a first data merging operation on the first entity management unit; setting a first threshold according to a first loss evaluation value of the first entity management unit; and after setting the first threshold, performing a second data merging operation in response to the second loss evaluation value of the second entity management unit being greater than the first threshold and a difference between the third loss evaluation value of the third entity management unit and the fourth loss evaluation value of the fourth entity management unit being greater than the second threshold, comprising: collecting first data from the fourth entity management unit and storing the first data into the first entity management unit; erasing the fourth entity management unit; and collecting the second data from the third entity management unit and storing the second data into the fourth entity management unit. Thus, wear leveling operations can be optimized and the lifetime of the memory module can be effectively prolonged.
Description
Technical Field
The present invention relates to a memory management technology, and more particularly, to a wear leveling method, a memory storage device and a memory controller.
Background
Smartphones, tablet computers, and notebook computers have grown very rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable multimedia devices.
The rewritable nonvolatile memory has a plurality of physical blocks (physical blocks), and each physical block has a plurality of physical pages (physical pages). The physical block is the minimum unit of data erasing, and the physical page is the minimum unit of data writing. Generally, in order to extend the life of a rewritable nonvolatile memory module, physical blocks in the rewritable nonvolatile memory module are used as evenly as possible. Since the physical blocks also have a service life, in the process of using the memory storage device, if the service life difference between the physical blocks is too large, the data is easy to be unstable.
Therefore, it is an object of the art to effectively measure the wear level of the physical blocks to perform the wear-leveling operation, thereby effectively extending the life of the rewritable nonvolatile memory module.
Disclosure of Invention
The invention provides a wear leveling method, a memory storage device and a memory controller, which can optimize wear leveling operation and effectively prolong the service life of a memory module.
An embodiment of the present invention provides a wear leveling method for a memory module including a plurality of entity management units, each entity management unit including a plurality of entity units, the wear leveling method including: selecting a first entity management unit from the plurality of entity management units and executing a first data merging operation on the first entity management unit to release the first entity management unit; setting a first threshold according to a first loss evaluation value of the first entity management unit; and after setting the first threshold, performing a second data integration operation in response to a second loss evaluation value of a second entity management unit of the plurality of entity management units being greater than the first threshold and a difference between a third loss evaluation value of a third entity management unit of the plurality of entity management units and a fourth loss evaluation value of a fourth entity management unit of the plurality of entity management units being greater than a second threshold, wherein the second data integration operation comprises: collecting first data from the fourth entity management unit and storing the first data into the first entity management unit; erasing the fourth entity management unit; and collecting second data from the third entity management unit and storing the second data into the fourth entity management unit.
The embodiment of the invention further provides a memory storage device, which comprises a connection interface, a memory module and a memory controller. The connection interface is used for connecting to a host system. The memory module comprises a plurality of entity management units, and each entity management unit comprises a plurality of entity units. The memory controller is connected to the connection interface and the memory module. The memory controller is to: selecting a first entity management unit from the plurality of entity management units and executing a first data merging operation on the first entity management unit to release the first entity management unit; setting a first threshold according to a first loss evaluation value of the first entity management unit; and after setting the first threshold, performing a second data integration operation in response to a second loss evaluation value of a second entity management unit of the plurality of entity management units being greater than the first threshold and a difference between a third loss evaluation value of a third entity management unit of the plurality of entity management units and a fourth loss evaluation value of a fourth entity management unit of the plurality of entity management units being greater than a second threshold, wherein the second data integration operation comprises: collecting first data from the fourth entity management unit and storing the first data into the first entity management unit; erasing the fourth entity management unit; and collecting second data from the third entity management unit and storing the second data into the fourth entity management unit.
Embodiments of the present invention further provide a memory controller for controlling a memory module. The memory module includes a plurality of entity management units. Each entity management unit comprises a plurality of entity units. The memory controller includes a host interface, a memory interface, and a memory control circuit. The host interface is configured to connect to a host system. The memory interface is configured to connect to the memory module. The memory control circuit is connected to the host interface and the memory interface. The memory control circuit is to: selecting a first entity management unit from the plurality of entity management units and executing a first data merging operation on the first entity management unit to release the first entity management unit; setting a first threshold according to a first loss evaluation value of the first entity management unit; and after setting the first threshold, performing a second data integration operation in response to a second loss evaluation value of a second entity management unit of the plurality of entity management units being greater than the first threshold and a difference between a third loss evaluation value of a third entity management unit of the plurality of entity management units and a fourth loss evaluation value of a fourth entity management unit of the plurality of entity management units being greater than a second threshold, wherein the second data integration operation comprises: collecting first data from the fourth entity management unit and storing the first data into the first entity management unit; erasing the fourth entity management unit; and collecting second data from the third entity management unit and storing the second data into the fourth entity management unit.
Based on the above, the wear-leveling method, the memory storage device and the memory controller provided by the invention can conduct wear-leveling on a plurality of entity management units in the memory module through customized and optimized wear-leveling operation, thereby effectively prolonging the service life of the memory module.
Drawings
FIG. 1 is a schematic diagram of a memory storage device according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a managed memory module shown in accordance with an embodiment of the present invention;
fig. 4 is a flow chart of a loss balancing method according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
FIG. 1 is a schematic diagram of a memory storage device according to an embodiment of the present invention. Referring to fig. 1, a memory storage system 10 includes a host system 11 and a memory storage device 12. Host system 11 may be any type of computer system. For example. The host system 11 may be a notebook computer, a desktop computer, a smart phone, a tablet computer, an industrial computer, a game console, a digital camera, and other electronic systems. The memory storage device 12 is used to store data from the host system 11. For example, memory storage 12 may include a solid state disk, a USB flash drive, a memory card, or other type of non-volatile storage. The host system 11 may be electrically connected to the memory storage device 12 via a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) interface, a high speed peripheral component interconnect interface (Peripheral Component Interconnect Express, PCI Express), a universal serial bus (Universal Serial Bus, USB), or other type of interconnect interface. Thus, host system 11 may store data to memory storage device 12 and/or read data from memory storage device 12.
Memory storage device 12 may include a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the memory storage device 12 to the host system 11. For example, connection interface 121 may support connection interface standards such as SATA, PCI Express, or USB. Memory storage 12 may communicate with host system 11 via connection interface 121.
The memory module 122 is used for storing data. The memory module 122 may include a rewritable nonvolatile memory module. Further, the memory module 122 may include an array of memory cells. The memory cells in the memory module 122 store data in the form of voltages. For example, the memory module 122 may include a single Level Cell (Single Level Cell, SLC) NAND type flash memory module, a Multi Level Cell (MLC) NAND type flash memory module, a third Level Cell (Triple Level Cell, TLC) NAND type flash memory module, a Quad Level Cell (QLC) NAND type flash memory module, or other memory modules having similar characteristics.
The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 may be used to control the memory storage device 12. For example, the memory controller 123 may control the connection interface 121 and the memory module 122 for data access and data management. For example, the memory controller 123 may include a Central Processing Unit (CPU), or other programmable general purpose or special purpose microprocessor, digital signal processor (Digital Signal Processor, DSP), programmable controller, application specific integrated circuit (Application Specific Integrated Circuits, ASIC), programmable logic device (Programmable Logic Device, PLD), or other similar device or combination of devices.
In one embodiment, memory controller 123 is also referred to as a flash memory controller. In one embodiment, the memory module 122 is also referred to as a flash memory module. The memory module 122 may receive a sequence of instructions from the memory controller 123 and access the memory unit according to the sequence of instructions.
FIG. 2 is a schematic diagram of a memory controller according to an embodiment of the invention. Referring to fig. 1 and 2, the memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is configured to connect to the memory module 122 to communicate with the memory module 122.
The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 may communicate with the host system 11 via the host interface 21 and access the memory module 122 via the memory interface 22. For example, the memory control circuit 23 may receive various operation instructions (e.g. a read instruction, a write instruction, or an erase instruction) from the host system 11 via the host interface 21 and issue corresponding instruction sequences (e.g. a read instruction sequence, a write instruction sequence, or an erase instruction sequence) to the memory module 122 via the memory interface 22. Further, the memory control circuit 23 may transfer data to the host system 11 via the host interface 21. In one embodiment, the memory control circuit 23 may also be considered a control core of the memory controller 123. In the following embodiment, the explanation of the memory control circuit 23 is equivalent to the explanation of the memory controller 123. In addition, the memory control circuit 23 may include one or more buffer memories for temporarily storing data.
FIG. 3 is a schematic diagram illustrating managing memory modules according to an embodiment of the invention. Referring to fig. 1 to 3, the memory module 122 includes a plurality of physical units 301 (1) to 301 (B). Each physical unit comprises a plurality of memory cells and is used for non-volatile storage of data. For example, a physical unit may include one or more physical blocks. Each entity unit may include a plurality of entity pages. Multiple memory cells in one physical page may be programmed simultaneously to store data. All memory cells in a physical cell (or physical block) can be erased simultaneously.
In one embodiment, the physical units 301 (1) -301 (A) and 301 (A+1) -301 (B) in the memory module 122 can be respectively divided into a memory area 310 and an idle area 320. The entity units 301 (1) to 301 (a) in the storage area 310 store data (also referred to as user data) from the host system 11. The physical units 301 (a+1) -301 (B) in the spare area 320 do not store data.
In one embodiment, when new data from the host system 11 needs to be stored, one or more physical units in the idle area 320 are selected and used to store the new data. The physical units used to store data in the spare area 320 may be divided into storage areas 310. As more and more physical units in the spare area 320 are used to store data, the total number of physical units in the spare area 320 gradually decreases.
In one embodiment, memory control circuit 23 may configure a plurality of logic units 302 (1) -302 (C) to map physical units in memory area 310. For example, a logical unit may be composed of one or more logical addresses. For example, one logical address may include one or more logical block addresses (Logical Block Address, LBA). The mapping relationship between the logical unit and the physical unit may be recorded in the logical-to-physical mapping table. When receiving an access command from the host system 11, the memory control circuit 23 can access the physical units in the storage area 310 and/or the spare area 320 according to the logical-to-physical mapping table.
In one embodiment, if a certain physical unit is currently mapped by a logical unit, it indicates that valid data is stored in the physical unit. However, if a certain physical unit is not currently mapped by any logical unit, it indicates that no valid data is stored in the physical unit. In one embodiment, the physical units that do not store valid data may be repartitioned into the spare area 320. In one embodiment, each physical unit belonging to the idle region 320 is also referred to as an idle physical unit.
In one embodiment, the memory control circuit 23 can manage the physical units 301 (1) to 301 (B) through a plurality of physical management units. For example, the memory control circuit 23 may logically group each of the entity units 301 (1) to 301 (B) into one specific entity management unit. Each entity management unit may comprise a plurality of entity units. The memory control circuit 23 can synchronously access (e.g., program, read or erase) a plurality of physical units belonging to the same physical management unit.
In one embodiment, memory module 122 includes multiple planes. Each or at least part of the entity management units may span the plurality of planes. For example, a plurality of entity units in one entity management unit may be evenly dispersed in the plurality of planes. For example, assuming that memory module 122 includes planes (1) -4, each or at least a portion of the physical management units may span these 4 planes. For example, one entity management unit may include one or more entity units located in plane (1), one or more entity units located in plane (2), one or more entity units located in plane (3), and one or more entity units located in plane (4) at the same time.
In one embodiment, the memory control circuit 23 may record wear-leveling values for each entity management unit. The wear assessment value of an entity management unit may reflect the level of use and/or wear of the entity management unit and/or the entity units in the entity management unit. Further, the memory control circuit 23 may sort the wear-leveling values of the plurality of entity management units.
In one embodiment, the memory control circuit 23 can obtain the wear-leveling value of each physical management unit according to at least one of the programming count, the erasing count, the reading count and the Bit Error Rate (BER) corresponding to each physical management unit. The corresponding programming count of an entity management unit may reflect the number of times the entity management unit (or entity units belonging to the entity management unit) is programmed. The erase count corresponding to an entity management unit may reflect the number of times the entity management unit (or entity units belonging to the entity management unit) is erased. The corresponding count of reads of an entity management unit may reflect the number of times the entity management unit (or entity units belonging to the entity management unit) is read. The bit error rate corresponding to an entity management unit may reflect the bit error rate of data read from the entity management unit (or entity units belonging to the entity management unit).
In one embodiment, multiple physical units belonging to the same physical management unit may be accessed (e.g., programmed, read, or erased) simultaneously. Thus, multiple entity units belonging to the same entity management unit may have the same degree of usage and/or degree of wear, and the wear assessment value of an entity management unit may be the same as (or close to) the wear assessment value of any of such entity units.
In one embodiment, a plurality of entity units belonging to the same entity management unit may also have different usage levels and/or wear levels. Therefore, a plurality of entity units belonging to the same entity management unit may also have different wear assessment values. In one embodiment, if a plurality of entity units belonging to a certain entity management unit have different wear-leveling values, the memory control circuit 23 may set the wear-leveling value of the entity management unit according to the average or median of the wear-leveling values.
In one embodiment, it is assumed that the initial value of the loss evaluation value of each entity management unit is the same (e.g., "0"). The memory control circuit 23 may update the wear-leveling value of each entity management unit according to the use status of the entity management unit to reflect the latest use status (i.e., the degree of use and/or the degree of wear) of each entity management unit. For example, after a period of use of the memory module 122, an entity management unit that is used at a relatively high frequency may have a relatively high wear assessment value.
In one embodiment, the memory control circuit 23 may perform wear leveling on the entity management units in the memory module 122 according to the described wear leveling values (or the sorted wear leveling values), thereby effectively prolonging the lifetime of the memory module 122.
In one embodiment, after the memory module 122 is used for a period of time, the memory control circuit 23 may select at least one entity management unit (also referred to as a first entity management unit) from the plurality of entity management units according to the recorded wear-leveling values of the plurality of entity management units. For example, the memory control circuit 23 may select the entity management unit having the largest wear-out evaluation value from the memory area 310 as the first entity management unit. The memory control circuit 23 may then perform a data merging operation (also referred to as a first data merging operation) on the first entity management unit. For example, the data consolidation operation may include a garbage collection (Garbage Collection, GC) operation.
In the first data integration operation, the memory control circuit 23 may collect valid data from the first entity management unit and store the collected valid data into another entity management unit. Then, the memory control circuit 23 can regroup the first physical management units to the idle area 320 and erase the first physical management units. In one embodiment, the operation of regrouping the first entity management units into the idle zone 320 is also referred to as releasing the first entity management units.
In one embodiment, the memory control circuit 23 may temporarily disable the first entity management unit after releasing the first entity management unit. For example, after releasing the first entity management unit, the memory control circuit 23 may temporarily mark the first entity management unit as unusable. In a state in which the first entity management unit is marked as unusable, the memory control circuit 23 does not store any data (i.e., new data) into the first entity management unit. Alternatively, in one embodiment, in the state that the first entity management unit is marked as unusable, the first entity management unit is kept in the idle area 320 and is not extracted from the idle area 320 to store new data.
In one embodiment, after the first entity management unit is selected to perform the first data merging operation, the memory control circuit 23 may set a threshold value (also referred to as a first threshold value) according to the wear-leveling value (also referred to as a first wear-leveling value) of the first entity management unit. For example, the first threshold value may be the same or positively correlated (positively correlated to) to the first loss estimate. After setting the first threshold, the memory control circuit 23 may continuously update the wear-leveling value of each entity management unit during the use of the memory module 122. On the other hand, during the use of the memory module 122, the memory control circuit 23 can continuously detect whether the wear-leveling value of any one of the physical management units is greater than the first threshold value.
In one embodiment, after setting the first threshold, it is assumed that the memory control circuit 23 detects that a wear-leveling value (also referred to as a second wear-leveling value) of a certain entity management unit (also referred to as a second entity management unit) in the storage area 310 is greater than the first threshold. In response to the second wear-leveling value being greater than the first threshold value, the memory control circuit 23 may determine whether a difference between a wear-leveling value (also referred to as a third wear-leveling value) of one entity management unit (also referred to as a third entity management unit) in the memory area 310 and a wear-leveling value (also referred to as a fourth wear-leveling value) of another entity management unit (also referred to as a fourth entity management unit) in the memory area 310 is greater than a threshold value (also referred to as a second threshold value). The second threshold may be 10 or other values, which is not limited by the present invention. In response to the difference being greater than the second threshold, the memory control circuit 23 may perform a data merging operation (also referred to as a second data merging operation).
In one embodiment, in response to the second wear-out assessment value being greater than the first threshold value, the memory control circuit 23 may select the entity management unit having the largest wear-out assessment value from the memory area 310 as the third entity management unit, and select the entity management unit having the smallest wear-out assessment value from the memory area 310 as the fourth entity management unit. The second entity management unit and the third entity management unit may be the same entity management unit or different entity management units, which is not limited in the present invention. In one embodiment, the memory control circuit 23 may also select the third entity management unit and the fourth entity management unit according to other rules, which is not limited by the present invention.
In the second data merging operation, the memory control circuit 23 may collect valid data (also referred to as first data) from a fourth entity management unit (e.g., an entity management unit with the smallest wear-level evaluation value) and store the first data into the first entity management unit previously reserved in the idle area 320. For example, in a second data consolidation operation, the memory control circuit 23 may instead mark the first entity management unit as available and extract the first entity management unit from the idle area 320 to store the first data.
After the first data is completely copied to the first entity management unit, the memory control circuit 23 may erase the fourth entity management unit. Then, the memory control circuit 23 may collect valid data (also referred to as second data) from a third entity management unit (for example, the entity management unit with the largest wear-leveling value) and store the second data into the erased fourth entity management unit. After the second data is completely stored in the fourth entity management unit, the memory control circuit 23 may erase the third entity management unit and regroup the third entity management unit to the idle area 320. Thus, one loss balance operation is completed.
In one embodiment, the memory control circuit 23 may further update the first threshold according to the wear-leveling value of the third entity management unit (i.e. the third wear-leveling value). For example, the memory control circuit 23 may reset the first threshold value according to the third wear-leveling value. For example, the updated first threshold value may be the same as the third loss evaluation value. After updating the first threshold, the wear-leveling operation may be performed based on the updated first threshold, which is not repeated herein.
Fig. 4 is a flow chart of a loss balancing method according to an embodiment of the present invention. Referring to fig. 4, in step S410, a first entity management unit is selected and a first data merging operation is performed on the first entity management unit to release the first entity management unit. In step S420, a first threshold is set according to a first loss evaluation value of the first entity management unit. In step S430, it is determined whether the second loss evaluation value of the second entity management unit is greater than the first threshold value. In response to the second loss evaluation value being greater than the first threshold, in step S440, it is determined whether a difference between the third loss evaluation value of the third entity management unit and the fourth loss evaluation value of the fourth entity management unit is greater than the second threshold. In response to the difference being greater than the second threshold, a second data merge operation is performed in step S450. On the other hand, if the determination in step S430 or S440 is negative, the process may return to the previous step or perform other predetermined procedures.
Step S450 includes steps S451 to S453. In step S451, first data is collected from the fourth entity management unit and stored into the first entity management unit. In step S452, the fourth entity management unit is erased. In step S453, the second data is collected from the third entity management unit and stored into the fourth entity management unit.
However, the steps in fig. 4 are described in detail above, and will not be described again here. It should be noted that each step in fig. 4 may be implemented as a plurality of program codes or circuits, and the present invention is not limited thereto. In addition, the method of fig. 4 may be used with the above exemplary embodiment, or may be used alone, and the present invention is not limited thereto.
In summary, the wear-leveling method, the memory storage device and the memory controller according to the embodiments of the present invention can perform wear-leveling on the entity management units in the memory module according to the described wear-leveling values (or the sorted wear-leveling values). By optimizing the wear leveling, the lifetime of the memory module can be effectively extended.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (21)
1. A wear leveling method for a memory module, the memory module comprising a plurality of entity management units, each entity management unit comprising a plurality of entity units, the wear leveling method comprising:
selecting a first entity management unit from the plurality of entity management units and executing a first data merging operation on the first entity management unit to release the first entity management unit;
setting a first threshold according to a first loss evaluation value of the first entity management unit; and
after setting the first threshold, performing a second data integration operation in response to the second loss evaluation value of a second entity management unit of the plurality of entity management units being greater than the first threshold and a difference between the third loss evaluation value of a third entity management unit of the plurality of entity management units and the fourth loss evaluation value of a fourth entity management unit of the plurality of entity management units being greater than the second threshold,
wherein the second data merging operation comprises:
collecting first data from the fourth entity management unit and storing the first data into the first entity management unit;
erasing the fourth entity management unit; and
second data is collected from the third entity management unit and stored into the fourth entity management unit.
2. The wear leveling method of claim 1, wherein selecting the first entity management unit from the plurality of entity management units comprises:
and selecting an entity management unit with the largest loss evaluation value from the plurality of entity management units as the first entity management unit.
3. The wear leveling method according to claim 1, wherein after setting the first threshold value, in response to the second wear leveling value of the second one of the plurality of entity management units being greater than the first threshold value and the difference between the third wear leveling value of the third one of the plurality of entity management units and the fourth wear leveling value of the fourth one of the plurality of entity management units being greater than the second threshold value, the step of performing the second data leveling operation includes:
after setting the first threshold value, in response to the second loss evaluation value being greater than the first threshold value, selecting an entity management unit having the largest loss evaluation value from the plurality of entity management units as the third entity management unit, and selecting an entity management unit having the smallest loss evaluation value from the plurality of entity management units as the fourth entity management unit;
judging whether the difference between the third loss evaluation value of the third entity management unit and the fourth loss evaluation value of the fourth entity management unit is greater than the second threshold; and
and performing the second data merging operation in response to the difference between the third loss evaluation value and the fourth loss evaluation value being greater than the second threshold value.
4. The loss balancing method of claim 1, further comprising:
after releasing the first entity management unit, the first entity management unit is marked as unusable.
5. The loss balancing method of claim 1, wherein the second data merge operation further comprises:
and updating the first threshold value according to the third loss evaluation value.
6. The loss balancing method of claim 1, further comprising:
and obtaining the wear evaluation value of each entity management unit according to at least one of the programming count, the erasing count, the reading count and the bit error rate corresponding to each entity management unit.
7. The wear leveling method according to claim 1, wherein the memory module includes a plurality of planes, and the each entity management unit spans the plurality of planes.
8. A memory storage device, comprising:
a connection interface for connecting to a host system;
the memory module comprises a plurality of entity management units, and each entity management unit comprises a plurality of entity units; and
a memory controller connected to the connection interface and the memory module,
wherein the memory controller is to:
selecting a first entity management unit from the plurality of entity management units and executing a first data merging operation on the first entity management unit to release the first entity management unit;
setting a first threshold according to a first loss evaluation value of the first entity management unit; and
after setting the first threshold, performing a second data integration operation in response to the second loss evaluation value of a second entity management unit of the plurality of entity management units being greater than the first threshold and a difference between the third loss evaluation value of a third entity management unit of the plurality of entity management units and the fourth loss evaluation value of a fourth entity management unit of the plurality of entity management units being greater than the second threshold,
wherein the second data merging operation comprises:
collecting first data from the fourth entity management unit and storing the first data into the first entity management unit;
erasing the fourth entity management unit; and
second data is collected from the third entity management unit and stored into the fourth entity management unit.
9. The memory storage device of claim 8, wherein the operation of the memory controller to select the first entity management unit from the plurality of entity management units comprises:
and selecting an entity management unit with the largest loss evaluation value from the plurality of entity management units as the first entity management unit.
10. The memory storage device of claim 8, wherein after setting the first threshold value, the memory controller performs the operation of the second data merge operation in response to the second wear-assessment value of the second one of the plurality of entity management units being greater than the first threshold value and the difference between the third wear-assessment value of the third one of the plurality of entity management units and the fourth wear-assessment value of the fourth one of the plurality of entity management units being greater than the second threshold value, comprising:
after setting the first threshold value, in response to the second loss evaluation value being greater than the first threshold value, selecting an entity management unit having the largest loss evaluation value from the plurality of entity management units as the third entity management unit, and selecting an entity management unit having the smallest loss evaluation value from the plurality of entity management units as the fourth entity management unit;
judging whether the difference between the third loss evaluation value of the third entity management unit and the fourth loss evaluation value of the fourth entity management unit is greater than the second threshold; and
and performing the second data merging operation in response to the difference between the third loss evaluation value and the fourth loss evaluation value being greater than the second threshold value.
11. The memory storage device of claim 8, wherein the memory controller is further to:
after releasing the first entity management unit, the first entity management unit is marked as unusable.
12. The memory storage device of claim 8, wherein the second data merge operation further comprises:
and updating the first threshold value according to the third loss evaluation value.
13. The memory storage device of claim 8, wherein the memory controller is further to:
and obtaining the wear evaluation value of each entity management unit according to at least one of the programming count, the erasing count, the reading count and the bit error rate corresponding to each entity management unit.
14. The memory storage device of claim 8, wherein the memory module comprises a plurality of planes, and the each entity management unit spans the plurality of planes.
15. A memory controller for controlling a memory module, the memory module comprising a plurality of entity management units, each entity management unit comprising a plurality of entity units, and the memory controller comprising:
a host interface for connecting to a host system;
a memory interface for connecting to the memory module; and
a memory control circuit connected to the host interface and the memory interface,
wherein the memory control circuit is to:
selecting a first entity management unit from the plurality of entity management units and executing a first data merging operation on the first entity management unit to release the first entity management unit;
setting a first threshold according to a first loss evaluation value of the first entity management unit; and
after setting the first threshold, performing a second data integration operation in response to the second loss evaluation value of a second entity management unit of the plurality of entity management units being greater than the first threshold and a difference between the third loss evaluation value of a third entity management unit of the plurality of entity management units and the fourth loss evaluation value of a fourth entity management unit of the plurality of entity management units being greater than the second threshold,
wherein the second data merging operation comprises:
collecting first data from the fourth entity management unit and storing the first data into the first entity management unit;
erasing the fourth entity management unit; and
second data is collected from the third entity management unit and stored into the fourth entity management unit.
16. The memory controller of claim 15, wherein the operation of the memory control circuit to select the first entity management unit from the plurality of entity management units comprises:
and selecting an entity management unit with the largest loss evaluation value from the plurality of entity management units as the first entity management unit.
17. The memory controller of claim 15, wherein after setting the first threshold value, the memory control circuit performs the operation of the second data merge operation in response to the second wear-leveling value of the second one of the plurality of entity management units being greater than the first threshold value and the difference between the third wear-leveling value of the third one of the plurality of entity management units and the fourth wear-leveling value of the fourth one of the plurality of entity management units being greater than the second threshold value, comprising:
after setting the first threshold value, in response to the second loss evaluation value being greater than the first threshold value, selecting an entity management unit having the largest loss evaluation value from the plurality of entity management units as the third entity management unit, and selecting an entity management unit having the smallest loss evaluation value from the plurality of entity management units as the fourth entity management unit;
judging whether the difference between the third loss evaluation value of the third entity management unit and the fourth loss evaluation value of the fourth entity management unit is greater than the second threshold; and
and performing the second data merging operation in response to the difference between the third loss evaluation value and the fourth loss evaluation value being greater than the second threshold value.
18. The memory controller of claim 15, wherein the memory control circuitry is further to:
after releasing the first entity management unit, the first entity management unit is marked as unusable.
19. The memory controller of claim 15, wherein the second data merge operation further comprises:
and updating the first threshold value according to the third loss evaluation value.
20. The memory controller of claim 15, wherein the memory control circuitry is further to:
and obtaining the wear evaluation value of each entity management unit according to at least one of the programming count, the erasing count, the reading count and the bit error rate corresponding to each entity management unit.
21. The memory controller of claim 15, wherein the memory module comprises a plurality of planes, and the each entity management unit spans the plurality of planes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310639730.5A CN116719477A (en) | 2023-06-01 | 2023-06-01 | Wear leveling method, memory storage device and memory controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310639730.5A CN116719477A (en) | 2023-06-01 | 2023-06-01 | Wear leveling method, memory storage device and memory controller |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116719477A true CN116719477A (en) | 2023-09-08 |
Family
ID=87870816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310639730.5A Pending CN116719477A (en) | 2023-06-01 | 2023-06-01 | Wear leveling method, memory storage device and memory controller |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116719477A (en) |
-
2023
- 2023-06-01 CN CN202310639730.5A patent/CN116719477A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9098395B2 (en) | Logical block management method for a flash memory and control circuit storage system using the same | |
| US9268687B2 (en) | Data writing method, memory control circuit unit and memory storage apparatus | |
| US10409525B2 (en) | Memory management method, memory control circuit unit and memory storage device | |
| US10101914B2 (en) | Memory management method, memory control circuit unit and memory storage device | |
| US9772797B2 (en) | Buffer memory management method, memory control circuit unit and memory storage device | |
| US10620874B2 (en) | Memory management method, memory control circuit unit and memory storage apparatus | |
| US20130304965A1 (en) | Storage unit management method, memory controller and memory storage device using the same | |
| US8037236B2 (en) | Flash memory writing method and storage system and controller using the same | |
| CN108733577B (en) | Memory management method, memory control circuit unit and memory storage device | |
| CN113885692B (en) | Memory efficiency optimization method, memory control circuit unit and memory device | |
| US20130332653A1 (en) | Memory management method, and memory controller and memory storage device using the same | |
| US9298610B2 (en) | Data writing method, memory control circuit unit and memory storage apparatus | |
| US9001585B1 (en) | Data writing method, memory control circuit unit and memory storage apparatus | |
| CN111625197A (en) | Memory control method, memory storage device and memory controller | |
| CN112230849B (en) | Memory control method, memory storage device and memory controller | |
| CN112860193B (en) | Sorting instruction processing method, memory control circuit unit and memory device | |
| US10203886B2 (en) | Data writing method, memory control circuit unit and memory storage apparatus for writing data from buffer memory and moving valid data | |
| CN106354651B (en) | Average wear method, memory control circuit unit and memory storage device | |
| CN110471612B (en) | Memory management method and memory controller | |
| CN114063933B (en) | Block management method, memory controller and memory storage device | |
| US9710374B2 (en) | Data writing method, memory controller and memory storage device | |
| CN113094306B (en) | Effective data management method, memory storage device and memory controller | |
| CN115185468A (en) | Memory management method, memory controller and memory storage device | |
| CN109032957B (en) | Memory management method, memory control circuit unit and memory storage device | |
| CN112068782B (en) | Memory management method, memory storage device and memory control circuit unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |