TWI699774B - Semiconductor device and operating method thereof - Google Patents

Abstract

A semiconductor device includes a substrate including a doped region of a first doping concentration that extends downward from an upper surface of the substrate; a first stack disposed on the upper surface, including first insulating layers and first conductive layers alternatively stacked, a first channel layer, a first memory layer and a first conductive connector configured to receive a first voltage, the first conductive connector disposed on the first channel layer, having a second doping concentration; a second stack disposed on the first stack including second insulating layers and second conductive layers alternatively stacked, a second channel layer, a second memory layer, the second conductive layer configured to receive the second voltage; a bonding pad disposed on the second channel layer, configured to receive an erasing voltage, the first conductive connector electrically connected to the first and second channel layers; the first doping concentration smaller than the second doping concentration.

Description

Semiconductor device and its operation method

The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a peripheral circuit part and an array part are vertically stacked.

Recently, in order to reduce the size of the chip, the semiconductor structure (that is, the circuit under array (CUA)) in which the memory array portion is vertically stacked on the peripheral circuit portion has become more and more popular. In this structure Among them, the memory array part generally includes a semiconductor substrate; a multi-layer stack structure formed by alternately stacking a plurality of insulating layers and polysilicon layers on the semiconductor substrate; and a memory layer formed in sequence on the sidewalls of the through openings passing through the multi-layer stack structure (E.g. silicon oxynitride-oxide-nitride-oxide memory layer, oxide-nitride-oxide-nitride-oxide (BE-SONOS) memory layer, or charge trapping memory )) and a polysilicon channel layer; and a plurality of memory cells defined on the channel layer, memory layer, and polysilicon layer. The memory cells are electrically connected to the semiconductor substrate as the bottom common source line through the channel layer. Among them, the semiconductor The substrate usually needs to be doped with high-concentration N-type semiconductor dopants, so that the bottom common source line can be used for block erase operations of the memory array portion.

However, after the manufacturing process of the semiconductor device (for example, a thermal process), the N-type dopants in the semiconductor substrate easily diffuse upward through the channel layer, thereby affecting the function of the ground selection line device adjacent to the substrate.

Therefore, there is a need to provide a vertical channel flash memory device to solve the problems faced by the prior art.

The present invention relates to a semiconductor device. Since the N-type doping region of the substrate of the semiconductor device of the present invention has a relatively low doping concentration (for example, less than 5×10 ¹⁸ cm ^-3 ), it can reduce the dissipation of the N-type dopant of the substrate of the semiconductor device to The channel layer affects the ground select line device (GSL device), so the utilization rate of the ground select line device can be improved.

According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a substrate, a first stack and a second stack. The substrate has an upper surface, wherein the substrate includes a doped region extending downward from the upper surface, and the doped region has a first doping concentration. The first stack is disposed on the upper surface, wherein the first stack includes a plurality of first insulating layers and a plurality of first conductive layers, a first channel layer, a first memory layer, and a first conductive connection member alternately stacked. The first conductive layer is configured to receive a first voltage. The first channel layer passes through the first stack. The first memory layer surrounds the first channel layer. The first conductive connection member is disposed on the first channel layer and has a second doping concentration. The second stack is disposed on the first conductive connection member and located on the first stack, wherein the second stack includes a plurality of second insulating layers and a plurality of second conductive layers stacked alternately, a second channel layer, and a second The memory layer and a second conductive connection member, wherein the second conductive layer is configured to receive a second voltage different from the first voltage. The second channel layer passes through the second stack, and the second memory layer surrounds the second channel layer. The second conductive connection member is arranged on the second channel layer. The second conductive connection member has a third doping concentration and is configured to receive an erasing voltage, wherein the first conductive connection member is electrically connected to the first channel layer and the second channel layer. The first doping concentration is less than the second doping concentration and the third doping concentration.

According to another aspect of the present invention, an operating method of a semiconductor device is provided. This method includes the following steps. First, this semiconductor device is provided. The semiconductor device includes a substrate, a first stack and a second stack. The substrate has an upper surface, wherein the substrate includes a doped region extending downward from the upper surface, and the doped region has a first doping concentration. The first stack is disposed on the upper surface, wherein the first stack includes a plurality of first insulating layers and a plurality of first conductive layers, a first channel layer, a first memory layer, and a first conductive connection member alternately stacked. The first channel layer passes through the first stack. The first memory layer surrounds the first channel layer. The first conductive connection member is disposed on the first channel layer and has a second doping concentration. The second stack is disposed on the first conductive connection member and located on the first stack, wherein the second stack includes a plurality of second insulating layers and a plurality of second conductive layers stacked alternately, a second channel layer, and a second The memory layer and a second conductive connection member. The second channel layer passes through the second stack, and the second memory layer surrounds the second channel layer. The second conductive connection member is arranged on the second channel layer. The second conductive connection member has a third doping concentration, and the first conductive connection member is electrically connected to the first channel layer and the second channel layer. The first doping concentration is less than the second doping concentration and the third doping concentration. Then, during an erase operation, apply an erase voltage to the second conductive connection; during an erase operation, apply a first voltage to the first conductive layer; and during an erase operation, apply a second The voltage is on the second conductive layer; wherein the second voltage is greater than the first voltage.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are described in detail with the accompanying drawings as follows:

FIG. 1 shows a cross-sectional view of a semiconductor device 10 according to an embodiment of the invention.

Referring to FIG. 1, the semiconductor device 10 includes a peripheral circuit portion 100a and an array portion 100b, wherein the array portion 100b is located on the peripheral circuit portion 100a. The peripheral circuit part 100a includes a Complementary Metal-Oxide-Semiconductor structure C1 and other suitable structures. The array portion 100b includes a substrate 101, a first stack S1, a second stack S2, an interconnect 156, and a cover layer 158. The second stack S2 is disposed on the first stack S1. The substrate 101 has an upper surface 101s, and includes a doped region 101R extending downward from the upper surface 101s. The peripheral circuit part 100a is disposed under the substrate 101. In some embodiments, the array portion 100b including the first stack S1 and the second stack S2 overlaps with the peripheral circuit portion 100a in the normal direction of the upper surface 101s.

The array part 100b of the present invention exemplarily describes an embodiment of a gate-all-around (GAA) memory structure. However, the present invention is not limited to this. The array part 100b of the present invention can be any nitride-based The non-volatile memory structure of the memory material.

The first stack S1 is disposed on the upper surface 101s, where the first stack S1 includes a plurality of first insulating layers 121 to 124... and a plurality of first conductive layers 111 to 113... which are alternately stacked along the Z-axis direction. Figure 1 only exemplarily shows three first conductive layers 111 to 113 and four first insulating layers 121 to 124 in the first stack S1. However, the present invention is not limited thereto. In the first stack S1 More conductive and insulating layers can be included. In this embodiment, the first insulating layers 121 and 124 are respectively located at the bottom and top layers of the first stack S1, and the first insulating layer 121 is in direct contact with the substrate 101. The first conductive layers 111-113 are configured to receive a first voltage V ₁ (shown in Figure 2). The first insulating pillar 103, the first channel layer 104, and the first memory layer 102 pass through the first stack S1 perpendicularly (for example, along the Z-axis direction). Wherein, the first channel layer 104 and the first memory layer 102 surround the first insulating pillar 103. The first memory layer 102 surrounds the first channel layer 104. The first memory layer 102 is located between the first channel layer 104, the first insulating layers 121-124, and the first conductive layers 111-113. The first conductive connection member 152 is disposed on the first memory layer 102, the first insulating pillar 103 and the first channel layer 104 and electrically contacts the first channel layer 104. The first dielectric layer 116 is located between the first memory layer 102, the first insulating layers 121-124 and the first conductive layers 111-113, and can surround the first conductive layers 111-113.

The second stack S2 is disposed on the first stack S1, wherein the second stack S2 includes a plurality of second insulating layers 141 to 144... and a plurality of second conductive layers 131 to 133... which are alternately stacked along the Z-axis direction. Figure 1 only exemplarily shows three second conductive layers 131 to 133 and four second insulating layers 141 to 144 in the second stack S2. However, the present invention is not limited thereto. In the second stack S2 More conductive and insulating layers can be included.

In this embodiment, the second insulating layers 141 and 144 are respectively located at the bottom and top layers of the second stack S2. The second conductive layers 131 to 133 are configured to receive a second voltage V ₂ (shown in Figure 2) that is different from the first voltage V ₁ . In some embodiments, the second voltage V _{2 is} greater than the first voltage V ₁ . The second insulating pillar 105, the second channel layer 108, and the second memory layer 106 perpendicularly pass through the second stack S2 (for example, along the Z-axis direction). Among them, the second channel layer 108 and the second memory layer 106 surround the second insulating pillar 105. The second memory layer 106 surrounds the second channel layer 108. The second memory layer 106 is located between the second channel layer 108, the second insulating layers 141-144, and the second conductive layers 131-133. The second conductive connection member 154 is disposed on the second insulating pillar 105, the second memory layer 106 and the second channel layer 108 and electrically contacts the second channel layer 108. The second conductive connection member 154 is configured to receive an erasing voltage _Ver (shown in Figure 2). The first conductive connection member 152 is located between the first channel layer 104 and the second channel layer 108 and is electrically connected to the first channel layer 104 and the second channel layer 108. The second dielectric layer 136 is located between the second memory layer 106, the second insulating layers 141-144, and the second conductive layers 131-133, and can surround the second conductive layers 131-133. The inner wire 156 is electrically connected to the second conductive connecting member 154. The cover layer 158 is located on the second stack S2.

In some embodiments, the substrate 101 is, for example, a silicon substrate or other suitable substrates, such as an N-type doped polysilicon substrate. The first conductive connection member 152 and the second conductive connection member 154 are, for example, an N-type doped polysilicon layer. The doped region 101R, the first conductive connector 152, and the second conductive connector 154 of the substrate 101 can be doped with N-type dopants, respectively, and have a first doping concentration and a second doping concentration. And a third doping concentration. The first doping concentration may be different from the second doping concentration and the third doping concentration. For example, the first doping concentration may be less than 5×10 ¹⁸ cm ^-3 , and the second doping concentration and the third doping concentration may be greater than 1×10 ¹⁹ cm ^{-3 respectively} . In some embodiments, the first doping concentration is less than the second doping concentration and the third doping concentration, and the second doping concentration may be the same as the third doping concentration. In some embodiments, the second doping concentration may be less than the third doping concentration. Compared with the comparative example in which the substrate has a high concentration of N-type dopants (for example, greater than 1×10 ¹⁹ cm ^-3 ), since the first doping concentration of the doped region 101R of the substrate 101 in this case is lower, The degree of dispersion of N-type dopants to the first channel layer 104 can be reduced, and thus the ground selection line device adjacent to the substrate 101 (for example, the crossing position between the first conductive layer 111, 112 and the first memory layer 102 can be slowed down. The formed transistor is continuously turned on under the influence of the N-type dopant, and thus cannot function.

For example, the first conductive layer 111 closest to the substrate 101 among the first conductive layers 111 to 113 can be used as a ground select line (GSL), and the first conductive layer 111 and the second conductive layer 111 closest to the substrate 101 The intersection of a memory layer 102 and the first channel layer 104 can form a ground selection line transistor T _G. Among the second conductive layers 131 to 133, the second conductive layer 133 closest to the second conductive connector 154 can be used as a string select line (SSL), and the second conductive layer closest to the second conductive connector 154 133. The intersection of the second memory layer 106 and the second channel layer 108 can form a tandem select line transistor T _S. The first conductive layers 112, 113... and the second conductive layers 131, 132... located between the ground selection line and the series selection line can be used as word lines (WL). Each intersection between the first conductive layers 112, 113..., the second conductive layers 131, 132..., the first memory layer 102 and the second memory layer 106 can form a memory cell M for storing data. The memory cell M defined by the first conductive layer 112, 113..., the second conductive layer 131, 132..., the first memory layer 102, the second memory layer 106, the first channel layer 104 and the second channel layer 108 can be It is electrically coupled to a decoder (not shown) through a bit line (not shown), and the decoder is, for example, a row decoder or a column decoder.

Assuming that the first channel layer 104 adjacent to the first conductive layer 111 is interfered by N-type dopants, the first conductive layer 112 above the first conductive layer 111 is used as the ground selection line instead, and the first conductive layer 112 is used. The crossing point between the first memory layer 102 and the first channel layer 104 is used as a ground selection line transistor; assuming that the first channel layer 104 adjacent to the first conductive layer 112 is interfered by N-type dopants, then use The first conductive layer above the first conductive layer 112 is used as the ground selection line, and the first conductive layer above the first conductive layer 112, the intersection between the first memory layer 102 and the first channel layer 104 are used as the ground selection line Transistor, and so on.

In some embodiments, the materials of the first insulating layers 121 to 124, the first conductive layers 111 to 113, the first channel layer 104, the first memory layer 104, and the first insulating pillar 103 may be the same or similar to those of the second insulating layer. Layers 141 to 144, second conductive layers 131 to 133, second channel layer 108, second memory layer 106, and second insulating pillar 105. The first insulating layers 121 to 124, the first insulating pillars 103, the second insulating layers 141 to 144, the second insulating pillars 105, and the covering layer 158 may be formed of oxide, such as silicon dioxide (SiO ₂ ). The first conductive layers 111-113 and the second conductive layers 131-133 can be formed of conductive materials, such as tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), or other suitable materials . The first memory layer 102 and the second memory layer 106 may be composed of a composite layer (ie, an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the first memory layer 102 and the second memory layer 106 may include a tunneling layer, a capturing layer, and a barrier layer, respectively. The tunneling layer may include a double-layer structure formed of silicon oxynitride (SiON) and silicon dioxide (SiO ₂ ) or other suitable materials. The capture layer may include silicon nitride or other suitable materials. The barrier layer may include silicon dioxide (SiO ₂ ) or other suitable materials. The first dielectric layer 116 and the second dielectric layer 136 may include a high-k material, such as aluminum oxide (Al ₂ O ₃ ) or other suitable materials. The first channel layer 104 and the second channel layer 108 can be monocrystalline or polycrystalline silicon layers (also epitaxial growth layers).

In the embodiment of the present invention, the first channel layer 104 and the second channel layer 108 are respectively formed under different process steps, instead of forming a channel opening by a single etching process and filling the channel material in the channel opening. Formed together. As the number of word lines increases, it is necessary to form a memory stack structure with a high aspect ratio. The formation of vertical channels is becoming more and more challenging. If vertical channel openings are formed by a single etching process, it is easy to cause process problems. It is impossible to form a channel layer with good electrical connection effect. Therefore, compared with the conventional example of forming the channel opening by a single etching process, this case uses a different process to form the first channel layer 104 in the first stack S1 before forming the second channel in the second stack S2. The layer 108 can improve the above-mentioned process problems, so that the first channel layer 104 and the second channel layer 108 can have a good electrical connection with the substrate 101 through the first conductive connector 152.

FIG. 2 is a cross-sectional view of a method of erasing operation of the semiconductor device 10 according to an embodiment of the present invention.

Please refer to Figures 1 and 2 at the same time. During an erasing operation, the erasing voltage _{Ver is} applied to the second conductive connection member 154 through a bit line (not shown), and the band tunneling (band The to band tunneling (BTB tunneling) mechanism increases the potential of the second channel layer 108, and then injects holes into the second memory layer 106. During the erasing operation, the high potential of the second channel layer 108 increases the potential of the first conductive connection 152, and another band-to-band tunneling mechanism further increases the potential of the first channel layer 104. Then, holes are injected into the first memory layer 102, where the first channel layer 104 and the second channel layer 108 respectively have a first internal voltage and a second internal voltage different from the first internal voltage. In some embodiments, the second internal voltage is greater than the first internal voltage. Since there is a voltage difference between the first internal voltage and the second internal voltage, during this erasing operation, it is necessary to apply the first voltage V ₁ to the first conductive layer 111~113... A second voltage V _{2 of the} voltage V ₁ is applied to the second conductive layers 131 to 133, so that the erasing speed of all the memory cells M of the first stack S1 and the second stack S2 can be consistent. In addition, during the erasing operation, the substrate 101 and the first conductive connection member 152 are floating. That is, no voltage is applied to the substrate 101 and the first conductive connection member 152.

In some embodiments, the second voltage V _{2 is} greater than the first voltage V ₁ ; the erasing voltage _{Ver is} greater than the first voltage V ₁ and the second voltage V ₂ ; the voltage between the first voltage V ₁ and the first internal voltage The difference is equal to the voltage difference between the second voltage V ₂ and the second internal voltage. In some embodiments, the voltage difference between the second voltage V ₂ and the first voltage V ₁ is greater than 0 and less than 5V.

Compared with the comparative example in which the erasing voltage is applied to the substrate, since the erasing voltage Ver of one embodiment of the present invention is applied to the second conductive connection member 154, the substrate 101 is floating, and the N-type dopant is removed from the substrate. The degree of diffusion of 101 to the first channel layer 104 can be reduced, so that excessive waste of the use of the ground selection line device can be avoided. For example, in the comparative example of applying the erasing voltage to the substrate, at least three ground selection line devices adjacent to the substrate cannot perform normal functions. In the present invention, the number of ground selection line devices that cannot be used can be reduced to two. Below. In this way, the semiconductor device 10 of the present invention can be used more efficiently.

FIG. 3 is a waveform diagram of the erase operation of the semiconductor device 10 according to an embodiment of the invention.

Please refer to FIG. 3, which shows the waveform deduction of the incremental step pulse erase (ISPE) of the semiconductor device 10. The bit line voltage V _B indicates that when the erasing voltage _{Ver is} applied to the second conductive connection member 154 by the bit line (not shown), the voltage of the bit line is derived from different waveforms with time. The first conductive layer voltage V _L represents the different waveforms of the voltages of the first conductive layers 111 to 113... over time when the first voltage V ₁ is applied to the first conductive layers 111 to 113... in the first stack S1 Deduction. The second conductive layer voltage V _U indicates that when the second voltage V ₂ is applied to the second conductive layers 131 to 133... in the second stack S2, the voltages of the second conductive layers 131 to 133... are derived from different waveforms over time . It can be seen from the results in Fig. 3 that as time increases, the erasing voltage _Ver gradually increases (for example, 1V every 2 milliseconds), the first voltage V ₁ maintains 0V, and the second voltage V ₂ maintains 2V.

According to the above-mentioned embodiments, the present invention provides a semiconductor device and an operating method thereof. The semiconductor device includes a substrate, a first stack and a second stack. The substrate has an upper surface, wherein the substrate includes a doped region extending downward from the upper surface, and the doped region has a first doping concentration. The first stack is disposed on the upper surface, wherein the first stack includes a plurality of first insulating layers and a plurality of first conductive layers, a first channel layer, a first memory layer, and a first conductive connection member alternately stacked. The first conductive layer is configured to receive a first voltage. The first channel layer passes through the first stack. The first memory layer surrounds the first channel layer. The first conductive connection member is disposed on the first channel layer and has a second doping concentration. The second stack is disposed on the first conductive connection member and located on the first stack, wherein the second stack includes a plurality of second insulating layers and a plurality of second conductive layers stacked alternately, a second channel layer, and a second The memory layer and a second conductive connection member, wherein the second conductive layer is configured to receive a second voltage different from the first voltage. The second channel layer passes through the second stack, and the second memory layer surrounds the second channel layer. The second conductive connection member is arranged on the second channel layer. The second conductive connection member has a third doping concentration and is configured to receive an erasing voltage, wherein the first conductive connection member is electrically connected to the first channel layer and the second channel layer. The first doping concentration is less than the second doping concentration and the third doping concentration.

Compared with the comparative example with heavily doped N-type dopants in the substrate, since the N-type doped region of the substrate of the semiconductor device of the present invention has a lower doping concentration, the N-type doping can be reduced. To the extent that the mass escapes from the substrate to the channel layer, the situation where the ground selection line device is affected can be improved. In addition, since the erasing voltage is applied to the second conductive connection member instead of the substrate during the erasing operation, the ground selection line device adjacent to the substrate can be slowed to be continuously turned on due to the influence of the N-type dopants. In the case of failure to function, the utilization rate of the ground selection line device in the semiconductor device can be improved. Furthermore, by applying different first voltages and second voltages to the first conductive layer and the second conductive layer, the internal voltages of the first channel layer and the second channel layer are not the same, so that the first The erasing speed of all memory cells in the same series in the stack and the second stack can be the same.

In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to those defined by the attached patent scope.

10: semiconductor device 100a: peripheral circuit part 100b: array part 101: substrate 101s: upper surface 101R: doped area 102: first memory layer 103: first insulating pillar 104: first channel layer 105: second insulating pillar 106 : Second memory layer 108: second channel layer 111~113: first conductive layer 116: first dielectric layer 121~124: first insulating layer 131~133: second conductive layer 136: second dielectric layer 141 ~144: second insulating layer 152: first conductive connection 154: second conductive connection 156: interconnection 158: cover layer C1: metal oxide semiconductor structure M: memory cell S1: first stack S2: second stack T _G: ground selection line transistor T _S: series select line transistor V _1: a first voltage V _2: the second voltage V _B: bit line voltage V _er: erase voltage V _L: a first conductive layer voltage V _U : second conductive layer voltage

FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the invention. FIG. 2 is a cross-sectional view of a method of erasing a semiconductor device according to an embodiment of the invention. FIG. 3 is a waveform diagram of the erase operation of the semiconductor device according to an embodiment of the invention.

10: Semiconductor device

101: substrate

101s: upper surface

101R: doped area

102: The first memory layer

104: The first channel layer

106: second memory layer

108: second channel layer

111~113: the first conductive layer

116: first dielectric layer

121~124: first insulating layer

131~133: second conductive layer

136: second dielectric layer

141~144: second insulating layer

152: The first conductive connection

154: second conductive connection

S1: First stack

S2: second stack

V ₁ : first voltage

V ₂ : second voltage

V _er : erase voltage

Claims (10)

A semiconductor device including: A substrate having an upper surface, wherein the substrate includes a doped region extending downward from the upper surface, and the doped region has a first doping concentration; A first stack is disposed on the upper surface, wherein the first stack includes: A plurality of first insulating layers and a plurality of first conductive layers alternately stacked, wherein the first conductive layers are configured to receive a first voltage; A first channel layer passing through the first stack; A first memory layer surrounding the first channel layer; and A first conductive connection member disposed on the first channel layer and having a second doping concentration; A second stack is disposed on the first stack, wherein the second stack includes: A plurality of second insulating layers and a plurality of second conductive layers alternately stacked, wherein the second conductive layers are configured to receive a second voltage different from the first voltage; A second channel layer passing through the second stack; A second memory layer surrounding the second channel layer; and A second conductive connection member is disposed on the second channel layer, the second conductive connection member has a third doping concentration and is configured to receive an erase voltage, wherein the first conductive connection member is electrically connected to the second A channel layer and the second channel layer; The first doping concentration is less than the second doping concentration and the third doping concentration. According to the semiconductor device described in claim 1, wherein the first doping concentration is less than 5×10 ¹⁸ cm ^-3 . The semiconductor device described in claim 1, wherein the second voltage is greater than the first voltage. The semiconductor device described in item 1 of the scope of the patent application further includes a peripheral circuit portion, and the peripheral circuit portion is disposed under the substrate. An operating method of a semiconductor device includes: The semiconductor device is provided, and the semiconductor device includes: A substrate having an upper surface, wherein the substrate includes a doped region extending downward from the upper surface, and the doped region has a first doping concentration; A first stack is disposed on the upper surface, wherein the first stack includes: A plurality of first insulating layers and a plurality of first conductive layers stacked alternately; A first channel layer passing through the first stack; A first memory layer surrounding the first channel layer; and A first conductive connection member disposed on the first channel layer and having a second doping concentration; A second stack is disposed on the first stack, wherein the second stack includes: A plurality of second insulating layers and a plurality of second conductive layers stacked alternately; A second channel layer passing through the second stack; A second memory layer surrounding the second channel layer; and A second conductive connection element is disposed on the second channel layer, the second conductive connection element has a third doping concentration, and the first conductive connection element is electrically connected to the first channel layer and the second channel Floor; Wherein the first doping concentration is less than the second doping concentration and the third doping concentration; Applying an erasing voltage to the second conductive connection member during an erasing operation; Applying a first voltage to the first conductive layers during the erasing operation; and Applying a second voltage to the second conductive layers during the erasing operation; The second voltage is greater than the first voltage. According to the operation method of the semiconductor device described in the 5th patent application, the first doping concentration is less than 5×10 ¹⁸ cm ^-3 . According to the operating method of the semiconductor device described in the 5th patent application, the voltage difference between the second voltage and the first voltage is less than 5V. According to the method of operating a semiconductor device described in the 5th item of the scope of the patent application, the substrate is floating during the erasing operation. According to the method of operating a semiconductor device as described in item 5 of the scope of the patent application, during the erasing operation, the first conductive connection member is floating. According to the operation method of the semiconductor device described in the fifth item of the scope of the patent application, during the erasing operation, the erasing voltage is greater than the first voltage and the second voltage.

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