TWI699774B - Semiconductor device and operating method thereof - Google Patents
Semiconductor device and operating method thereof Download PDFInfo
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本發明是有關於一種半導體裝置,且特別是有關於週邊電路部分與陣列部分垂直堆疊的一種半導體裝置。The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a peripheral circuit part and an array part are vertically stacked.
近來,為了減小晶片的尺寸,將記憶體陣列部分垂直堆疊於週邊電路部分上的半導體結構(亦即是電路設置於陣列下(Circuit under array, CUA)越來越受到歡迎。在此種結構中,記憶體陣列部分一般包括一半導體基板;複數絕緣層和多晶矽層交錯堆疊在半導體基板上所形成的多層堆疊結構;依序在穿過多層堆疊結構之貫穿開口的側壁上所形成的記憶層(例如氮氧化矽-氧化物-氮化物-氧化物的記憶層、氧化物-氮化物-氧化物-氮化物-氧化物(BE-SONOS)的記憶層、或電荷捕捉記憶體(charge trapping memory))以及多晶矽通道層;以及在通道層、記憶層以及多晶矽層上定義出的複數個記憶胞。記憶胞是藉由通道層與作為底部共用源極線的半導體基板電性連接。其中,半導體基板通常需要摻雜高濃度的N型半導體摻雜物,使得底部共用源極線可用來進行記憶體陣列部分的區塊抹除(block erase)操作。Recently, in order to reduce the size of the chip, the semiconductor structure (that is, the circuit under array (CUA)) in which the memory array portion is vertically stacked on the peripheral circuit portion has become more and more popular. In this structure Among them, the memory array part generally includes a semiconductor substrate; a multi-layer stack structure formed by alternately stacking a plurality of insulating layers and polysilicon layers on the semiconductor substrate; and a memory layer formed in sequence on the sidewalls of the through openings passing through the multi-layer stack structure (E.g. silicon oxynitride-oxide-nitride-oxide memory layer, oxide-nitride-oxide-nitride-oxide (BE-SONOS) memory layer, or charge trapping memory )) and a polysilicon channel layer; and a plurality of memory cells defined on the channel layer, memory layer, and polysilicon layer. The memory cells are electrically connected to the semiconductor substrate as the bottom common source line through the channel layer. Among them, the semiconductor The substrate usually needs to be doped with high-concentration N-type semiconductor dopants, so that the bottom common source line can be used for block erase operations of the memory array portion.
然而,經過半導體裝置的製程之後(例如是熱製程),半導體基板中的N型摻雜物卻容易經由通道層向上擴散,進而影響鄰近於基板之接地選擇線裝置的功能。However, after the manufacturing process of the semiconductor device (for example, a thermal process), the N-type dopants in the semiconductor substrate easily diffuse upward through the channel layer, thereby affecting the function of the ground selection line device adjacent to the substrate.
因此,有需要提供一種垂直通道快閃記憶體元件,來解決習知技術所面臨的問題。Therefore, there is a need to provide a vertical channel flash memory device to solve the problems faced by the prior art.
本發明係有關於一種半導體裝置。由於本發明的半導體裝置的基板的N型摻雜區之中具有較低的摻雜濃度(例如是小於5×10 18cm -3),能夠減輕半導體裝置的基板的N型摻雜質散逸至通道層而影響接地選擇線裝置(ground select line device, GSL device)的情形,故可提高接地選擇線裝置的利用率。 The present invention relates to a semiconductor device. Since the N-type doping region of the substrate of the semiconductor device of the present invention has a relatively low doping concentration (for example, less than 5×10 18 cm -3 ), it can reduce the dissipation of the N-type dopant of the substrate of the semiconductor device to The channel layer affects the ground select line device (GSL device), so the utilization rate of the ground select line device can be improved.
根據本發明之一方面,提出一種半導體裝置。半導體裝置包括一基板、一第一堆疊及一第二堆疊。基板具有一上表面,其中基板包括由上表面向下延伸的一摻雜區,摻雜區具有一第一摻雜濃度。第一堆疊設置於上表面上,其中第一堆疊包括交替堆疊的複數個第一絕緣層及複數個第一導電層、一第一通道層、一第一記憶層以及一第一導電連接件。第一導電層配置為接收一第一電壓。第一通道層穿過第一堆疊。第一記憶層環繞第一通道層。第一導電連接件設置於第一通道層上,且具有一第二摻雜濃度。第二堆疊設置於第一導電連接件上且位於第一堆疊之上,其中第二堆疊包括交替堆疊的複數個第二絕緣層及複數個第二導電層、一第二通道層、一第二記憶層以及一第二導電連接件,其中第二導電層配置為接收不同於該第一電壓的一第二電壓。第二通道層穿過第二堆疊,第二記憶層環繞第二通道層。第二導電連接件設置於第二通道層上。第二導電連接件具有一第三摻雜濃度,且配置為接收一抹除電壓,其中第一導電連接件電性連接第一通道層及第二通道層。第一摻雜濃度小於第二摻雜濃度及第三摻雜濃度。According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a substrate, a first stack and a second stack. The substrate has an upper surface, wherein the substrate includes a doped region extending downward from the upper surface, and the doped region has a first doping concentration. The first stack is disposed on the upper surface, wherein the first stack includes a plurality of first insulating layers and a plurality of first conductive layers, a first channel layer, a first memory layer, and a first conductive connection member alternately stacked. The first conductive layer is configured to receive a first voltage. The first channel layer passes through the first stack. The first memory layer surrounds the first channel layer. The first conductive connection member is disposed on the first channel layer and has a second doping concentration. The second stack is disposed on the first conductive connection member and located on the first stack, wherein the second stack includes a plurality of second insulating layers and a plurality of second conductive layers stacked alternately, a second channel layer, and a second The memory layer and a second conductive connection member, wherein the second conductive layer is configured to receive a second voltage different from the first voltage. The second channel layer passes through the second stack, and the second memory layer surrounds the second channel layer. The second conductive connection member is arranged on the second channel layer. The second conductive connection member has a third doping concentration and is configured to receive an erasing voltage, wherein the first conductive connection member is electrically connected to the first channel layer and the second channel layer. The first doping concentration is less than the second doping concentration and the third doping concentration.
根據本發明之另一方面,提出一種半導體裝置的操作方法。此方法包括下列步驟。首先,提供此半導體裝置。半導體裝置包括一基板、一第一堆疊及一第二堆疊。基板具有一上表面,其中基板包括由上表面向下延伸的一摻雜區,摻雜區具有一第一摻雜濃度。第一堆疊設置於上表面上,其中第一堆疊包括交替堆疊的複數個第一絕緣層及複數個第一導電層、一第一通道層、一第一記憶層以及一第一導電連接件。第一通道層穿過第一堆疊。第一記憶層環繞第一通道層。第一導電連接件設置於第一通道層上,且具有一第二摻雜濃度。第二堆疊設置於第一導電連接件上且位於第一堆疊之上,其中第二堆疊包括交替堆疊的複數個第二絕緣層及複數個第二導電層、一第二通道層、一第二記憶層以及一第二導電連接件。第二通道層穿過第二堆疊,第二記憶層環繞第二通道層。第二導電連接件設置於第二通道層上。第二導電連接件具有一第三摻雜濃度,其中第一導電連接件電性連接第一通道層及第二通道層。第一摻雜濃度小於第二摻雜濃度及第三摻雜濃度。接著,在一抹除操作的期間,施加抹除電壓至第二導電連接件上;在抹除操作的期間,施加第一電壓至第一導電層上;以及在抹除操作的期間,施加第二電壓於第二導電層上;其中第二電壓大於第一電壓。According to another aspect of the present invention, an operating method of a semiconductor device is provided. This method includes the following steps. First, this semiconductor device is provided. The semiconductor device includes a substrate, a first stack and a second stack. The substrate has an upper surface, wherein the substrate includes a doped region extending downward from the upper surface, and the doped region has a first doping concentration. The first stack is disposed on the upper surface, wherein the first stack includes a plurality of first insulating layers and a plurality of first conductive layers, a first channel layer, a first memory layer, and a first conductive connection member alternately stacked. The first channel layer passes through the first stack. The first memory layer surrounds the first channel layer. The first conductive connection member is disposed on the first channel layer and has a second doping concentration. The second stack is disposed on the first conductive connection member and located on the first stack, wherein the second stack includes a plurality of second insulating layers and a plurality of second conductive layers stacked alternately, a second channel layer, and a second The memory layer and a second conductive connection member. The second channel layer passes through the second stack, and the second memory layer surrounds the second channel layer. The second conductive connection member is arranged on the second channel layer. The second conductive connection member has a third doping concentration, and the first conductive connection member is electrically connected to the first channel layer and the second channel layer. The first doping concentration is less than the second doping concentration and the third doping concentration. Then, during an erase operation, apply an erase voltage to the second conductive connection; during an erase operation, apply a first voltage to the first conductive layer; and during an erase operation, apply a second The voltage is on the second conductive layer; wherein the second voltage is greater than the first voltage.
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式詳細說明如下:In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are described in detail with the accompanying drawings as follows:
第1圖繪示依照本發明一實施例的半導體裝置10的剖面圖。FIG. 1 shows a cross-sectional view of a
請參照第1圖,半導體裝置10包括一週邊電路部分100a以及一陣列部分100b,其中陣列部分100b位於週邊電路部分100a上。週邊電路部分100a包括金氧半導體結構(Complementary Metal-Oxide-Semiconductor structure )C1及其他合適的結構。陣列部分100b包括一基板101、一第一堆疊S1、一第二堆疊S2、一內連線156及一覆蓋層158。第二堆疊S2設置於第一堆疊S1之上。基板101具有一上表面101s,且包括由上表面101s向下延伸的一摻雜區101R。週邊電路部分100a設置於基板101之下。在一些實施例中,包括第一堆疊S1及第二堆疊S2的陣列部分100b是與週邊電路部分100a在上表面101s的法線方向上互相重疊。Referring to FIG. 1, the
本發明的陣列部分100b示例性描述環繞式閘極(Gate-all-around, GAA)的記憶體結構的實施例 ,然本發明並不限於此,本發明的陣列部分100b可為任何氮化物基的記憶體材料的非揮發性記憶體結構。The
第一堆疊S1設置於上表面101s上,其中第一堆疊S1包括沿著Z軸方向交替堆疊的多個第一絕緣層121~124…及多個第一導電層111~113…。第1圖僅示例性繪示第一堆疊S1中的其中3個第一導電層111~113及4個第一絕緣層121~124,然本發明並不以此為限,第一堆疊S1中可包括更多層的導電層及絕緣層。在本實施例之中,第一絕緣層121及124分別是位於第一堆疊S1的底層以及最頂層,而第一絕緣層121是與基板101直接接觸。第一導電層111~113配置為接收一第一電壓V
1(繪示於第2圖中)。第一絕緣柱103、第一通道層104及第一記憶層102垂直穿過第一堆疊S1(例如是沿著Z軸方向)。其中,第一通道層104及第一記憶層102環繞第一絕緣柱103。第一記憶層102環繞第一通道層104。第一記憶層102位於第一通道層104、第一絕緣層121~124及第一導電層111~113之間。第一導電連接件152設置於第一記憶層102、第一絕緣柱103及第一通道層104上,且電性接觸於第一通道層104。第一介電層116位於第一記憶層102、第一絕緣層121~124及第一導電層111~113之間,且可環繞第一導電層111~113。
The first stack S1 is disposed on the
第二堆疊S2設置於第一堆疊S1上,其中第二堆疊S2包括沿著Z軸方向交替堆疊的多個第二絕緣層141~144…及多個第二導電層131~133…。第1圖僅示例性繪示第二堆疊S2中的其中3個第二導電層131~133及4個第二絕緣層141~144,然本發明並不以此為限,第二堆疊S2中可包括更多層的導電層及絕緣層。The second stack S2 is disposed on the first stack S1, wherein the second stack S2 includes a plurality of second
在本實施例之中,第二絕緣層141及144分別是位於第二堆疊S2的底層以及最頂層。第二導電層131~133配置為接收不同於第一電壓V
1的一第二電壓V
2(繪示於第2圖中)。在一些實施例中,第二電壓V
2大於第一電壓V
1。第二絕緣柱105、第二通道層108及第二記憶層106垂直穿過第二堆疊S2(例如是沿著Z軸方向)。其中,第二通道層108及第二記憶層106環繞第二絕緣柱105。第二記憶層106環繞第二通道層108。第二記憶層106位於第二通道層108、第二絕緣層141~144及第二導電層131~133之間。第二導電連接件154設置於第二絕緣柱105、第二記憶層106及第二通道層108上,且電性接觸於第二通道層108。第二導電連接件154配置為接收一抹除電壓V
er(繪示於第2圖中)。第一導電連接件152位於第一通道層104與第二通道層108之間,並電性連接於第一通道層104與第二通道層108。第二介電層136位於第二記憶層106、第二絕緣層141~144及第二導電層131~133之間,且可環繞第二導電層131~133。內連線156電性接觸於第二導電連接件154。覆蓋層158位於第二堆疊S2上。
In this embodiment, the second insulating
在一些實施例中,基板101例如是矽基板或其他合適的基板,例如是N型摻雜的多晶矽基板。第一導電連接件152及第二導電連接件154例如是N型摻雜的多晶矽層。基板101的摻雜區101R、第一導電連接件152及第二導電連接件154可分別藉由N型摻雜質所摻雜,而分別具有一第一摻雜濃度、一第二摻雜濃度及一第三摻雜濃度。第一摻雜濃度可不同於第二摻雜濃度及第三摻雜濃度。例如,第一摻雜濃度可小於 5×10
18cm
-3,第二摻雜濃度及第三摻雜濃度可分別大於1×10
19cm
-3。在一些實施例中,第一摻雜濃度小於第二摻雜濃度及第三摻雜濃度,且第二摻雜濃度可相同於第三摻雜濃度。在一些實施例中,第二摻雜濃度可小於第三摻雜濃度。相較於基板具有高濃度的N型摻雜物(例如是大於1×10
19cm
-3)的比較例而言,由於本案的基板101的摻雜區101R的第一摻雜濃度較低,可降低N型摻雜物散逸至第一通道層104的程度,因而可減緩鄰近於基板101的接地選擇線裝置(例如是第一導電層111、112與第一記憶層102之間的交叉位置所形成的電晶體)受到N型摻雜物的影響而持續導通,進而無法發揮功能的情形。
In some embodiments, the
舉例而言,第一導電層111~113中最接近於基板101的第一導電層111可作為接地選擇線(Ground select line, GSL),而最接近於基板101的第一導電層111、第一記憶層102與第一通道層104的交叉部分可形成一接地選擇線電晶體T
G。第二導電層131~133中最接近第二導電連接件154的第二導電層133可作為串列選擇線(String Select Line, SSL) ,而最接近第二導電連接件154的第二導電層133、第二記憶層106與第二通道層108的交叉部分可形成一串列選擇線電晶體T
S。位於接地選擇線與串列選擇線之間的第一導電層112、113…及第二導電層131、132…可作為字元線(WL)。第一導電層112、113…、第二導電層131, 132…、第一記憶層102與第二記憶層106之間的每個交叉點可形成用於儲存數據的記憶胞M。由第一導電層112、113…,第二導電層131、132…,第一記憶層102、第二記憶層106、第一通道層104和第二通道層108所定義的記憶胞元M可以透過位元線(未繪示)電性耦接於解碼器(未繪示),解碼器例如是行解碼器或列解碼器。
For example, the first
假設鄰近於第一導電層111的第一通道層104受到N型摻雜物的干擾,則改採用第一導電層111上方的第一導電層112作為接地選擇線,並採用第一導電層112、第一記憶層102與第一通道層104之間的交叉點作為接地選擇線電晶體;假設鄰近於第一導電層112的第一通道層104受到N型摻雜物的干擾,則改採用第一導電層112上方的第一導電層作為接地選擇線,並採用第一導電層112上方的第一導電層、第一記憶層102與第一通道層104之間的交叉點作為接地選擇線電晶體,以此類推。Assuming that the
在一些實施例中,第一絕緣層121~124、第一導電層111~113、第一通道層104、第一記憶層104、第一絕緣柱103的材料可分別相同或類似於第二絕緣層141~144、第二導電層131~133、第二通道層108、第二記憶層106、第二絕緣柱105。第一絕緣層121~124、第一絕緣柱103、第二絕緣層141~144、第二絕緣柱105及覆蓋層158可由氧化物所形成,例如是二氧化矽(SiO
2)。第一導電層111~113與第二導電層131~133可由導電材料所形成,此導電材料例如是鎢(W)、氮化鈦(TiN)、氮化鉭(TaN)、或其他合適的材料。第一記憶層102及第二記憶層106可以由包含氧化矽(silicon oxide)層、氮化矽(silicon nitride)層和氧化矽層的複合層(即,ONO層)所構成。例如,第一記憶層102及第二記憶層106可分別包括穿隧層、捕捉層及阻擋層。穿隧層可包括氮氧化矽(SiON)及二氧化矽(SiO
2)所形成的雙層結構或其他合適的材料。捕捉層可包括氮化矽或其他合適的材料。阻擋層可包括二氧化矽(SiO
2)或其他合適的材料。第一介電層116及第二介電層136可包括一高介電常數材料(high k material),例如是氧化鋁(Al
2O
3)或其他合適的材料。第一通道層104及第二通道層108可為單晶或多晶矽層(亦可為磊晶成長層)。
In some embodiments, the materials of the first insulating
本發明實施例中的第一通道層104及第二通道層108是分別在不同製程步驟之下所形成的,並非是藉由單一次蝕刻製程形成通道開口並填入通道材料於通道開口中所一併形成的。隨著字元線的數量需求的增加,需要形成高深寬比的記憶體堆疊結構,垂直通道的形成受到越來越高的挑戰,若藉由單一次蝕刻製程形成垂直通道開口,容易造成製程上的失誤,而無法形成電性連接效果良好的通道層。因此,相較於一般藉由單一次蝕刻製程形成通道開口的比較例而言,本案藉由不同製程在第一堆疊S1中形成第一通道層104之後才在第二堆疊S2中形成第二通道層108,如此可改善上述的製程問題,使得第一通道層104與第二通道層108可透過第一導電連接件152而與基板101具有良好的電性連接。In the embodiment of the present invention, the
第2圖繪示依照本發明一實施例的半導體裝置10的抹除操作的方法的剖面圖。FIG. 2 is a cross-sectional view of a method of erasing operation of the
請同時參照第1及2圖,在一抹除操作的期間,藉由位元線(未繪示)施加抹除電壓V
er至第二導電連接件154上,並藉由帶間隧穿(band to band tunneling, BTB tunneling)的機制提高第二通道層108的電位,接著將電洞注入第二記憶層106中。在此抹除操作的期間,藉由第二通道層108的高電位提高第一導電連接件152的電位,並藉由另一次的帶間隧穿的機制進一步提高第一通道層104的電位,接著將電洞注入第一記憶層102中,其中第一通道層104及第二通道層108分別具有一第一內部電壓及不同於第一內部電壓的一第二內部電壓。在一些實施例中,第二內部電壓大於第一內部電壓。由於第一內部電壓與第二內部電壓之間具有電壓差,故在此抹除操作的期間,需要施加第一電壓V
1至第一導電層上111~113…上,並施加不同於第一電壓V
1的一第二電壓V
2至第二導電層131~133上,使得第一堆疊S1與第二堆疊S2的所有記憶胞M的抹除速度能夠一致。此外,在抹除操作的期間,基板101及第一導電連接件152為浮接(floating)。亦即,基板101及第一導電連接件152並沒有施加任何的電壓。
Please refer to Figures 1 and 2 at the same time. During an erasing operation, the erasing voltage Ver is applied to the second
在一些實施例中,第二電壓V 2大於第一電壓V 1;抹除電壓V er大於第一電壓V 1及第二電壓V 2;第一電壓V 1與第一內部電壓之間的電壓差是等於第二電壓V 2與第二內部電壓之間的電壓差。在一些實施例中,第二電壓V 2與第一電壓V 1之間的電壓差是大於0且小於5 V。 In some embodiments, the second voltage V 2 is greater than the first voltage V 1 ; the erasing voltage Ver is greater than the first voltage V 1 and the second voltage V 2 ; the voltage between the first voltage V 1 and the first internal voltage The difference is equal to the voltage difference between the second voltage V 2 and the second internal voltage. In some embodiments, the voltage difference between the second voltage V 2 and the first voltage V 1 is greater than 0 and less than 5V.
相較於施加抹除電壓至基板的比較例而言,由於本發明之一實施例的抹除電壓Ver是施加至第二導電連接件154,基板101為浮接,N型摻雜物由基板101擴散至第一通道層104的程度可較為降低,故可避免過於浪費接地選擇線裝置的使用。例如,在施加抹除電壓至基板的比較例中,至少有3個鄰近於基板的接地選擇線裝置無法執行正常的功能,而本發明中,無法使用的接地選擇線裝置的數量可下降至2個以下。如此一來,本發明的半導體裝置10可作為更有效率的利用。Compared with the comparative example in which the erasing voltage is applied to the substrate, since the erasing voltage Ver of one embodiment of the present invention is applied to the second
第3圖繪示依照本發明一實施例的半導體裝置10的抹除操作的波形圖。FIG. 3 is a waveform diagram of the erase operation of the
請參照第3圖,其繪示對半導體裝置10進行增量步進脈衝抹除(incremental step pulse erase, ISPE)的波形推演。位元線電壓V
B表示藉由位元線(未繪示)施加抹除電壓V
er至第二導電連接件154上時,位元線的電壓隨著時間的不同的的波形推演。第一導電層電壓V
L表示施加第一電壓V
1至第一堆疊S1中的第一導電層111~113…上時,第一導電層111~113…的電壓隨著時間的不同的的波形推演。第二導電層電壓V
U表示施加第二電壓V
2至第二堆疊S2中的第二導電層131~133…上時,第二導電層131~133…的電壓隨著時間的不同的波形推演。由第3圖的結果可知,隨著時間的增加,抹除電壓V
er逐漸增加(例如是每2毫秒增加1V),第一電壓V
1維持0V,第二電壓V
2則維持2V。
Please refer to FIG. 3, which shows the waveform deduction of the incremental step pulse erase (ISPE) of the
根據上述實施例,本發明提供一種半導體裝置及其操作方法。半導體裝置包括一基板、一第一堆疊及一第二堆疊。基板具有一上表面,其中基板包括由上表面向下延伸的一摻雜區,摻雜區具有一第一摻雜濃度。第一堆疊設置於上表面上,其中第一堆疊包括交替堆疊的複數個第一絕緣層及複數個第一導電層、一第一通道層、一第一記憶層以及一第一導電連接件。第一導電層配置為接收一第一電壓。第一通道層穿過第一堆疊。第一記憶層環繞第一通道層。第一導電連接件設置於第一通道層上,且具有一第二摻雜濃度。第二堆疊設置於第一導電連接件上且位於第一堆疊之上,其中第二堆疊包括交替堆疊的複數個第二絕緣層及複數個第二導電層、一第二通道層、一第二記憶層以及一第二導電連接件,其中第二導電層配置為接收不同於第一電壓的一第二電壓。第二通道層穿過第二堆疊,第二記憶層環繞第二通道層。第二導電連接件設置於第二通道層上。第二導電連接件具有一第三摻雜濃度,且配置為接收一抹除電壓,其中第一導電連接件電性連接第一通道層及第二通道層。第一摻雜濃度小於第二摻雜濃度及第三摻雜濃度。According to the above-mentioned embodiments, the present invention provides a semiconductor device and an operating method thereof. The semiconductor device includes a substrate, a first stack and a second stack. The substrate has an upper surface, wherein the substrate includes a doped region extending downward from the upper surface, and the doped region has a first doping concentration. The first stack is disposed on the upper surface, wherein the first stack includes a plurality of first insulating layers and a plurality of first conductive layers, a first channel layer, a first memory layer, and a first conductive connection member alternately stacked. The first conductive layer is configured to receive a first voltage. The first channel layer passes through the first stack. The first memory layer surrounds the first channel layer. The first conductive connection member is disposed on the first channel layer and has a second doping concentration. The second stack is disposed on the first conductive connection member and located on the first stack, wherein the second stack includes a plurality of second insulating layers and a plurality of second conductive layers stacked alternately, a second channel layer, and a second The memory layer and a second conductive connection member, wherein the second conductive layer is configured to receive a second voltage different from the first voltage. The second channel layer passes through the second stack, and the second memory layer surrounds the second channel layer. The second conductive connection member is arranged on the second channel layer. The second conductive connection member has a third doping concentration and is configured to receive an erasing voltage, wherein the first conductive connection member is electrically connected to the first channel layer and the second channel layer. The first doping concentration is less than the second doping concentration and the third doping concentration.
相較於基板中有重摻雜N型摻雜質的比較例而言,由於本發明的半導體裝置的基板的N型摻雜區之中具有較低的摻雜濃度,能夠減輕N型摻雜質由基板散逸至通道層的程度,故可改善接地選擇線裝置受到影響的情形。此外,由於抹除操作期間是施加抹除電壓於第二導電連接件,而非是施加於基板,故可減緩鄰近於基板的接地選擇線裝置受到N型摻雜物的影響而持續導通,進而無法發揮功能的情形,因而可提高半導體裝置中接地選擇線裝置的利用率。再者,藉由分別施加不同的第一電壓及第二電壓至第一導電層及第二導電層上,可克服第一通道層及第二通道層的內部電壓不相同的情形,使得第一堆疊與第二堆疊中的相同串列的所有記憶胞的抹除速度能夠一致。Compared with the comparative example with heavily doped N-type dopants in the substrate, since the N-type doped region of the substrate of the semiconductor device of the present invention has a lower doping concentration, the N-type doping can be reduced. To the extent that the mass escapes from the substrate to the channel layer, the situation where the ground selection line device is affected can be improved. In addition, since the erasing voltage is applied to the second conductive connection member instead of the substrate during the erasing operation, the ground selection line device adjacent to the substrate can be slowed to be continuously turned on due to the influence of the N-type dopants. In the case of failure to function, the utilization rate of the ground selection line device in the semiconductor device can be improved. Furthermore, by applying different first voltages and second voltages to the first conductive layer and the second conductive layer, the internal voltages of the first channel layer and the second channel layer are not the same, so that the first The erasing speed of all memory cells in the same series in the stack and the second stack can be the same.
綜上所述,雖然本發明已以實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to those defined by the attached patent scope.
10:半導體裝置
100a:週邊電路部分
100b:陣列部分
101:基板
101s:上表面
101R:摻雜區
102:第一記憶層
103:第一絕緣柱
104:第一通道層
105:第二絕緣柱
106:第二記憶層
108:第二通道層
111~113:第一導電層
116:第一介電層
121~124:第一絕緣層
131~133:第二導電層
136:第二介電層
141~144:第二絕緣層
152:第一導電連接件
154:第二導電連接件
156:內連線
158:覆蓋層
C1:金氧半導體結構
M:記憶胞
S1:第一堆疊
S2:第二堆疊
TG:接地選擇線電晶體
TS:串列選擇線電晶體
V1:第一電壓
V2:第二電壓
VB:位元線電壓
Ver:抹除電壓
VL:第一導電層電壓
VU:第二導電層電壓10:
第1圖繪示依照本發明一實施例的半導體裝置的剖面圖。 第2圖繪示依照本發明一實施例的半導體裝置的抹除操作的方法的剖面圖。 第3圖繪示依照本發明一實施例的半導體裝置的抹除操作的波形圖。 FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the invention. FIG. 2 is a cross-sectional view of a method of erasing a semiconductor device according to an embodiment of the invention. FIG. 3 is a waveform diagram of the erase operation of the semiconductor device according to an embodiment of the invention.
10:半導體裝置 10: Semiconductor device
101:基板 101: substrate
101s:上表面 101s: upper surface
101R:摻雜區 101R: doped area
102:第一記憶層 102: The first memory layer
104:第一通道層 104: The first channel layer
106:第二記憶層 106: second memory layer
108:第二通道層 108: second channel layer
111~113:第一導電層 111~113: the first conductive layer
116:第一介電層 116: first dielectric layer
121~124:第一絕緣層 121~124: first insulating layer
131~133:第二導電層 131~133: second conductive layer
136:第二介電層 136: second dielectric layer
141~144:第二絕緣層 141~144: second insulating layer
152:第一導電連接件 152: The first conductive connection
154:第二導電連接件 154: second conductive connection
S1:第一堆疊 S1: First stack
S2:第二堆疊 S2: second stack
V1:第一電壓 V 1 : first voltage
V2:第二電壓 V 2 : second voltage
Ver:抹除電壓 V er : erase voltage
Claims (10)
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