TWI697091B - Semiconductor package having outer metal element and fabricating method thereof - Google Patents
Semiconductor package having outer metal element and fabricating method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
Description
本發明係關於一種半導體封裝結構及其製程,尤指一種具外金屬元件之半導體封裝結構及其製法。 The invention relates to a semiconductor packaging structure and its manufacturing process, in particular to a semiconductor packaging structure with external metal components and its manufacturing method.
在特殊應用之半導體封裝結構需要將天線一併整合至該半導體封裝結構中;然而,目前在具有天線的半導體封裝結構的製程中,是將天線元件與晶片及被動元件一併銲接在基板上,再壓模灌膠,以將天線、晶片及被動元件一次性封裝在一封裝體內。 In special application semiconductor packaging structures, it is necessary to integrate the antenna into the semiconductor packaging structure; however, at present, in the manufacturing process of a semiconductor packaging structure with an antenna, the antenna element is soldered to the substrate together with the chip and the passive element, Then the mold is filled with glue to encapsulate the antenna, the chip and the passive components in one package at a time.
目前製程雖與一般半導體封裝製程無異,但實際上天線位置必須高過晶片及被動元件,使得該封裝體厚度增加,除了膠材用量增加外,更需另外準備特製壓模模具,才能順利將天線、晶片及被動元件一次性封裝在一封裝體內,對於後續切割步驟中,切割較厚的封膠體也出現如:刀具壽命減短、切削速度減低、產量減低等問題,而切割後的半導體封裝結構也會有如:公差過大、切割面歪斜、偏移等等問題產生。 Although the current process is no different from the general semiconductor packaging process, in fact, the antenna position must be higher than the chip and passive components, so that the thickness of the package increases. In addition to the increase in the amount of glue, a special stamping mold must be prepared separately to successfully Antennas, chips and passive components are packaged in one package at a time. For subsequent cutting steps, cutting thicker encapsulants also has problems such as shortened tool life, reduced cutting speed, and reduced yield. The semiconductor package after cutting The structure may also have problems such as too large tolerances, skewed cutting surfaces, offsets, etc.
因此,針對目前具有天線的半導體封裝結構的製程有必要進一步改良之。 Therefore, it is necessary to further improve the current manufacturing process of the semiconductor packaging structure with an antenna.
有鑑於目前具有天線的半導體封裝結構的製程造成前揭諸多問題,本發明主要發明目的係提供一新的具外金屬元件之半導體封裝結構及其製法,以克服前揭問題。 In view of the fact that the current manufacturing process of the semiconductor packaging structure with an antenna causes many problems, the main object of the present invention is to provide a new semiconductor packaging structure with an external metal element and a manufacturing method thereof to overcome the problem of the previous disclosure.
欲達上述目的所使用的主要技術手段係令該具外金屬元件之半導體封裝結構包含有:一線路基板,其表面形成有複數第一接墊及複數第二接墊;複數電子元件,各該電子元件之接腳係分別電性連接於對應的元件接墊;一封膠層,係形成在該線路基板的表面上,以包覆該些電子元件於其中,且該封膠層係對應各該第二接墊位置形成有一貫穿孔,令各該第二接墊外露;一外金屬元件,係預先成型並電性連接該線路基板,並包含有:一金屬外板,係位在該封膠層之上,該金屬外板未平貼於該封膠體的上表面;以及複數金屬柱,係自該金屬外板底面向下垂直延伸,並分別電性連接至該第二接墊;以及一保護層,係充填於各該貫孔穿中,以與封膠體的上表面平齊。 The main technical means used to achieve the above purpose is that the semiconductor package structure with external metal components includes: a circuit substrate on which a plurality of first pads and a plurality of second pads are formed on the surface; a plurality of electronic components, each of which The pins of the electronic components are respectively electrically connected to the corresponding component pads; an adhesive layer is formed on the surface of the circuit substrate to cover the electronic components therein, and the sealing layer corresponds to each A through hole is formed at the position of the second pad to expose each of the second pads; an outer metal element is pre-formed and electrically connected to the circuit board, and includes: a metal outer plate, which is located at the seal Above the adhesive layer, the metal outer plate is not flat on the upper surface of the sealing body; and a plurality of metal pillars extend vertically downward from the bottom surface of the metal outer plate and are electrically connected to the second pads, respectively; and A protective layer is filled in each of the through holes to be flush with the upper surface of the sealant.
由上述說明可知,本發明的具外金屬元件之半導體封裝結構係主要於形成該封膠體後才進行外金屬元件的封裝;如此,本發明的半導體封裝結構的封膠體不必另外準備特製的壓模模具來增厚封膠層以包覆該外金屬元件,可維持切割用刀具壽命以及切削的後的半導體封裝結構不會歪斜或偏移,確保製程良率。 As can be seen from the above description, the semiconductor package structure with an external metal element of the present invention is mainly used to encapsulate the external metal element after forming the encapsulant; thus, the encapsulant of the semiconductor package structure of the present invention does not need to separately prepare a special stamper The mold is used to thicken the sealant layer to cover the outer metal component, which can maintain the life of the cutting tool and the semiconductor package structure after cutting without skew or deviation, ensuring the yield of the process.
欲達上述目的所使用的主要技術手段係令該具外金屬元件之半導體封裝結構的製法包含以下步驟: (a)準備一線路基板及複數預先成型的外金屬元件,該線路基板包含有複數個元件區域;其中於各元件區域中,該線路基板的一第一表面上分別包含有複數第一接墊及複數第二接墊;(b)將複數電子元件電性連接至對應的第一接墊上;(c)於該線路基板的第一表面形成有一封膠體,以包覆該些電子元件於其中;(d)自該封膠體的上表面向下對應各該第二接墊位置形成有一貫穿孔;(e)將該些預先成型之外金屬元件分別設置在各該元件區域之該封膠體之上,並透過該些貫穿孔與該第二接墊電性連接,又各該金屬外板未平貼於該封膠體的上表面;以及(f)於各該貫穿孔內充填有一保護層;其中,各該貫穿孔內的保護層與該封膠層平齊;以及(g)以該線路基板之元件區域的相鄰處為準,使用切具自該封膠體向下切開,以成形複數個獨立的具外金屬元件之半體封裝結構。 The main technical means used to achieve the above purpose is to make the manufacturing method of the semiconductor package structure with external metal components include the following steps: (a) prepare a circuit substrate and a plurality of pre-formed outer metal components, the circuit substrate includes a plurality of component regions; wherein in each component region, a first surface of the circuit substrate includes a plurality of first pads, respectively And a plurality of second pads; (b) electrically connect the plurality of electronic components to the corresponding first pads; (c) a gel is formed on the first surface of the circuit substrate to cover the electronic components therein ; (D) A through hole is formed downward from the upper surface of the sealing body corresponding to each second pad position; (e) The pre-formed metal components are respectively disposed in the sealing body of each of the component regions And electrically connect to the second pad through the through holes, and each of the metal outer plates is not flat on the upper surface of the sealant; and (f) a protective layer is filled in each of the through holes; Wherein, the protective layer in each of the through holes is flush with the sealant layer; and (g) Based on the adjacent part of the device area of the circuit substrate, a cutting tool is used to cut down from the sealant to form a plurality of An independent half-body package structure with external metal components.
由上述說明可知,本發明的製法係主要先形成該封膠體,之後才進行外金屬元件的封裝;如此,本發明的半導體封裝結構的封膠體不必另外準備特製的壓模模具來增厚封膠層以包覆該外金屬元件,可維持切割用刀具壽命以及切削的後的半導體封裝結構不會歪斜或偏移,確保製程良率。 It can be seen from the above description that the manufacturing method of the present invention mainly forms the encapsulant first, and then encapsulates the outer metal components; thus, the encapsulant of the semiconductor package structure of the present invention does not need to prepare a special stamper mold to thicken the encapsulant The layer covers the outer metal component, which can maintain the life of the cutting tool and the semiconductor package structure after cutting without skew or deviation, ensuring the yield of the process.
1、1’:半體封裝結構 1. 1’: Half body package structure
10:線路基板 10: circuit board
100:元件區域 100: component area
11:第一接墊 11: First pad
12:第二接墊 12: second pad
20:電子元件 20: Electronic components
30:封膠體 30: Sealant
31:貫穿孔 31: through hole
32:保護層 32: protective layer
40、40’:外金屬元件 40, 40’: outer metal components
41:金屬外板 41: Metal outer plate
42:金屬柱 42: Metal pillar
43:錫 43: Tin
43’:錫球 43’: Tin ball
圖1A至圖1H:係分別對應本發明之一半導體封裝結構製法的一半導體封裝結構的緃向剖面圖。 FIGS. 1A to 1H are cross-sectional views of a semiconductor package structure corresponding to a method of manufacturing a semiconductor package structure of the present invention.
圖2:係由圖1A至圖1D製法所製成的一半導體封裝結構的一緃向剖面圖。 FIG. 2 is a cross-sectional view of a semiconductor package structure made by the manufacturing method of FIGS. 1A to 1D.
圖3:係由圖1A至圖1D製法所製成的另一半導體封裝結構的一緃向剖面圖。 FIG. 3 is a cross-sectional view of another semiconductor package structure made by the manufacturing method of FIGS. 1A to 1D.
圖4A至圖4H:係分別對應本發明之另一半導體封裝結構製法的一半導體封裝結構的緃向剖面圖。 4A to 4H are cross-sectional views of a semiconductor package structure corresponding to another method of manufacturing a semiconductor package structure of the present invention.
本發明係針對具有外金屬元件之半導體封裝結構及其製法進行改良,避免使用特殊壓模模具來形成過厚的封膠體,以維持正常的封裝良率。以下謹以複數實施例配合圖式詳加說明本發明具有外金屬元件之半導體封裝結構及其製法的技術內容。 The present invention is to improve the semiconductor packaging structure with external metal components and its manufacturing method, avoiding the use of special stamper molds to form excessively thick encapsulants, so as to maintain normal packaging yield. The following is a detailed description of the technical contents of the semiconductor package structure with an external metal element and its manufacturing method according to the present invention in conjunction with a plurality of embodiments.
請參閱圖1A至圖1H所示,首先介紹本發明半導體封裝結構之製法的第一較佳實施例,其包括以下步驟: Please refer to FIG. 1A to FIG. 1H, the first preferred embodiment of the manufacturing method of the semiconductor package structure of the present invention is introduced first, which includes the following steps:
如圖1A所示,於步驟(a)中,先準備一線路基板10,該線路基板10包含有複數個元件區域100,於各元件區域100中,該線路基板10的一第一表面上分別包含有複數第一接墊11及複數第二接墊12。
As shown in FIG. 1A, in step (a), a
如圖1B所示,於步驟(b)中,將複數電子元件20電性連接至對應的第一接墊11上;於本實施例,該些電子元件20係銲接至對應的第一接墊11,且該些電子元件20包含有晶片及被動元件。
As shown in FIG. 1B, in step (b), a plurality of
如圖1C所示,於步驟(c)中,於該線路基板10的第一表面上形成有一封膠體30,該封膠體30用以包覆該些電子元件20於其中。於本實施例,係以一壓模模具於該線路基板10上灌入液態膠,待液態膠固化後即形成該封膠體30。
As shown in FIG. 1C, in step (c), a
如圖1D所示,於步驟(d)中,自該封膠體30的上表面向下對應各該第二接墊12位置形成有一貫穿孔31。於本實施例,係以一雷射開孔方式於該封膠體30的上表面形成該些貫穿孔31。
As shown in FIG. 1D, in step (d), a
如圖1E所示,於步驟(e)中,將預先成型的複數外金屬元件40分別對應設置在各該元件區域100之該封膠體30上,各該外金屬元件40再透過該些貫穿孔31與該第二接墊12電性連接。於本實施例,該外金屬元件40係包含有一金屬外板41及複數金屬柱42;其中各該金屬柱42係自該金屬外板41底面向下垂直延伸,且各該金屬柱42的一自由端係預先沾錫43後再置入對應的貫穿孔31後,以與該第二接墊12銲接;此外,該外金屬元件40係為一天線元件,該金屬外板41形成有天線圖案,而該些金屬柱42係作為該天線元件的訊號饋入接腳與電源訊號接腳。
As shown in FIG. 1E, in step (e), a plurality of pre-formed
如圖1F所示,於步驟(f)中,於各該貫穿孔31內充填有一保護層32,令該些金屬柱42與該第二接墊12與外界隔離,該保護層32係與該封膠層30的上表面平齊。
As shown in FIG. 1F, in step (f), each of the
如圖1G及圖1H所示,於步驟(g)中,以該線路基板10之元件區域100的相鄰處L為準,使用切具自該封膠體30向下切開,以成形複數個獨立的具外金屬元件之半體封裝結構1。
As shown in FIG. 1G and FIG. 1H, in step (g), the adjacent area L of the
即如圖2所示,以前揭製法的第一較佳實施例所製成的半導體封裝結構1包含有一線路基板10、複數電子元件20、一封膠層30、一外金屬元件40及一保護層32。
That is, as shown in FIG. 2, the
上述線路基板10的第一表面包含有複數第一接墊11及複數第二接墊12。
The first surface of the
該些電子元件20係分別電性連接於對應的第一接墊11;於本實施例,該些電子元件20係包含有晶片及被動元件。
The
該封膠層30係形成在該線路基板10的第一表面上,以包覆該些電子元件20於其中,且該封膠層30係對應各該第二接墊12位置形成有一貫穿孔31,令各該第二接墊12外露。
The
該外金屬元件40係電性連接該線路基板10,並包含有一金屬外板41及複數金屬柱42;其中該金屬外板41係位在該封膠層30之上,並與該封膠體30的上表面保持有一間距,而該些金屬柱42則自該金屬外板41底面向下垂直延伸,並分別電性連接至該第二接墊12;於本實施例,該些金屬柱42係銲接至該第二接墊12。
The
該保護層係充填於各該貫穿孔31內充填有一保護層32,並與該封膠層30的上表面平齊,令該些金屬柱42與該第二接墊12與外界隔離。
The protective layer is filled in each of the through-
再請參閱圖3所示,以前揭製法的第一較佳實施例所製成的另一半導體封裝結構1’,其同樣包含有一線路基板10、複數電子元件20、一封膠層30、一外金屬元件40’及一保護層34,惟該外金屬元件40’係為一金屬外殼,故其該金屬外板41係全面平貼於該封膠體30的上表面,作為散熱用;且各該金屬柱42係呈板狀,自該金屬外板41四周向下形成,以對應電性連接至該第二接墊12,而固定於該線路基板10上。又,為使該金屬外殼具有抗電磁干擾的功能,則其電性連接之該些第二接墊12係為接地訊號接墊。
Please refer to FIG. 3 again. Another semiconductor package structure 1'made by the first preferred embodiment of the previously disclosed manufacturing method also includes a
再請參閱圖4A至圖4H所示,為本發明半導體封裝結構之製法的第二較佳實施例,其包括以下步驟: Please refer to FIGS. 4A to 4H again, which is the second preferred embodiment of the manufacturing method of the semiconductor package structure of the present invention, which includes the following steps:
如圖4A所示,於步驟(a)中,先準備一線路基板10,該線路基板10包含有複數個元件區域100,於各元件區域100中,該線路基板10的一第一表面上分別包含有複數第一接墊11及複數第二接墊12。
As shown in FIG. 4A, in step (a), a
如圖4B所示,於步驟(b)中,將複數電子元件20電性連接至對應的第一接墊11上,並於各該第二接墊12上形成有錫球43’;於本實施例,該些電
子元件20係銲接至對應的第一接墊11,且該些電子元件20包含有晶片及被動元件。
As shown in FIG. 4B, in step (b), a plurality of
如圖4C所示,於步驟(c)中,於該線路基板10的第一表面上形成有一封膠體30,該封膠體30用以包覆該些電子元件20及錫球43’於其中。於本實施例,係以一壓模模具於該線路基板上灌入液態膠,待液態膠固化後即形成該封膠體30。
As shown in FIG. 4C, in step (c), a
如圖4D所示,於步驟(d)中,自該封膠體30的上表面向下對應各該第二接墊12位置形成有一貫穿孔31。於本實施例,係以一雷射開孔方式於該封膠體30的上表面形成該些貫穿孔31,由於雷射開孔時具有高熱,故可一併融熔該錫球43’。
As shown in FIG. 4D, in step (d), a through
如圖4E所示,於步驟(e)中,將預先成型的複數外金屬元件40分別對應設置在各該元件區域100之該封膠體30上,各該外金屬元件40再透過該些貫穿孔31與該第二接墊12電性連接。於本實施例,該外金屬元件40係包含有一金屬外板41及複數金屬柱42;其中各該金屬柱42係自該金屬外板41底面向下垂直延伸,且各該金屬柱42的一自由端係直接置入對應的貫穿孔31中,以與融熔的錫球43’接觸,待錫球43’固化後,即與該第二接墊12完成銲接。
As shown in FIG. 4E, in step (e), a plurality of pre-formed
如圖4F所示,於步驟(f)中,於各該貫穿孔31內充填有一保護層32,令該些金屬柱與42該第二接墊12與外界隔離。
As shown in FIG. 4F, in step (f), each of the through
如圖4G及圖4H所示,於步驟(g)中,以該線路基板10之元件區域100的相鄰處為準,使用切具自該封膠體30向下切開,以成形獨立的具外金屬元件之半體封裝結構1。
As shown in FIGS. 4G and 4H, in step (g), the adjacent area of the
綜上所述,由前揭本發明製法第一及第二較佳實施例可知,壓模灌膠形成封膠體步驟係在設置複數預先成型的外金屬元件之前,故可延用既有的半導體元件之壓模模具,無需另外準備特殊壓模模具,該封膠體的厚度也 只要足以包覆晶片、被動元件等即可,故可維持既有的厚度;之後,也只需要增加該封膠體開孔步驟,即可順利將該外金屬元件與該線路基板的第二接墊電性連接,開孔步驟已是封裝製程的既有製程技術,不必另外準備或設置相應的機台,而且不影響製程良率。因此,本發明的半導體封裝結構的外金屬元件的金屬外板即外露在封膠體之外,而不會被封膠體包覆。 In summary, from the first and second preferred embodiments of the manufacturing method of the present invention, it can be seen that the step of forming the sealant by the die-casting is before the provision of a plurality of pre-formed external metal components, so the existing semiconductor can be used For the component's stamping die, no special stamping die is required, and the thickness of the sealant is also As long as it is enough to cover the chip, passive components, etc., it can maintain the existing thickness; after that, it is only necessary to increase the opening step of the encapsulant to smoothly connect the external metal component and the second pad of the circuit substrate The electrical connection and the opening step are already the existing process technology of the packaging process. There is no need to separately prepare or set up corresponding machines, and it does not affect the process yield. Therefore, the metal outer plate of the outer metal element of the semiconductor package structure of the present invention is exposed outside the encapsulant without being covered by the encapsulant.
以上所述僅是本發明的實施例而已,並非對本發明做任何形式上的限制,雖然本發明已以實施例揭露如上,然而並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明技術方案的範圍內,當可利用上述揭示的技術內容作出些許更動或修飾為等同變化的等效實施例,但凡是未脫離本發明技術方案的內容,依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾,均仍屬於本發明技術方案的範圍內。 The above is only an embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed in the above embodiment, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field belongs to, Within the scope of not departing from the technical solution of the present invention, when the technical contents disclosed above can be used to make some changes or modifications to equivalent embodiments of equivalent changes, but any content that does not depart from the technical solution of the present invention is based on the technical essence of the present invention Any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the technical solution of the present invention.
1:半體封裝結構 1: Half body packaging structure
10:線路基板 10: circuit board
11:第一接墊 11: First pad
12:第二接墊 12: second pad
20:電子元件 20: Electronic components
30:封膠體 30: Sealant
31:貫穿孔 31: through hole
32:保護層 32: protective layer
40:外金屬元件 40: outer metal element
41:金屬外板 41: Metal outer plate
42:金屬柱 42: Metal pillar
43:錫 43: Tin
Claims (10)
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Citations (4)
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US20120062439A1 (en) * | 2010-09-09 | 2012-03-15 | Advanced Semiconductor Engineering, Inc. | Semiconductor package integrated with conformal shield and antenna |
TWM540392U (en) * | 2017-01-16 | 2017-04-21 | Jorjin Tech Inc | Minimized system-level package structure |
TW201834203A (en) * | 2017-01-27 | 2018-09-16 | 日商半導體能源研究所股份有限公司 | Capacitor, semiconductor device, and manufacturing method of semiconductor device |
TW201834249A (en) * | 2016-12-09 | 2018-09-16 | 日商半導體能源硏究所股份有限公司 | Semiconductor device and method for manufacturing the same |
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US20120062439A1 (en) * | 2010-09-09 | 2012-03-15 | Advanced Semiconductor Engineering, Inc. | Semiconductor package integrated with conformal shield and antenna |
TW201834249A (en) * | 2016-12-09 | 2018-09-16 | 日商半導體能源硏究所股份有限公司 | Semiconductor device and method for manufacturing the same |
TWM540392U (en) * | 2017-01-16 | 2017-04-21 | Jorjin Tech Inc | Minimized system-level package structure |
TW201834203A (en) * | 2017-01-27 | 2018-09-16 | 日商半導體能源研究所股份有限公司 | Capacitor, semiconductor device, and manufacturing method of semiconductor device |
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