TWI697091B - Semiconductor package having outer metal element and fabricating method thereof - Google Patents

Semiconductor package having outer metal element and fabricating method thereof Download PDF

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Publication number
TWI697091B
TWI697091B TW107133005A TW107133005A TWI697091B TW I697091 B TWI697091 B TW I697091B TW 107133005 A TW107133005 A TW 107133005A TW 107133005 A TW107133005 A TW 107133005A TW I697091 B TWI697091 B TW I697091B
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metal
outer plate
pads
pad
external
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TW107133005A
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Chinese (zh)
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TW202013665A (en
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尤啟仲
金惠彬
彭鈺朝
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力成科技股份有限公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

The present invention relates to a semiconductor package having outer metal element and fabricating method thereof. The semiconductor package has a circuit substrate having a plurality of first and second pads. A plurality of electronic devices electrically connected to the first pads. An encapsulation is formed on the circuit substrate to encapsulate the electric devices. A plurality of openings are formed through the encapsulation and the second pads are exposed to the openings. A previously-formed metal element plugs into the openings to electrically connect the second pads. Therefore, the metal element is placed outside the encapsulation and isn’t encapsulated in the encapsulation. A unique mold is not required to form the encapsulation. In addition, a thickness of the capsulation is not increased to encapsulate the metal element to ensure a production yield of the semiconductor package.

Description

具外金屬元件之半導體封裝結構及其製法Semiconductor packaging structure with external metal element and its manufacturing method

本發明係關於一種半導體封裝結構及其製程,尤指一種具外金屬元件之半導體封裝結構及其製法。 The invention relates to a semiconductor packaging structure and its manufacturing process, in particular to a semiconductor packaging structure with external metal components and its manufacturing method.

在特殊應用之半導體封裝結構需要將天線一併整合至該半導體封裝結構中;然而,目前在具有天線的半導體封裝結構的製程中,是將天線元件與晶片及被動元件一併銲接在基板上,再壓模灌膠,以將天線、晶片及被動元件一次性封裝在一封裝體內。 In special application semiconductor packaging structures, it is necessary to integrate the antenna into the semiconductor packaging structure; however, at present, in the manufacturing process of a semiconductor packaging structure with an antenna, the antenna element is soldered to the substrate together with the chip and the passive element, Then the mold is filled with glue to encapsulate the antenna, the chip and the passive components in one package at a time.

目前製程雖與一般半導體封裝製程無異,但實際上天線位置必須高過晶片及被動元件,使得該封裝體厚度增加,除了膠材用量增加外,更需另外準備特製壓模模具,才能順利將天線、晶片及被動元件一次性封裝在一封裝體內,對於後續切割步驟中,切割較厚的封膠體也出現如:刀具壽命減短、切削速度減低、產量減低等問題,而切割後的半導體封裝結構也會有如:公差過大、切割面歪斜、偏移等等問題產生。 Although the current process is no different from the general semiconductor packaging process, in fact, the antenna position must be higher than the chip and passive components, so that the thickness of the package increases. In addition to the increase in the amount of glue, a special stamping mold must be prepared separately to successfully Antennas, chips and passive components are packaged in one package at a time. For subsequent cutting steps, cutting thicker encapsulants also has problems such as shortened tool life, reduced cutting speed, and reduced yield. The semiconductor package after cutting The structure may also have problems such as too large tolerances, skewed cutting surfaces, offsets, etc.

因此,針對目前具有天線的半導體封裝結構的製程有必要進一步改良之。 Therefore, it is necessary to further improve the current manufacturing process of the semiconductor packaging structure with an antenna.

有鑑於目前具有天線的半導體封裝結構的製程造成前揭諸多問題,本發明主要發明目的係提供一新的具外金屬元件之半導體封裝結構及其製法,以克服前揭問題。 In view of the fact that the current manufacturing process of the semiconductor packaging structure with an antenna causes many problems, the main object of the present invention is to provide a new semiconductor packaging structure with an external metal element and a manufacturing method thereof to overcome the problem of the previous disclosure.

欲達上述目的所使用的主要技術手段係令該具外金屬元件之半導體封裝結構包含有:一線路基板,其表面形成有複數第一接墊及複數第二接墊;複數電子元件,各該電子元件之接腳係分別電性連接於對應的元件接墊;一封膠層,係形成在該線路基板的表面上,以包覆該些電子元件於其中,且該封膠層係對應各該第二接墊位置形成有一貫穿孔,令各該第二接墊外露;一外金屬元件,係預先成型並電性連接該線路基板,並包含有:一金屬外板,係位在該封膠層之上,該金屬外板未平貼於該封膠體的上表面;以及複數金屬柱,係自該金屬外板底面向下垂直延伸,並分別電性連接至該第二接墊;以及一保護層,係充填於各該貫孔穿中,以與封膠體的上表面平齊。 The main technical means used to achieve the above purpose is that the semiconductor package structure with external metal components includes: a circuit substrate on which a plurality of first pads and a plurality of second pads are formed on the surface; a plurality of electronic components, each of which The pins of the electronic components are respectively electrically connected to the corresponding component pads; an adhesive layer is formed on the surface of the circuit substrate to cover the electronic components therein, and the sealing layer corresponds to each A through hole is formed at the position of the second pad to expose each of the second pads; an outer metal element is pre-formed and electrically connected to the circuit board, and includes: a metal outer plate, which is located at the seal Above the adhesive layer, the metal outer plate is not flat on the upper surface of the sealing body; and a plurality of metal pillars extend vertically downward from the bottom surface of the metal outer plate and are electrically connected to the second pads, respectively; and A protective layer is filled in each of the through holes to be flush with the upper surface of the sealant.

由上述說明可知,本發明的具外金屬元件之半導體封裝結構係主要於形成該封膠體後才進行外金屬元件的封裝;如此,本發明的半導體封裝結構的封膠體不必另外準備特製的壓模模具來增厚封膠層以包覆該外金屬元件,可維持切割用刀具壽命以及切削的後的半導體封裝結構不會歪斜或偏移,確保製程良率。 As can be seen from the above description, the semiconductor package structure with an external metal element of the present invention is mainly used to encapsulate the external metal element after forming the encapsulant; thus, the encapsulant of the semiconductor package structure of the present invention does not need to separately prepare a special stamper The mold is used to thicken the sealant layer to cover the outer metal component, which can maintain the life of the cutting tool and the semiconductor package structure after cutting without skew or deviation, ensuring the yield of the process.

欲達上述目的所使用的主要技術手段係令該具外金屬元件之半導體封裝結構的製法包含以下步驟: (a)準備一線路基板及複數預先成型的外金屬元件,該線路基板包含有複數個元件區域;其中於各元件區域中,該線路基板的一第一表面上分別包含有複數第一接墊及複數第二接墊;(b)將複數電子元件電性連接至對應的第一接墊上;(c)於該線路基板的第一表面形成有一封膠體,以包覆該些電子元件於其中;(d)自該封膠體的上表面向下對應各該第二接墊位置形成有一貫穿孔;(e)將該些預先成型之外金屬元件分別設置在各該元件區域之該封膠體之上,並透過該些貫穿孔與該第二接墊電性連接,又各該金屬外板未平貼於該封膠體的上表面;以及(f)於各該貫穿孔內充填有一保護層;其中,各該貫穿孔內的保護層與該封膠層平齊;以及(g)以該線路基板之元件區域的相鄰處為準,使用切具自該封膠體向下切開,以成形複數個獨立的具外金屬元件之半體封裝結構。 The main technical means used to achieve the above purpose is to make the manufacturing method of the semiconductor package structure with external metal components include the following steps: (a) prepare a circuit substrate and a plurality of pre-formed outer metal components, the circuit substrate includes a plurality of component regions; wherein in each component region, a first surface of the circuit substrate includes a plurality of first pads, respectively And a plurality of second pads; (b) electrically connect the plurality of electronic components to the corresponding first pads; (c) a gel is formed on the first surface of the circuit substrate to cover the electronic components therein ; (D) A through hole is formed downward from the upper surface of the sealing body corresponding to each second pad position; (e) The pre-formed metal components are respectively disposed in the sealing body of each of the component regions And electrically connect to the second pad through the through holes, and each of the metal outer plates is not flat on the upper surface of the sealant; and (f) a protective layer is filled in each of the through holes; Wherein, the protective layer in each of the through holes is flush with the sealant layer; and (g) Based on the adjacent part of the device area of the circuit substrate, a cutting tool is used to cut down from the sealant to form a plurality of An independent half-body package structure with external metal components.

由上述說明可知,本發明的製法係主要先形成該封膠體,之後才進行外金屬元件的封裝;如此,本發明的半導體封裝結構的封膠體不必另外準備特製的壓模模具來增厚封膠層以包覆該外金屬元件,可維持切割用刀具壽命以及切削的後的半導體封裝結構不會歪斜或偏移,確保製程良率。 It can be seen from the above description that the manufacturing method of the present invention mainly forms the encapsulant first, and then encapsulates the outer metal components; thus, the encapsulant of the semiconductor package structure of the present invention does not need to prepare a special stamper mold to thicken the encapsulant The layer covers the outer metal component, which can maintain the life of the cutting tool and the semiconductor package structure after cutting without skew or deviation, ensuring the yield of the process.

1、1’:半體封裝結構 1. 1’: Half body package structure

10:線路基板 10: circuit board

100:元件區域 100: component area

11:第一接墊 11: First pad

12:第二接墊 12: second pad

20:電子元件 20: Electronic components

30:封膠體 30: Sealant

31:貫穿孔 31: through hole

32:保護層 32: protective layer

40、40’:外金屬元件 40, 40’: outer metal components

41:金屬外板 41: Metal outer plate

42:金屬柱 42: Metal pillar

43:錫 43: Tin

43’:錫球 43’: Tin ball

圖1A至圖1H:係分別對應本發明之一半導體封裝結構製法的一半導體封裝結構的緃向剖面圖。 FIGS. 1A to 1H are cross-sectional views of a semiconductor package structure corresponding to a method of manufacturing a semiconductor package structure of the present invention.

圖2:係由圖1A至圖1D製法所製成的一半導體封裝結構的一緃向剖面圖。 FIG. 2 is a cross-sectional view of a semiconductor package structure made by the manufacturing method of FIGS. 1A to 1D.

圖3:係由圖1A至圖1D製法所製成的另一半導體封裝結構的一緃向剖面圖。 FIG. 3 is a cross-sectional view of another semiconductor package structure made by the manufacturing method of FIGS. 1A to 1D.

圖4A至圖4H:係分別對應本發明之另一半導體封裝結構製法的一半導體封裝結構的緃向剖面圖。 4A to 4H are cross-sectional views of a semiconductor package structure corresponding to another method of manufacturing a semiconductor package structure of the present invention.

本發明係針對具有外金屬元件之半導體封裝結構及其製法進行改良,避免使用特殊壓模模具來形成過厚的封膠體,以維持正常的封裝良率。以下謹以複數實施例配合圖式詳加說明本發明具有外金屬元件之半導體封裝結構及其製法的技術內容。 The present invention is to improve the semiconductor packaging structure with external metal components and its manufacturing method, avoiding the use of special stamper molds to form excessively thick encapsulants, so as to maintain normal packaging yield. The following is a detailed description of the technical contents of the semiconductor package structure with an external metal element and its manufacturing method according to the present invention in conjunction with a plurality of embodiments.

請參閱圖1A至圖1H所示,首先介紹本發明半導體封裝結構之製法的第一較佳實施例,其包括以下步驟: Please refer to FIG. 1A to FIG. 1H, the first preferred embodiment of the manufacturing method of the semiconductor package structure of the present invention is introduced first, which includes the following steps:

如圖1A所示,於步驟(a)中,先準備一線路基板10,該線路基板10包含有複數個元件區域100,於各元件區域100中,該線路基板10的一第一表面上分別包含有複數第一接墊11及複數第二接墊12。 As shown in FIG. 1A, in step (a), a circuit substrate 10 is first prepared. The circuit substrate 10 includes a plurality of device regions 100. In each device region 100, a first surface of the circuit substrate 10 is respectively A plurality of first pads 11 and a plurality of second pads 12 are included.

如圖1B所示,於步驟(b)中,將複數電子元件20電性連接至對應的第一接墊11上;於本實施例,該些電子元件20係銲接至對應的第一接墊11,且該些電子元件20包含有晶片及被動元件。 As shown in FIG. 1B, in step (b), a plurality of electronic components 20 are electrically connected to the corresponding first pads 11; in this embodiment, the electronic components 20 are soldered to the corresponding first pads 11. The electronic components 20 include chips and passive components.

如圖1C所示,於步驟(c)中,於該線路基板10的第一表面上形成有一封膠體30,該封膠體30用以包覆該些電子元件20於其中。於本實施例,係以一壓模模具於該線路基板10上灌入液態膠,待液態膠固化後即形成該封膠體30。 As shown in FIG. 1C, in step (c), a sealant 30 is formed on the first surface of the circuit substrate 10, and the sealant 30 is used to cover the electronic components 20 therein. In this embodiment, a liquid mold is poured on the circuit substrate 10 by a stamper mold, and the sealing body 30 is formed after the liquid gel is cured.

如圖1D所示,於步驟(d)中,自該封膠體30的上表面向下對應各該第二接墊12位置形成有一貫穿孔31。於本實施例,係以一雷射開孔方式於該封膠體30的上表面形成該些貫穿孔31。 As shown in FIG. 1D, in step (d), a through hole 31 is formed downward from the upper surface of the sealing body 30 corresponding to the position of each second pad 12. In this embodiment, the through holes 31 are formed on the upper surface of the sealing body 30 by a laser opening method.

如圖1E所示,於步驟(e)中,將預先成型的複數外金屬元件40分別對應設置在各該元件區域100之該封膠體30上,各該外金屬元件40再透過該些貫穿孔31與該第二接墊12電性連接。於本實施例,該外金屬元件40係包含有一金屬外板41及複數金屬柱42;其中各該金屬柱42係自該金屬外板41底面向下垂直延伸,且各該金屬柱42的一自由端係預先沾錫43後再置入對應的貫穿孔31後,以與該第二接墊12銲接;此外,該外金屬元件40係為一天線元件,該金屬外板41形成有天線圖案,而該些金屬柱42係作為該天線元件的訊號饋入接腳與電源訊號接腳。 As shown in FIG. 1E, in step (e), a plurality of pre-formed outer metal elements 40 are respectively disposed on the encapsulant 30 of each element area 100, and each of the outer metal elements 40 passes through the through holes 31 is electrically connected to the second pad 12. In this embodiment, the outer metal element 40 includes a metal outer plate 41 and a plurality of metal posts 42; wherein each of the metal posts 42 extends vertically downward from the bottom surface of the metal outer plate 41, and one of each metal post 42 The free end is pre-dipped with tin 43 and then inserted into the corresponding through-hole 31 to be soldered with the second pad 12; in addition, the outer metal element 40 is an antenna element, and the metal outer plate 41 is formed with an antenna pattern The metal pillars 42 are used as the signal feeding pin and the power signal pin of the antenna element.

如圖1F所示,於步驟(f)中,於各該貫穿孔31內充填有一保護層32,令該些金屬柱42與該第二接墊12與外界隔離,該保護層32係與該封膠層30的上表面平齊。 As shown in FIG. 1F, in step (f), each of the through holes 31 is filled with a protective layer 32 to isolate the metal pillars 42 from the second pad 12 from the outside world, and the protective layer 32 is connected to the The upper surface of the sealant layer 30 is flush.

如圖1G及圖1H所示,於步驟(g)中,以該線路基板10之元件區域100的相鄰處L為準,使用切具自該封膠體30向下切開,以成形複數個獨立的具外金屬元件之半體封裝結構1。 As shown in FIG. 1G and FIG. 1H, in step (g), the adjacent area L of the device region 100 of the circuit substrate 10 is used as a standard, and a cutting tool is used to cut down from the sealing compound 30 to form a plurality of independent The half body packaging structure 1 with external metal components.

即如圖2所示,以前揭製法的第一較佳實施例所製成的半導體封裝結構1包含有一線路基板10、複數電子元件20、一封膠層30、一外金屬元件40及一保護層32。 That is, as shown in FIG. 2, the semiconductor package structure 1 manufactured by the first preferred embodiment of the previously disclosed manufacturing method includes a circuit substrate 10, a plurality of electronic components 20, an adhesive layer 30, an outer metal component 40, and a protection Layer 32.

上述線路基板10的第一表面包含有複數第一接墊11及複數第二接墊12。 The first surface of the circuit board 10 includes a plurality of first pads 11 and a plurality of second pads 12.

該些電子元件20係分別電性連接於對應的第一接墊11;於本實施例,該些電子元件20係包含有晶片及被動元件。 The electronic components 20 are electrically connected to the corresponding first pads 11 respectively. In this embodiment, the electronic components 20 include a chip and a passive component.

該封膠層30係形成在該線路基板10的第一表面上,以包覆該些電子元件20於其中,且該封膠層30係對應各該第二接墊12位置形成有一貫穿孔31,令各該第二接墊12外露。 The sealant layer 30 is formed on the first surface of the circuit substrate 10 to cover the electronic components 20 therein, and the sealant layer 30 is formed with a through hole 31 corresponding to the position of each second pad 12 So that each second pad 12 is exposed.

該外金屬元件40係電性連接該線路基板10,並包含有一金屬外板41及複數金屬柱42;其中該金屬外板41係位在該封膠層30之上,並與該封膠體30的上表面保持有一間距,而該些金屬柱42則自該金屬外板41底面向下垂直延伸,並分別電性連接至該第二接墊12;於本實施例,該些金屬柱42係銲接至該第二接墊12。 The outer metal element 40 is electrically connected to the circuit board 10 and includes a metal outer plate 41 and a plurality of metal pillars 42; wherein the metal outer plate 41 is located on the sealing layer 30 and is in contact with the sealing body 30 The upper surface of the metal is kept at a distance, and the metal pillars 42 extend vertically downward from the bottom surface of the metal outer plate 41 and are electrically connected to the second pads 12 respectively; in this embodiment, the metal pillars 42 are Solder to the second pad 12.

該保護層係充填於各該貫穿孔31內充填有一保護層32,並與該封膠層30的上表面平齊,令該些金屬柱42與該第二接墊12與外界隔離。 The protective layer is filled in each of the through-holes 31 with a protective layer 32 that is flush with the upper surface of the sealant layer 30 to isolate the metal pillars 42 from the second pad 12 from the outside world.

再請參閱圖3所示,以前揭製法的第一較佳實施例所製成的另一半導體封裝結構1’,其同樣包含有一線路基板10、複數電子元件20、一封膠層30、一外金屬元件40’及一保護層34,惟該外金屬元件40’係為一金屬外殼,故其該金屬外板41係全面平貼於該封膠體30的上表面,作為散熱用;且各該金屬柱42係呈板狀,自該金屬外板41四周向下形成,以對應電性連接至該第二接墊12,而固定於該線路基板10上。又,為使該金屬外殼具有抗電磁干擾的功能,則其電性連接之該些第二接墊12係為接地訊號接墊。 Please refer to FIG. 3 again. Another semiconductor package structure 1'made by the first preferred embodiment of the previously disclosed manufacturing method also includes a circuit substrate 10, a plurality of electronic components 20, an adhesive layer 30, a The outer metal element 40' and a protective layer 34, but the outer metal element 40' is a metal shell, so the metal outer plate 41 is fully flat on the upper surface of the sealing body 30 for heat dissipation; and The metal post 42 is in the shape of a plate and is formed downward from around the metal outer plate 41 to be electrically connected to the second pad 12 and fixed on the circuit substrate 10. In addition, in order to make the metal shell have the function of resisting electromagnetic interference, the second pads 12 electrically connected to them are ground signal pads.

再請參閱圖4A至圖4H所示,為本發明半導體封裝結構之製法的第二較佳實施例,其包括以下步驟: Please refer to FIGS. 4A to 4H again, which is the second preferred embodiment of the manufacturing method of the semiconductor package structure of the present invention, which includes the following steps:

如圖4A所示,於步驟(a)中,先準備一線路基板10,該線路基板10包含有複數個元件區域100,於各元件區域100中,該線路基板10的一第一表面上分別包含有複數第一接墊11及複數第二接墊12。 As shown in FIG. 4A, in step (a), a circuit substrate 10 is first prepared. The circuit substrate 10 includes a plurality of device regions 100. In each device region 100, a first surface of the circuit substrate 10 is respectively A plurality of first pads 11 and a plurality of second pads 12 are included.

如圖4B所示,於步驟(b)中,將複數電子元件20電性連接至對應的第一接墊11上,並於各該第二接墊12上形成有錫球43’;於本實施例,該些電 子元件20係銲接至對應的第一接墊11,且該些電子元件20包含有晶片及被動元件。 As shown in FIG. 4B, in step (b), a plurality of electronic components 20 are electrically connected to corresponding first pads 11, and solder balls 43' are formed on each second pads 12; Examples, the electricity The sub-components 20 are soldered to the corresponding first pads 11, and the electronic components 20 include chips and passive components.

如圖4C所示,於步驟(c)中,於該線路基板10的第一表面上形成有一封膠體30,該封膠體30用以包覆該些電子元件20及錫球43’於其中。於本實施例,係以一壓模模具於該線路基板上灌入液態膠,待液態膠固化後即形成該封膠體30。 As shown in FIG. 4C, in step (c), a sealant 30 is formed on the first surface of the circuit substrate 10, and the sealant 30 is used to cover the electronic components 20 and the solder balls 43' therein. In this embodiment, a stamper mold is used to fill the circuit board with liquid glue, and the sealing body 30 is formed after the liquid glue is cured.

如圖4D所示,於步驟(d)中,自該封膠體30的上表面向下對應各該第二接墊12位置形成有一貫穿孔31。於本實施例,係以一雷射開孔方式於該封膠體30的上表面形成該些貫穿孔31,由於雷射開孔時具有高熱,故可一併融熔該錫球43’。 As shown in FIG. 4D, in step (d), a through hole 31 is formed downward from the upper surface of the sealing body 30 corresponding to the position of each second pad 12. In this embodiment, the through holes 31 are formed in the upper surface of the sealing body 30 by a laser opening method. Since the laser opening has high heat, the solder balls 43' can be melted together.

如圖4E所示,於步驟(e)中,將預先成型的複數外金屬元件40分別對應設置在各該元件區域100之該封膠體30上,各該外金屬元件40再透過該些貫穿孔31與該第二接墊12電性連接。於本實施例,該外金屬元件40係包含有一金屬外板41及複數金屬柱42;其中各該金屬柱42係自該金屬外板41底面向下垂直延伸,且各該金屬柱42的一自由端係直接置入對應的貫穿孔31中,以與融熔的錫球43’接觸,待錫球43’固化後,即與該第二接墊12完成銲接。 As shown in FIG. 4E, in step (e), a plurality of pre-formed outer metal elements 40 are respectively disposed on the encapsulant 30 of each element area 100, and the outer metal elements 40 pass through the through holes 31 is electrically connected to the second pad 12. In this embodiment, the outer metal element 40 includes a metal outer plate 41 and a plurality of metal posts 42; wherein each of the metal posts 42 extends vertically downward from the bottom surface of the metal outer plate 41, and one of each metal post 42 The free end is directly inserted into the corresponding through hole 31 to make contact with the molten solder ball 43'. After the solder ball 43' is solidified, the soldering with the second pad 12 is completed.

如圖4F所示,於步驟(f)中,於各該貫穿孔31內充填有一保護層32,令該些金屬柱與42該第二接墊12與外界隔離。 As shown in FIG. 4F, in step (f), each of the through holes 31 is filled with a protective layer 32 to isolate the metal pillars and 42 from the second pad 12 from the outside world.

如圖4G及圖4H所示,於步驟(g)中,以該線路基板10之元件區域100的相鄰處為準,使用切具自該封膠體30向下切開,以成形獨立的具外金屬元件之半體封裝結構1。 As shown in FIGS. 4G and 4H, in step (g), the adjacent area of the device region 100 of the circuit board 10 is used as a standard, and a cutting tool is used to cut down from the encapsulant 30 to form an independent tool. Metal component half package structure 1.

綜上所述,由前揭本發明製法第一及第二較佳實施例可知,壓模灌膠形成封膠體步驟係在設置複數預先成型的外金屬元件之前,故可延用既有的半導體元件之壓模模具,無需另外準備特殊壓模模具,該封膠體的厚度也 只要足以包覆晶片、被動元件等即可,故可維持既有的厚度;之後,也只需要增加該封膠體開孔步驟,即可順利將該外金屬元件與該線路基板的第二接墊電性連接,開孔步驟已是封裝製程的既有製程技術,不必另外準備或設置相應的機台,而且不影響製程良率。因此,本發明的半導體封裝結構的外金屬元件的金屬外板即外露在封膠體之外,而不會被封膠體包覆。 In summary, from the first and second preferred embodiments of the manufacturing method of the present invention, it can be seen that the step of forming the sealant by the die-casting is before the provision of a plurality of pre-formed external metal components, so the existing semiconductor can be used For the component's stamping die, no special stamping die is required, and the thickness of the sealant is also As long as it is enough to cover the chip, passive components, etc., it can maintain the existing thickness; after that, it is only necessary to increase the opening step of the encapsulant to smoothly connect the external metal component and the second pad of the circuit substrate The electrical connection and the opening step are already the existing process technology of the packaging process. There is no need to separately prepare or set up corresponding machines, and it does not affect the process yield. Therefore, the metal outer plate of the outer metal element of the semiconductor package structure of the present invention is exposed outside the encapsulant without being covered by the encapsulant.

以上所述僅是本發明的實施例而已,並非對本發明做任何形式上的限制,雖然本發明已以實施例揭露如上,然而並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明技術方案的範圍內,當可利用上述揭示的技術內容作出些許更動或修飾為等同變化的等效實施例,但凡是未脫離本發明技術方案的內容,依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾,均仍屬於本發明技術方案的範圍內。 The above is only an embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed in the above embodiment, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field belongs to, Within the scope of not departing from the technical solution of the present invention, when the technical contents disclosed above can be used to make some changes or modifications to equivalent embodiments of equivalent changes, but any content that does not depart from the technical solution of the present invention is based on the technical essence of the present invention Any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the technical solution of the present invention.

1:半體封裝結構 1: Half body packaging structure

10:線路基板 10: circuit board

11:第一接墊 11: First pad

12:第二接墊 12: second pad

20:電子元件 20: Electronic components

30:封膠體 30: Sealant

31:貫穿孔 31: through hole

32:保護層 32: protective layer

40:外金屬元件 40: outer metal element

41:金屬外板 41: Metal outer plate

42:金屬柱 42: Metal pillar

43:錫 43: Tin

Claims (10)

一種具外金屬元件之半導體封裝結構,包括:一線路基板,其第一表面包含有複數第一接墊及複數第二接墊;複數電子元件,各該電子元件係分別電性連接於對應的元件接墊;一封膠層,係形成在該線路基板的第一表面上,以包覆該些電子元件於其中,且該封膠層係對應各該第二接墊位置形成有一貫穿孔,令各該第二接墊外露;一外金屬元件,係預先成型並電性連接該線路基板,並包含有:一金屬外板,係位在該封膠層之上,該金屬外板未平貼於該封膠體的上表面;以及複數金屬柱,係自該金屬外板底面向下垂直延伸,並分別電性連接至該第二接墊;以及一保護層,係充填於各該貫孔穿中,以與封膠體的上表面平齊。 A semiconductor packaging structure with external metal components includes: a circuit substrate whose first surface includes a plurality of first pads and a plurality of second pads; a plurality of electronic components, each of which is electrically connected to a corresponding A component pad; an adhesive layer is formed on the first surface of the circuit substrate to cover the electronic components therein, and the sealing layer is formed with a through hole corresponding to each second pad position, Each of the second pads is exposed; an outer metal element is pre-formed and electrically connected to the circuit board, and includes: a metal outer plate, which is located on the sealant layer, the metal outer plate is not flat It is attached to the upper surface of the encapsulant; and a plurality of metal posts extending vertically downward from the bottom surface of the metal outer plate and are electrically connected to the second pads respectively; and a protective layer filled in each through hole Wear it to be flush with the upper surface of the sealant. 如請求項1所述之具外金屬元件之半導體封裝結構,其中:該外金屬元件係為一天線元件,該金屬外板形成有天線圖案,並包含有複數金屬柱,作為該天線元件的訊號饋入接腳與電源訊號接腳;以及該金屬外板係與該封膠體的上表面保持有一間距。 The semiconductor packaging structure with an external metal element as described in claim 1, wherein the external metal element is an antenna element, the metal outer plate is formed with an antenna pattern, and includes a plurality of metal pillars as a signal of the antenna element The feeding pin and the power signal pin; and the metal outer plate is kept at a distance from the upper surface of the sealing body. 如請求項1所述之具外金屬元件之半導體封裝結構,其中:該外金屬元件係為一金屬外殼,該金屬外板係全面平貼於該封膠體的上表面,且各該金屬柱係呈板狀,自該金屬外板四周向下形成,以對應電性連接至該第二接墊。 The semiconductor packaging structure with an external metal element as described in claim 1, wherein: the external metal element is a metal shell, the metal outer plate is fully flat on the upper surface of the encapsulant, and each of the metal pillars is It is in the form of a plate and is formed downward from the periphery of the metal outer plate to be electrically connected to the second pad. 如請求項3所述之具外金屬元件之半導體封裝結構,該第二接墊係為接地訊號接墊。 As described in claim 3, in the semiconductor package structure with external metal elements, the second pad is a ground signal pad. 如請求項1至4中任一項所述之具外金屬元件之半導體封裝結構,各該金屬柱係以銲錫與對應的第二接墊銲接。 As described in any one of claims 1 to 4, the semiconductor package structure with an external metal element, each of the metal pillars is soldered to the corresponding second pad with solder. 一種具外金屬元件之半導體封裝結構的製法,包括以下步驟:(a)準備一線路基板及複數預先成型的外金屬元件,該線路基板包含有複數個元件區域;其中於各元件區域中,該線路基板的一第一表面上分別包含有複數第一接墊及複數第二接墊;(b)將複數電子元件電性連接至對應的第一接墊上;(c)於該線路基板的第一表面形成有一封膠體,以包覆該些電子元件於其中;(d)自該封膠體的上表面向下對應各該第二接墊位置形成有一貫穿孔;(e)將該些預先成型之外金屬元件分別設置在各該元件區域之該封膠體之上,並透過該些貫穿孔與該第二接墊電性連接,又各該金屬外板未平貼於該封膠體的上表面;以及(f)於各該貫穿孔內充填有一保護層;其中,各該貫穿孔內的保護層與該封膠層平齊;以及(g)以該線路基板之元件區域的相鄰處為準,使用切具自該封膠體向下切開,以成形複數個獨立的具外金屬元件之半體封裝結構。 A method for manufacturing a semiconductor packaging structure with external metal components includes the following steps: (a) preparing a circuit substrate and a plurality of pre-formed external metal components, the circuit substrate includes a plurality of component regions; wherein in each component region, the A first surface of the circuit substrate respectively includes a plurality of first pads and a plurality of second pads; (b) electrically connects the plurality of electronic components to the corresponding first pads; (c) on the circuit board A gel is formed on a surface to cover the electronic components therein; (d) a through hole is formed downward from the upper surface of the gel to correspond to each second pad position; (e) the pre-molds The external metal components are respectively disposed on the sealing body in each of the component regions, and are electrically connected to the second pad through the through holes, and each metal outer plate is not flat on the upper surface of the sealing body ; And (f) a protective layer is filled in each of the through-holes; wherein, the protective layer in each of the through-holes is flush with the sealant layer; and (g) the adjacent area of the circuit board element area is It is accurate to use a cutting tool to cut down from the sealing body to form a plurality of independent half-body packaging structures with external metal components. 如請求項6所述之具外金屬元件之半導體封裝結構的製法,於步驟(e)中,各該外金屬元件係包含有一金屬外板及複數金屬柱;其中各該金屬柱係自該金屬外板底面向下垂直延伸,且各該金屬柱的一自由端係預先沾錫後再置入對應的貫穿孔後,以與該第二接墊銲接。 The method for manufacturing a semiconductor package structure with an external metal element as described in claim 6, in step (e), each of the external metal elements includes a metal outer plate and a plurality of metal pillars; wherein each of the metal pillars is derived from the metal The bottom surface of the outer plate extends vertically downward, and a free end of each metal post is pre-dipped with tin and then placed into a corresponding through hole to be welded with the second pad. 如請求項6所述之具外金屬元件之半導體封裝結構的製法,其中:上述步驟(b)進一步於各該第二接墊上形成有錫球; 上述步驟(c)中的封膠體係包覆該些錫球;於上述步驟(d)中,以雷射開孔方式形成該些貫穿孔,並一併融熔錫球;以及於上述步驟(e)中,各該外金屬元件係包含有一金屬外板及複數金屬柱;其中各該金屬柱係自該金屬外板底面向下垂直延伸,且各該金屬柱的一自由端係置入對應的貫穿孔後,以與該第二接墊銲接。 The method for manufacturing a semiconductor package structure with an external metal element as described in claim 6, wherein: the above step (b) further forms solder balls on each of the second pads; The sealing system in the step (c) covers the solder balls; in the step (d), the through holes are formed by laser opening and the solder balls are melted together; and in the step ( In e), each of the outer metal components includes a metal outer plate and a plurality of metal pillars; wherein each of the metal pillars extends vertically downward from the bottom surface of the metal outer plate, and a free end of each metal pillar is placed into the corresponding After the through hole, to weld with the second pad. 如請求項7或8所述之具外金屬元件之半導體封裝結構的製法,其中:各該外金屬元件係為一天線元件,其該金屬外板形成有天線圖案,而該些金屬柱係作為該天線元件的訊號饋入接腳與電源訊號接腳;以及該金屬外板係與該封膠體的上表面保持有一間距。 The method for manufacturing a semiconductor package structure with an external metal element as described in claim 7 or 8, wherein each of the external metal elements is an antenna element, the metal outer plate is formed with an antenna pattern, and the metal pillars are used as The signal feeding pin of the antenna element and the power signal pin; and the metal outer plate is kept at a distance from the upper surface of the sealing compound. 如請求項7或8所述之具外金屬元件之半導體封裝結構的製法,該外金屬元件係為一金屬外殼,該金屬外板係全面平貼於該封膠體的上表面,且各該金屬柱係呈板狀,自該金屬外板四周向下垂直延伸。 The method for manufacturing a semiconductor packaging structure with an external metal element as described in claim 7 or 8, the external metal element is a metal shell, the metal outer plate is fully flat on the upper surface of the encapsulant, and each metal The column is in the form of a plate and extends vertically downward from the periphery of the metal outer plate.
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