TWI696022B - Pixel array substrate - Google Patents

Abstract

A pixel array substrate including a substrate, a plurality of pixel structures, a plurality of signal lines, a plurality of impedance adjusting structures and a plurality of fan-out lines is provided. The signal lines are disposed on the substrate and electrically connected to the pixel structures. The impedance adjusting structures are electrically connected to the signal lines and the fan-out lines. Each of the impedance adjusting structures includes a first conductive pattern, a first insulation layer, a second conductive pattern, a second insulation layer and a third conductive pattern. The first insulation layer has a first contact window. The second insulation layer has a third contact window. The third conductive pattern is electrically connected to the first conductive pattern and the second conductive pattern via the first contact window and the third contact window, respectively. The area of the vertical projection of at least one of the first contact window and the third contact window increases with the impedance adjusting structure being away from an imaginary line.

Description

Pixel array substrate

The invention relates to a pixel array substrate, and in particular to a pixel array substrate applied to a display device.

With the popularization of display panels, home TVs, e-sports screens, large outdoor billboards, public information screens in stores, and even portable or wearable electronic devices are all visible. In recent years, in addition to increasing the mainstream size of display panels, in response to consumer demand for high-end electronic products, display panels with narrow bezels are one of the key projects actively developed by many panel manufacturers.

In a display panel with a narrow bezel, the pixel array substrate is used to connect the fan-out traces of the driving elements (such as flip-flops, gate driving elements) and signal lines (such as data lines and scanning lines), The different extension lengths make the difference in impedance more obvious, which in turn causes the problem of mura.

The invention provides a pixel array substrate with good circuit impedance matching.

The pixel array substrate of the present invention includes a substrate, multiple pixel structures, multiple Multiple signal lines, multiple impedance adjustment structures, multiple fan-out traces, and multiple pads. The substrate has an active area, a transition area, a fan-out area and a pad area arranged in sequence. Multiple pixel structures are disposed in the active area of the substrate. Multiple signal lines are electrically connected to multiple pixel structures, and extend from the active area to the transition area. Multiple impedance adjustment structures are disposed in the transfer area of the substrate, and are electrically connected to multiple signal lines. Each impedance adjustment structure includes a first conductive pattern, a first insulating layer, a second conductive pattern, a second insulating layer, and a third conductive pattern. The first conductive pattern is disposed on the substrate. The first insulating layer is disposed on the first conductive pattern and has a first contact window overlapping the first conductive pattern. The second conductive pattern is disposed on the first insulating layer. The second insulating layer is disposed on the second conductive pattern, and has a second contact window overlapping the first contact window and a third contact window overlapping the second conductive pattern. The third conductive pattern is disposed on the second insulating layer, and electrically connects the first conductive pattern and the second conductive pattern through the first contact window, the second contact window, and the third contact window. Multiple fan-out traces are provided in the fan-out area of the substrate, are electrically connected to multiple impedance adjustment structures, and are arranged on both sides of the virtual line. The area of the vertical projection of at least one of the first contact window and the third contact window of each impedance adjustment structure increases as the impedance adjustment structure moves away from the virtual line. A plurality of pads are disposed in the pad area of the substrate, and are electrically connected to a plurality of fan-out traces.

The pixel array substrate of the present invention includes a substrate, multiple pixel structures, multiple signal lines, multiple fan-out traces, and multiple impedance adjustment structures. The substrate has an active area, a transition area and a fan-out area arranged in sequence. Multiple pixel structures are disposed in the active area of the substrate. Multiple signal lines are electrically connected to multiple pixel structures and extend from the active area to Transit area. Multiple fan-out traces are provided in the fan-out area of the substrate and electrically connected to the driving element. Multiple fan-out traces are arranged in sequence in the first direction. Each fan-out trace has an impedance, and the impedance of multiple fan-out traces decreases along the first direction. Multiple impedance adjustment structures are provided in the transfer area of the substrate, and are electrically connected to multiple signal lines and multiple fan-out traces. Each impedance adjustment structure includes a first conductive pattern, a first insulating layer, a second conductive pattern, a second insulating layer, and a third conductive pattern. The first conductive pattern is disposed on the substrate. The first insulating layer is disposed on the first conductive pattern and has a first contact window overlapping the first conductive pattern. The second conductive pattern is disposed on the first insulating layer. The second insulating layer is disposed on the second conductive pattern, and has a second contact window overlapping the first contact window and a third contact window overlapping the second conductive pattern. The third conductive pattern is disposed on the second insulating layer, and electrically connects the first conductive pattern and the second conductive pattern through the first contact window, the second contact window, and the third contact window. The area of the vertical projection of at least one of the first contact window and the third contact window of each impedance adjustment structure increases along the opposite direction of the first direction.

Based on the above, in the pixel array substrate of the embodiment of the present invention, the impedance adjustment structure connected between the fan-out wiring and the signal line is adjusted by the size of the contact window between the conductive patterns and the distance between each other. The impedance adjustment structures corresponding to different fan-out traces have different impedances to compensate for the difference in impedance between different fan-out traces. Therefore, the display device of the pixel array substrate is less prone to display mura problems due to impedance differences.

In order to make the above features and advantages of the present invention more obvious and understandable, The embodiments are described in detail in conjunction with the attached drawings as follows.

10.10A~10E: Pixel array substrate

11: substrate

11a: side

12: Electronic components

110: first conductive pattern

120, 120A, 120B: second conductive pattern

120op: opening

120s: side wall

130, 130A, 130B: third conductive pattern

130a: the first conductive part

130b: Second conductive part

130c: Third conductive part

140: fourth conductive pattern

210: first insulating layer

410, 410-1, 410-n: the first contact window

420, 420-1, 420-n: second contact window

430, 430-1, 430-n: third contact window

440, 440-1, 440-n: fourth contact window

450, 450-1, 450-n: fifth contact window

220: second insulating layer

AA: Active area

BL: Pad area

BP: pad

C: virtual line

D1, D2: direction

FL, FL-1~FL-n, FL-n+1~FL-m, FLA, FLA-1~FLA-n, FLB, FLB-1~FLB-n, FLB-n+1~FLB-m: Fan out trace

FLAa: first wire

FLAb: second wire

FO: Fan-out area

I: area

L1, L1-1, L1-n: the first distance

L2, L2-1, L2-n: second distance

PE: pixel electrode

PX: pixel structure

300, 300-1~300-n, 300-n+1~300-m, 300A-1~300A-n, 300B-1~300B-n, 300C-1~300C-n, 300D-1~300D- n: impedance adjustment structure

R1, R2, R1(1), R1(n), R2(1), R2(n), R1(m), R2(m): impedance

SLX, SLY, SLY1~SLYn, SLYn+1~SLYm: signal line

T: Active component

TR: transit area

W1, W1-1, W1-n: width

FIG. 1 is a schematic diagram of a pixel array substrate according to a first embodiment of the invention.

FIG. 2 is a schematic diagram of impedance distribution of multiple fan-out traces of FIG. 1.

FIG. 3 is a schematic diagram of the impedance distribution of the multiple impedance adjustment structures of FIG. 1.

FIG. 4 is an enlarged schematic view of the local area I of the pixel array substrate of FIG. 1.

FIG. 5 is a schematic diagram of an impedance adjustment structure of FIG. 4.

6 is a schematic diagram of another impedance adjustment structure of FIG. 4.

7 is a schematic cross-sectional view of the impedance adjustment structure of FIG. 5.

8 is an enlarged schematic view of a partial area of a pixel array substrate according to a second embodiment of the invention.

9 is a schematic diagram of one of the impedance adjustment structures of FIG. 8.

FIG. 10 is a schematic diagram of another impedance adjustment structure of FIG. 8.

11 is a schematic cross-sectional view of the impedance adjustment structure of FIG. 9.

12 is an enlarged schematic view of a partial area of a pixel array substrate according to a third embodiment of the invention.

13 is a schematic diagram of an impedance adjustment structure of FIG.

14 is a schematic diagram of another impedance adjustment structure of FIG. 12.

15 is a partial area of the pixel array substrate of the fourth embodiment of the present invention Enlarge the schematic.

FIG. 16 is a schematic diagram of an impedance adjustment structure of FIG. 15.

17 is a schematic diagram of another impedance adjustment structure of FIG. 15.

18 is a schematic cross-sectional view of the impedance adjustment structure of FIG. 16.

19 is an enlarged schematic view of a partial area of a pixel array substrate of a fifth embodiment of the invention.

FIG. 20 is a schematic diagram of an impedance adjustment structure of FIG. 19.

21 is a schematic diagram of another impedance adjustment structure of FIG. 19.

22 is a schematic cross-sectional view of one of the impedance adjustment structures of FIG. 19.

23 is a schematic diagram of a pixel array substrate according to a sixth embodiment of the invention.

FIG. 24 is a schematic diagram of impedance distribution of multiple fan-out traces of FIG. 23.

FIG. 25 is a schematic diagram of the impedance distribution of the multiple impedance adjustment structures of FIG. 23.

Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Throughout the specification, the same reference numerals denote the same elements. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “connected to” another element, it can be directly on the other element or be connected to another element. An element is connected, or an intermediate element may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connections. Furthermore, "electrical connection" or "coupling" may be that there are other elements between the two elements.

As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within an acceptable deviation range for a particular value determined by one of ordinary skill in the art, taking into account the measurements and A specific amount of measurement-related errors (eg, measurement system and/or process error limits). For example, "about" may mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately", or "substantially" can be based on optical properties, etching properties, or other properties to select a more acceptable range of deviation or standard deviation, and one standard deviation can be applied to all properties .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and the present invention, and will not be interpreted as idealized or excessive Formal meaning unless explicitly defined as such in this article.

FIG. 1 is a schematic diagram of a pixel array substrate according to a first embodiment of the invention. FIG. 2 is a schematic diagram of impedance distribution of multiple fan-out traces of FIG. 1. FIG. 3 is a schematic diagram of the impedance distribution of the multiple impedance adjustment structures of FIG. 1. For clarity, Figure 1 is simplified 4 illustrates the impedance adjustment structure 300 and the fan-out trace FL, and FIG. 1 does not show the detailed structure of the impedance adjustment structure 300 of FIG. 4 (eg, the first contact window 410, the third contact window 430, etc.) and FIG. Detail structure of the partial fan-out trace FL (for example: the bent section of the fan-out trace FL-n).

Please refer to FIG. 1. In this embodiment, the pixel array substrate 10 includes a substrate 11 and a plurality of signal lines SLX and SLY. The substrate 11 has an active area AA, a transition area TR, a fan-out area FO and a pad area BL arranged in this order. The multiple signal lines SLY extend from the active area AA of the substrate 11 to the transition area TR. For example, in this embodiment, the multiple signal lines SLX are, for example, multiple scan lines, and the multiple signal lines SLY are, for example, multiple data lines, but the present invention is not limited to this. In other embodiments, the multiple signal lines SLX may also be multiple data lines, and the multiple signal lines SLY may also be multiple scan lines.

In this embodiment, a plurality of signal lines SLX are sequentially arranged in the active area AA of the substrate 11 in the direction D2, and a plurality of signal lines SLX extend in the direction D1. The plurality of signal lines SLY includes a plurality of signal lines SLY1~SLYn, SLYn+1~SLYm sequentially arranged in the active area AA of the substrate 11 in the direction D1, and the plurality of signal lines SLY extend in the direction D2, where n, m is a positive integer, and n is less than m. The direction D1 is interleaved with the direction D2. For example, in this embodiment, the direction D1 is substantially perpendicular to the direction D2, but the invention is not limited thereto.

In this embodiment, the pixel array substrate 10 further includes a plurality of pixel structures PX, which are disposed in the active area AA of the substrate 11. Each pixel structure PX has an active element The element T and the pixel electrode PE electrically connected to the active element T. In detail, the active element T of each pixel structure PX is electrically connected to a corresponding signal line SLX and a corresponding signal line SLY, respectively. In this embodiment, the active element T of the pixel structure PX may be a top-gate thin film transistor (top-gate TFT). However, the present invention is not limited to this. According to other embodiments, the active element T of the pixel structure PX may also be a bottom-gate thin film transistor (bottom-gate TFT) or other suitable types of thin film transistors. In this embodiment, the pixel electrode PE is, for example, a transmissive electrode, and the material of the transmissive electrode includes metal oxides, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide , Or other suitable oxides, or a stacked layer of at least two of the above. However, the present invention is not limited to this. In other embodiments, the pixel electrode PE may also be a reflective electrode, or a combination of a reflective electrode and a transmissive electrode.

In this embodiment, the pixel array substrate 10 further includes a plurality of fan-out traces FL, which are disposed in the fan-out area FO of the substrate 11 and extend to the pad area BL and the transfer area TR toward both sides of the fan-out area FO . A plurality of fan-out traces FL are sequentially arranged in the fan-out area FO of the substrate 11 along the direction D1. The fan-out area FO may have a virtual line C; more specifically, in this embodiment, a plurality of fan-out traces FL-1~FL-m electrically connected to one electronic component 12 may optionally have a Virtual line C; that is to say, multiple fan-out traces FL-1~FL-m are arranged on both sides of a virtual line C. In one embodiment, the fan-out traces FL-1~FL-m can selectively mirror the virtual line C, but not limited to this. In this embodiment, multiple fan-out traces electrically connected to one electronic component 12 The number of FL-1~FL-m can be optionally even, and the fan-out traces FL-1~Fn and FLn+1~Fm can be symmetrically arranged on both sides of the virtual line C. However, the invention is not limited to this. According to another embodiment, the number of the plurality of fan-out traces FL-1~FL-m electrically connected to one electronic component 12 may also be an odd number; according to another embodiment, The fan-out traces FL-1~FL-m electrically connected to an electronic component 12 can also be arranged in an asymmetrical manner. The following paragraphs will illustrate with other drawings.

Please refer to FIGS. 1 and 2. In this embodiment, the extension lengths of the plurality of fan-out traces FL in the fan-out area FO are different from each other, and have different impedances R1. For example, the extension length of the fan-out trace FL increases as the fan-out trace FL moves away from the virtual line C, where the fan-out trace FL-1 (or fan-out trace FL-m) farthest from the virtual line C is due to The longest extension has the largest impedance R1(1); the fan-out trace FL-n (or fan-out trace FL-n+1 or fan-out trace on virtual line C) closest to virtual line C, because of its The extension length is the shortest and has the smallest impedance R1(n), but the invention is not limited thereto. In this embodiment, the fan-out trace FL-1 and the fan-out trace FL-m, which are far from the virtual line C and symmetrical to the virtual line C, have substantially equal impedance R1(1), and are adjacent to the virtual line C and opposite the virtual line C is symmetrical fan-out trace FL-n and fan-out trace FL-n+1 have substantially equal impedance R1(n), where R1(n)-R1(1)=-△R; located in fan-out trace FL The impedance R1 of the fan-out trace FL between -1 and the fan-out trace FL-n (or fan-out trace FL-n+1 and fan-out trace FL-m) and the degree of the fan-out trace FL away from the virtual line C show a Positive correlation; in this embodiment, a positive linear relationship (positive linear relationship) is presented, but the present invention is not limited to this, in other embodiments, may Presented with a curvilinear positive correlation.

In this embodiment, based on the consideration of conductivity, the materials of the signal line SLX, the signal line SLY, and the fan-out trace FL are generally metal materials. However, the present invention is not limited to this. According to other embodiments, the signal line SLX, the signal line SLY, and the fan-out trace FL can also use other conductive materials, such as alloys, nitrides of metal materials, and oxides of metal materials. , Nitrogen oxides of metal materials, or other suitable materials, or stacked layers of metal materials and other conductive materials.

Please refer to FIG. 1. In this embodiment, the pixel array substrate 10 further includes a plurality of impedance adjustment structures 300 disposed in the transition region TR of the substrate 11. The multiple impedance adjustment structures 300 are electrically connected between the multiple signal lines SLY and the multiple fan-out traces FL. Specifically, in this embodiment, a plurality of impedance adjustment structures 300 are sequentially arranged in the transition area TR along the direction D1, and each impedance adjustment structure 300 is respectively associated with a corresponding signal line SLY and a corresponding fan-out trace FL is electrically connected. For example, the impedance adjustment structure 300-1 is connected between the fan-out trace FL-1 and the signal line SLY1, the impedance adjustment structure 300-2 is connected between the fan-out trace FL-2 and the signal line SLY2, and the impedance adjustment structure 300 -n is connected between the fan-out trace FL-n and the signal line SLYn, but the invention is not limited to this.

Please refer to FIGS. 1 and 3. In this embodiment, the multiple impedance adjustment structures 300 have different sizes of impedance R2. For example, the impedance R2 of the impedance adjustment structure 300 decreases as the impedance adjustment structure 300 moves away from the virtual line C, where the impedance adjustment structure 300-1 (or the impedance adjustment structure 300-m) farthest from the virtual line C has the smallest The impedance R2(1), the impedance adjustment structure 300-n closest to the virtual line C (or the impedance adjustment structure 300-n+1, or the impedance adjustment structure on the virtual line C) has the largest impedance R2(n), However, the invention is not limited to this. In this embodiment, the impedance adjustment structure 300-1 and the impedance adjustment structure 300-m which are farthest from the virtual line C and symmetrical to the virtual line C have substantially equal impedance R2(1), and the closest to the virtual line C Impedance adjustment structure 300-n and impedance adjustment structure 300-n+1 have substantially equal impedance R2(n), where R2(n)-R2(1)=△R; located in impedance adjustment structure 300-1 and impedance adjustment The impedance R2 of the impedance adjustment structure 300 between the structure 300-n (or the impedance adjustment structure 300-n+1 and the impedance adjustment structure 300-m) and the degree of the impedance adjustment structure 300 away from the virtual line C show a negative correlation; In the embodiment, a negative linear relationship is presented, but the invention is not limited to this. In other embodiments, a negative curve relationship may be presented.

Please refer to FIGS. 1, 2 and 3. In this embodiment, each fan-out trace FL of the pixel array substrate 10 and the impedance sum R1+R2 of a corresponding impedance adjustment structure 300 are substantially equal. For example, the sum of the impedance R1(1)+R2 of the fan-out trace FL-1 and the impedance adjustment structure 300-1 (or the fan-out trace FL-m and the impedance adjustment structure 300-m connected to each other) connected to each other (1) Substantially equal to the sum of the impedances of the fan-out traces FL-n and the impedance adjustment structure 300-n connected to each other (or the fan-out traces FL-n+1 and the impedance adjustment structure 300-n+1 connected to each other) R1(n)+R2(n), namely R1(n)+R2(n)=(R1(1)-△R)+(△R+R2(1))=R1(1)+R2(1) . Therefore, the impedance adjustment structure 300 can compensate for the impedance difference between the fan-out traces FL In order to improve the problem of mura caused by the impedance difference of the fan-out trace FL.

Referring to FIG. 1, in this embodiment, the pixel array substrate 10 further includes a plurality of pads BP, which are sequentially arranged in the pad area BL of the substrate 11 along the direction D1, and are electrically connected to a plurality of fan-out traces FL. For example, in the present embodiment, the pixel array substrate 10 further includes a plurality of electronic components 12, which are sequentially arranged on one side 11a of the substrate 11 along the direction D1, and through the bonding with the plurality of pads BP, the Sexually connected to multiple fan-out traces FL.

In this embodiment, the material of the pad BP is generally a metal material, but the invention is not limited thereto. According to other embodiments, the pad BP may also use other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxides of metal materials, or other suitable materials, or metal materials and Stacked layers of other conductive materials. In this embodiment, the electronic component 12 includes, for example, a flexible printed circuit board, and the electronic component 12 may optionally include a driving chip to be a driving component, and the driving component may be packaged on a chip on chip film, COF) to integrate the driver chip into the flexible circuit board. However, the present invention is not limited to this. According to other embodiments, the driver chip can also be integrated into the flexible circuit board using tape automated bonding (TAB) technology, that is, the flexible circuit board can also be rolled Tape Carrier Package (TCP). It should be noted that the present invention does not limit that the electronic component 12 must include a driver chip. According to other embodiments, the electronic component 12 may not include There is a flexible circuit board that drives the chip.

Hereinafter, different embodiments of the impedance adjustment structure 300 will be described, and other identical or similar components are denoted by the same or similar symbols, and the description of the same technical content is omitted. The description of the omitted parts can refer to the first embodiment, and the following description will not be repeated.

FIG. 4 is an enlarged schematic view of the local area I of the pixel array substrate of FIG. 1. FIG. 5 is a schematic diagram of an impedance adjustment structure of FIG. 4. 6 is a schematic diagram of another impedance adjustment structure of FIG. 4. 7 is a schematic cross-sectional view of the impedance adjustment structure of FIG. 5. In particular, FIGS. 5 and 6 may correspond to the impedance adjustment structure 300-1 and the impedance adjustment structure 300-n in FIG. 4, respectively. Fig. 7 may correspond to the section line A-A' of Fig. 5.

Referring to FIGS. 4, 5 and 7, in this embodiment, each impedance adjustment structure 300 connected between the signal line SLY and the fan-out trace FL includes a first conductive pattern 110, a first insulating layer 210 and a second Second conductive pattern 120. The first conductive pattern 110 is disposed on the substrate 11 and electrically connected to a corresponding fan-out trace FL. The first insulating layer 210 is disposed on the first conductive pattern 110 and has a first contact window 410 overlapping the first conductive pattern 110. The second conductive pattern 120 is disposed on the first insulating layer 210 and is electrically connected to a corresponding signal line SLY. For example, in this embodiment, the second conductive pattern 120 may overlap a portion of the first conductive pattern 110, but the invention is not limited thereto.

In this embodiment, each impedance adjustment structure 300 further includes a second insulating layer 220 and a third conductive pattern 130. The second insulating layer 220 is disposed on the second conductive pattern 120, and has a second contact window 420 overlapping the first contact window 410 and a third contact window 430 overlapping the second conductive pattern 120. The third conductive pattern 130 is disposed on the second insulating layer 220, and is electrically connected to the first conductive pattern 110 and the second conductive pattern 120 through the first contact window 410, the second contact window 420, and the third contact window 430. For example, in this embodiment, the first contact window 410 of the first insulating layer 210 is aligned with the second contact window 420 of the second insulating layer 220, and the third conductive pattern 130 passes through the first contact window 410 and the second The contact window 420 is electrically connected to the first conductive pattern 110, and the third conductive pattern 130 is electrically connected to the second conductive pattern 120 through the third contact window 430 of the second insulating layer 220, but the invention is not limited thereto.

4, 5 and 6, in this embodiment, the area of the vertical projection of at least one of the first contact window 410 and the third contact window 430 of each impedance adjustment structure 300 on the substrate 11 varies The impedance adjustment structure 300 increases away from the virtual line C. For example, the first contact window 410-1 and the third contact window 430 of the impedance adjustment structure 300-1 (that is, the impedance adjustment structure away from the virtual line C) connected between the signal line SLY1 and the fan-out trace FL-1 -1 The area of the vertical projection on the substrate 11 is larger than the first contact window of the impedance adjustment structure 300-n (that is, the impedance adjustment structure adjacent to the virtual line C) connected between the signal line SLYn and the fan-out trace FL-n The area of the vertical projection of 410-n and the third contact window 430-n on the substrate 11, but the invention is not limited thereto.

In this embodiment, the vertical projection of the first contact window 410 of each impedance adjustment structure 300 on the substrate 11 and the vertical projection of the third contact window 430 on the substrate 11 The shadow has a first distance L1, and the first distance L1 decreases as the impedance adjustment structure 300 moves away from the virtual line C. Specifically, in this embodiment, the first contact window 410-1 of the impedance adjustment structure 300-1 (ie, the impedance adjustment structure away from the virtual line C) connected between the signal line SLY1 and the fan-out trace FL-1 The first distance L1-1 between the two vertical projections of the third contact window 430-1 on the substrate 11 is smaller than the impedance adjustment structure 300-n (i.e., adjacent to the signal line SLYn and the fan-out trace FL-n The first contact window 410-n and the third contact window 430-n of the impedance adjustment structure of the virtual line C) are the first distance L1-n between two vertical projections on the substrate 11.

In this embodiment, the second contact window 420 (or the first contact window 410) and the third contact window 430 of each impedance adjustment structure 300 are arranged in the direction D1. That is to say, the vertical projection of the first contact window 410 on the substrate 11 of each impedance adjustment structure 300 and the vertical projection of the third contact window 430 on the substrate 11 have a first distance L1 in the direction D1, but the invention does not This is the limit.

In this embodiment, compared to the impedance adjustment structure 300-n adjacent to the virtual line C, the first contact window 410-1 and the third contact window 430-1 of the impedance adjustment structure 300-1 far from the virtual line C are on the substrate The two vertical projections on 11 have a larger area, and the distance between the two vertical projections (that is, the first distance L1-1) is smaller, so that the impedance R2(1) of the impedance adjustment structure 300-1 away from the virtual line C is smaller than the adjacent The impedance adjustment structure 300-n of the virtual line C has an impedance R2(n). In other words, any one of the impedance adjusting structures 300-1~300-n can adjust the area of the vertical projection of the first contact window 410 and the third contact window 430 on the substrate 11 according to the degree of being away from the virtual line C Size and spacing (ie The first distance L1) makes it have the impedance R2 distribution as shown in FIG. 3.

For example, in this embodiment, the first conductive pattern 110 of the impedance adjustment structure 300 and the signal line SLX can selectively belong to the same film layer, and the second conductive pattern 120 and the signal line SLY can selectively belong to the same film layer The third conductive pattern 130 and the pixel electrode PE can selectively belong to the same film layer to avoid an increase in production cost due to the arrangement of the impedance adjustment structure 300, but the invention is not limited to this. In particular, in this embodiment, the electrical resistivity of the third conductive pattern 130 (eg, indium tin oxide) may be greater than that of the first conductive pattern 110 (eg, metal) and the second conductive pattern 120 By adjusting the resistivity of the metal (for example, metal), the adjustment margin of the impedance R2 of the impedance adjustment structure 300 can be increased by adjusting the length (ie, the first distance L1) of the main portion of the third conductive pattern 130 having a large resistivity. However, the present invention is not limited to this. According to other embodiments, the resistivity of the third conductive pattern 130 may also be less than or equal to that of the first conductive pattern 110 and the second conductive pattern 120.

In this embodiment, the materials of the first conductive pattern 110 and the second conductive pattern 120 include metal materials, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, alloys, or other suitable materials, Or a stack of metal materials and other conductive materials. The material of the third conductive pattern 130 includes metal oxides, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or other suitable oxides, or a stacked layer of at least two of the above . However, the present invention is not limited to this. According to other embodiments, the material of the third conductive pattern 130 may also be a metal material, a nitride of a metal material, an oxide of a metal material, or gold Nitrogen oxides, alloys, or other suitable materials, or stacked layers of metallic materials and other conductive materials. In this embodiment, the materials of the first insulating layer 210 and the second insulating layer 220 include inorganic materials (for example: silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or stacked layers of at least two materials ), organic materials, or other suitable materials, or a combination of the above.

8 is an enlarged schematic view of a partial area of the pixel array substrate 10A of the second embodiment of the invention. 9 is a schematic diagram of one of the impedance adjustment structures of FIG. 8. FIG. 10 is a schematic diagram of another impedance adjustment structure of FIG. 8. 11 is a schematic cross-sectional view of the impedance adjustment structure of FIG. 9. In particular, FIGS. 9 and 10 may correspond to the impedance adjustment structure 300A-1 and the impedance adjustment structure 300A-n of FIG. 8, respectively. Fig. 11 may correspond to the section line B-B' of Fig. 9.

8 to 11, the difference between the impedance adjustment structure 300A of this embodiment and the impedance adjustment structure 300 of the first embodiment is that the second conductive pattern 120A of the impedance adjustment structure 300A of this embodiment overlaps the first insulation The opening 120op of the first contact window 410 of the layer 210 and the second contact window 420 of the second insulating layer 220 overlap the opening 120op of the second conductive pattern 120A. For example, in this embodiment, the vertical projection of the first contact window 410 of the first insulating layer 210 on the substrate 11 and the vertical projection of the second contact window 420 of the second insulating layer 220 on the substrate 11 may be located at the The opening 120 op of the two conductive patterns 120A is within the vertical projection on the substrate 11. The second conductive pattern 120A has a side wall 120s (shown in FIG. 11) defining the opening 120op, and the second insulating layer 220 can cover the side wall 120s, but the invention is not limited thereto.

In this embodiment, the second insulating layer 220 further has a fourth contact window 440 overlapping the second conductive pattern 120A. The third contact window 430 and the fourth contact window 440 of the second insulating layer 220 are located on both sides of the second contact window 420, respectively. For example, a plurality of vertical projections of the third contact window 430, the second contact window 420, and the fourth contact window 440 on the substrate 11 of the impedance adjustment structure 300A of this embodiment are arranged in the direction D1, and the third contact window The 430 and the fourth contact window 440 may be selectively disposed on both sides of the second contact window 420 in a symmetrical manner, but the invention is not limited thereto. In this embodiment, the third conductive pattern 130 is electrically connected to the second conductive pattern 120A through the fourth contact window 440 of the second insulating layer 220. That is, compared to the first embodiment, the third conductive pattern 130 of the impedance adjusting structure 300A of this embodiment passes through the third contact window 430 and the fourth contact window 440 of the second insulating layer 220 and the second conductive pattern 120A The electrical connection can further increase the impedance R2 adjustment margin of the impedance adjustment structure 300A.

FIG. 12 is an enlarged schematic view of a partial area of the pixel array substrate 10B of the third embodiment of the invention. 13 is a schematic diagram of an impedance adjustment structure of FIG. 14 is a schematic diagram of another impedance adjustment structure of FIG. 12. In particular, FIGS. 13 and 14 may correspond to the impedance adjustment structure 300B-1 and the impedance adjustment structure 300B-n in FIG. 12, respectively.

12 to 14, the difference between the impedance adjustment structure 300B of this embodiment and the impedance adjustment structure 300A of the second embodiment lies in: the first contact window 410 and the third contact window 430 of the impedance adjustment structure 300B of this embodiment And the fourth contact window 440 The system is arranged in the direction D2. In other words, the pixel array substrate 10B of this embodiment can adjust the spacing between the first contact window 410 and the third contact window 430 in the direction D2 (ie, the first distance L1) to make the impedance adjustment structures 300B-1~300B -n has different magnitudes of impedance R2.

15 is an enlarged schematic view of a partial area of the pixel array substrate 10C of the fourth embodiment of the present invention. FIG. 16 is a schematic diagram of an impedance adjustment structure of FIG. 15. 17 is a schematic diagram of another impedance adjustment structure of FIG. 15. 18 is a schematic cross-sectional view of the impedance adjustment structure 300C-1 of FIG. 16. In particular, FIGS. 16 and 17 may correspond to the impedance adjustment structure 300C-1 and the impedance adjustment structure 300C-n in FIG. 15, respectively. Fig. 18 may correspond to the section line C-C' of Fig. 16.

15-18, the difference between the impedance adjustment structure 300C of this embodiment and the impedance adjustment structure 300B of the third embodiment is that the first conductive pattern 110 of the impedance adjustment structure 300C of this embodiment does not overlap the second conductive Pattern 120B, and the first conductive pattern 110 and the second conductive pattern 120B are arranged in the direction D2. In this embodiment, any one of the impedance adjustment structures 300C-1 to 300C-n can adjust the first contact window 410 overlapping the first conductive pattern 110 and the second overlap according to the degree of being away from the virtual line C The area and distance (ie, the first distance L1) of the two perpendicular projections of the third contact window 430 of the conductive pattern 120B on the substrate 11 have the impedance R2 distribution as shown in FIG. 3.

In this embodiment, the third conductive pattern 130A includes a first conductive portion 130a, a second conductive portion 130b, and a third conductive portion 130c. The first conductive portion 130a Overlap with the first conductive pattern 110. The second conductive portion 130b overlaps the second conductive pattern 120B. The third conductive portion 130c connects the first conductive portion 130a and the second conductive portion 130b. For example, in this embodiment, the third conductive portion 130c may refer to a portion of the third portion between the first conductive portion 130a and the second conductive portion 130b that does not overlap the first conductive pattern 110 and the second conductive pattern 120B Conductive pattern 130A. However, the present invention is not limited to this. According to other embodiments, the third conductive portion 130c may also partially overlap at least one of the first conductive pattern 110 and the second conductive pattern 120.

15, 16 and 17, in this embodiment, part of the third conductive pattern 130A has a width W1 in the direction D1, and the width W1 increases as the impedance adjustment structure 300C moves away from the virtual line C. However, the present invention is not limited to this. According to other embodiments, the width W1 of the third conductive pattern 130A decreases along the direction D1. Specifically, in this embodiment, the third conductive portion 130c of the impedance adjustment structure 300C-1 away from the virtual line C has a larger width W1-1 in the direction D1, so the impedance adjustment structure 300C away from the virtual line C -1 has a smaller impedance R2(1), and the third conductive portion 130c of the impedance adjustment structure 300C-n adjacent to the virtual line C has a smaller width W1-n in the direction D1, so the impedance adjustment structure 300C-n Has a large impedance R2(n). Compared to the impedance adjustment structure 300B of the third embodiment, the impedance adjustment structure 300C of this embodiment can further increase the impedance R2 adjustment margin of the impedance adjustment structure 300C by changing the width W1 of the third conductive portion 130c.

FIG. 19 is an enlarged schematic view of a partial area of the pixel array substrate 10C of the fifth embodiment of the invention. FIG. 20 is a schematic diagram of an impedance adjustment structure of FIG. 19. 21 is a schematic diagram of another impedance adjustment structure of FIG. 19. 22 is a schematic cross-sectional view of one of the impedance adjustment structures of FIG. 19. In particular, FIGS. 20 and 21 may correspond to the impedance adjustment structure 300D-1 and the impedance adjustment structure 300D-n in FIG. 19, respectively. Fig. 22 may correspond to the section line D-D' of Fig. 19.

Referring to FIGS. 19-22, the difference between the impedance adjustment structure 300D of this embodiment and the impedance adjustment structure 300A of the second embodiment is that the impedance adjustment structure 300D of this embodiment further includes a fourth conductive pattern 140 disposed on the first The insulating layer 210 is structurally separated from the second conductive pattern 120A. The second insulating layer 220 also has a fifth contact window 450 overlapping the fourth conductive pattern 140. The third conductive pattern 130B is electrically connected to the fourth conductive pattern 140 through the fifth contact window 450. For example, in this embodiment, the second conductive pattern 120A and the fourth conductive pattern 140 are arranged in the direction D2, but the invention is not limited thereto.

In particular, each fan-out trace FLA of the pixel array substrate 10D of this embodiment includes overlapping first and second conductors FLAa and FLAb, that is, the fan-out trace FLA-1 of this embodiment FLA-n is a multilayer structure. In detail, one end of the first lead FLAa of the fan-out trace FLA is directly connected to the first conductive pattern 110 of the impedance adjustment structure 300D, and one end of the second lead FLAb of the fan-out trace FLA is connected to the second conductive pattern of the impedance adjustment structure 300D 120A is directly connected, and the first wire FLAa and the second wire FLAb of the fan-out trace FLA are electrically connected to each other through the third conductive pattern 130B of the impedance adjustment structure 300D. For example, in this embodiment, the first wire FLAa of the fan-out trace FLA and the first A conductive pattern 110 may be formed on the same first conductive layer. The second conductive line FLAb of the fan-out trace FLA and the second conductive pattern 120A of the impedance adjustment structure 300D may be formed on the same second conductive layer, but the invention is not limited to this . In addition, in this embodiment, the fourth conductive pattern 140 of the impedance adjustment structure 300D and the signal line SLY may be formed on the same second conductive layer and directly connected.

In this embodiment, the configuration of the third conductive pattern 130B is similar to the configuration of the third conductive pattern 130A in the fourth embodiment. Specifically, the third conductive pattern 130B of this embodiment includes a first conductive portion 130a, a second conductive portion 130b, and a third conductive portion 130c. The first conductive portion 130a overlaps with the second conductive pattern 120A. The second conductive portion 130b overlaps the fourth conductive pattern 140. The third conductive portion 130c connects the first conductive portion 130a and the second conductive portion 130b. A plurality of signal lines SLY1~SLYn are arranged in the direction D1, the second conductive pattern 120A and the fourth conductive pattern 140 are arranged in the direction D2, the direction D2 and the direction D1 are staggered, and the third conductive portion 130c of the impedance adjustment structure 300D is in the direction D1 The upper portion has a width W1, and the width W1 increases as the impedance adjustment structure 300D moves away from the virtual line C. The width W1 of the plurality of impedance adjustment structures 300D decreases along the direction D1. The difference between the impedance adjustment structure 300D of this embodiment and the impedance adjustment structure 300A of the second embodiment will be further described below.

19, 20 and 21, in this embodiment, the vertical projection of the first contact window 410 on the substrate 11 and the vertical projection of the fifth contact window 450 on the substrate 11 have a second distance L2, and The second distance L2 decreases as the impedance adjustment structure 300D moves away from the virtual line C. Specifically, in this embodiment, away from virtual The second distance L2-1 of the impedance adjustment structure 300D-1 of the line C is smaller than the second distance L2-n of the impedance adjustment structure 300D-n of the adjacent virtual line C. For example, in this embodiment, the vertical projection area of the fifth contact window 450 of the impedance adjustment structure 300D on the substrate 11 increases as the impedance adjustment structure 300D moves away from the virtual line C, but the invention is not limited to this. According to other embodiments, the vertical projection area of the fifth contact window 450 of each impedance adjustment structure 300D on the substrate 11 decreases along the direction D1.

Overall, in the impedance adjustment structures 300D-1 to 300D-n of this embodiment, the impedance adjustment structure 300D-1 far from the virtual line C has a shorter second distance L2-1 and the projected area on the substrate 11 The larger fifth contact window 450-1, so the impedance adjustment structure 300D-1 far from the virtual line C has a smaller impedance R2(1), and the impedance adjustment structure 300D-n adjacent to the virtual line C has a longer The two distances L2-n and the fifth contact window 450-n with a smaller projection area on the substrate 11, the impedance adjustment structure 300D-n adjacent to the virtual line C has a larger impedance R2(n). In particular, compared to the impedance adjustment structure 300A of the second embodiment, the impedance adjustment structure 300D of this embodiment can adjust the second distance L2, the size of the fifth contact window 450, and the width W1 of the third conductive portion 130c. The impedance R2 adjustment margin of the impedance adjustment structure 300D is further increased.

23 is a schematic diagram of a pixel array substrate according to a sixth embodiment of the invention. FIG. 24 is a schematic diagram of impedance distribution of multiple fan-out traces of FIG. 23. FIG. 25 is a schematic diagram of the impedance distribution of the multiple impedance adjustment structures of FIG. 23. 23, in this embodiment, the difference between the pixel array substrate 10E and the pixel array substrate 10 of the first embodiment The reason is that the length of the plurality of fan-out traces FLB-1~FLB-m of the pixel array substrate 10E in the fan-out area FO decreases along the direction D1, that is, the fan-out traces FLB-1~FLB-m The impedance R1 decreases along the direction D1. In addition, the vertical projection area of at least one of the first contact window (not shown) and the third contact window (not shown) on the substrate 11 of the impedance adjustment structure 300 decreases along the direction D1, that is, the impedance The impedance R2 of the adjustment structures 300-1~300-m increases along the direction D1.

In particular, in the pixel array substrate 10E of this embodiment and the pixel array substrate 10 of the first embodiment, the same or similar elements are denoted by the same or similar symbols, and the description of the same technical content is omitted . The description of the omitted parts can refer to the first embodiment, and will not be repeated here. The differences between the pixel array substrate 10E of this embodiment and the pixel array substrate 10 of the first embodiment will be further described below.

Please refer to FIGS. 23 and 24. In this embodiment, the fan-out traces FLB-1~FLB-m do not have virtual lines (virtual line C as shown in FIG. 1), that is, they are connected to the same electronic component The fan-out traces 12 of FLB-1 to FLB-m are arranged in the fan-out area FO of the substrate 11 in an asymmetric manner. For example, the fan-out trace FLB-1 in the fan-out trace FLB has the longest extension length and thus has the largest impedance R1(1), and the fan-out trace FLB-m in the fan-out trace FLB has the shortest extension length and thus has The minimum impedance R1(m), where R1(m)-R1(1)=-△R, but the invention is not limited to this. In this embodiment, the impedance R1 of the fan-out trace FLB and the degree to which the fan-out trace FLB is away from the fan-out trace FLB-1 in the direction D1 show a linear negative correlation, but The invention is not limited to this.

Please refer to FIGS. 23 and 25. In this embodiment, the impedance R2 of the impedance adjustment structure 300 and the impedance adjustment structure 300 are far away from the impedance adjustment structure 300-1 in the direction D1, showing a linear positive correlation, and R2(m )-R2(1)=△R, but the invention is not limited to this. In this embodiment, each fan-out trace FLB of the pixel array substrate 10E and the impedance sum R1+R2 of the corresponding impedance adjustment structure 300 are substantially equal. Specifically, the sum of the impedances R1(1)+R2(1) of the fan-out traces FLB-1 and the impedance adjustment structure 300-1 connected to each other is substantially equal to the fan-out traces FLB-m and the impedance adjustment structure connected to each other 300-m impedance sum R1(m)+R2(m), that is R1(m)+R2(m)=(R1(1)-△R)+(△R+R2(1))=R1(1 )+R2(1). Therefore, the impedance adjustment structure 300 can compensate for the impedance difference between the plurality of fan-out traces FLB, so as to improve the mura problem caused by the impedance difference between the fan-out traces FLB.

In summary, in the pixel array substrate of the embodiment of the present invention, the impedance adjustment structure connected between the fan-out wiring and the signal line is adjusted by the size of the contact window between each conductive pattern and the distance between each other So that the impedance adjustment structures corresponding to different fan-out traces have different impedances to compensate for the difference in impedance between different fan-out traces. Therefore, the display device of the pixel array substrate is less prone to display mura problems due to impedance differences.

Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field of the art will not deviate from the present invention. Within the spirit and scope, some changes and modifications can be made, so the scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

10: Pixel array substrate 11: Substrate 110: First conductive pattern 120: Second conductive pattern 130: Third conductive pattern 300, 300-1~300-n: Impedance adjustment structure 410: First contact window 430: Third Contact window AA: Active area BL: Pad area BP: Pad C: Virtual lines D1, D2: Direction FL, FL-1~FL-n: Fan-out trace FO: Fan-out area I: Area PE: Pixel electrode PX: pixel structure SLX, SLY, SLY1~SLYn: signal line T: active component TR: transfer area

Claims (22)

A pixel array substrate includes: a substrate having an active area, a transition area, a fan-out area and a pad area arranged in sequence; a plurality of pixel structures are disposed in the active area of the substrate; A plurality of signal lines are electrically connected to the pixel structures and extend from the active area to the transition area; a plurality of impedance adjustment structures are provided in the transition area of the substrate and are electrically connected to the signal lines Each of the impedance adjustment structures includes: a first conductive pattern disposed on the substrate; a first insulating layer disposed on the first conductive pattern and having a first contact window overlapping the first conductive pattern A second conductive pattern disposed on the first insulating layer; a second insulating layer disposed on the second conductive pattern and having a second contact window overlapping the first contact window and overlapping the A third contact window of the second conductive pattern; and a third conductive pattern, disposed on the second insulating layer, and electrically connected to the first contact window, the second contact window, and the third contact window The first conductive pattern and the second conductive pattern; a plurality of fan-out traces, disposed in the fan-out area of the substrate, electrically connected to the impedance adjustment structures, and arranged on both sides of a virtual line, wherein each of the impedances The area of the vertical projection of at least one of the first contact window and the third contact window of the adjustment structure increases as the impedance adjustment structure moves away from the virtual line; and a plurality of pads are provided on the pad of the substrate Area, and are electrically connected to the fan-out traces. The pixel array substrate according to item 1 of the patent application scope, wherein the vertical projection of the first contact window of each of the impedance adjustment structures and the vertical projection of the third contact window have a first distance, and each of the impedance adjustment structures The first distance decreases with the impedance adjustment structure away from the virtual line. The pixel array substrate of claim 1, wherein the first conductive pattern overlaps the second conductive pattern, the second conductive pattern further has an opening overlapping the first contact window, the second The second contact window of the insulating layer also overlaps the opening of the second conductive pattern. The pixel array substrate of claim 3, wherein the vertical projection of the first contact window of the first insulating layer and the vertical projection of the second contact window of the second insulating layer are located on the second conductive Within the vertical projection of the opening of the pattern, the second conductive pattern has a side wall that defines the opening, and the second insulating layer covers the side wall. The pixel array substrate as described in item 1 of the patent application range, wherein the second insulating layer further has a fourth contact window overlapping the second conductive pattern, the third contact window and the fourth contact window are located respectively On both sides of the second contact window, the third conductive pattern is electrically connected to the second conductive pattern through the fourth contact window. The pixel array substrate as described in item 1 of the patent application range, wherein the first contact window and the third contact window of each impedance adjustment structure are arranged in a first direction, and the signal lines are at the first Arranged in the direction. The pixel array substrate according to item 1 of the patent application scope, wherein the first contact window and the third contact window of each impedance adjustment structure are arranged in a first direction, and the signal lines are in a second direction The first direction and the second direction are staggered. The pixel array substrate as described in item 1 of the patent scope, wherein each of the impedance adjustment structures further includes: a fourth conductive pattern, the first conductive pattern overlaps with the second conductive pattern, and the fourth conductive pattern is disposed on On the first insulating layer and separated from the second conductive pattern structure, wherein the second insulating layer further has a fifth contact window overlapping the fourth conductive pattern, the third conductive pattern penetrates the first contact window , The second contact window and the fifth contact window are electrically connected to the first conductive pattern and the fourth conductive pattern. The pixel array substrate as described in item 8 of the patent application range, wherein the first contact window and the third contact window of each impedance adjustment structure are arranged in a first direction, the second conductive pattern and the fourth The conductive patterns are arranged in a third direction, and the third direction is staggered with the first direction. The pixel array substrate as described in item 8 of the patent application, wherein the vertical projection of the first contact window of each of the impedance adjustment structures and the vertical projection of the fifth contact window have a second distance, and each of the impedance adjustment structures The second distance decreases as the impedance adjustment structure moves away from the virtual line. The pixel array substrate as described in item 8 of the patent application range, wherein the area of the vertical projection of the fifth contact window of each of the impedance adjustment structures increases as the impedance adjustment structure moves away from the virtual line. The pixel array substrate as described in item 8 of the patent application range, wherein the third conductive pattern includes: a first conductive portion overlapping the second conductive pattern; a second conductive portion overlapping the fourth conductive pattern ; And a third conductive portion connecting the first conductive portion and the second conductive portion; wherein the signal lines are arranged in a first direction, and the second conductive pattern and the fourth conductive pattern are arranged in a third direction The third direction intersects the first direction, the third conductive portion has a width in the first direction, and the width increases as the impedance adjustment structure moves away from the virtual line. The pixel array substrate as described in item 1 of the patent application range, wherein the first conductive pattern does not overlap the second conductive pattern. The pixel array substrate as described in item 13 of the patent application range, wherein the third conductive pattern includes: a first conductive portion overlapping the first conductive pattern; a second conductive portion overlapping the second conductive pattern ; And a third conductive portion connecting the first conductive portion and the second conductive portion; wherein the signal lines are arranged in a first direction, the first conductive pattern and the second conductive pattern are in a fourth direction Arranged upward, the fourth direction intersects the first direction, the third conductive portion has a width in the first direction, and the width increases as the impedance adjustment structure moves away from the virtual line. A pixel array substrate includes: a substrate having an active area, a transition area and a fan-out area arranged in sequence; a plurality of pixel structures disposed in the active area of the substrate; a plurality of signal lines, The pixel structures are electrically connected and extend from the active area to the transition area; a plurality of fan-out traces are provided in the fan-out area of the substrate and electrically connected to a driving element, wherein the fan-out traces The lines are sequentially arranged in a first direction, each of the fan-out traces has an impedance, and the impedance of the fan-out traces decreases along the first direction; and a plurality of impedance adjustment structures are provided on the substrate The transfer area is electrically connected to the signal lines and the fan-out traces. Each of the impedance adjustment structures includes: a first conductive pattern disposed on the substrate; a first insulating layer disposed on the first conductive On the pattern, and having a first contact window overlapping the first conductive pattern; a second conductive pattern, disposed on the first insulating layer; a second insulating layer, disposed on the second conductive pattern, and A second contact window overlapping the first contact window and a third contact window overlapping the second conductive pattern; and a third conductive pattern disposed on the second insulating layer and passing through the first The contact window, the second contact window and the third contact window are electrically connected to the first conductive pattern and the second conductive pattern; wherein at least one of the first contact window and the third contact window of each impedance adjustment structure The vertical projection area of the person increases along the direction opposite to the first direction. The pixel array substrate according to item 15 of the patent application range, wherein the vertical projection of the first contact window and the vertical projection of the third contact window of each impedance adjustment structure have a first distance, the first distance is along Increasing in this first direction. The pixel array substrate of claim 15 of the patent application, wherein each of the impedance adjustment structures further includes: a fourth conductive pattern, the first conductive pattern overlaps with the second conductive pattern, and the fourth conductive pattern is disposed on On the first insulating layer and separated from the second conductive pattern structure, wherein the second insulating layer further has a fifth contact window overlapping the fourth conductive pattern, the third conductive pattern penetrates the first contact window , The second contact window and the fifth contact window are electrically connected to the first conductive pattern and the fourth conductive pattern. The pixel array substrate of claim 17 of the patent application, wherein the vertical projection of the first contact window and the vertical projection of the fifth contact window of each impedance adjustment structure have a second distance, the second distance is along The first direction is increasing. The pixel array substrate as described in Item 17 of the patent application range, wherein the area of the fifth contact window of each of the impedance adjusting structures decreases along the first direction. The pixel array substrate as described in Item 17 of the patent application range, wherein the third conductive pattern includes: a first conductive portion overlapping the second conductive pattern; a second conductive portion overlapping the fourth conductive pattern And a third conductive portion connecting the first conductive portion and the second conductive portion; wherein the second conductive pattern and the fourth conductive pattern are arranged in a third direction, and the third direction is interleaved with the first direction, The third conductive portion has a width in the first direction, and the width decreases along the first direction. The pixel array substrate as recited in item 15 of the patent application range, wherein the first conductive pattern does not overlap the second conductive pattern. The pixel array substrate of claim 21, wherein the third conductive pattern includes: a first conductive portion overlapping the first conductive pattern; a second conductive portion overlapping the second conductive pattern ; And a third conductive portion connecting the first conductive portion and the second conductive portion; wherein the first conductive pattern and the second conductive pattern are arranged in a fourth direction, the fourth direction and the first direction Interleaved, the third conductive portion has a width in the first direction, and the width decreases along the first direction.

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