TW201818394A - Display device, pixel array substrate and line array structure - Google Patents

Abstract

A line array structure is provided, including long wirings, short wirings, first dummy wirings and connection lines. The substrate has an elongated region, a protruding region and a drive connection region. The elongated region has a first side and second side that respectively elongates along a long-side and short-side directions. The protruding region protrudes out from the first side and is connected to the elongated region. The drive connection region is connected to the second side of the elongated region. The long wirings are disposed in the elongated region and extend to the drive connection region. The short wirings are disposed in the protruding region and are disposed in parallel with the long wirings. The first dummy wirings are disposed in the elongated region and extend to the drive connection region. Each of the short wirings is electrically connected to a corresponding first dummy wiring through one connection line.

Description

Display panel, pixel array substrate and line array structure

The present invention relates to a line array structure, and more particularly to a pixel array substrate including a line array structure and a display panel.

As electronic product designs have become more diverse, at present, a variety of display panels having irregular/non-rectangular display area ranges have been developed, for example, display panels having a watch shape. However, for this type of electronic product, since the display area is not a fixed range of a rectangle, there is a problem that the impedance value is uneven. For example, in a circular display product, in order to connect the signal lines to the display areas on both sides, since the connection manner of the signal lines is a gradual change, an uneven impedance value may occur when driving the signal lines. . Further, it causes severe color unevenness in displaying graphics and affects the display quality of electronic products. In order to meet the needs of the market, there is an urgent need for an electronic product that can solve the problem of uneven impedance values in non-rectangular displays.

The invention provides a line array structure, which can be used to solve the problem of uneven impedance value.

A circuit array structure of the present invention includes a substrate, a plurality of long traces, a plurality of short traces, a plurality of first dummy traces, and a plurality of first connection lines. The substrate has an elongated region, a protruding region, and a driving connection region. The elongated region has a first side extending in a longitudinal direction and a second side extending in a short side. The convex region protrudes outward from the first side edge and is connected to the elongated region. The drive connection area is connected to the second side of the elongated area. A plurality of long traces are disposed in the elongated region and are respectively parallel to the long side direction and extend to the drive connection region. A plurality of short traces are disposed in the protruding area and are disposed in parallel with the long trace. A plurality of first dummy traces are disposed in the elongated region and respectively parallel to the long side direction and extend to the drive connection region. Each short trace is electrically connected to the corresponding first virtual trace through one of the first connecting lines.

In an embodiment of the invention, the circuit array structure further includes a driving circuit disposed in the driving connection region, wherein the long trace and the first dummy trace extend to the driving connection region and are electrically connected to the driving circuit.

In an embodiment of the invention, each long trace is disposed adjacent to at least one first virtual trace.

In an embodiment of the invention, the long traces are the same length as the first dummy traces.

In an embodiment of the invention, the length L2 of the connecting edge connecting the protruding region and the elongated region is smaller than the length L1 of the first side.

In an embodiment of the invention, the line array structure further includes a plurality of second virtual traces and a plurality of second connection lines. A plurality of second dummy traces are disposed in the protruding region and disposed in parallel with the first dummy trace. Each of the long traces is electrically connected to the corresponding second virtual trace through one of the second connecting lines.

In an embodiment of the invention, each short trace is disposed adjacent to at least one second virtual trace.

In an embodiment of the invention, the long traces and the short traces are data lines or scan lines.

The invention further provides a pixel array substrate, which can be used to solve the problem of uneven impedance value.

A pixel array substrate of the present invention includes a substrate and a pixel array. The substrate has an elongated region, a protruding region, and a driving connection region. The elongated region has a first side extending in a longitudinal direction and a second side extending in a short side. The convex region protrudes outward from the first side edge and is connected to the elongated region. The drive connection area is connected to the second side of the elongated area. The pixel array is located on the substrate, wherein the pixel array comprises a plurality of pixel structures, a plurality of first signal lines and a plurality of second signal lines, a plurality of first virtual lines, and a plurality of first connecting lines. The pixel structure is disposed in the elongated region and the protruding region, wherein each pixel structure includes a pixel electrode and an active element. The plurality of first signal lines and the plurality of second signal lines are electrically connected to the corresponding pixel structures, respectively, and the first signal lines and the second signal lines are used to drive the pixel structure. The first signal line or the second signal line includes a plurality of long lines and a plurality of short lines. The long traces are disposed in the elongated regions and are respectively parallel to the long side direction and extend to the drive connection region, and the short traces are disposed in the protruding regions and are disposed in parallel with the long traces. A plurality of first dummy traces are disposed in the elongated region and respectively parallel to the long side direction and extend to the drive connection region. Each short trace is electrically connected to the corresponding first virtual trace through one of the first connecting lines.

In an embodiment of the invention, the pixel array substrate further includes a driving circuit disposed in the driving connection region, wherein the long trace and the first dummy trace extend to the driving connection region and are electrically connected to the driving circuit .

In an embodiment of the invention, each long trace is disposed adjacent to at least one first virtual trace.

In an embodiment of the invention, the long traces are the same length as the first dummy traces.

In an embodiment of the invention, the length L2 of the connecting edge connecting the protruding region and the elongated region is smaller than the length L1 of the first side.

In an embodiment of the invention, the pixel array substrate further includes a plurality of second dummy traces and a plurality of second connection lines. A plurality of second dummy traces are disposed in the protruding regions and are respectively disposed in parallel with the first dummy traces. Each of the long traces is electrically connected to the corresponding second virtual trace through one of the second connecting lines.

In an embodiment of the invention, each of the short traces is disposed adjacent to the at least one second virtual trace.

In an embodiment of the invention, the first signal line is a data line and the second signal line is a scan line.

In an embodiment of the invention, the first signal line is a scan line and the second signal line is a data line.

The present invention further provides a display panel that can be used to solve the problem of uneven impedance values. A display panel of the present invention includes the pixel array substrate and the display medium as described above, and the display medium is driven by the pixel array substrate for display.

Based on the above, in the line array structure, the pixel array substrate and the display panel of the present invention, the short trace is electrically connected to the corresponding first dummy trace through one of the first connection lines, and the first dummy trace is The long trace also extends to the drive connection area. Therefore, the difference in impedance value formed between the long trace and the short trace can be reduced, and the problem of uneven impedance value can be solved.

The above described features and advantages of the invention will be apparent from the following description.

FIG. 1A is a schematic diagram of a display panel according to an embodiment of the invention. As shown in FIG. 1A, the display panel DP includes a pixel array substrate 10 and a display medium 20, wherein the display medium 20 can be driven by the pixel array substrate 10 for display, and the pixel array substrate 10 includes a pixel array 10B and a substrate 10A. In this embodiment, the material of the substrate 10A may be glass, quartz, organic polymer, or an opaque/reflective material (eg, conductive material, metal, wafer, ceramic, or other applicable material), or It is another applicable material. If a conductive material or metal is used, an insulating layer (not shown) is coated on the substrate to avoid short circuit problems. When applied to a flexible device, the substrate can have flexible properties. The pixel array 10B is disposed on the substrate 10A for transmitting a driving signal to drive the display medium 20. Additionally, display medium 20 can include liquid crystal molecules, electrophoretic display media, or other suitable media. The display medium in the following embodiments of the present invention is exemplified by liquid crystal molecules, but is not limited thereto. Further, the liquid crystal molecules in the following embodiments of the present invention are preferably liquid crystal molecules which can be rotated or switched by a horizontal electric field or liquid crystal molecules which can be rotated or switched by a lateral electric field, but are not limited thereto.

Specifically, please refer to FIG. 1B , which is a schematic diagram of a pixel array substrate in a display panel according to an embodiment of the invention. In the embodiment of FIG. 1B, the pixel array substrate is exemplified by a display panel applied to a watch shape, but the invention is not limited thereto. Referring to FIG. 1B, the pixel array substrate 10 includes a pixel array 10B and a substrate 10A. The substrate 10A has an elongated region 102, a protruding region 104, and a driving connection region 106. The elongated region 102 has a first side 102A extending in the longitudinal direction D1 and a second side 102B extending in the short-side direction D2. The raised region 104 projects outwardly from the first side edge 102A and is coupled to the elongated region 102. In addition, the drive connection region 106 is coupled to the second side 102B of the elongated region 102.

In the present embodiment, the elongated region 102 and the protruding region 104 are, for example, display regions constituting the display panel DP, and the display region has an appearance of a watch shape. In addition, the drive connection area 106 is, for example, a non-display area located on the display panel DP. In the above embodiment, a watch having a circular surface is taken as an example, but the present invention is not limited thereto. For example, the raised regions 104 can have other shapes such that the display regions formed by the elongated regions 102 and the raised regions have surface appearances of other shapes (eg, square shapes, triangles, trapezoids, dumbbells, etc.). In the above embodiment, the length L2 of the connecting side of the connecting projection region 104 and the elongated region 102 is smaller than the length L1 of the first side 102A of the elongated region 102. Even when measured in a direction parallel to the first side edge 102A, the length of the convex region 104 is smaller than the length of the elongated region 102. Therefore, the convex region 104 that protrudes outward from the first side edge 102A of the elongated region 102 does not actually exceed the length of the first side edge 102A. According to this, a display panel having a watch-shaped appearance can be constructed.

In the embodiment of FIG. 1A and FIG. 1B, the pixel array 10B is located on the substrate 10A, and includes a plurality of pixel structures 130, a plurality of signal lines 110, a plurality of signal lines 112, a plurality of first virtual traces 120A, and A plurality of second virtual traces 120B. In the embodiment of FIG. 1, the number of the signal line 110, the signal line 112, the first virtual trace 120A, and the second virtual trace 120B is merely an example, and actually does not take the signal line shown in FIG. The number of lines is limited. The pixel structure 130 includes a pixel electrode 131 and an active element 132. Only one pixel electrode 131 and active element 132 are illustrated in FIG. 1B to enable the present invention to be clearly understood by those skilled in the art. The signal line 110 and the signal line 112 are electrically connected to the corresponding pixel structure 130, and the signal line 110 and the signal line 112 are used to drive the pixel electrode 131. In more detail, the signal line 110 can be a data line and the signal line 112 can be a scan line, but the invention is not limited thereto. In another embodiment, the signal line 110 can be a scan line and the signal line 112 can be a data line. In the above embodiment, the scan lines (110 or 112) and the data lines (110 or 112) are disposed to cross each other, and an insulating layer is interposed between the scan lines and the data lines. In other words, the extending direction of the scanning line is not parallel to the extending direction of the data line. Preferably, the extending direction of the scanning line intersects or even perpendicular to the extending direction of the data line. Based on the conductivity considerations, the scan lines and data lines are generally made of a metal material. However, the present invention is not limited thereto, and according to other embodiments, other conductive materials may be used for the scan lines and the data lines. For example: alloys, nitrides of metallic materials, oxides of metallic materials, oxynitrides of metallic materials, or other suitable materials), or stacked layers of metallic materials and other conductive materials.

Referring to FIG. 1B, the signal line 110 includes a plurality of long traces 110A and a plurality of short traces 110B. The long traces 110A are disposed in the elongated regions 102 and are respectively parallel to the longitudinal direction D1 and extend to the drive connection region 106. The short trace 110B is disposed in the protruding region 104 and disposed in parallel with the long trace 110A. In addition, the first dummy traces 120A are disposed in the elongated regions 102 and are respectively parallel to the longitudinal direction D1 and extend to the drive connection region 106. The second dummy trace 120B is disposed in the protruding region 104 and disposed in parallel with the first dummy trace 120A. In an embodiment of the invention, each long trace 110A is disposed adjacent to at least one first dummy trace 120A, and the long trace 110A is the same length as the first dummy trace 120A. In addition, each short trace 110B is disposed adjacent to at least one second dummy trace 120B.

In the above embodiment, the long trace 110A and the short trace 110B are one of a data line or a scan line. That is to say, the long trace 110A and the short trace 110B are both data lines or scan lines, and have different lengths. In the case of a non-rectangular display panel, data lines/scan lines of different lengths are susceptible to different impedance values when driven, wherein differences in impedance values affect the display quality of the display panel. The display panel of the embodiment of the present invention is provided with a first virtual trace 120A and a second dummy trace 120B, in order to reduce the difference in the impedance values of the long trace 110A and the short trace 110B. In more detail, the pixel array substrate 10 further includes a driving circuit 140 disposed in the driving connection region 106, wherein the long trace 110A and the first dummy trace 120A extend to the driving connection region 106 and are electrically connected to the driving circuit 140. Sexual connection. In addition, the short trace 110B is electrically connected to the corresponding first dummy trace 120A through a connection line (not shown). That is, the short trace 110B can be electrically connected to the driving circuit 140 through the first dummy trace 120A. In addition, the long trace 110A is electrically connected to the corresponding second dummy trace 120B through a connection line (not shown). Accordingly, by connecting the short trace 110B to the longer first dummy trace 120A and the long trace 110A to the shorter second dummy trace 120B, it is possible to reduce the drive long trace 110A and short. The difference in impedance value when the line 110B is traced.

In the above embodiment, the long trace 110A and the short trace 110B are electrically connected to the first dummy trace 120A or the second dummy trace 120B through the connection line, respectively. Hereinafter, the manner in which the connecting lines are set will be described.

2A is an enlarged schematic view of a line array within block 200 of FIG. 1B in accordance with an embodiment of the present invention. Referring to FIG. 2A, the circuit array WRA1 includes a substrate, a plurality of long traces 110A, a plurality of short traces 110B, a plurality of first dummy traces 120A, a plurality of second dummy traces 120B, and a plurality of first connection lines C1. With a plurality of second connecting lines C2. The substrate may refer to the substrate 10A of FIGS. 1A and 1B described above, wherein the substrate includes an elongated region 102, a protruding region 104, and a driving connection region 106. The elongated region 102 has a first side 102A extending in the longitudinal direction D1 and a second side 102B extending in the short-side direction D2. The raised region 104 projects outwardly from the first side edge 102A and is coupled to the elongated region 102, and the drive connection region 106 is coupled to the second side 102B of the elongated region 102.

In the embodiment of FIG. 2A, the long trace 110A and the first dummy trace 120A are disposed in the elongated region 102, and as shown in FIG. 1B, the long trace 110A is parallel to the first dummy trace 120A in the longitudinal direction D1. The driving connection region 106 is electrically connected to the driving circuit 140. In addition, the short trace 110B and the second dummy trace 120B are disposed in the protruding region 104, and are disposed in parallel with the long trace 110A and the first dummy trace 120A. In this embodiment, the short trace 110B is electrically connected to the corresponding first virtual trace 120A through one of the first connection lines C1, and the long trace 110A passes through one of the second connection lines C2 and the corresponding second virtual The wiring 120B is electrically connected. In more detail, the short trace 110B located at the extreme edge of the raised region 104 is electrically connected to the first dummy trace 120A that is farther (or closer to the center of the elongated region 102). In addition, the short trace 110B located on the inner side of the protruding region 104 closer to the elongated region 102 is electrically connected to the first dummy trace 120A that is closer (or closer to the edge of the elongated region 102). Similarly, the long trace 110A at the center of the elongated region 102 is electrically connected to the second dummy trace 120B that is farther (the edge of the raised region 104). In addition, the long trace 110A at the edge of the elongated region 102 is electrically connected to the second dummy trace 120B that is closer (the inner side of the projected region 104). In this embodiment, the short trace 110B is connected to the longer first dummy trace 120A by the first connection line C1, and the long trace 110A is connected to the shorter header by the second connection line C2. The two dummy traces 120B can therefore be used to reduce the difference in impedance values shaped when driving the long trace 110A and the short trace 110B.

2B is an enlarged schematic view of a line array in the block 200 of FIG. 1B in another embodiment of the present invention. The embodiment of FIG. 2B is similar to the embodiment of FIG. 2A except that the first connection line C1 and the second connection line C2 are connected differently. Referring to FIG. 2B, in the line array WRA2, the long trace 110A and the first dummy trace 120A are disposed in the elongated region 102, and as shown in FIG. 1B, the long trace 110A is parallel to the first virtual trace 120A. D1 extends to the drive connection region 106 to be electrically connected to the drive circuit 140. In addition, the short trace 110B and the second dummy trace 120B are disposed in the protruding region 104, and are disposed in parallel with the long trace 110A and the first dummy trace 120A. In this embodiment, the short trace 110B is electrically connected to the corresponding first virtual trace 120A through one of the first connection lines C1, and the long trace 110A passes through one of the second connection lines C2 and the corresponding second virtual The wiring 120B is electrically connected. In more detail, the short trace 110B located at the outermost edge of the raised region 104 is electrically connected to the first dummy trace 120A that is closest (or closer to the edge of the elongated region 102). In addition, the short trace 110B located on the inner side of the protruding region 104 closer to the elongated region 102 is electrically connected to the first dummy trace 120A that is farther (or closer to the center of the elongated region 102). Similarly, the long trace 110A at the center of the elongated region 102 is electrically connected to the second dummy trace 120B that is closest (the inner side of the projected region 104). In addition, the long trace 110A at the edge of the elongated region 102 is electrically connected to the second dummy trace 120B that is farther (the edge of the raised region 104). In this embodiment, the short trace 110B is connected to the longer first dummy trace 120A by the first connection line C1, and the long trace 110A is connected to the shorter header by the second connection line C2. The two dummy traces 120B can therefore be used to reduce the difference in impedance values shaped when driving the long trace 110A and the short trace 110B.

In the embodiment of FIG. 1B, FIG. 2A and FIG. 2B, all the short traces 110B are electrically connected to the first dummy traces 120A, and all the long traces 110A are electrically connected to the second dummy traces 120B. Connection, but the invention is not limited thereto. For example, in another embodiment, all of the short traces 110B are electrically connected to the first dummy trace 120A, but the second dummy trace 120B is not disposed. In this embodiment, since the short trace 110B has been connected to the first dummy trace 120A through the first connection line C1, the technical effect of reducing the difference in the impedance value can also be achieved. In addition, although in the embodiment of FIG. 1B, FIG. 2A and FIG. 2B described above, the display panel of the watch shape is taken as an example, it can be known that the concept of the present invention can be applied to any irregularity. / Non-rectangular display panel.

In addition, in an embodiment of the present invention, the line array structure may be the substrate, the plurality of long traces 110A, the plurality of short traces 110B, the plurality of first dummy traces 120A, and the plurality of first connection lines C1. The plurality of second virtual traces 120B and the plurality of second connection lines C2 are formed. Accordingly, the line array structure of the present invention can be similarly used to solve the problem of uneven impedance values.

In summary, in the line array structure, the pixel array substrate, and the display panel of the present invention, the short trace is connected to the longer first virtual trace by the first connection line, and the long trace is borrowed. Connected by the second connecting line to the shorter second virtual trace, and the first dummy trace and the long trace extend to the driving connection region, therefore, the difference in impedance value formed between the long trace and the short trace It can reduce and solve the problem of uneven impedance value. Accordingly, the provision of virtual traces can provide better display quality for non-rectangular display products.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧ pixel array substrate

10A‧‧‧Substrate

10B‧‧‧ pixel array

102‧‧‧Slong area

102A‧‧‧ first side

102B‧‧‧Second side

104‧‧‧Protruding area

106‧‧‧Drive connection area

110‧‧‧Signal line

110A‧‧‧Long trace

110B‧‧‧ short trace

112‧‧‧Signal line

120A‧‧‧First virtual trace

120B‧‧‧Second virtual trace

130‧‧‧ pixel structure

131‧‧‧pixel electrodes

132‧‧‧Active components

140‧‧‧Drive circuit

20‧‧‧ Display media

200‧‧‧ blocks

D1‧‧‧Longside direction

D2‧‧‧ Short-term direction

DP‧‧‧ display panel

L1, L2‧‧‧ length

WRA1, WRA2‧‧‧ line array

FIG. 1A is a schematic diagram of a display panel according to an embodiment of the invention. FIG. 1B is a top view of a pixel array substrate in a display panel according to an embodiment of the invention. 2A is an enlarged schematic view of a line array in block 200 of FIG. 1B in accordance with an embodiment of the present invention. 2B is an enlarged schematic view of a line array in block 200 of FIG. 1B in accordance with another embodiment of the present invention.

Claims (18)

A circuit array structure comprising: a substrate having an elongated region, a protruding region, and a driving connection region, wherein the elongated region has a first side extending along a longitudinal direction and extending along a short side direction a second side, the protruding portion is outwardly protruded from the first side and connected to the elongated region, the driving connection region is connected to the second side of the elongated region; and a plurality of long traces are disposed on the second side The long and narrow regions are parallel to the longitudinal direction and extend to the driving connection region; a plurality of short traces are disposed in the protruding region and are disposed in parallel with the long traces; and the plurality of first virtual walks a line disposed in the elongated area and parallel to the longitudinal direction and extending to the driving connection area; and a plurality of first connecting lines, wherein each of the short lines passes through one of the first connecting lines and the corresponding first Virtual wiring is electrically connected. The circuit array structure of claim 1, further comprising: a driving circuit disposed in the driving connection region, wherein the long traces and the first dummy traces extend to the driving connection region It is electrically connected to the driving circuit. The line array structure of claim 1, wherein each of the long traces is disposed adjacent to the at least one first virtual trace. The line array structure of claim 1, wherein the long traces are the same length as the first dummy traces. The line array structure according to claim 1, wherein a length L2 of the connecting side connecting the protruding portion and the elongated area is smaller than a length L1 of the first side. The circuit array structure of claim 1, further comprising: a plurality of second virtual traces disposed in the protruding region and disposed in parallel with the first virtual traces; and a plurality of second connections a line, wherein each of the long traces is electrically connected to the corresponding second dummy trace through one of the second connection lines. The line array structure of claim 6, wherein each of the short traces is disposed adjacent to the at least one second virtual trace. The line array structure of claim 1, wherein the long traces and the short traces are data lines or scan lines. A pixel array substrate comprising: a substrate having an elongated region, a protruding region, and a driving connection region, wherein the elongated region has a first side extending along a longitudinal direction and extending along a short side direction a second side, the protruding portion is outwardly convex from the first side and connected to the elongated region, the driving connection region is connected to the second side of the elongated region; a pixel array is located at the second side On the substrate, the pixel array includes: a plurality of pixel structures disposed in the elongated region and the protruding region, wherein each of the pixel structures includes a pixel electrode and an active component; and the plurality of first signal lines And the plurality of second signal lines are respectively electrically connected to the corresponding pixel structure, and the first signal lines and the second signal lines are used to drive the pixel structures, wherein the first signal lines or The second signal lines include a plurality of long traces and a plurality of short traces disposed in the elongated region and parallel to the longitudinal direction and extending to the drive connection region, and the plurality of traces The short trace is set to the convex And extending in parallel with the long traces; a plurality of first dummy traces disposed in the elongated region and parallel to the longitudinal direction and extending to the drive connection region; and a plurality of first connections a line, wherein each of the short traces is electrically connected to the corresponding first virtual trace through one of the first connection lines. The pixel array substrate of claim 9, further comprising: a driving circuit disposed in the driving connection region, wherein the long traces and the first dummy traces extend to the driving connection region And electrically connected to the drive circuit. The pixel array substrate of claim 9, wherein each of the long traces is disposed adjacent to the at least one first dummy trace. The pixel array substrate of claim 9, wherein the long traces are the same length as the first dummy traces. The pixel array substrate of claim 9, wherein the length L2 of the connecting edge connecting the protruding region to the elongated region is smaller than the length L1 of the first side. The pixel array substrate of claim 9, wherein the pixel array further comprises: a plurality of second dummy traces disposed in the protruding region, and respectively disposed in parallel with the first virtual traces And a plurality of second connecting lines, wherein each of the long connecting lines is electrically connected to the corresponding second virtual connecting line through one of the second connecting lines. The pixel array substrate of claim 14, wherein each of the short traces is disposed adjacent to at least one second dummy trace. The pixel array substrate of claim 9, wherein the first signal lines are data lines and the second signal lines are scan lines. The pixel array substrate of claim 9, wherein the first signal lines are scan lines and the second signal lines are data lines. A display panel comprising the pixel array substrate according to claim 9 to claim 17, and a display medium driven by the pixel array substrate for display.