TWI694561B - Sensor packages and manufactuirng methods thereof - Google Patents
Sensor packages and manufactuirng methods thereof Download PDFInfo
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- TWI694561B TWI694561B TW105133182A TW105133182A TWI694561B TW I694561 B TWI694561 B TW I694561B TW 105133182 A TW105133182 A TW 105133182A TW 105133182 A TW105133182 A TW 105133182A TW I694561 B TWI694561 B TW I694561B
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- G06—COMPUTING; CALCULATING OR COUNTING
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Abstract
Description
本發明實施例是關於感測器封裝件及其製造方法。 The embodiment of the invention relates to a sensor package and a manufacturing method thereof.
將數個系統所需的積體電路組合在單一封裝件中,是現在對於複雜的電子系統的普遍做法,且通常稱作系統級封裝(system-in-package,SIP)。SIP組合件可在單一封裝件中包含數位、類比、混合信號,且通常包含射頻功能。對於SIP應用方面,設計為接收或發射電磁波的天線收發器(transceiver)可應用於毫米波無線通信(millimeter wave wireless communication)、無線網路(WiFi)以及電信(telecommunication)等。然而,天線收發器的大尺寸以及製造成本已成為問題。 Combining integrated circuits required by several systems in a single package is now common practice for complex electronic systems, and is commonly referred to as system-in-package (SIP). SIP assemblies can contain digital, analog, and mixed signals in a single package, and usually include radio frequency functions. For SIP applications, antenna transceivers designed to receive or transmit electromagnetic waves can be used in millimeter wave wireless communication, wireless network (WiFi), and telecommunications. However, the large size of the antenna transceiver and the manufacturing cost have become problems.
根據本發明的一些實施例,一種感測器封裝件包括半導體晶粒以及重佈線層結構。所述半導體晶粒具有感測表面。所述重佈線層結構經配置以形成天線發送器結構以及天線接收器結構,所述天線發送器結構位於所述半導體晶粒側邊,且所述天線接收器結構位於所述半導體晶粒的所述感測表面上方。 According to some embodiments of the present invention, a sensor package includes a semiconductor die and a redistribution layer structure. The semiconductor die has a sensing surface. The redistribution layer structure is configured to form an antenna transmitter structure and an antenna receiver structure, the antenna transmitter structure is located on the side of the semiconductor die, and the antenna receiver structure is located on the semiconductor die Above the sensing surface.
根據本發明的一些替代性實施例,一種感測器封裝件包括半導體晶粒以及重佈線層結構。所述半導體晶粒具有感測表面。所述重佈線層結構經配置以形成多個感測圖案、天線發送器結構以及天線接收器結構,所述感測圖案位於所述半導體晶粒的所述感測表面上方,所述天線發送器結構以及所述天線接收器結構位於所述多個感測圖案側邊。 According to some alternative embodiments of the invention, a sensor package includes a semiconductor die and a redistribution layer structure. The semiconductor die has a sensing surface. The redistribution layer structure is configured to form a plurality of sensing patterns, an antenna transmitter structure, and an antenna receiver structure, the sensing patterns are located above the sensing surface of the semiconductor die, the antenna transmitter The structure and the antenna receiver structure are located on the sides of the plurality of sensing patterns.
根據本發明的另一些替代性實施例,一種感測器封裝件的形成方法包括:提供具有感測表面的半導體晶粒;於所述感測表面上方形成重佈線層結構,其中形成所述重佈線層結構包括形成天線發送器結構以及天線接收器結構;以及於所述重佈線層結構上方形成聚合物層。 According to other alternative embodiments of the present invention, a method for forming a sensor package includes: providing a semiconductor die having a sensing surface; forming a redistribution layer structure above the sensing surface, wherein the heavy The wiring layer structure includes forming an antenna transmitter structure and an antenna receiver structure; and forming a polymer layer above the redistribution layer structure.
1、2、3、4、5、6、7、8、9:感測器封裝件 1, 2, 3, 4, 5, 6, 7, 8, 9: sensor package
10:封裝區域 10: Package area
12:晶粒區域 12: grain area
14:周邊區域 14: surrounding area
100:半導體晶粒 100: semiconductor die
101:感測表面 101: Sensing surface
102:基底 102: base
103:接墊 103: pad
104:鈍化層 104: passivation layer
105:接點 105: contact
108:封裝體 108: package
110、114、115、116:聚合物層 110, 114, 115, 116: polymer layer
112、118:重佈線層結構 112, 118: Redistribution layer structure
120:焊球 120: solder ball
122:底膠層 122: primer layer
124:保護層 124: protective layer
200:緩衝層 200: buffer layer
300、302、304:製程 300, 302, 304: process
AR:天線接收器結構 AR: antenna receiver structure
AT:天線發送器結構 AT: antenna transmitter structure
C1、C2、C3、C4:載板 C1, C2, C3, C4: carrier board
EP:增強圖案 EP: Enhanced pattern
ML:分子連接物 ML: molecular linker
P1:第一圖案 P1: the first pattern
P2:第二圖案 P2: second pattern
P3:第三圖案 P3: third pattern
RDL、RDL1、RDL2、RDL3:重佈線層 RDL, RDL1, RDL2, RDL3: redistribution layer
SP:感測圖案 SP: Sensing pattern
TV:穿孔 TV: perforated
圖1A至圖1G為根據一些實施例所繪示的感測器封裝件的製造方法的剖面示意圖。 1A to 1G are schematic cross-sectional views of a method of manufacturing a sensor package according to some embodiments.
圖2以及圖3為根據一些實施例所繪示的感測器封裝件的天線發送器結構以及天線接收器結構的簡化上視圖。 2 and 3 are simplified top views of the antenna transmitter structure and the antenna receiver structure of the sensor package according to some embodiments.
圖4A至圖4F為根據替代性實施例所繪示的感測器封裝件的製造方法的剖面示意圖。 4A to 4F are schematic cross-sectional views of a method of manufacturing a sensor package according to an alternative embodiment.
圖5以及圖7至圖10為根據一些實施例所繪示的感測器封裝件的剖面示意圖。 5 and 7 to 10 are schematic cross-sectional views of a sensor package according to some embodiments.
圖6為根據一些實施例所繪示的感測器封裝件的天線發送器結構以及天線接收器結構的簡化上視圖。 6 is a simplified top view of an antenna transmitter structure and an antenna receiver structure of a sensor package according to some embodiments.
圖11至圖13為根據又一些替代性實施例所繪示的感測器封裝件的剖面示意圖。 11 to 13 are schematic cross-sectional views of sensor packages according to still other alternative embodiments.
圖14為根據又一些替代性實施例所繪示的感測器封裝件的天線發送器結構以及天線接收器結構的簡化上視圖。 14 is a simplified top view of an antenna transmitter structure and an antenna receiver structure of a sensor package according to yet other alternative embodiments.
圖15為根據一些實施例所繪示的感測器封裝件的製造方法的流程圖。 15 is a flowchart of a method for manufacturing a sensor package according to some embodiments.
以下揭露內容提供許多不同的實施例或實例,用於實現所提供標的之不同特徵。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本揭露為目的。當然,這些僅僅為實例而非用以限制。舉例來說,於以下描述中,在第一特徵上方或在第一特徵上形成第二特徵可包括第二特徵與第一特徵形成為直接接觸的實施例,且亦可包括第二特徵與第一特徵之間可形成有額外特徵使得第二特徵與第一特徵可不直接接觸的實施例。此外,本揭露在各種實例中可使用相同的元件符號及/或字母來指代相同或類似的部件。元件符號的重複使用是為了簡單及清楚起見,且並不表示所欲討論的各個實施例及/或配置本身之間的關係。 The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations described below are for the purpose of conveying the present disclosure in a simplified manner. Of course, these are only examples and not limiting. For example, in the following description, forming the second feature above or on the first feature may include an embodiment where the second feature is formed in direct contact with the first feature, and may also include the second feature and the first feature An embodiment in which additional features may be formed between features so that the second feature and the first feature may not directly contact. In addition, the present disclosure may use the same element symbols and/or letters to refer to the same or similar components in various examples. The repeated use of element symbols is for simplicity and clarity, and does not represent the relationship between the various embodiments and/or configurations to be discussed.
另外,為了易於描述附圖中所繪示的一個構件或特徵與另一構件或特徵的關係,本文中可使用例如「在...下」、「在...下方」、「下部」、「在...上」、「在...上方」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外,所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向(旋轉90度或在其他定向),而本文所用的空間相對術 語相應地作出解釋。 In addition, in order to easily describe the relationship between one component or feature depicted in the drawings and another component or feature, for example, "below", "below", "lower", Spatially relative terms such as "on", "above", "upper" and similar terms. In addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of elements in use or operation. The device can be otherwise oriented (rotated 90 degrees or at other orientations), and the spatial relative technique used herein The language is interpreted accordingly.
圖1A至圖1G為根據一些實施例所繪示的感測器封裝件的製造方法的剖面示意圖。 1A to 1G are schematic cross-sectional views of a method of manufacturing a sensor package according to some embodiments.
請參照圖1A,提供載板C1,其中載板C1具有半導體晶粒100以及至少一穿孔TV。在一些實施例中,載板C1具有形成於其上的剝離層(未繪示)以及介電層(未繪示),且剝離層位於載板C1與介電層之間。在一些實施例中,舉例來說,載板C1為玻璃基板,形成於玻璃基板上的剝離層為光熱轉換(light-to-heat conversion;LTHC)釋放層,且形成於剝離層上的介電層為聚苯並噁唑(polybenzoxazole;PBO)層。在一些實施例中,載板C1具有封裝區域10,其中封裝區域10包括晶粒區域12以及周邊區域14,且周邊區域14位於晶粒區域12側邊或圍繞晶粒區域12。半導體晶粒100位於晶粒區域12中,且穿孔TV位於周邊區域14中。在一些實施例中,半導體晶粒100為邏輯晶粒、感測器晶粒或成像晶粒(imaging chip),且其正面處具有感測表面101。在一些實施例中,半導體晶粒100具有基底102、位於基底102上方的至少一接墊103、位於基底102上方且裸露出部分接墊103的鈍化層104,以及位於鈍化層104上方且電性連接至接墊103的接點105。具體地說,接點105形成為半導體晶粒100的上部。接點105從半導體晶粒100的下部或剩餘部分延伸出來。在一些實施例中,接點105包括錫凸塊、金凸塊、銅柱或類似物,且由電鍍製程所形成。在一些實施例中,穿孔TV包括銅、鎳、錫、其組合或類似物,且由電鍍製程所形成。在一些實施例中,取放半導體晶粒100於載板C1上之後,於載板C1上形成穿孔TV。在替代性實施例中,
取放半導體晶粒100於載板C1上之前,於載板C1上形成穿孔TV。
1A, a carrier board C1 is provided, wherein the carrier board C1 has a semiconductor die 100 and at least one through-hole TV. In some embodiments, the carrier board C1 has a peeling layer (not shown) and a dielectric layer (not shown) formed thereon, and the peeling layer is located between the carrier board C1 and the dielectric layer. In some embodiments, for example, the carrier C1 is a glass substrate, the peeling layer formed on the glass substrate is a light-to-heat conversion (LTHC) release layer, and the dielectric formed on the peeling layer The layer is a polybenzoxazole (PBO) layer. In some embodiments, the carrier board C1 has a
請參照圖1B,於載板C1上方形成封裝體108,以囊封半導體晶粒100以及穿孔TV。在一些實施例中,封裝體108環繞半導體晶粒100以及穿孔TV,且裸露出穿孔TV以及接點105的表面。封裝體108包括模製化合物(例如環氧樹脂)、光敏材料(例PBO)、聚醯亞胺(polyimide;PI)或苯環丁烯(benzocyclobutene;BCB)、其組合或類似物。封裝體108的形成方法包括:於載板C1上形成封裝體材料層(未繪示),且所述封裝體材料層覆蓋半導體晶粒100以及穿孔TV;以及進行研磨製程以移除部分所述封裝體材料層,直到裸露出穿孔TV以及接點105的表面。
1B, a
請參照圖1C,於半導體晶粒100的感測表面101上方(在此例子中,同時於封裝體108上方)形成重佈線層結構112,其中重佈線層結構112經圖案化以定義天線發送器結構AT、天線接收器結構AR以及重佈線層RDL。貫穿全文,重佈線層結構112稱為「前側重佈線層結構」。在一些實施例中,重佈線層RDL形成於天線發送器結構AT與天線接收器結構AR之間。在一些實施例中,天線接收器結構AR包括位於半導體晶粒100的感測表面101上方的多個第一圖案P1。在一些實施例中,重佈線層RDL形成為電性連接至穿孔TV以及接點105,天線發送器結構AT形成為電性耦接至訊號發送端(未繪示),且天線接收器結構AR形成為電性耦接至半導體晶粒100。
1C, a
在一些實施例中,天線接收器結構AR的第一圖案P1排列為陣列,且天線發送器結構AT環繞天線接收器結構AR的第一圖案P1。在一些實施例中,天線發送器結構AT中的每一者具有 環狀,且天線接收器結構AR的第一圖案P1具有島狀或魚骨狀,如圖2以及圖3的上視圖所示。然而,本發明實施例並不以此為限。依天線收發器的電磁場的頻率以及極性,可調整天線發送器結構AT以及天線接收器結構AR中的每一者的形狀。換句話說,依製程需要,天線發送器結構AT可具有環狀、條狀、螺旋狀、波狀、彎曲狀或其組合,且天線接收器結構AR的第一圖案P1中的每一者可具有環狀、蛇狀、條狀、魚骨狀、柵欄狀、網格狀、環狀或其組合。 In some embodiments, the first pattern P1 of the antenna receiver structure AR is arranged in an array, and the antenna transmitter structure AT surrounds the first pattern P1 of the antenna receiver structure AR. In some embodiments, each of the antenna transmitter structures AT has The ring shape, and the first pattern P1 of the antenna receiver structure AR has an island shape or a fishbone shape, as shown in the upper views of FIGS. 2 and 3. However, the embodiments of the present invention are not limited thereto. The shape of each of the antenna transmitter structure AT and the antenna receiver structure AR can be adjusted according to the frequency and polarity of the electromagnetic field of the antenna transceiver. In other words, according to process requirements, the antenna transmitter structure AT may have a ring shape, a strip shape, a spiral shape, a wave shape, a curved shape, or a combination thereof, and each of the first patterns P1 of the antenna receiver structure AR may It has a ring shape, a snake shape, a strip shape, a fish bone shape, a fence shape, a grid shape, a ring shape, or a combination thereof.
重佈線層結構112的形成方法包括以下操作。在一些實施例中,聚合物層110形成為橫跨晶粒區域12以及周邊區域14,且裸露出穿孔TV以及接點105的表面。在一些實施例中,聚合物層110包括PBO、聚醯亞胺,BCB、其組合或類似物。接著,晶種材料層(未繪示)形成為橫跨晶粒區域12以及周邊區域14、覆蓋聚合物層110的表面,且覆蓋由聚合物層110所裸露出的穿孔TV以及接點105的表面。在一些實施例中,晶種材料層包括鈦/銅複合層,且由濺鍍製程所形成。接著,於晶種材料層上形成具有開口的光阻層(未繪示),且光阻層的開口裸露出隨後形成的重佈線層結構112的預定位置。然後,進行電鍍製程,以於光阻層的開口所裸露出的晶種材料層上形成金屬材料層(例如,銅層)。移除光阻層以及下伏晶種材料層,以形成重佈線層結構112。接著,於重佈線層結構112上方形成聚合物層114。在一些實施例中,聚合物層114包括PBO、聚醯亞胺、BCB、其組合或類似物。
The method of forming the
請參照圖1D,載板C1從結構的背側剝離,且另一個載板C2接合至相同結構的前側。在一些實施例中,載板C1連同半
導體晶粒100、穿孔TV、封裝體108以及重佈線層結構112一起翻轉並接合至載板C2,載板C1的剝離層於光熱作用下分解,接著,載板C1從結構剝離。在一些實施例中,載板C2具有最終結構。在一些實施例中,載板C2具有形成於其上的剝離層(未繪示)以及介電層(未繪示),剝離層位於載板C2與介電層之間,且介電層接合至聚合物層114。在一些實施例中,舉例來說,載板C2為玻璃基板,形成於玻璃基板上的剝離層為LTHC釋放層,且形成於剝離層上的介電層為PBO層。
Referring to FIG. 1D, the carrier board C1 is peeled from the back side of the structure, and another carrier board C2 is bonded to the front side of the same structure. In some embodiments, carrier board C1
The conductor die 100, the through-hole TV, the
請參照圖1E,於半導體晶粒100的背側上方形成重佈線層結構118。貫穿全文,重佈線層結構118稱為「背側重佈線層結構」。在一些實施例中,重佈線層結構118形成為電性連接至穿孔TV。
Referring to FIG. 1E, a
重佈線層結構118的形成方法包括以下操作。在一些實施例中,聚合物層116形成為橫跨晶粒區域12以及周邊區域14,並裸露出穿孔TV的表面。在一些實施例中,聚合物層116包括PBO、聚醯亞胺、BCB、其組合或類似物。接著,晶種材料層(未繪示)形成為橫跨晶粒區域12以及周邊區域14、覆蓋聚合物層116的表面,且覆蓋由聚合物層116所裸露出的穿孔TV的表面。在一些實施例中,晶種材料層包括鈦/銅複合層,且由濺鍍製程所形成。接著,於晶種材料層上形成具有開口的光阻層(未繪示),且光阻層的開口裸露出隨後形成的重佈線層結構118的預定位置。然後,進行電鍍製程,以於光阻層的開口所裸露出的晶種材料層上形成金屬材料層(例如,銅層)。移除光阻層以及下伏晶種材料層,以形成重佈線層結構118。
The method of forming the
請參照圖1F,於重佈線層結構118上置放焊凸塊(例如,焊球120),且焊凸塊電性連接至重佈線層結構118。在一些實施例中,焊球120由具有低阻值的導電材料所構成,例如錫、鉛、銀、銅、鎳、鉍或其合金,且由合適的製程所形成,例如蒸鍍、電鍍、落球(ball drop)、或網印(screen printing)。接著,視情況形成底膠層122,以囊封重佈線層結構118以及焊球120的下部。底膠層122包括模製化合物(例如環氧樹脂),且使用點膠(dispensing)、注入(injecting),及/或噴灑(spraying)技術來形成。
Referring to FIG. 1F, a solder bump (for example, a solder ball 120) is placed on the
圖1F的結構以球柵陣列(ball grid array;BGA)封裝為例來說明。然而,本發明實施例並不以此為限。在替代性實施例中,依製程需要,也可使用其他封裝形式,例如平面網格陣列(land grid array;LGA)封裝。 The structure of FIG. 1F is illustrated by taking a ball grid array (BGA) package as an example. However, the embodiments of the present invention are not limited thereto. In alternative embodiments, other packaging forms, such as a land grid array (LGA) package, can also be used as required by the manufacturing process.
請參照圖1G,載板C2從結構的前側剝離,且視情況於相同結構的背側形成保護層124。在一些實施例中,載板C2連同半導體晶粒100、穿孔TV、封裝體108、重佈線層結構112/118以及焊球120一起翻轉,載板C2的剝離層於光熱作用下分解,接著,載板C2從結構剝離。在一些實施例中,於聚合物層114上方形成保護層124。在一些實施例中,保護層124為具有足夠機械強度的介電層或絕緣層。在一些實施例中,保護層124配置為保護下伏結構抵抗來自(舉例來說)指頭表面的移動離子。由此形成本發明實施例的感測器封裝件1,其可作為指紋感測器封裝件。
1G, the carrier C2 is peeled from the front side of the structure, and a
在一些實施例中,耦合至半導體晶粒100的第一圖案P1作為感測/偵測電極或感測畫素,且第一圖案P1中的每一者與指 頭表面之間所形成的電容取決於被偵測的指紋的不平坦度,由此得到所謂的指紋圖案。在替代性實施例中,第一圖案P1作為增強圖案(enhancement patterns),用以增強電磁波的強度。在一些實施例中,作為增強圖案的第一圖案P1為浮置電極,舉例來說,依設計需要,第一圖案P1與感測電極可部分重疊或彼此分開。 In some embodiments, the first pattern P1 coupled to the semiconductor die 100 serves as a sensing/detecting electrode or sensing pixel, and each of the first pattern P1 and the fingers The capacitance formed between the head surfaces depends on the unevenness of the detected fingerprint, thereby obtaining a so-called fingerprint pattern. In an alternative embodiment, the first pattern P1 serves as an enhancement pattern to enhance the intensity of electromagnetic waves. In some embodiments, the first pattern P1 as the enhancement pattern is a floating electrode. For example, according to design requirements, the first pattern P1 and the sensing electrode may partially overlap or separate from each other.
貫穿全文,圖1A至圖1G中描述的方法又稱為「先取放晶粒(chip PnP first;chip pick-and-place first)製程」,其中取放半導體晶粒100於載板上之前,先形成背側重佈線層結構118。然而,本發明實施例並不以此為限。在一些實施例中,本發明實施例的感測器封裝件可由「先背側RDL(backside RDL first)製程」所製作,其中取放半導體晶粒100於載板上之後,才形成背側重佈線層結構118。
Throughout the text, the method described in FIGS. 1A to 1G is also referred to as “chip pick-and-place first (chip PnP first) process”, in which the semiconductor die 100 is placed on the carrier board before The backside
圖4A至圖4F為根據替代性實施例所繪示的感測器封裝件的製造方法的剖面示意圖。圖4A至圖4F中構件的材料與形成方法與描述於圖1A至圖1G中構件的材料與形成方法類似,故以下描述方法之間的不同處,相似處則不再贅述。 4A to 4F are schematic cross-sectional views of a method of manufacturing a sensor package according to an alternative embodiment. The materials and forming methods of the members in FIGS. 4A to 4F are similar to the materials and forming methods described in FIGS. 1A to 1G. Therefore, the differences between the following description methods will not be repeated.
請參照圖4A,提供載板C3,其中載板C3具有重佈線層結構118(即,背側重佈線層結構)以及焊球120。在一些實施例中,載板C3具有形成於其上的剝離層以及介電層,且剝離層位於載板C3與介電層之間。在一些實施例中,載板C3具有封裝區域10,其中封裝區域10包括晶粒區域12以及周邊區域14,且周邊區域14位於晶粒區域12側邊或圍繞晶粒區域12。在一些實施例中,聚合物層116形成為橫跨晶粒區域12以及周邊區域14,且具有裸露出部分載板C3的開口。於聚合物層116上方形成重佈線層
結構,且重佈線層結構填入開口。於重佈線層結構118上置放焊球120,且焊球120電性連接至重佈線層結構118。底膠層122形成為囊封重佈線層結構118以及焊球120的下部。
4A, a carrier board C3 is provided, wherein the carrier board C3 has a redistribution layer structure 118 (ie, a backside redistribution layer structure) and a
請參照圖4B,包括重佈線層結構118以及焊球120的結構從載板C3剝離,且相同結構一起翻轉並通過緩衝層200接合至另一個載板C4。在一些實施例中,緩衝層200包括聚合物,例如模製化合物及/或黏著劑。在一些實施例中,於按壓(pressing)技術之後,緩衝層200覆蓋由焊球120以及底膠層122裸露出的表面。
Referring to FIG. 4B, the structure including the
請參照圖4C,於載板C4上置放至少一穿孔TV以及半導體晶粒100。在一些實施例中,於聚合物層116上方形成穿孔TV,且穿孔TV電性連接至重佈線層結構118,半導體晶粒100的背側接合至聚合物層116。在一些實施例中,半導體晶粒100為邏輯晶粒、感測器晶粒或成像晶粒,且其正面處具有感測表面101。在一些實施例中,半導體晶粒100具有基底102、位於基底102上方的接墊103、位於基底102上方且裸露出部分接墊103的鈍化層104,以及位於鈍化層104上方且電性連接至接墊103的接點105。
Referring to FIG. 4C, at least one through-hole TV and semiconductor die 100 are placed on the carrier C4. In some embodiments, a through-hole TV is formed over the
請參照圖4D,於載板C4上方形成封裝體108以囊封半導體晶粒100以及穿孔TV。在一些實施例中,封裝體108環繞半導體晶粒100以及穿孔TV,且裸露出穿孔TV以及接點105的表面。
4D, a
請參照圖4E,於半導體晶粒100的感測表面101上方形成重佈線層結構112(即,前側重佈線層結構),其中形成重佈線層結構112包括形成天線發送器結構AT、天線接收器結構AR以
及重佈線層RDL。接著,於重佈線層結構112上方形成聚合物層114。
Referring to FIG. 4E, a redistribution layer structure 112 (ie, a front-side redistribution layer structure) is formed above the
請參照圖4F,視情況於聚合物層114上方形成保護層124,並移除緩衝層200以及載板C4。由此完成如圖1G所示的感測器封裝件1。
Referring to FIG. 4F, a
在上述實施例中,在感測器封裝件1中,是以天線發送器結構AT具有單環且天線接收器結構AR的第一圖案P1為單層作為例子來說明,但並不用以限定本發明實施例。在替代性實施例中,天線發送器結構AT可設計為具有雙環或其他合適形狀,且天線接收器結構AR可設計為具有位於不同水平(levels)處的多層圖案。
In the above embodiment, in the
以下將說明本發明實施例的感測器封裝件,其可作為指紋感測器封裝件。在一些實施例中,感測器封裝件1/2/3/4/5/6包括半導體晶粒100以及重佈線層結構112。半導體晶粒100具有感測表面101。重佈線層結構112經配置以形成天線發送器結構AT以及天線接收器結構AR。天線發送器結構AT位於半導體晶粒100側邊,且天線接收器結構AR位於半導體晶粒100的感測表面101上方。在一些實施例中,周邊區域14中的天線發送器結構AT環繞晶粒區域12中的天線接收器結構AR。
The sensor package of the embodiment of the present invention will be described below, which can be used as a fingerprint sensor package. In some embodiments, the
在一些實施例中,重佈線層結構112更包括位於天線發送器結構AT與天線接收器結構AR之間的重佈線層RDL。重佈線層RDL配置為將周邊區域14中的穿孔TV連接至晶粒區域12中的半導體晶粒100的接點105。在一些實施例中,天線發送器結構AT具有單環結構,其環繞天線接收器結構AR的第一圖案P1,如
圖1G及圖4F的剖面圖和圖2及圖3的上視圖所示。在替代性實施例中,天線發送器結構AT具有雙環結構,其環繞天線接收器結構AR的第一圖案P1,如圖5的剖面圖以及圖6的上視圖所示。
In some embodiments, the
在一些實施例中,重佈線層結構112為多層結構,而非單層結構。舉例來說,如圖7的感測器封裝件3以及圖8的感測器封裝件4所示,重佈線層結構112為雙層結構,其包括重佈線層RDL1以及RDL2、天線發送器結構AT,以及包括第一圖案P1以及第二圖案P2的天線接收器結構AR。在一些實施例中,重佈線層RDL1形成為電性連接至穿孔TV,且天線接收器結構AR的第一圖案P1同時形成於半導體晶粒100的感測表面101上方。接著,重佈線層RDL2形成為電性連接至重佈線層RDL1,天線接收器結構AR的第二圖案P2同時形成於第一圖案P1上方,且天線發送器結構AT同時形成為圍繞第二圖案P2。接著,於天線發送器結構AT以及天線接收器結構AR上方形成聚合物層115以及視情況選擇的保護層124。在一些實施例中,第二圖案P2未對齊於第一圖案P1,如圖7所示。在一些實施例中,第一圖案P1作為增強圖案,且第二圖案P2作為感測電極。在替代性實施例中,第二圖案P2對齊於第一圖案P1,如圖8所示。在替代性實施例中,第一圖案P1以及第二圖案P2均作為感測電極。
In some embodiments, the
圖9的感測器封裝件5類似於圖7的感測器封裝件3,其差別在於:圖9中的天線發送器結構AT具有位於不同水平處的兩層圖案。具體地說,於形成重佈線層RDL1以及第一圖案P1期間,形成天線發送器結構AT的內層圖案,且於形成重佈線層RDL2以及第二圖案P2期間,形成天線發送器結構AT的外層圖案。
The
在一些實施例中,如圖10的感測器封裝件6所示,重佈線層結構112為三層結構,其包括重佈線層RDL1、RDL2以及RDL3、天線發送器結構AT,以及具有第一圖案P1、第二圖案P2以及第三圖案P3的天線接收器結構AR。在一些實施例中,重佈線層RDL1形成為電性連接至穿孔TV,且天線接收器結構AR的第一圖案P1同時形成於半導體晶粒100的感測表面101上方。接著,重佈線層RDL2形成為電性連接至重佈線層RDL1,且天線接收器結構AR的第二圖案P2同時形成於第一圖案P1上方。然後,重佈線層RDL3形成為電性連接至重佈線層RDL2,天線接收器結構AR的第三圖案P3同時形成於第二圖案P2上方,且天線發送器結構AT同時形成為圍繞第三圖案P3。在一些實施例中,第二圖案P2未對齊於第一圖案P1,而第三圖案P3對齊於第二圖案P2。在一些實施例中,第一圖案P1作為增強圖案,且第二圖案P2以及第三圖案P3均作為感測電極。接著,於天線發送器結構AT以及天線接收器結構AR上方形成聚合物層117以及視情況選擇的保護層124。
In some embodiments, as shown in the
在替代性實施例中,第一圖案P1、第二圖案P2以及第三圖案P3為彼此對齊且均作為感測電極。在又一些替代性實施例中,第一圖案P1以及第三圖案P3彼此對齊且均作為感測電極,而第二圖案P2未對齊於第一圖案P1以及第三圖案P3且作為增強圖案。在又一些替代性實施例中,第一圖案P1以及第二圖案P2彼此對齊且均作為感測電極,而第三圖案P3未對齊於第一圖案P1以及第二圖案P2且作為增強圖案。 In an alternative embodiment, the first pattern P1, the second pattern P2, and the third pattern P3 are aligned with each other and all serve as sensing electrodes. In still other alternative embodiments, the first pattern P1 and the third pattern P3 are aligned with each other and both serve as sensing electrodes, and the second pattern P2 is not aligned with the first pattern P1 and the third pattern P3 and serve as enhancement patterns. In still other alternative embodiments, the first pattern P1 and the second pattern P2 are aligned with each other and both serve as sensing electrodes, and the third pattern P3 is not aligned with the first pattern P1 and the second pattern P2 and serve as enhancement patterns.
依製程需要,天線發送器結構AT中的每一個圖案可具有 環狀、條狀、螺旋狀、波狀、彎曲狀或其組合,以及天線發送器結構AT的第一圖案P1、第二圖案P2以及第三圖案P3中的每一者可具有環狀、蛇狀、條狀、魚骨狀、柵欄狀、網格狀、環狀或其組合。 Depending on the process requirements, each pattern in the antenna transmitter structure AT may have Each of the ring shape, the strip shape, the spiral shape, the wave shape, the curved shape, or a combination thereof, and the first pattern P1, the second pattern P2, and the third pattern P3 of the antenna transmitter structure AT may have a ring shape, a snake shape Shape, strip shape, fish bone shape, fence shape, grid shape, ring shape or a combination thereof.
在一些實施例中,天線發送器圖案以及天線接收器圖案(即,第一至第三圖案)的形狀或數量僅僅提供為說明目的,並不用以限定本發明實施例的範圍。本領域具有通常知識者應了解,天線發送器圖案以及天線接收器圖案的其他組合或配置為可能的。在一些實施例中,於晶粒區域中均勻地分布天線接收器圖案。在替代性實施例中,於晶粒區域中隨意地、不均勻地分布天線接收器圖案。天線收發器圖案以及天線接收器圖案的形狀、尺寸、變化、配置以及分布並不以本發明實施例為限。 In some embodiments, the shapes or numbers of the antenna transmitter patterns and the antenna receiver patterns (ie, the first to third patterns) are provided for illustrative purposes only, and are not intended to limit the scope of the embodiments of the present invention. Those of ordinary skill in the art should understand that other combinations or configurations of antenna transmitter patterns and antenna receiver patterns are possible. In some embodiments, the antenna receiver pattern is evenly distributed in the die area. In an alternative embodiment, the antenna receiver pattern is randomly and unevenly distributed in the die area. The shape, size, variation, configuration and distribution of the antenna transceiver pattern and the antenna receiver pattern are not limited to the embodiments of the present invention.
在上述實施例中,感測器封裝件1/2/3/4/5/6中的每一者作為指紋感測器封裝件。然而,本發明實施例並不以此為限。只要於形成重佈線層結構期間可形成天線發送器結構以及天線接收器結構的感測器封裝件,則這種感測器封裝件視為落入本發明實施例的精神與範疇內。舉例來說,本發明實施例的感測器封裝件可作為基於分子的感測器封裝件(molecular-based sensor package),例如生物感測器封裝件(biosensor package)。
In the above-described embodiment, each of the
圖11至圖13為根據又一些替代性實施例所繪示的感測器封裝件的剖面示意圖。圖14為根據又一些替代性實施例所繪示的感測器封裝件的天線發送器結構以及天線接收器結構的簡化上視圖。圖15為根據一些實施例所繪示的感測器封裝件的製造方法的流程圖。 11 to 13 are schematic cross-sectional views of sensor packages according to still other alternative embodiments. 14 is a simplified top view of an antenna transmitter structure and an antenna receiver structure of a sensor package according to yet other alternative embodiments. 15 is a flowchart of a method for manufacturing a sensor package according to some embodiments.
感測器封裝件7/8/9的形成方法為類似於感測器封裝件1/2/3/4/5/6的形成方法,且其不同處在於:重佈線層結構112的圖案分布。
The formation method of the
於製程300中,提供具有感測表面101的半導體晶粒100。在一些實施例中,半導體晶粒100為邏輯晶粒、感測器晶粒或成像晶粒,且其正面處具有感測表面101。
In the
於製程302中,於感測表面101上方形成重佈線層結構112,其中形成所述重佈線層結構112包括形成天線發送器結構AT以及天線接收器結構AR。
In the
在一些實施例中,在感測器封裝件1/2/3/4/5/6中,重佈線層結構112形成為具有天線發送器結構AT、天線接收器結構AR以及重佈線層RDL,其中天線發送器結構AT位於半導體晶粒100側邊,天線接收器結構AR位於半導體晶粒100的感測表面101上方,且重佈線層RDL位於天線發送器結構AT與天線接收器結構AR之間。
In some embodiments, in the
在感測器封裝件7/8中,重佈線層結構112形成為具有感測圖案SP、天線發送器結構AT、天線接收器結構AR以及重佈線層RDL,其中感測圖案SP位於半導體晶粒100的感測表面101上方,天線發送器結構AT以及天線接收器結構AR位於感測圖案SP兩側,且重佈線層RDL位於天線發送器結構AT側邊。在一些實施例中,在感測器封裝件7/8中,重佈線層RDL形成為電性連接至穿孔TV以及接點105,天線發送器結構AT形成為電性耦合至訊號發送端(未繪示),感測圖案SP形成為電性耦合至半導體晶粒100,且天線接收器結構AR形成為電性連接至半導體晶粒100
側邊的另一個穿孔TV。
In the
在感測器封裝件9中,重佈線層結構112形成為具有增強圖案EP、重佈線層RDL1、感測圖案SP、天線發送器結構AT、天線接收器結構AR、以及重佈線層RDL2,其中增強圖案EP位於半導體晶粒100的感測表面101上方,重佈線層RDL1位於增強圖案EP側邊,感測圖案SP位於增強圖案EP上方,天線發送器結構AT以及天線接收器結構AR位於感測圖案SP兩側,且重佈線層RDL2位於天線發送器結構AT側邊。在一些實施例中,在感測器封裝件9中,重佈線層RDL1形成為電性連接至穿孔TV以及接點105,重佈線層RDL2形成為電性連接至重佈線層RDL1,天線發送器結構AT形成為電性耦合至訊號發送端(未繪示),感測圖案SP形成為電性耦合至半導體晶粒100,以及天線接收器結構AR形成為電性連接至位於半導體晶粒100側邊的另一個穿孔TV。在一些實施例中,增強圖案EP為浮置電極,舉例來說,依設計需要,增強圖案EP與感測電極可部分重疊或彼此分開。在替代性實施例中,增強圖案EP電性耦合至感測圖案SP。
In the
於製程304中,於重佈線層結構112上方形成聚合物層114。在一些實施例中,在感測器封裝件1/2/3/4/5/6中,聚合物層114完全覆蓋天線發送器結構AT以及天線接收器結構AR。在替代性實施例中,在感測器封裝件7/8/9中,聚合物層114覆蓋天線發送器結構AT以及天線接收器結構AR而裸露出感測圖案SP的上表面。舉例來說,於重佈線層結構112上方先毯覆式形成(blanket-formed)聚合物層114,接著,進行部分移除直到裸露出感測圖案SP。
In the
以下描述本發明實施例的感測器封裝件,其可作為基於分子的感測器封裝件。在一些實施例中,感測器封裝件7/8/9包括半導體晶粒100以及重佈線層結構112。半導體晶粒100具有感測表面101。重佈線層結構112經配置以形成感測圖案SP、天線發送器結構AT以及天線接收器結構AR,其中感測圖案SP位於半導體晶粒100的感測表面101上方,且天線發送器結構AT以及天線接收器結構AR位於感測圖案SP側邊。在一些實施例中,感測器封裝件7/8/9更包括聚合物層114以及分子連接物(molecular linker)ML,聚合物層114覆蓋天線發送器結構AT以及天線接收器結構AR而裸露出感測圖案SP的上表面,且分子連接物ML分別覆蓋感測圖案SP的裸露出的上表面。
The following describes a sensor package according to an embodiment of the present invention, which can be used as a molecular-based sensor package. In some embodiments, the
在一些實施例中,分子連接物ML的表面低於相鄰的聚合物層114的表面,如圖11以及圖13所示。在替代性實施例中,分子連接物ML的表面高於相鄰的聚合物層114的表面,如圖12所示。
In some embodiments, the surface of the molecular linker ML is lower than the surface of the
在一些實施例中,感測器封裝件7/8/9作為基於分子的感測器封裝件或生物感測器封裝件,用以感測以及偵測目標分子或生物分子,且位於天線發送器結構AT與天線接收器結構AR之間的感測圖案SP作為共振器(resonator)且排列為陣列。在一些實施例中,當目標分子或生物分子結合至(binds to)分子連接物ML或生物連接物(bio-linkers),感測器封裝件7/8/9中會有RF共振頻率的變化、電容變化及/或電流變化,因此基於電容變化及/或電流變化,可得到空氣中或液體中目標分子或生物分子的濃度/數量。
In some embodiments, the
在一些實施例中,天線發送器結構AT以及天線接收器結構AR中的每一者具有條狀,且感測圖案SP中的每一者具有開環狀(split-ring shape),如圖14的上視圖所示。然而,本發明實施例並不以此為限。天線發送器結構AT、天線接收器結構AR以及感測圖案SP中的每一者的形狀可依製程需要調整。換句話說,天線發送器結構以及天線接收器結構中的每一者具有條狀、螺旋狀、波狀、彎曲狀或其組合,且感測圖案SP中的每一者具有開環狀或可展現與收發器相同的共振頻率的其他形狀。 In some embodiments, each of the antenna transmitter structure AT and the antenna receiver structure AR has a bar shape, and each of the sensing patterns SP has a split-ring shape, as shown in FIG. 14 As shown in the top view. However, the embodiments of the present invention are not limited thereto. The shape of each of the antenna transmitter structure AT, the antenna receiver structure AR, and the sensing pattern SP can be adjusted according to process requirements. In other words, each of the antenna transmitter structure and the antenna receiver structure has a bar shape, a spiral shape, a wave shape, a curved shape, or a combination thereof, and each of the sensing patterns SP has an open ring shape or Other shapes exhibiting the same resonance frequency as the transceiver.
天線收發器圖案以及感測圖案的形狀或數量僅僅提供為說明目的,並不用以限定本發明實施例的範圍。本領域具有通常知識者應了解,天線收發器圖案以及感測圖案的其他組合或配置為可能的。在一些實施例中,於晶粒區域中均勻地分布感測圖案。在替代性實施例中,於晶粒區域中隨意地、不均勻地分布感測圖案。天線收發器圖案以及感測圖案的形狀、尺寸、變化、配置以及分布並不以本發明實施例為限。 The shapes and numbers of the antenna transceiver patterns and the sensing patterns are provided for illustrative purposes only, and are not intended to limit the scope of the embodiments of the present invention. Those of ordinary skill in the art should understand that other combinations or configurations of antenna transceiver patterns and sensing patterns are possible. In some embodiments, the sensing pattern is evenly distributed in the die area. In an alternative embodiment, the sensing pattern is randomly and unevenly distributed in the grain area. The shape, size, change, configuration and distribution of the antenna transceiver pattern and the sensing pattern are not limited to the embodiments of the present invention.
基於上述,根據本發明的一些實施例,在感測器封裝件中,於形成重佈線層結構期間形成天線發送器結構以及天線接收器結構,可大幅簡化製程且可顯著減少封裝尺寸。本發明實施例的感測器封裝件可作為指紋感測器封裝件或基於分子的感測器(例如,生物感測器)封裝件。 Based on the above, according to some embodiments of the present invention, in the sensor package, forming the antenna transmitter structure and the antenna receiver structure during the formation of the redistribution layer structure can greatly simplify the manufacturing process and significantly reduce the package size. The sensor package of the embodiment of the present invention may be used as a fingerprint sensor package or a molecular-based sensor (eg, biosensor) package.
根據本發明的一些實施例,一種感測器封裝件包括半導體晶粒以及重佈線層結構。半導體晶粒具有感測表面。所述重佈線層結構經配置以形成天線發送器結構以及天線接收器結構,所述天線發送器結構位於所述半導體晶粒側邊,且所述天線接收器 結構位於所述半導體晶粒的所述感測表面上方。 According to some embodiments of the present invention, a sensor package includes a semiconductor die and a redistribution layer structure. The semiconductor die has a sensing surface. The rewiring layer structure is configured to form an antenna transmitter structure and an antenna receiver structure, the antenna transmitter structure is located on the side of the semiconductor die, and the antenna receiver The structure is located above the sensing surface of the semiconductor die.
在所述感測器封裝件中,所述天線發送器結構環繞所述天線接收器結構。 In the sensor package, the antenna transmitter structure surrounds the antenna receiver structure.
在所述感測器封裝件中,所述天線發送器結構具有環狀、條狀、螺旋狀、波狀、彎曲狀或其組合。 In the sensor package, the antenna transmitter structure has a ring shape, a strip shape, a spiral shape, a wave shape, a curved shape, or a combination thereof.
在所述感測器封裝件中,所述天線接收器結構具有位於所述半導體晶粒的所述感測表面上方的多個第一圖案。 In the sensor package, the antenna receiver structure has a plurality of first patterns above the sensing surface of the semiconductor die.
在所述感測器封裝件中,所述多個第一圖案中的每一者具有島狀、蛇狀、條狀、魚骨狀、柵欄狀、網格狀、環狀或其組合。 In the sensor package, each of the plurality of first patterns has an island shape, a snake shape, a strip shape, a fishbone shape, a fence shape, a grid shape, a ring shape, or a combination thereof.
在所述感測器封裝件中,所述天線接收器結構更具有位於所述多個第一圖案上方的多個第二圖案。 In the sensor package, the antenna receiver structure further has a plurality of second patterns above the plurality of first patterns.
在所述感測器封裝件中,所述多個第二圖案對齊於所述多個第一圖案。 In the sensor package, the plurality of second patterns are aligned with the plurality of first patterns.
在所述感測器封裝件中,所述天線接收器結構更具有位於所述多個第二圖案上方的多個第三圖案,所述多個第三圖案對齊於所述多個第二圖案,且所述多個第二圖案未對齊於所述多個第一圖案。 In the sensor package, the antenna receiver structure further has a plurality of third patterns located above the plurality of second patterns, the plurality of third patterns being aligned with the plurality of second patterns , And the plurality of second patterns are not aligned with the plurality of first patterns.
在所述感測器封裝件中,所述多個第二圖案未對齊於所述多個第一圖案。 In the sensor package, the plurality of second patterns are not aligned with the plurality of first patterns.
在所述感測器封裝件中,所述感測器封裝件為指紋感測器封裝件。 In the sensor package, the sensor package is a fingerprint sensor package.
根據本發明的一些替代性實施例,一種感測器封裝件包括半導體晶粒以及重佈線層結構。所述半導體晶粒具有感測表 面。所述重佈線層結構經配置以形成多個感測圖案、天線發送器結構以及天線接收器結構,所述感測圖案位於所述半導體晶粒的所述感測表面上方,所述天線發送器結構以及所述天線接收器結構位於所述多個感測圖案側邊。 According to some alternative embodiments of the invention, a sensor package includes a semiconductor die and a redistribution layer structure. The semiconductor die has a sensing table surface. The redistribution layer structure is configured to form a plurality of sensing patterns, an antenna transmitter structure, and an antenna receiver structure, the sensing patterns are located above the sensing surface of the semiconductor die, the antenna transmitter The structure and the antenna receiver structure are located on the sides of the plurality of sensing patterns.
在所述感測器封裝件中,所述感測器封裝件更包括聚合物層,所述聚合物層覆蓋所述天線發送器結構以及所述天線接收器結構,而裸露出所述感測圖案的上表面。 In the sensor package, the sensor package further includes a polymer layer that covers the antenna transmitter structure and the antenna receiver structure, and exposes the sensor The upper surface of the pattern.
在所述感測器封裝件中,更包括分子連接物,所述分子連接物分別覆蓋所述感測圖案的裸露出的所述上表面。 In the sensor package, molecular connectors are further included, and the molecular connectors respectively cover the exposed upper surface of the sensing pattern.
在所述感測器封裝件中,所述天線接收器結構電性連接至位於所述半導體晶粒側邊的穿孔。 In the sensor package, the antenna receiver structure is electrically connected to the through hole located on the side of the semiconductor die.
在所述感測器封裝件中,所述天線發送器結構以及所述天線接收器結構中的每一者具有條狀、螺旋狀、波狀、彎曲狀或其組合。 In the sensor package, each of the antenna transmitter structure and the antenna receiver structure has a bar shape, a spiral shape, a wave shape, a curved shape, or a combination thereof.
在所述感測器封裝件中,所述感測圖案中的每一者具有開環狀。 In the sensor package, each of the sensing patterns has an open ring shape.
在所述感測器封裝件中,所述感測器封裝件為基於分子的感測器封裝件。 In the sensor package, the sensor package is a molecule-based sensor package.
根據本發明的另一些替代性實施例,一種感測器封裝件的形成方法包括:提供具有感測表面的半導體晶粒;於所述感測表面上方形成重佈線層結構,其中形成所述重佈線層結構包括形成天線發送器結構以及天線接收器結構;以及於所述重佈線層結構上方形成聚合物層。 According to other alternative embodiments of the present invention, a method for forming a sensor package includes: providing a semiconductor die having a sensing surface; forming a redistribution layer structure above the sensing surface, wherein the heavy The wiring layer structure includes forming an antenna transmitter structure and an antenna receiver structure; and forming a polymer layer above the redistribution layer structure.
在所述感測器封裝件的形成方法中,所述天線接收器結 構包括位於所述半導體晶粒的所述感測表面上方的多個第一圖案。 In the method of forming the sensor package, the antenna receiver junction The structure includes a plurality of first patterns above the sensing surface of the semiconductor die.
在所述感測器封裝件的形成方法中,形成所述重佈線層結構更包括形成位於所述天線發送器結構與所述天線接收器結構之間的多個感測圖案,且所述感測圖案形成於所述半導體晶粒的所述感測表面上方。 In the method of forming the sensor package, forming the redistribution layer structure further includes forming a plurality of sensing patterns between the antenna transmitter structure and the antenna receiver structure, and the sensor A sensing pattern is formed above the sensing surface of the semiconductor die.
以上概述了數個實施例的特徵,使本領域具有通常知識者可更佳了解本揭露的態樣。本領域具有通常知識者應理解,其可輕易地使用本揭露作為設計或修改其他製程與結構的依據,以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解,這種等效的配置並不悖離本揭露的精神與範疇,且本領域具有通常知識者在不悖離本揭露的精神與範疇的情況下可對本文做出各種改變、置換以及變更。 The above outlines the features of several embodiments so that those with ordinary knowledge in the art can better understand the aspect of the disclosure. Those of ordinary skill in the art should understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to carry out the same purposes and/or achieve the same advantages of the embodiments described herein. Those with ordinary knowledge in this field should also understand that this equivalent configuration does not deviate from the spirit and scope of this disclosure, and those with ordinary knowledge in this field can do this without departing from the spirit and scope of this disclosure. Make various changes, replacements, and changes.
1‧‧‧感測器封裝件 1‧‧‧Sensor package
10‧‧‧封裝區域 10‧‧‧Package area
12‧‧‧晶粒區域 12‧‧‧grain area
14‧‧‧周邊區域 14‧‧‧ surrounding area
100‧‧‧半導體晶粒 100‧‧‧Semiconductor die
101‧‧‧感測表面 101‧‧‧sensing surface
102‧‧‧基底 102‧‧‧ base
103‧‧‧接墊 103‧‧‧ Pad
104‧‧‧鈍化層 104‧‧‧passivation layer
105‧‧‧接點 105‧‧‧Contact
108‧‧‧封裝體 108‧‧‧Package
110、114、116‧‧‧聚合物層 110, 114, 116 ‧‧‧ polymer layer
112、118‧‧‧重佈線層結構 112, 118‧‧‧ Rewiring layer structure
120‧‧‧焊球 120‧‧‧solder ball
122‧‧‧底膠層 122‧‧‧Bottom rubber layer
124‧‧‧保護層 124‧‧‧Protective layer
AR‧‧‧天線接收器結構 AR‧‧‧ Antenna receiver structure
AT‧‧‧天線發送器結構 AT‧‧‧ Antenna transmitter structure
P1‧‧‧第一圖案 P1‧‧‧The first pattern
RDL‧‧‧重佈線層 RDL‧‧‧Rewiring layer
TV‧‧‧穿孔 TV‧‧‧Perforation
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US201662341633P | 2016-05-26 | 2016-05-26 | |
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Also Published As
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US20210257717A1 (en) | 2021-08-19 |
US20240128635A1 (en) | 2024-04-18 |
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US10636713B2 (en) | 2020-04-28 |
US11855333B2 (en) | 2023-12-26 |
US10978782B2 (en) | 2021-04-13 |
US20190115271A1 (en) | 2019-04-18 |
US20220368005A1 (en) | 2022-11-17 |
US10157807B2 (en) | 2018-12-18 |
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