TWI691169B - Tunable pll and communication system - Google Patents

Abstract

The present invention provides a tunable phase-locked loops system, which can be applied to transmission system and comprises a voltage-controlled oscillator, a charge pump, a filter, a phase frequency detector and a tunable feedback divider. The voltage-controlled oscillator generates an operating clock signal based on a voltage-controlled voltage signal. The charge pump is connected to the voltage-controlled oscillator, which generates the voltage-controlled voltage signal to adjust the voltage level based on an error signal. The filter is connected between the charge pump and the voltage-controlled oscillator. The phase frequency detector receives a reference clock signal and a feedback signal, and compares the phase or frequency thereof, so as to generate the error signal. The tunable feedback divider is connected between the voltage-controlled oscillator and the phase frequency detector, and divides the working clock signal by a divider to generate the feedback signal. Wherein, the tunable feedback divider adjusts the divider according to a clock tuning signal, so as to change the feedback signal in real time to dynamically adjust the frequency of the operating clock signal.

Description

Adjustable phase-locked loop system and its transmission system

The invention relates to a phase-locked loop system and its transmission system. More specifically, the phase-locked loop system of the present invention is different from the previous phase-locked loop system. Its adjustable feedback divider has a dynamically adjustable divisor and can adjust the frequency of the working clock signal.

The phase-locked loop (Phase-Locked Loop; PLL) is a closed loop system, which is often used as a signal bridge between two or more different electronic devices of a signal transmission device and a signal reception device. When the phase and frequency of the output working clock signal and the input reference clock signal are inconsistent, adjust through the phase-locked loop system until the two signals can operate at the same frequency.

Referring to FIG. 1, a schematic diagram of a conventional transmission system 100 applied between two different electronic devices, a signal transmission device 10 and a signal receiving device 20. For example, the signal transmission device 10 may be a computer, and the signal reception device 20 may be a USB sound card. When the transmission speed of the signal transmission device 10 is greater than the reception speed of the signal reception device 20, the signal will overflow. For example, the USB sound card cannot process too many playback messages, resulting in incorrect sound quality. When the transmission speed of the signal transmission device 10 is lower than the reception speed of the signal reception device 20, the signal will generate an underflow. For example, the USB sound card cannot process the next segment of the playback message, causing playback interruption. Therefore, the PLL system 100 plays a very important role here. Through the adjustment of the PLL system 100, The signal transmission device 10 and the signal receiving device 20 can be operated at the same operating frequency with two or more different electronic devices.

Referring to FIG. 2 is a structural diagram of a conventional phase-locked loop system 100, including a phase frequency detector 110, a charge pump 120, a filter 130, a voltage controlled oscillator 140, and a feedback frequency divider 150.

In the conventional phase-locked loop system 100, if a new output signal frequency is required, the operation settings of the new phase-locked loop system 100 need to be stored in a register in advance. As shown in Table 1 below, the gray background represents the stored operation parameter address, and the white background represents the operation field.

As mentioned above, in the conventional phase-locked loop system 100, when the old register settings cannot provide suitable calculation conditions for the phase-locked loop system 100, and the working clock signal reaches a suitable frequency, it needs to be recalculated New scratchpad settings. However, it will take a while after the calculation is started, and sometimes only a slight frequency adjustment is required, thus further delaying the time for the user to perform normal work.

Therefore, the present invention proposes an adjustable phase-locked loop system. The adjustable feedback frequency divider can help the user to find that the frequency of the current working clock signal is only slightly different from the frequency of the target working clock signal. Stop the current working state, and dynamically perform the frequency adjustment of the working clock signal.

The invention provides an adjustable phase-locked loop system, which includes a voltage-controlled oscillator, which generates a working clock signal and a charge pump according to the voltage-controlled voltage signal, is connected to the voltage-controlled oscillator, and generates a voltage-controlled voltage signal according to the error signal, Adjust the voltage level and filter of the voltage-controlled voltage signal, connected between the charge pump and the voltage-controlled oscillator, the phase frequency detector, connected to the charge pump, and receive the reference clock signal and the feedback signal. The phase or frequency of the pulse signal and the feedback signal to generate the error signal, and the adjustable feedback divider, connected between the voltage controlled oscillator and the phase frequency detector, and receives the working pulse signal to divide The divider divides the working clock signal to generate the feedback signal. The adjustable feedback divider further receives the clock adjustment signal, and adjusts the frequency of the working clock signal according to the clock adjustment signal, thereby fine-tuning the working clock signal in real time.

Preferably, the adjustable feedback divider includes a fine-tuning circuit. When the clock adjustment signal represents an increase in the frequency of the working clock signal, by reducing the divisor, the fine-tuning circuit increases the frequency of the working clock signal through the unit fine-tuning frequency. The error signal generated by the phase frequency detector represents that the phase or clock of the feedback signal lags behind the reference clock signal, so that the charge pump increases the voltage level of the voltage-controlled voltage signal, which in turn causes the voltage-controlled oscillator to generate a higher frequency The working clock signal.

Preferably, the adjustable feedback divider includes a fine-tuning circuit. When the clock adjustment signal represents a reduction in the frequency of the working clock signal, by reducing the divisor, the fine-tuning circuit reduces the frequency of the working clock signal through the unit fine-tuning frequency. Make the error signal generated by the phase frequency detector represent that the phase or clock of the feedback signal is ahead of the reference clock signal, so that the charge pump reduces the voltage level of the voltage-controlled voltage signal, and thus the voltage-controlled oscillator generates a lower frequency The working clock signal.

Preferably, the adjustable feedback divider adjusts the original feedback divisor to make the working clock signal frequency satisfy the following relationship: CLKO’=CLKO+freq.×n

Among them, CLKO' is the frequency after working clock signal adjustment, CLKO is the frequency before working clock signal adjustment, freq. is the unit fine-tuning frequency, and n is a positive integer or a negative integer.

The invention further relates to a transmission system, including a signal transmission device and a signal reception device. Among them, the signal transmission device includes a microprocessor and an adjustable phase-locked loop system provided in the microprocessor to generate a working clock signal. The signal receiving device is connected to the signal transmission device, and forms a communication link with the signal transmission device according to the working clock signal. The signal receiving device includes a buffer to temporarily store the data received by the signal transmitting device.

Among them, the signal transmission device generates the request signal according to the data storage capacity of the buffer, so that the microprocessor sends the clock adjustment signal to the adjustable phase-locked loop system according to the request signal, and the adjustable phase-locked loop system dynamically adjusts the frequency of the working clock signal .

Preferably, the adjustable phase-locked loop system of the signal transmission device includes a voltage-controlled oscillator, generates a working clock signal and a charge pump according to the voltage-controlled voltage signal, is connected to the voltage-controlled oscillator, and generates a voltage-controlled voltage signal according to the error signal , To adjust the voltage level and filter of the voltage-controlled voltage signal, connected between the charge pump and the voltage-controlled oscillator, the phase frequency detector, connected to the charge pump, and receiving the reference clock signal and the feedback signal, and Compare the phase or frequency of the reference clock signal and the feedback signal to generate an error signal, and an adjustable feedback divider connected between the voltage controlled oscillator and the phase frequency detector to receive the working clock signal , And divides the working clock signal by a divider to generate the feedback signal. Among them, the adjustable feedback divider receives the clock adjustment signal, and adjusts the frequency of the working clock signal according to the clock adjustment signal, thereby fine-tuning the working clock signal in real time.

When the data storage capacity of the buffer is lower than the first threshold, the signal transmission device generates a request signal requesting to increase the frequency of the working pulse signal; when the data storage capacity of the buffer is higher than the second threshold, the signal transmission device generates a request Request signal to reduce the frequency of the working clock signal.

Preferably, the adjustable feedback divider includes a fine-tuning circuit. When the clock adjustment signal represents an increase in the frequency of the working clock signal, by reducing the divisor, the fine-tuning circuit increases the frequency of the working clock signal through the unit fine-tuning frequency. The error signal generated by the phase frequency detector represents that the phase or clock of the feedback signal lags behind the reference clock signal, so that the charge pump increases the voltage level of the voltage-controlled voltage signal, which in turn causes the voltage-controlled oscillator to generate a higher frequency The working clock signal.

Preferably, the adjustable feedback frequency divider includes a fine-tuning circuit. When the clock adjustment signal represents a reduction in the frequency of the working clock signal, by increasing the divisor, the fine-tuning circuit reduces the frequency of the working clock signal through the unit fine-tuning frequency. Make the error signal generated by the phase frequency detector represent that the phase or clock of the feedback signal is ahead of the reference clock signal, so that the charge pump reduces the voltage level of the voltage-controlled voltage signal, and thus the voltage-controlled oscillator generates a lower frequency The working clock signal.

Preferably, the adjustable feedback divider adjusts the original feedback divisor to make the working clock signal frequency satisfy the following relationship: CLKO’=CLKO+freq.×n

Among them, CLKO' is the frequency after working clock signal adjustment, CLKO is the frequency before working clock signal adjustment, freq. is the unit fine-tuning frequency, and n is a positive integer or a negative integer.

10.30: Signal transmission device

20, 40: Signal receiving device

50: original feedback divisor

51: Fine-tune the divisor

52: Adjusted feedback divisor

100: phase-locked loop system

110, 310, 710: phase frequency detector

120, 320, 720: charge pump

130, 330, 730: filter

140, 340, 740: voltage controlled oscillator

150: Feedback divider

300: Adjustable phase-locked loop system

350, 750: Adjustable feedback divider

351, 751: fine-tuning circuit

400, 500: buffer

760: Input divider

770: output divider

MCU: Microprocessor

REG: register

Figure 1 is a schematic diagram of a conventional transmission system.

Figure 2 is a structural diagram of a conventional phase-locked loop.

Figure 3 is a schematic diagram of a transmission system according to an embodiment of the present invention.

FIG. 4 is a working schematic diagram of a buffer according to an embodiment of the present invention.

FIG. 5 is a structural diagram of an adjustable phase-locked loop system according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of an adjusted feedback divisor according to an embodiment of the present invention after adjustment.

FIG. 7 is a structural diagram of an adjustable phase-locked loop system according to another embodiment of the present invention.

In the following, the invention will be described in detail by illustrating various embodiments of the invention. However, the concept of the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to facilitate the understanding of the spirit of the present invention by those having ordinary knowledge in the art With category. In addition, the same element symbols in the drawings may be used to indicate similar elements.

Refer to FIG. 3, which is a schematic diagram of a transmission system according to an embodiment of the present invention. As shown in the figure, the transmission system includes a signal transmission device 30 and a signal reception device 40. The signal transmission device 30 includes a microprocessor MCU and a register REG. The register REG stores a clock adjustment signal. The microprocessor MCU includes an adjustable phase-locked loop system 300 and a buffer 400. Through the adjustable phase-locked loop The system 300 generates a working clock signal, and the buffer 400 transmits data to the signal receiving device 40 according to the frequency of the working clock signal. The signal receiving device 40 is connected to the signal transmitting device 30 and receives and temporarily stores the data transmitted by the signal transmitting device 30 through the buffer 500 of the signal receiving device 40.

Here, the present invention provides an example. The signal transmission device 30 may be a computer, and the signal reception device 40 may be a USB sound card. The USB sound card uses pulse-code modulation (PCM) with a sampling rate of 48000 Hz. The audio data is sampled by data, which is equivalent to processing only 48 patterns of data per millisecond. The normal audio quality is 2-byte for each pattern of data. Set buffer 500 to In the USB audio card, this buffer 500 can temporarily store 8192-byte data storage, which is equivalent to 4096 temporary data. Therefore, it can be seen that the buffer 500 can only temporarily store 85.3 ms of data storage. When the buffer 400 of the microprocessor MCU over-transmits data, the buffer 500 receives more than 85.3 ms of data storage, and the signal receiving device 40 loses the audio signal, causing distortion of sound quality. When the buffer 400 of the microprocessor MCU transmits the data too slowly, and the buffer 500 receives too low a data amount, the signal receiving device 40 lacks an audio signal, causing distortion in sound quality.

Referring to FIG. 4, FIG. 4 is a working schematic diagram of the buffer 500 according to an embodiment of the present invention. The first threshold t0 and the second threshold t1 are defined in the buffer 500, respectively. When the data storage capacity of the buffer 500 is lower than the first threshold t0, the signal transmission device 30 generates a request signal to increase the frequency of the working clock signal to the microprocessor MCU, and the microprocessor MCU accordingly reads from the register REG Select the clock adjustment signal to increase the working clock frequency, the microprocessor MCU then sends the clock adjustment signal to increase the working clock frequency to the adjustable phase-locked loop system 300, the adjustable phase-locked loop system 300 to increase the working clock signal Frequency of. When the data storage capacity of the buffer 400 is higher than the second threshold value t1, the signal transmission device 30 generates a request signal to reduce the frequency of the working clock signal to the microprocessor MCU, and the microprocessor MCU accordingly reads from the register REG Select the clock adjustment signal that reduces the working clock frequency. The microprocessor MCU then sends the clock adjustment signal that reduces the working clock frequency to the adjustable phase-locked loop system 300. The adjustable phase-locked loop system 300 reduces the working clock signal. Frequency of. However, in the present invention, the first threshold t0 and the second threshold t1 are determined according to the amount of data storage that the buffer 400 can provide, so the first threshold can be further adjusted according to the amount of data storage that the buffer 400 can provide t0 is adjusted with the second threshold t1.

As exemplified above, the buffer 400 can temporarily store 8192-byte data storage, which is equivalent to 85.3ms of data storage. In the buffer 400, the first threshold t0 is defined as 20 ms and the second threshold t1 is defined as 65.3 ms. When the data storage capacity of the buffer 400 is lower than the first threshold t0 (for example: 19.9ms), the signal transmission device 30 generates a request signal to increase the frequency of the working clock signal to the microprocessor MCU, the microprocessor MCU accordingly selects the clock adjustment signal to increase the working clock frequency from the register REG, micro The processor MCU successively sends a clock adjustment signal to increase the working clock frequency to the adjustable phase-locked loop system 300, which can increase the frequency of the working clock signal. When the data storage capacity of the buffer 400 is higher than the second threshold t1 (for example: 65.4 ms), the signal transmission device 30 generates a request signal to reduce the frequency of the working pulse signal to the microprocessor MCU. This selects the clock adjustment signal that reduces the working clock frequency from the register REG. The microprocessor MCU then sends the clock adjustment signal that reduces the working clock frequency to the adjustable phase-locked loop system 300 and the adjustable phase-locked loop system 300 This reduces the frequency of the pulse signal during operation.

Referring to FIG. 5, FIG. 5 is a structural diagram of an adjustable phase-locked loop system 300 according to an embodiment of the present invention. As shown in the figure, the adjustable phase-locked loop system 300 includes a voltage-controlled oscillator 340 that can generate a working clock signal according to a voltage-controlled voltage signal, and is connected to the voltage-controlled oscillator 340 and can generate a voltage-controlled voltage signal according to an error signal to adjust the voltage Charge pump 320 for controlling the voltage level of the voltage signal, filter 330 connected between charge pump 320 and voltage-controlled oscillator 340, connected to charge pump 320 and receiving the reference clock signal and the feedback signal according to the comparison reference time The phase or frequency of the pulse signal and the feedback signal to generate an error signal, and a phase frequency detector 310 connected between the voltage controlled oscillator 340 and the phase frequency detector 310 to receive the working pulse signal and divide by a divisor (divider) An adjustable feedback divider 350 that divides the working clock signal and generates a feedback signal.

As shown in FIG. 5, the adjustable feedback frequency divider 350 further includes a trimming circuit 351 to receive the clock adjustment signal as described above. When the adjustable feedback frequency divider 350 receives the clock adjustment signal sent by the microprocessor MCU, the original feedback divisor 50 of the adjustable feedback frequency divider 350 is finely adjusted through the fine adjustment circuit 351, thereby real-time Fine-tune the frequency of the working clock signal.

Referring to FIG. 6, FIG. 6 is a schematic diagram of the feedback divisor 52 after adjustment of the adjustable feedback divider 350 according to an embodiment of the present invention. As can be seen from the figure, the adjustable feedback divider 350 gives the original feedback divisor 50 an increased or decreased fine-tuned divisor 51 through the fine-tune circuit 351, and then the adjusted feedback divisor 52 is obtained. So that the frequency of the working pulse signal can satisfy the following relationship (Equation 1): CLKO'=CLKO+freg.×n......................... Equation 1 where CLKO' is the adjusted frequency of the working clock signal, CLKO' is The frequency before the adjustment of the pulse signal during operation, freg. is the unit for fine-tuning the frequency, and n is a positive or negative integer that can be dynamically adjusted.

Therefore, when the data storage capacity of the buffer 400 is lower than the first threshold value t0, the signal receiving device 40 generates a request signal to increase the frequency of the working clock signal to the microprocessor MCU, and the microprocessor MCU accordingly reads from the scratchpad REG selects and sends a clock adjustment signal to the adjustable feedback frequency divider 350 in the adjustable phase-locked loop system 300, and the divisor of the adjustable feedback frequency divider 350 is reduced through the fine-tuning circuit 351, so that the operating clock The frequency of the signal is increased, so that the phase frequency detector 310 generates an error signal in which the phase or clock of the feedback signal lags behind the reference clock signal, so that the charge pump 320 increases the voltage level of the voltage-controlled voltage signal, so that the voltage control The oscillator 340 generates a higher frequency working clock signal. When the data storage capacity of the buffer 400 is higher than the second threshold value t1, the signal receiving device 40 generates a request signal to reduce the frequency of the working clock signal to the microprocessor MCU, and the microprocessor MCU accordingly reads from the register REG Select and send the clock adjustment signal to the adjustable feedback frequency divider 350 in the adjustable phase-locked loop system 300, the divisor of the adjustable feedback frequency divider 350 is increased through the fine-tuning circuit 351, so as to make the working clock signal The frequency of the frequency is reduced, so that the phase frequency detector 310 generates an error signal that the phase or clock of the feedback signal is ahead of the reference clock signal, so that the charge pump 320 lowers the voltage level of the voltage-controlled voltage signal, thereby causing the voltage-controlled oscillation The device 340 generates a lower frequency working clock signal.

As shown in the above example, set the unit fine-tuning frequency to 100 Hz. When the data storage capacity of the buffer 400 is below the first threshold t0 for 20 ms (for example: 19.9 ms), the data storage capacity differs by only 0.1 ms, which is equivalent to one per second 4800 samples are missing, and the working clock signal frequency is slowed by 4800 Hz, the signal transmission device 30 generates a request signal to increase the working clock signal frequency to the microprocessor MCU, and the microprocessor MCU accordingly Select from the register REG and send the clock adjustment signal to the adjustable feedback divider 350 in the adjustable phase-locked loop system 300, then the trimming circuit 351 provides a trimming divisor 51 of about -0.005 to make the original feedback divisor 50 is reduced, and the adjusted feedback divisor 52 is about 0.995. Compare the frequency of the working clock signal before adjustment with the frequency of the adjusted working clock signal to satisfy the relationship: CLKO’=CLKO+100Hz×n, where n is 48, thereby increasing the frequency of 4800Hz.

As shown in the above example, set the unit fine-tuning frequency to 100 Hz. When the data storage capacity of the buffer 400 is higher than the second threshold t1 of 65.3 ms (for example: 65.4 ms), the data storage capacity differs by only 0.1 ms, which is equivalent to There are 4800 samples of data in seconds, and it is learned that the frequency of the working pulse signal is faster by 4800Hz, then the signal transmission device 30 generates a request signal to increase the frequency of the working pulse signal to the microprocessor MCU. The register REG selects and sends a clock adjustment signal to the adjustable feedback divider 350 in the adjustable phase-locked loop system 300, then the fine-tuning circuit 351 provides a fine-tuned divisor 51 of approximately +0.0015 to increase the original feedback divisor 50 , The adjusted feedback divisor 52 is about 1.0015. Compare the frequency of the working clock signal before adjustment with the frequency of the adjusted working clock signal to satisfy the relationship: CLKO’=CLKO+100Hz×n, where n is -48, thereby reducing the frequency of 4800Hz.

As described above, after the adjustable feedback frequency divider 350 adjusts the frequency of the working clock signal through the fine-tuning circuit 351, the frequency can satisfy the following relationship: CLKO'=CLKO+freg.×n, where n can be ±1 ±2, ±3..., ±256. If the unit fine-tuning frequency is 100Hz, and n is a positive integer 1, it means that the frequency of the working clock signal is increased by 100Hz, which is equivalent to an increase of about 0.002ms of data storage. If n When it is a negative integer 1, it means that the frequency of the working clock signal is reduced by 100Hz, which is equivalent to a reduction of about 0.002ms of data storage.

According to the above description, the adjustable phase-locked loop system of the present invention can substantially adjust the dynamic frequency of the working clock signal, thereby improving the work efficiency of the user in performing normal work. The above is only exemplary, and not restrictive. Any equivalent modifications or changes made without departing from the spirit and scope of the present invention shall be included in the scope of the attached patent application.

Preferably, as shown in FIG. 7, the present invention provides another embodiment. The adjustable phase-locked loop system 700 may further include an input frequency divider 760, which is connected to the phase frequency detector 710 and receives the reference clock signal. It is connected to the output frequency divider 770 and the voltage controlled oscillator 740 and receives the working clock signal (as shown in FIG. 7). This embodiment and the embodiment of FIG. 5 only add the input frequency divider 760 and the output frequency divider 770, and the remaining structures or components are substantially the same as the embodiment of FIG. 5, so the positions of the relevant structures or the functions of the components are repeated. The detailed description will be omitted.

In the phase-locked loop system of the conventional technology (additional input frequency divider and output frequency divider), when the input frequency divider receives the reference clock signal, the reference clock signal is divided by a divisor to make the reference time The frequency of the pulse signal is reduced to the operating frequency range of the phase frequency detector 110. When the output frequency divider receives the working clock signal, the working clock signal is divided by an integer to reduce the frequency of the reference clock signal to the working frequency range of the signal transmission device 10. Since the input frequency divider and the output frequency divider cannot perform fine-tuning of the frequency, in the transmission system, when the signal receiving device 20 transmits a clock adjustment signal representing the frequency of increasing or decreasing the working clock signal, the working clock signal is To reach a suitable frequency, you must stop the work being performed and recalculate the new buffer settings, so it is inconvenient to use.

In this embodiment, the adjustable phase-locked loop system 300 includes an adjustable feedback divider 350. When the adjustable feedback divider 350 receives the clock adjustment signal from the microprocessor MCU, The trimming circuit in the adjustable feedback divider 350 can be used to give the original feedback divisor 50 an increase/decrease fine-tuning divisor 51 to obtain the adjusted feedback divisor 52, thereby real-time feedback of the working clock signal The frequency is fine-tuned to reduce/increase the frequency of the working clock signal, so that the phase frequency detector 310 generates an error signal of the phase of the feedback signal or the clock leads/lags behind the reference clock signal, so as to reduce the charge pump 320 /Increase the voltage level of the voltage-controlled voltage signal, so that the voltage-controlled oscillator 340 generates a lower/higher frequency working clock signal. The adjustment method is as described above, and will not be repeated here.

Based on the above viewpoints, the adjustable phase-locked loop system and transmission system of the present invention can solve the inconvenience caused by the non-fine-tuning of the conventional phase-locked loop system. The above is only exemplary, and not restrictive. Any equivalent modifications or changes made without departing from the spirit and scope of the present invention shall be included in the scope of the attached patent application.

300: Adjustable phase-locked loop system

310: phase frequency detector

320: charge pump

330: filter

340: voltage controlled oscillator

350: Adjustable feedback divider

351: fine-tuning circuit

50: original feedback divisor

Claims (10)

An adjustable phase-locked loop system includes: a voltage-controlled oscillator, which generates an undivided working clock signal based on a voltage-controlled voltage signal; a charge pump, connected to the voltage-controlled oscillator, which is based on An error signal generates the voltage-controlled voltage signal to adjust the voltage level of the voltage-controlled voltage signal; a filter is connected between the charge pump and the voltage-controlled oscillator; a phase frequency detector is connected to the Charge pump, the phase frequency detector receives an operating frequency and a feedback signal, and compares the operating frequency and the phase or frequency of the feedback signal to generate the error signal accordingly; an adjustable feedback divider , The adjustable feedback divider receives a working clock signal, and divides the working clock signal by a first divider to generate the feedback signal; an input divider is connected The phase frequency detector divides a reference clock signal by a second divisor to obtain the working signal; and an output frequency divider connects the adjustable feedback frequency divider and the voltage controlled oscillator , Dividing the undivided working clock signal by a third divisor to obtain the working clock signal; wherein, the adjustable feedback divider further receives a clock adjustment signal and adjusts according to the clock The signal adjusts the first divisor, thereby dynamically changing the feedback signal to adjust the frequency of the working clock signal. For example, the adjustable phase-locked loop system of item 1 of the patent scope, where the adjustable feedback divider includes a fine-tuning circuit, and when the clock adjustment signal represents an increase in When the frequency of the clock signal is reduced, by reducing the first divisor, the fine-tuning circuit increases the frequency of the working clock signal by a unit of fine-tuning frequency, so that the error signal generated by the phase frequency detector represents the return The phase or clock of the grant signal lags behind the reference clock signal, so that the charge pump raises the voltage level of the voltage-controlled voltage signal, so that the voltage-controlled oscillator generates the higher-frequency undivided working clock Signal. For example, the adjustable phase-locked loop system of claim 1 of the patent scope, wherein the adjustable feedback frequency divider includes a fine-tuning circuit. When the clock adjustment signal represents a decrease in the frequency of the working clock signal, by increasing the A divisor, so that the fine-tuning circuit reduces the frequency of the working clock signal through a unit of fine-tuning frequency, so that the error signal generated by the phase frequency detector represents the phase or clock of the feedback signal leading the reference time Pulse signal, so that the charge pump lowers the voltage level of the voltage-controlled voltage signal, so that the voltage-controlled oscillator generates the operating time pulse signal at a lower frequency. For example, the adjustable phase-locked loop system of claim 2 or 3, wherein the adjustable feedback divider adjusts the first divisor so that the frequency of the working clock signal satisfies the following relationship: CLKO' =CLKO+freq.×n where CLKO' is the frequency after the working pulse signal is adjusted, CLKO is the frequency before the working pulse signal is adjusted, freq. is the unit fine-tuning frequency, n is a positive integer or a negative Integer. A transmission system includes: a signal transmission device including a microprocessor and an adjustable phase-locked loop system provided in the microprocessor to generate a working clock signal; and A signal receiving device, connected to the signal transmitting device, and forming a communication link with the signal transmitting device according to the working clock signal, the signal receiving device includes a buffer to temporarily store the data received by the signal transmitting device; , The signal transmission device generates a request signal according to the data storage capacity of the buffer, so that the microprocessor sends a clock adjustment signal to the adjustable phase-locked loop system according to the request signal, and the adjustable phase-locked loop system dynamically adjusts The frequency of the working clock signal. For example, in the transmission system of claim 5, the adjustable phase-locked loop system of the signal transmission device includes: a voltage-controlled oscillator that generates the working clock signal based on a voltage-controlled voltage signal; a charge pump, Connected to the voltage controlled oscillator, the charge pump generates the voltage controlled voltage signal according to an error signal to adjust the voltage level of the voltage controlled voltage signal; a filter connected between the charge pump and the voltage controlled oscillator A phase frequency detector connected to the charge pump, the phase frequency detector receives a reference clock signal and a feedback signal, and compares the phase or frequency of the reference clock signal and the feedback signal, The error signal is generated accordingly; and an adjustable feedback frequency divider is connected between the voltage controlled oscillator and the phase frequency detector, and the adjustable feedback frequency divider receives the working clock signal, And divide the working clock signal by a divider to generate the feedback signal; wherein, the adjustable feedback divider receives the clock adjustment signal and adjusts the signal pair according to the clock The divisor is adjusted to fine-tune the working clock signal in real time. If the transmission system of patent application item 6 is used, the data in the buffer area is stored If the inventory is lower than a first threshold, the signal transmission device generates the request signal that requires increasing the frequency of the working clock signal; when the data storage capacity of the buffer is higher than a second threshold, the signal transmission device The request signal generating a request to reduce the frequency of the working clock signal is generated. For example, in the transmission system of claim 6, the adjustable feedback divider includes a fine-tuning circuit. When the clock adjustment signal represents an increase in the frequency of the working clock signal, by reducing the divisor, the The fine-tuning circuit increases the frequency of the working clock signal through a unit of fine-tuning frequency, so that the error signal generated by the phase frequency detector represents the phase or clock of the feedback signal lags behind the reference clock signal, so that the The charge pump increases the voltage level of the voltage-controlled voltage signal, so that the voltage-controlled oscillator generates the working clock signal at a higher frequency. For example, in the transmission system of claim 8, the adjustable feedback divider includes a fine-tuning circuit. When the clock adjustment signal represents a decrease in the frequency of the working clock signal, by increasing the divisor, the The fine-tuning circuit reduces the frequency of the working clock signal through the unit fine-tuning frequency, so that the error signal generated by the phase frequency detector represents the phase or clock of the feedback signal leading the reference clock signal, so that the The charge pump reduces the voltage level of the voltage-controlled voltage signal, so that the voltage-controlled oscillator generates the working clock signal at a lower frequency. For example, in the transmission system of patent application item 8 or 9, the adjustable feedback divider adjusts the divisor so that the frequency of the working clock signal satisfies the following relationship: CLKO'=CLKO+freq.× n Where CLKO' is the adjusted frequency of the working clock signal, CLKO is the adjusted frequency of the working clock signal, freq. is the unit fine-tuning frequency, and n is a positive integer or a negative integer.

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