CN101685334B - Device and method for generating frequency and computer system using same - Google Patents
Device and method for generating frequency and computer system using same Download PDFInfo
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- CN101685334B CN101685334B CN 200810165694 CN200810165694A CN101685334B CN 101685334 B CN101685334 B CN 101685334B CN 200810165694 CN200810165694 CN 200810165694 CN 200810165694 A CN200810165694 A CN 200810165694A CN 101685334 B CN101685334 B CN 101685334B
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Abstract
The invention relates to a device and a method for generating frequency and a computer system using same. The device for generating frequency comprises a phase-locked loop module and an adjusting module; the phase-locked loop module receives a reference frequency signal and generates an output frequency signal as the basic frequency of the computer system according to the phase difference between the reference frequency signal and a feedback signal, wherein the phase-locked loop module comprises a frequency eliminator which is used for adjusting the self frequency elimination rate according to a control signal and carrying out frequency elimination treatment on the output frequency signal to generate the feedback signal; the adjusting module is coupled with the phase-locked loop module and generates the control signal according to a voltage identification code of a central processor and the feedback signal or the reference frequency signal. Parts using output frequency signal as the basic frequency are adopted in the computer system so that the working frequency of the parts can be synchronously adjusted.
Description
Technical field
The invention relates to a kind of frequency generating device and method thereof, and the computer system of using this device, and particularly can adjust the device of the frequency of its output frequency signal according to the electric voltage identification code of central processing unit about a kind of.
Background technology
(information technology, IT) usefulness and the service time of industry in order to improve product, the requirement on power requirements also little by little increased Information technology now.Such as like high-order reduced instruction set computer machine (advance RISC machine; ARM), the processor of Intel (Intel) and ultra micro (AMD) all has dynamic electric voltage and frequency adjustment (dynamic voltage frequency scaling; DVFS) design; Use when computer system is left unused perhaps computing in a large number, dynamically reduce the frequency of operation and the WV of computer system.
Fig. 1 is the calcspar of computer system.Please with reference to Fig. 1, the frequency signal HCLK that central processing unit 120 and chipset 130 receive frequency generators 110 are produced is to operate as base frequency.The frequency identification sign indicating number that central processing unit 120 is produced (frequencyi dentification definition; FID)/electric voltage identification code (voltage identification definition; VID) can change with its operation mode, save power consumption dynamically to adjust its frequency of operation and WV.When computer system 100 need not the power consumption in a large amount of computings; Phase-locked loop (phaselock loop in the central processing unit 120; The frequency of the frequency signal HCLK that PLL) just can be received in inside adjustment or adjust self frequency elimination multiplying power; To reduce the frequency of operation of central processing unit 120; And central processing unit 120 also can produce according to its operation mode electric voltage identification code to VRM Voltage Regulator Module (voltage regulator module, VRM) 140, make VRM Voltage Regulator Module 140 can reduce the WV Vcore of central processing unit 120 according to electric voltage identification code.
But; The mechanism of above-mentioned dynamic electric voltage and frequency adjustment is frequency of operation and the WV that is applied to adjust central processing unit 120; Therefore through Front Side Bus (front side bus, (dynamic random accessmemory DRAM) 150 still keeps its original frequency of operation for chipset 130 that FSB) is connected with central processing unit 120 and DRAM; This has also caused computer system 100 when leaving unused or need not a large amount of computing, still has unnecessary power consumption.Therefore, in order to save the power consumption of computer system, must the perfect low-power design of development one cover.
Summary of the invention
The present invention provides a kind of frequency generating device and method thereof, and it can adjust the frequency of its output frequency signal that produces according to the electric voltage identification code of central processing unit.By this, just can be according to the operation mode of central processing unit, the suitable output frequency signal base frequency as computer system is provided, make computer system can operate and save power consumption more efficiently.
The present invention provides a kind of computer system in addition, and it adopts above-mentioned frequency generating device, also has above-mentioned advantage.
The present invention proposes a kind of frequency generating device and comprises phase-locked loop module and adjusting module.The phase-locked loop module receives reference frequency signal, and produces output frequency signal to computer system, with the base frequency as computer system.Wherein, the phase-locked loop module comprises frequency eliminator, and it adjusts the frequency elimination multiplying power according to control signal, and according to this output frequency signal is carried out frequency elimination and handle, to produce feedback signal.And adjusting module couples the phase-locked loop module, and it is according to the electric voltage identification code of central processing unit, and according to feedback signal or reference frequency signal, the generation control signal is with the frequency of adjustment output frequency signal.
The present invention proposes a kind of computer system and comprises central processing unit and frequency generating device.Central processing unit receives output frequency signal and operates as base frequency, and according to its operation mode, produces electric voltage identification code.Frequency generating device couples central processing unit, and it adjusts the frequency of output frequency signal according to electric voltage identification code, and produces output frequency signal.
The present invention proposes a kind of frequency generating method, so that the base frequency of output frequency signal as computer system to be provided.The method is the electric voltage identification code according to central processing unit, and according to feedback signal or reference frequency signal, adjusts the frequency elimination multiplying power, and according to this frequency elimination multiplying power, output frequency signal is carried out frequency elimination handle to produce feedback signal.Then, the phase differential between detecting reference frequency signal and the feedback signal, and produce output frequency signal according to this.
The present invention adjusts the frequency of output frequency signal because of the electric voltage identification code that adopts central processing unit, makes the frequency of output frequency signal can the dynamically adjustment according to the operation mode of central processing unit.And in the computer system, adopting the device of this output frequency signal as base frequency, its frequency of operation also can be adjusted with being synchronized, with usefulness and the reduction power consumption that improves computer system.
For let above and other objects of the present invention, feature and advantage can be more obviously understandable, hereinafter is special lifts preferred embodiment of the present invention, and cooperates appended graphicly, elaborates as follows.
Description of drawings
Fig. 1 is the calcspar of computer system.
Fig. 2 A is the calcspar of the computer system of one embodiment of the invention.
Fig. 2 B is the calcspar of embodiment of the invention Fig. 2 A medium frequency generation device.
Fig. 2 C is another calcspar of embodiment of the invention Fig. 2 A medium frequency generation device.
Embodiment
Fig. 2 A is the calcspar of the computer system of one embodiment of the invention.Please with reference to Fig. 2 A, computer system 200 comprises frequency generating device 210, central processing unit 220, chipset 230, VRM Voltage Regulator Module 240 and DRAM 250.The output frequency signal CLK that central processing unit 220 receive frequency generation devices 210 are produced; To operate as base frequency; And produce electric voltage identification code (voltage identification definition VID) gives VRM Voltage Regulator Module 240 according to the operation mode of itself.Therefore, VRM Voltage Regulator Module 240 just produces WV Vcore to central processing unit 220 according to electric voltage identification code, gives central processing unit 220 with power supply.For instance; When computer system 200 is in idle state; The operand of central processing unit 220 reduces; Therefore central processing unit 220 electric voltage identification code that produces corresponding operation mode is at present given VRM Voltage Regulator Module 240, makes VRM Voltage Regulator Module provide lower WV Vcore to central processing unit 220, to save the power consumption of computer system 200.
Fig. 2 B is the calcspar of embodiment of the invention Fig. 2 A medium frequency generation device 210.Please with reference to Fig. 2 A and Fig. 2 B, frequency generating device 210 comprises phase-locked loop module 211 and adjusting module 217.Phase-locked loop module 211 is according to the phase differential between reference frequency signal REF and the feedback signal FB, and generation output frequency signal CLK.Wherein, phase-locked loop module 211 comprises phase frequency detector 212, charge pump 213, low-pass filter 214, voltage controlled oscillator 215 and frequency eliminator 216.Phase differential between phase frequency detector 212 detecting reference frequency signal REF and the feedback signal FB, and draw signal P_up and pulldown signal P_down on producing according to this, with discharging and recharging of control charge pump 213.Because the variation of phase signal is small, amplifies this phase signal through discharging and recharging of charge pump 213, to produce the first signal S1.Low-pass filter 214 receives the first signal S1, and it carries out low-pass filtering treatment with the first signal S1, produces and is proportional to the direct-current control voltage of above-mentioned phase differential, and be sent to voltage controlled oscillator 215, with the running of control voltage controlled oscillator 215.Therefore, voltage controlled oscillator 215 just can be adjusted the frequency of output frequency signal CLK according to the first signal S1.The control signal CON that frequency eliminator 216 in the phase-locked loop module 211 is produced according to adjusting module 217 adjusts the frequency elimination multiplying power of itself, and output frequency signal CLK is carried out frequency elimination handle to produce feedback signal.
Adjusting module 217 couples phase-locked loop module 211, and it produces control signal CON according to electric voltage identification code that central processing unit 220 produced and feedback signal FB, with the frequency elimination multiplying power of adjustment frequency eliminator 216.In the present embodiment, adjusting module 217 receives the electric voltage identification code of numerical data form, and adopts the predetermined frequency elimination multiplying power of simple logical circuit with this electric voltage identification code reflection to correspondence.At this moment, adjusting module 217 forms a feedback loop with frequency eliminator 216.Adjusting module 217 is little by little adjusted frequency elimination multiplying power to the above-mentioned predetermined frequency elimination multiplying power of frequency eliminator 216 with small variable quantity, and the feedback signal FB that adopts frequency elimination to handle gained is used as reference frequency.This that is to say, the information of adjusting module 217 reference voltage identification codes is adjusted the frequency elimination multiplying power of frequency eliminators 216 in the phase-locked loop module 211 at leisure, avoids the change of frequency of output frequency signal CLK too fast.When output frequency signal CLK changes lentamente; Adopt the device (for example: central processing unit 220 and chipset 230) of output frequency signal CLK in the computer system 200 as base frequency; The change of frequency that output frequency signal CLK can fully be followed the trail of in its inner phase-locked loop (not being shown in Fig. 2 A); Make these phase-locked loops still can keep its synchronous regime, meet the input frequency range scope of these device inside phase-locked loops at this hypothesis output frequency signal CLK.
Fig. 2 C is another calcspar of embodiment of the invention Fig. 2 A medium frequency generation device 210.Please with reference to Fig. 2 C, electric voltage identification code and reference frequency signal REF that adjusting module 217 also can be produced according to central processing unit 220 produce the frequency elimination multiplying power that control signal CON adjusts frequency eliminator 216.In the present embodiment; Adjusting module 217 adopts reference frequency signal REF frequency as a reference; And the information of reference voltage identification code is adjusted the frequency elimination multiplying power of frequency eliminators 216 in the phase-locked loop module 211 at leisure, and is too fast with the change of frequency of avoiding output frequency signal CLK.The running of embodiment Fig. 2 C is of implementing illustration 2B, so do not add to give unnecessary details.
In sum, the foregoing description medium frequency generation device 210 changes the frequency of output frequency signal CLK with reference to the electric voltage identification code information of central processing unit 220.By this, when computer system 200 is in idle state or need not a large amount of computings, make the frequency that can little by little reduce output frequency signal CLK, to save the power consumption of computer system 200 through the adjusting module 217 in the frequency generating device 210.And, adopting the device of this output frequency signal CLK in the computer system 200 as base frequency, its frequency of operation also can synchronously be adjusted, and saves the power consumption of computer system 200 widely.Adjusting module 217 can be automatically and dynamically adjust the frequency of output frequency signal CLK in the foregoing description, and the user need not through basic input/output (basic input/output system, BIOS) computer system 200 of setting or reset.
Though the present invention discloses as above with preferred embodiment; Right its is not in order to limit the present invention; Has common knowledge the knowledgeable in the technical field under any; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (10)
1. a frequency generating device is suitable for computer system, it is characterized in that, the said frequencies generation device comprises:
The phase-locked loop module; Receive reference frequency signal; And producing the base frequency of output frequency signal as above-mentioned computer system, wherein above-mentioned phase-locked loop module comprises frequency eliminator, in order to adjust the frequency elimination multiplying power according to control signal; And above-mentioned output frequency signal is carried out frequency elimination handle, to produce feedback signal; And
Adjusting module couples above-mentioned phase-locked loop module, according to the electric voltage identification code of central processing unit, and according to above-mentioned feedback signal or above-mentioned reference frequency signal, produces above-mentioned control signal.
2. frequency generating device according to claim 1 is characterized in that, wherein above-mentioned phase-locked loop module also comprises:
The phase frequency detector is detected the phase differential between above-mentioned reference frequency signal and the above-mentioned feedback signal, and draws signal and pulldown signal on producing according to this;
Charge pump couples above-mentioned phase frequency detector, draws signal and above-mentioned pulldown signal to discharge and recharge according on above-mentioned, and produces first signal; And
Voltage controlled oscillator couples above-mentioned charge pump, receives above-mentioned first signal, and produces above-mentioned output frequency signal according to this.
3. frequency generating device according to claim 2 is characterized in that, wherein above-mentioned phase-locked loop module also comprises:
Low-pass filter is coupled between above-mentioned charge pump and the above-mentioned voltage controlled oscillator, in order to above-mentioned first signal is carried out low-pass filtering treatment, and is sent to above-mentioned voltage controlled oscillator.
4. a computer system is characterized in that, above-mentioned computer system comprises:
Central processing unit receives output frequency signal and operates as base frequency, and according to operation mode, produces electric voltage identification code; And
Frequency generating device couples above-mentioned central processing unit, according to above-mentioned electric voltage identification code, adjusts the frequency of above-mentioned output frequency signal, and produces above-mentioned output frequency signal, and wherein the said frequencies generation device comprises:
The phase-locked loop module receives reference frequency signal, and produces above-mentioned output frequency signal; Wherein above-mentioned phase-locked loop module comprises frequency eliminator; In order to according to control signal adjustment frequency elimination multiplying power, and above-mentioned output frequency signal is carried out frequency elimination handle, to produce feedback signal; And
Adjusting module couples above-mentioned phase-locked loop module, according to the electric voltage identification code of central processing unit, and according to above-mentioned feedback signal or above-mentioned reference frequency signal, produces above-mentioned control signal.
5. computer system according to claim 4 is characterized in that, wherein above-mentioned phase-locked loop module also comprises:
The phase frequency detector is detected the phase differential between above-mentioned reference frequency signal and the above-mentioned feedback signal, and draws signal and pulldown signal on producing according to this;
Charge pump couples above-mentioned phase frequency detector, draws signal and above-mentioned pulldown signal to discharge and recharge according on above-mentioned, and produces first signal; And
Voltage controlled oscillator couples above-mentioned charge pump, receives above-mentioned first signal, and produces above-mentioned output frequency signal according to this.
6. computer system according to claim 5 is characterized in that, wherein above-mentioned phase-locked loop module also comprises:
Low-pass filter is coupled between above-mentioned charge pump and the above-mentioned voltage controlled oscillator, in order to above-mentioned first signal is carried out low-pass filtering treatment, and is sent to above-mentioned voltage controlled oscillator.
7. computer system according to claim 4 is characterized in that, above-mentioned computer system also comprises:
VRM Voltage Regulator Module couples above-mentioned central processing unit, according to above-mentioned electric voltage identification code, produces WV, gives above-mentioned central processing unit with power supply.
8. computer system according to claim 4 is characterized in that, above-mentioned computer system also comprises:
Chipset couples the said frequencies generation device, receives above-mentioned output frequency signal and operates as base frequency.
9. a frequency generating method is suitable for providing the base frequency of output frequency signal as computer system, it is characterized in that the said frequencies production method comprises:
According to the electric voltage identification code of central processing unit, and according to feedback signal or reference frequency signal, adjustment frequency elimination multiplying power;
According to above-mentioned frequency elimination multiplying power, above-mentioned output frequency signal is carried out frequency elimination handle, and produce above-mentioned feedback signal; And
Detect the phase differential between above-mentioned reference frequency signal and the above-mentioned feedback signal, and produce above-mentioned output frequency signal according to this.
10. frequency generating method according to claim 9 is characterized in that, wherein detects the above-mentioned phase differential between above-mentioned reference frequency signal and the above-mentioned feedback signal, and the step that produces above-mentioned output frequency signal according to this comprises:
According to above-mentioned phase differential, draw signal and pulldown signal in the generation;
Draw signal and above-mentioned pulldown signal according on above-mentioned, the control charge pump discharges and recharges, and produces first signal according to this; And
According to above-mentioned first signal, adjust the frequency of above-mentioned output frequency signal, and produce above-mentioned output frequency signal.
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| US7073082B2 (en) * | 2003-10-31 | 2006-07-04 | Via Technologies, Inc. | Method for CPU power management and bus optimization |
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| US7073082B2 (en) * | 2003-10-31 | 2006-07-04 | Via Technologies, Inc. | Method for CPU power management and bus optimization |
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