TWI690955B - Multi-terminal inductor and method for forming multi-terminal inductor - Google Patents

Multi-terminal inductor and method for forming multi-terminal inductor Download PDF

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TWI690955B
TWI690955B TW108128851A TW108128851A TWI690955B TW I690955 B TWI690955 B TW I690955B TW 108128851 A TW108128851 A TW 108128851A TW 108128851 A TW108128851 A TW 108128851A TW I690955 B TWI690955 B TW I690955B
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Taiwan
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inductor
terminal
wire
layer
magnetic layer
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TW108128851A
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Chinese (zh)
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TW202013398A (en
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徐慶鐘
張天慈
張家龍
楊宗育
林哲永
謝政傑
李虹錤
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台灣積體電路製造股份有限公司
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Abstract

A multi-terminal inductor is provided. The multi-terminal inductor, including: a semiconductor substrate; an interconnect structure having a plurality of metal layers disposed over the semiconductor substrate; a first magnetic layer disposed over an uppermost surface of the interconnect structure; a conductive wire disposed over the first magnetic layer; a first input/output (I/O) bond structure that branches off of the conductive wire at a first location; a second I/O bond structure that branches off of the conductive wire at a second location, the second location being spaced apart from the first location; and a third I/O bond structure that branches off of the conductive wire at a third location between the first location and the second location, wherein a connection between the third I/O bond structure and the first I/O bond structure has a first inductance and an alternative connection between the first I/O bond structure and the second I/O bond structure has a second inductance that is greater than the first inductance.

Description

多端點電感器及多端點電感器形成方法Multi-terminal inductor and multi-terminal inductor forming method

本發明實施例係有關於一種積體電路的多端點電感器，特別是有關於能夠提供複數電感的多端點電感器。The embodiments of the present invention relate to a multi-terminal inductor of an integrated circuit, and particularly to a multi-terminal inductor capable of providing complex inductance.

積體電路是在單片半導體材料上的電子元件的組件(assembly)。電感器是積體電路中廣泛使用的電子元件。電感器是一種被動元件，當電流流過電感器時，電感器將電能儲存在磁場中。由於任何電流導體都具有電感特性，因此電感器的設計差異很大。電感器是通用元件，其可用於RL濾波器、LC電路、RLC電路、電源、變壓器及許多其他電路元件。Integrated circuits are assemblies of electronic components on a single piece of semiconductor material. Inductors are electronic components widely used in integrated circuits. An inductor is a passive component. When current flows through the inductor, the inductor stores electrical energy in a magnetic field. Since any current conductor has inductive characteristics, the design of the inductor varies greatly. Inductors are general-purpose components that can be used in RL filters, LC circuits, RLC circuits, power supplies, transformers, and many other circuit components.

本發明一些實施例提供一種多端點電感器，包括：一半導體基底；一互連結構，設置在半導體基底上，互連結構具有複數金屬層；一第一磁性層，設置在互連結構的一最上表面上；一導線，設置在第一磁性層上；一第一輸入/輸出(I/O)接合(bond)結構，在一第一位置從導線分岔(branch off)；一第二I/O接合結構，在一第二位置從導線分岔，第二位置與第一位置間隔開；以及一第三I/O接合結構，第三I/O接合結構在第一位置與第二位置之間的一第三位置從導電線分岔，其中第三I/O接合結構與第一I/O接合結構之間的一連接具有一第一電感，以及第一I/O接合結構與第二I/O接合結構之間的一替代連接具有一第二電感，第二電感大於第一電感。Some embodiments of the present invention provide a multi-terminal inductor, including: a semiconductor substrate; an interconnection structure disposed on the semiconductor substrate, the interconnection structure having a plurality of metal layers; and a first magnetic layer disposed on one of the interconnection structures On the uppermost surface; a wire, disposed on the first magnetic layer; a first input/output (I/O) bond structure, branching off from the wire at a first position; a second I /O junction structure, bifurcating from the wire at a second position, the second position is spaced from the first position; and a third I/O junction structure, the third I/O junction structure at the first position and the second position A third position between the two branches from the conductive line, wherein a connection between the third I/O junction structure and the first I/O junction structure has a first inductance, and the first I/O junction structure and the first An alternative connection between the two I/O junction structures has a second inductance, which is greater than the first inductance.

本發明一些實施例提供一種多端點電感器，包括：一半導體基底；一互連結構，設置在半導體基底上，互連結構具有複數金屬層；一鈍化層，設置在互連結構的一最上表面上；一磁性層，設置在鈍化層上；複數電感器單元分別包括複數導線，該等電感器單元彼此間隔開並設置在磁性層上，其中該等電感器單元之一第一電感器單元包括一介電層，介電層在第一電感器單元的一第一導線上延伸，並且包括一第一端點及一第二端點，其延伸穿過介電層以電性連接到第一電感器單元的第一導線；以及一連接結構，設置在介電層上並具有電性耦接到第一端點及第二端點的導電佈線，其中連接結構將該等電感器單元中的部分電感器單元彼此電串聯，但不是全部的電感器單元。Some embodiments of the present invention provide a multi-terminal inductor, including: a semiconductor substrate; an interconnection structure disposed on the semiconductor substrate, the interconnection structure having a plurality of metal layers; a passivation layer disposed on an uppermost surface of the interconnection structure A magnetic layer disposed on the passivation layer; a plurality of inductor units each including a plurality of wires, the inductor units are spaced apart from each other and disposed on the magnetic layer, wherein one of the inductor units includes a first inductor unit including A dielectric layer, which extends on a first wire of the first inductor unit, and includes a first terminal and a second terminal, which extend through the dielectric layer to be electrically connected to the first The first lead of the inductor unit; and a connection structure, which is provided on the dielectric layer and has conductive wiring electrically coupled to the first end point and the second end point, wherein the connection structure connects the Some inductor units are electrically connected in series with each other, but not all of the inductor units.

本發明一些實施例提供一種多端點電感器形成方法，包括：在一半導體基底上形成具有複數金屬層的一互連結構；在互連結構的一最上表面上形成一鈍化層；在鈍化層上形成一第一磁性層；在第一磁性層上形成彼此間隔開的複數導線；在該等導線上形成一介電層；在介電層上形成複數焊料凸塊，其中該等焊料凸塊中的不同焊料凸塊電性耦接到不同的導線；以及選擇性地將具有導電佈線的印刷電路板(PCB)連接到該等焊料凸塊中的部分焊料凸塊，但不是全部的焊料凸塊。Some embodiments of the present invention provide a method for forming a multi-terminal inductor, including: forming an interconnect structure having a plurality of metal layers on a semiconductor substrate; forming a passivation layer on an uppermost surface of the interconnect structure; on the passivation layer Forming a first magnetic layer; forming a plurality of conductive wires spaced apart from each other on the first magnetic layer; forming a dielectric layer on the wires; forming a plurality of solder bumps on the dielectric layer, wherein the solder bumps Different solder bumps are electrically coupled to different wires; and selectively connect a printed circuit board (PCB) with conductive wiring to some of the solder bumps, but not all of the solder bumps .

現在將參照圖式描述本發明實施例，其中相同的圖式標記始終用於指示相同的元件，並且其中所示出的結構不一定按比例繪製。應可理解的是，該詳細描述及相應圖式不以任何方式限定本發明實施例的範圍，並且詳細描述及圖式僅提供幾個示例來說明本發明構思可以體現其中的一些方式。Embodiments of the present invention will now be described with reference to the drawings, in which the same drawing marks are always used to indicate the same elements, and the structures shown therein are not necessarily drawn to scale. It should be understood that the detailed description and corresponding drawings do not limit the scope of the embodiments of the present invention in any way, and the detailed description and drawings only provide a few examples to illustrate some of the ways in which the inventive concept can be embodied.

以下公開許多不同的實施方法或是實施例來實行所提供之標的之不同特徵，以下描述具體的元件及其排列的實施例以闡述本發明實施例。當然這些實施例僅用以示例，且不該以此限定本案的範圍。例如，在說明書中提到第一特徵形成於第二特徵之上，其包括第一特徵與第二特徵是直接接觸的實施例，另外也包括於第一特徵與第二特徵之間另外有其他特徵的實施例，亦即，第一特徵與第二特徵並非直接接觸。此外，在不同實施例中可能使用重複的標號或標示，這些重複僅為了簡單清楚地敘述本案，不代表所討論的不同實施例及/或結構之間有特定的關係。Many different implementation methods or embodiments are disclosed below to implement different features of the provided subject matter. The following describes specific elements and arrangements of the embodiments thereof to illustrate the embodiments of the present invention. Of course, these embodiments are for illustration only, and should not be used to limit the scope of the case. For example, it is mentioned in the specification that the first feature is formed on the second feature, which includes the embodiment where the first feature and the second feature are in direct contact, and also includes between the first feature and the second feature. An embodiment of the feature, that is, the first feature and the second feature are not in direct contact. In addition, repeated reference numerals or marks may be used in different embodiments. These repetitions are merely for the simple and clear description of the case, and do not mean that there is a specific relationship between the different embodiments and/or structures discussed.

此外，其中可能用到與空間相關用詞，例如“在…下方”、“下方”、“較低的”、“上方”、“較高的”及類似的用詞，這些空間相關用詞係為了便於描述圖示中一個(些)元件或特徵與另一個(些)元件或特徵之間的關係，這些空間相關用詞包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位)，則其中所使用的空間相關形容詞也將依轉向後的方位來解釋。In addition, space-related words may be used, such as "below", "below", "lower", "above", "higher" and similar words, these space-related words In order to facilitate the description of the relationship between one or more elements or features in the illustration, these spatially related terms include the different orientations of the device in use or in operation, as well as the description in the drawings Position. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially related adjectives used in it will also be interpreted according to the turned orientation.

有些電感器整體地集成在一半導體基底上。在一些實施例中，積體電感器(integrated inductor)形成在基底上的後段製程(back-end-of-the-line，BEOL)的金屬互連層內。由於任何電流導體都具有電感特性，積體電感器可以採用多種佈局實現，例如螺旋電感器、平面螺旋電感器、直線電感器或耦合電感器。 此外，取決於應用，積體電感器可以包括例如介電材料(例如，空心(air core))、鐵磁或亞鐵磁芯。舉例而言，積體螺旋電感器可以包括設置在第一金屬層內的磁芯。金屬線可以以螺旋圖案纏繞磁芯，使得金屬線具有多個圍繞磁芯連續延伸的匝。Some inductors are integrally integrated on a semiconductor substrate. In some embodiments, an integrated inductor is formed in a back-end-of-the-line (BEOL) metal interconnect layer on the substrate. Since any current conductor has inductive characteristics, integrated inductors can be implemented in a variety of layouts, such as spiral inductors, planar spiral inductors, linear inductors, or coupled inductors. In addition, depending on the application, the integrated inductor may include, for example, a dielectric material (for example, an air core), a ferromagnetic or ferrimagnetic core. For example, the integrated spiral inductor may include a magnetic core disposed in the first metal layer. The metal wire may be wound around the magnetic core in a spiral pattern so that the metal wire has a plurality of turns extending continuously around the magnetic core.

上述電感器的一個挑戰是為客戶提供精確符合其需求的電感器。客戶通常設計需要電感器的積體電路(IC)。這些IC被設計為以特定的電感值運作。典型地，IC製造商將電感器實現於客戶的IC中。然而，由於每個特定的IC應用都需要特定的電感值來實現最佳運作，因此製造商通常會使用具有特定電感值的預先設計電感器。這種預先設計電感可能有一個固定的電感值，這可能比客戶IC所需要的更大或更少。這種電感值的差異可能會增加客戶IC的總電阻值，並導致客戶的IC在比最佳狀態差的狀態下運作。更進一步地，由於電感器的電感值與電感器的面積成正比，因此若在客戶的IC中實現大於所需電感值的電感器，就會佔用IC寶貴的空間。解決這一難題的部分方案是設計IC專用電感器。但是，這大大增加了製造IC的成本。因此，在不需要特定應用的電感器設計的情況下，就可選擇增加電感值的電感器，可以改善IC的功能性及製造IC的成本。One challenge of the above inductors is to provide customers with inductors that precisely meet their needs. Customers often design integrated circuits (ICs) that require inductors. These ICs are designed to operate with specific inductance values. Typically, IC manufacturers implement inductors in customers' ICs. However, because each specific IC application requires a specific inductance value for optimal operation, manufacturers often use pre-designed inductors with specific inductance values. This pre-designed inductor may have a fixed inductance value, which may be greater or less than what the customer IC requires. This difference in inductance value may increase the total resistance value of the customer's IC and cause the customer's IC to operate in a state that is worse than the optimal state. Furthermore, since the inductance value of the inductor is proportional to the area of the inductor, if an inductor larger than the required inductance value is realized in the customer's IC, it will occupy valuable space of the IC. Part of the solution to this problem is to design IC-specific inductors. However, this greatly increases the cost of manufacturing ICs. Therefore, when the design of the inductor for a specific application is not required, an inductor with an increased inductance can be selected, which can improve the functionality of the IC and the cost of manufacturing the IC.

本發明實施例涉及一種多端點電感器(以及相關方法)，其具有以固定增量提供電感的構造，從而當IC需要一電感器時，為客戶提供增加電感的選項。在一些實施例中，多端點電感器設置在一鈍化層(passivation layer)上方，該鈍化層設置在互連結構/內連線結構(interconnect structure)上方。多端點電感器可以包括佈置成陣列的複數電感器單元。每個電感器單元包括導線(conductive wire)，使得每個電感器單元具有可測量的電感值。此外，每個電感器單元包括至少兩個輸入/輸出(input/output，I/O)接合(bond)結構。因此，每個電感器單元的單獨I/O接合結構可以由最終用戶(或製造商)以各種組合耦合在一起，以實現各種電感值。因此，由於多端點電感器為客戶提供增加電感選項，多端點電感器改善了IC的功能性並降低了製造IC的成本。Embodiments of the present invention relate to a multi-terminal inductor (and related method) having a structure that provides inductance in fixed increments, so that when the IC needs an inductor, it provides customers with an option to increase inductance. In some embodiments, the multi-terminal inductor is disposed above a passivation layer, which is disposed above the interconnect structure/interconnect structure. The multi-terminal inductor may include a plurality of inductor units arranged in an array. Each inductor unit includes conductive wires so that each inductor unit has a measurable inductance value. In addition, each inductor unit includes at least two input/output (I/O) bond structures. Therefore, the individual I/O junction structure of each inductor unit can be coupled together by the end user (or manufacturer) in various combinations to achieve various inductance values. Therefore, since multi-terminal inductors provide customers with the option of increasing inductance, multi-terminal inductors improve the functionality of ICs and reduce the cost of manufacturing ICs.

參考第1A-1B圖，其提供了多端點電感器的一些實施例的各種俯視圖100A-100B，多端點電感器具有由印刷電路板以各種不同組合連接的複數電感器單元。Referring to FIGS. 1A-1B, which provide various top views 100A-100B of some embodiments of multi-terminal inductors, the multi-terminal inductors have multiple inductor units connected by a printed circuit board in various combinations.

如第1A-1B圖的俯視圖100A-100B所示，通常採取印刷電路板(PCB)形式的連接結構102a/102b，設置在多端點電感器104a/104b上方。多端點電感器104a/104b是形成在半導體基底上的積體電路(IC)的一部分。多端點電感器104a/104b包括佈置成陣列的複數電感器單元106a/106b。例如，第1A圖及第1B圖分別描繪了具有48個電感器單元106a/106b的陣列的多端點電感器104a/104b，其以六行(column)及八列(row)排列。為了表達清楚，在每個圖中，僅標註一個電感器單元106a/106b。As shown in the top views 100A-100B of FIGS. 1A-1B, the connection structure 102a/102b, usually in the form of a printed circuit board (PCB), is disposed above the multi-terminal inductors 104a/104b. The multi-terminal inductors 104a/104b are part of an integrated circuit (IC) formed on a semiconductor substrate. The multi-terminal inductors 104a/104b include a plurality of inductor units 106a/106b arranged in an array. For example, FIGS. 1A and 1B respectively depict a multi-terminal inductor 104a/104b having an array of 48 inductor cells 106a/106b, which are arranged in six columns and eight rows. For clarity, only one inductor unit 106a/106b is marked in each figure.

每個電感器單元106a/106b包括至少一第一輸入/輸出(I/O)接合結構108及一第二I/O接合結構110。每個電感器單元106a/106b包括具有電感特性的導線116，並且導線116將第一I/O接合結構108耦合到第二I/O接合結構110。因此，每個電感器單元106a/106b具有可測量的電感值，例如，1奈亨利(nanohenrry，nH)至100nH。在一些實施例中，多端點電感器104a/104b內的每個電感器單元106a/106b具有實質上相同的電感值。在其他實施例中，電感器單元106a/106b可以具有不同的電感值，或是一種實質上相同與不相同電感值的組合。在一些實施例中，每個電感器單元106a/106b還可以包括額外的I/O接合結構112/114。Each inductor unit 106a/106b includes at least a first input/output (I/O) junction structure 108 and a second I/O junction structure 110. Each inductor unit 106a/106b includes a wire 116 having an inductive characteristic, and the wire 116 couples the first I/O bonding structure 108 to the second I/O bonding structure 110. Therefore, each inductor unit 106a/106b has a measurable inductance value, for example, 1 nanohenrry (nH) to 100 nH. In some embodiments, each inductor cell 106a/106b within the multi-terminal inductor 104a/104b has substantially the same inductance value. In other embodiments, the inductor units 106a/106b may have different inductance values, or a combination of substantially the same and different inductance values. In some embodiments, each inductor unit 106a/106b may also include additional I/O junction structures 112/114.

PCB 102a/102b包括複數導電佈線(conductive trace)118，該等導電佈線118經由電感器單元106a/106b的I/O接合結構108/110/112/114連接到多端點電感器104a/104b。在一些實施例中，I/O接合結構也可以被稱為“端點(terminal)”。在一些實施例中，I/O接合結構108/110/112/114是焊料凸塊(solder bump)，該等焊料凸塊通過熱感應(例如，回流爐或紅外線加熱器)焊料流程，接合到PCB 102a/102b上的焊點(pad)(圖未示出)。PCB 102a/102b係與多端點電感器104a/104b分開，使得PCB 102a/102b的導電佈線118提供IC外部的連接。在一些實施例中，導電佈線118將多端點電感器104a/104b連接至外部裝置，例如外部電阻器、外部電容器及/或外部IC。因此，在製造多端點電感器104a/104b之後，可將多端點電感器104a/104b運送給客戶，並且客戶可以提供具有導電佈線118的PCB 102a/102b，其中導電佈線118被配置為將電感器單元106a/106b連接在一起，以實現客戶所期待的特定電感。The PCBs 102a/102b include a plurality of conductive traces 118 that are connected to the multi-terminal inductors 104a/104b via the I/O bonding structures 108/110/112/114 of the inductor units 106a/106b. In some embodiments, the I/O junction structure may also be referred to as "terminal". In some embodiments, the I/O bonding structures 108/110/112/114 are solder bumps, and the solder bumps are bonded to the solder flow through a thermal induction (eg, reflow oven or infrared heater) solder process Pads (not shown) on the PCB 102a/102b. The PCB 102a/102b is separated from the multi-terminal inductors 104a/104b so that the conductive wiring 118 of the PCB 102a/102b provides connection outside the IC. In some embodiments, conductive wiring 118 connects multi-terminal inductors 104a/104b to external devices, such as external resistors, external capacitors, and/or external ICs. Therefore, after manufacturing the multi-terminal inductors 104a/104b, the multi-terminal inductors 104a/104b can be shipped to the customer, and the customer can provide the PCB 102a/102b with the conductive wiring 118, wherein the conductive wiring 118 is configured to Units 106a/106b are connected together to achieve the specific inductance that customers expect.

舉例而言，如第1A圖所示，PCB 102a的導電佈線118串聯連接多端點電感器104a的頂部兩列(top two rows)的電感器單元106a，使得多端點電感器104a的頂部兩列具有十二倍電感值的一第一電感。此外，相同的PCB 102a可以連接相同的多端點電感器104a的另一列電感器單元106a，以輸出一第二電感。舉例而言，如多端點電感器104a的底部列(bottom row)所示，PCB 102a的導電佈線118連接到第一電感器單元106a的第一I/O接合結構108及第二I/O接合結構110，使得多端點電感器104a的底部列具有一倍電感值的第二電感。因此，客戶可以將兩個(或更多)不同的電感器單元106a/106b與IC及/或外部電路上的其他組件一起集成以實現期望的功能。For example, as shown in FIG. 1A, the conductive wiring 118 of the PCB 102a is connected in series to the top two rows of inductor units 106a of the multi-terminal inductor 104a, so that the top two rows of the multi-terminal inductor 104a have A first inductance with twelve times the inductance value. In addition, the same PCB 102a may be connected to another column of inductor units 106a of the same multi-terminal inductor 104a to output a second inductance. For example, as shown in the bottom row of the multi-terminal inductor 104a, the conductive wiring 118 of the PCB 102a is connected to the first I/O junction structure 108 and the second I/O junction of the first inductor unit 106a In the structure 110, the bottom column of the multi-terminal inductor 104a has a second inductance that is twice the inductance value. Therefore, the customer can integrate two (or more) different inductor units 106a/106b with the IC and/or other components on the external circuit to achieve the desired function.

此外，如第1B圖的視圖100B所示，每個電感器單元106b可以包括多個I/O接合結構108/110/112/114。在此實施例中，每個電感器單元106b可以輸出複數電感值。例如，電感器單元106b具有四個I/O接合結構108/110/112/114，電感器單元106b被配置為輸出至少一第一電感值、第二電感值、第三電感值及第四電感值。如果電感器單元106b透過PCB 102b的導電佈線118連接，使得電流從第一I/O接合結構108流向第二I/O接合結構110，則電感器將具有第一電感值。如果電感器單元106b透過PCB 102b的導電佈線118連接，使得電流從第三I/O接合結構112流向第二I/O接合結構110，則電感器將具有比第一電感值較小的第二電感值。如果電感器單元106b透過PCB 102b的導電佈線118連接，使得電流從第四I/O接合結構114流向第二I/O接合結構110，則電感器將具有比第二電感值較小的第三電感值。此外，如果電感單元106b透過PCB 102b的導電佈線118連接，使得電流從第三I/O接合結構112流到第四I/O接合結構114，則電感器將具有第四電感值，其可以與第一、第二及第三電感值中的每一個相同或不相同。In addition, as shown in view 100B of FIG. 1B, each inductor unit 106b may include a plurality of I/O junction structures 108/110/112/114. In this embodiment, each inductor unit 106b can output a complex inductance value. For example, the inductor unit 106b has four I/O junction structures 108/110/112/114, and the inductor unit 106b is configured to output at least a first inductance value, a second inductance value, a third inductance value, and a fourth inductance value. If the inductor unit 106b is connected through the conductive wiring 118 of the PCB 102b so that current flows from the first I/O junction structure 108 to the second I/O junction structure 110, the inductor will have a first inductance value. If the inductor unit 106b is connected through the conductive wiring 118 of the PCB 102b so that current flows from the third I/O junction structure 112 to the second I/O junction structure 110, the inductor will have a second value that is smaller than the first inductance value Inductance value. If the inductor unit 106b is connected through the conductive wiring 118 of the PCB 102b so that current flows from the fourth I/O junction structure 114 to the second I/O junction structure 110, the inductor will have a third value that is smaller than the second inductance value Inductance value. In addition, if the inductance unit 106b is connected through the conductive wiring 118 of the PCB 102b so that current flows from the third I/O junction structure 112 to the fourth I/O junction structure 114, the inductor will have a fourth inductance value, which can be Each of the first, second, and third inductance values is the same or different.

更進一步地，如第1B圖所示，一列電感器單元106b的一部分可以具有第一電感及第二電感。舉例而言，在多端點電感器104b的第二列中，由於連接第一電感器單元106b的PCB 102b的導電佈線118，多端點電感器104b的第二列會輸出第一電感，以允許電流從第一電感單元106b的第一I/O接合結構108流到第一電感單元106b的第二I/O接合結構112。在同一列中，由於PCB 102b的導電佈線118串聯連接第二電感器單元106b及第三電感器單元106b而輸出第二電感，使得電流從第二電感器單元106b的第四I/O接合結構114透過第二電感器單元106b的第二I/O接合結構110，流入第三電感器單元106b的第一I/O接合結構108，並從第三電感器單元106b的第二I/O接合結構110流出。Furthermore, as shown in FIG. 1B, a part of the inductor unit 106b in a column may have a first inductance and a second inductance. For example, in the second column of the multi-terminal inductor 104b, due to the conductive wiring 118 of the PCB 102b connected to the first inductor unit 106b, the second column of the multi-terminal inductor 104b outputs the first inductance to allow current Flowing from the first I/O junction structure 108 of the first inductor unit 106b to the second I/O junction structure 112 of the first inductor unit 106b. In the same column, since the conductive wiring 118 of the PCB 102b connects the second inductor unit 106b and the third inductor unit 106b in series to output the second inductance, the current flows from the fourth I/O junction structure of the second inductor unit 106b 114 passes through the second I/O junction structure 110 of the second inductor unit 106b, flows into the first I/O junction structure 108 of the third inductor unit 106b, and joins from the second I/O of the third inductor unit 106b Structure 110 flows out.

再者，如第1B圖的多端點電感器104b的底部兩列(bottom two rows)所示，分開列的電感器單元可以連接在一起。舉例而言，多端點電感器104b的底部列中的電感器單元與多端點電感器104b的倒數第二列中的電感器單元106b串聯連接。相應地，因為多端點電感器104a/104b的電感器單元106a/106b可以透過PCB102a/102b的導電佈線118，以各種組合連接，因此多端點電感器104a/104b向客戶(或製造商)提供了具有增加電感選項的電感器，而不需要特定應用的電感器設計。Furthermore, as shown in the bottom two rows of the multi-terminal inductor 104b of FIG. 1B, the inductor units of separate rows may be connected together. For example, the inductor unit in the bottom column of the multi-terminal inductor 104b and the inductor unit 106b in the penultimate column of the multi-terminal inductor 104b are connected in series. Accordingly, since the inductor units 106a/106b of the multi-terminal inductors 104a/104b can be connected in various combinations through the conductive wiring 118 of the PCB 102a/102b, the multi-terminal inductors 104a/104b provide customers (or manufacturers) Inductors with increased inductance options without requiring inductor designs for specific applications.

雖然第1A-1B圖僅示出了具有48個電感器單元陣列的多端點電感器104a/104b，其佈置成六行及八列，但應理解的是，多端點電感器104a/104b可包括任意數量的電感器單元106a/106b，並以任意數量的行與列佈置。Although FIGS. 1A-1B only show the multi-terminal inductors 104a/104b having an array of 48 inductor cells arranged in six rows and eight columns, it should be understood that the multi-terminal inductors 104a/104b may include Any number of inductor units 106a/106b are arranged in any number of rows and columns.

參考第2A-2C圖，提供了多端點電感器的一些實施例的各種視圖。第2A圖示出了多端點電感器的一些實施例的簡化俯視圖200A。第2A圖是“簡化的”，因為第2A圖僅示出了每個電感器單元204/206的導線216/218及第二磁性層236。第2B圖示出了第2A圖的多端點電感器的電感器單元的一些實施例的橫截面圖200B，其沿著第2A圖的線B-B'截取。第2C圖示出了第2A圖的多端點電感器的電感器單元的一些實施例的截面圖200C，其沿著第2A圖的線C-C'截取。With reference to Figures 2A-2C, various views of some embodiments of multi-terminal inductors are provided. Figure 2A shows a simplified top view 200A of some embodiments of a multi-terminal inductor. Figure 2A is "simplified" because Figure 2A shows only the wires 216/218 and the second magnetic layer 236 of each inductor unit 204/206. FIG. 2B shows a cross-sectional view 200B of some embodiments of the inductor unit of the multi-terminal inductor of FIG. 2A, which is taken along the line BB′ of FIG. 2A. FIG. 2C shows a cross-sectional view 200C of some embodiments of the inductor unit of the multi-terminal inductor of FIG. 2A, which is taken along the line CC′ of FIG. 2A.

如第2A-2C圖的視圖200A-200C所示，多端點電感器202包括排列成陣列的複數電感器單元204/206。例如，多端點電感器202包括第一電感器單元204及第二電感器單元206。在一些實施例中，第一電感器單元204及第二電感器單元206被設置在相同的橫向方向上。在其他實施例中，第一電感單元204及第二電感單元206相互垂直排列。在一些實施例中，第一電感器單元204的佈局與第二電感器單元206的佈局實質上相同。在其他實施例中，第一電感器單元204的佈局不同於第二電感器單元206的佈局。如第1A-1B圖所示，PCB可以以各種組合連接複數電感器單元204/206，以改變多端點電感器202的電感。為了表達清楚，僅詳細標記了一個電感器單元204。因為多端點電感器202包括可以透過PCB，以各種組合連接的複數電感器單元204/206，所以多端點電感器202提供了具有增加電感選項的電感器，而且不需要特定應用的電感器設計，後者可能導致製造成本的增加或低效的運作條件。As shown in views 200A-200C of FIGS. 2A-2C, the multi-terminal inductor 202 includes a plurality of inductor units 204/206 arranged in an array. For example, the multi-terminal inductor 202 includes a first inductor unit 204 and a second inductor unit 206. In some embodiments, the first inductor unit 204 and the second inductor unit 206 are arranged in the same lateral direction. In other embodiments, the first inductance unit 204 and the second inductance unit 206 are arranged perpendicular to each other. In some embodiments, the layout of the first inductor unit 204 and the layout of the second inductor unit 206 are substantially the same. In other embodiments, the layout of the first inductor unit 204 is different from the layout of the second inductor unit 206. As shown in FIGS. 1A-1B, the PCB may connect the multiple inductor units 204/206 in various combinations to change the inductance of the multi-terminal inductor 202. For clarity, only one inductor unit 204 is marked in detail. Because the multi-terminal inductor 202 includes multiple inductor units 204/206 that can be connected in various combinations through the PCB, the multi-terminal inductor 202 provides an inductor with increased inductance options and does not require an application-specific inductor design, The latter may result in increased manufacturing costs or inefficient operating conditions.

多端點電感器202包括半導體基底208。半導體基底208可以包括任何類型的半導體本體(body)(例如，單晶矽/CMOS基體(bulk)、矽鍺(SiGe)、絕緣體上的矽(silicon on insulator，SOI)等)。半導體基底208還可以包括至少一個半導體裝置(例如，電晶體、電阻器、二極體等)或部分半導體裝置。在一些實施例中，半導體裝置在前段製程(front-end-of-line，FEOL)中設置在半導體基底208之上/之內。舉例而言，半導體裝置可以是電晶體包括設置在半導體基底208之上，且在源極與汲極之間的閘極疊層(gate stack)(例如，設置在高k介電質(high-k dielectric)之上的金屬閘極)，同時源極與汲極設置在半導體基底208之內。The multi-terminal inductor 202 includes a semiconductor substrate 208. The semiconductor substrate 208 may include any type of semiconductor body (eg, single crystal silicon/CMOS bulk, silicon germanium (SiGe), silicon on insulator (SOI), etc.). The semiconductor substrate 208 may also include at least one semiconductor device (eg, transistor, resistor, diode, etc.) or part of the semiconductor device. In some embodiments, the semiconductor device is disposed on/in the semiconductor substrate 208 in a front-end-of-line (FEOL). For example, the semiconductor device may be a transistor including a gate stack disposed on the semiconductor substrate 208 and between the source and the drain (for example, disposed in a high-k dielectric (high-k dielectric k dielectric) metal gate), while the source and the drain are disposed within the semiconductor substrate 208.

互連結構210設置在半導體基底208上方。在一些實施例中，互連結構210在後段製程(BEOL)中形成。互連結構210可以包括複數導電特徵部件(conductive feature)，例如導電觸點(conductive contact)、導線、導電通孔(via)及/或接觸墊(contact pad)，其形成在層間介電(interlayer dielectric，ILD)材料內。導電特徵部件可以包括金屬，諸如銅、鋁、金、銀或其他合適的金屬。ILD材料可以包括二氧化矽(SiO 2)或其他種合適的氧化物，例如低k介電(low-k dielectric)材料。在一些實施例中，互連結構210可以包括設置在彼此之上的複數金屬層(例如，金屬層1、金屬層2等)。每個金屬層可以包括導線，並且導電通孔可以將來自第一金屬層的導線連接到第二金屬層的導線。一些導電通孔將導線連接到設置在互連結構210的頂表面(top surface)附近的接觸墊。 The interconnect structure 210 is disposed above the semiconductor substrate 208. In some embodiments, the interconnect structure 210 is formed in a back-end process (BEOL). The interconnect structure 210 may include a plurality of conductive features, such as conductive contacts, conductive wires, vias, and/or contact pads, which are formed in an interlayer dielectric dielectric (ILD) material. The conductive features may include metals, such as copper, aluminum, gold, silver, or other suitable metals. The ILD material may include silicon dioxide (SiO 2 ) or other suitable oxides, such as low-k dielectric materials. In some embodiments, the interconnect structure 210 may include a plurality of metal layers (eg, metal layer 1, metal layer 2, etc.) disposed on top of each other. Each metal layer may include a wire, and the conductive via may connect the wire from the first metal layer to the wire of the second metal layer. Some conductive vias connect the wires to contact pads disposed near the top surface of the interconnect structure 210.

鈍化層212設置在互連結構210上方。在一些實施例中，鈍化層在BEOL製程中形成。鈍化層212可以順應性地(conformally)形成在互連結構210的最上表面(uppermost surface)。在一些實施例中，鈍化層212具有實質上平坦的頂表面。鈍化層212可以包括SiO 2、氮化矽(Si 3N 4、聚醯亞胺化合物(polyimide compound)或其他合適的材料。 The passivation layer 212 is disposed above the interconnect structure 210. In some embodiments, the passivation layer is formed during the BEOL process. The passivation layer 212 may be conformally formed on the uppermost surface of the interconnect structure 210. In some embodiments, the passivation layer 212 has a substantially flat top surface. The passivation layer 212 may include SiO 2 , silicon nitride (Si 3 N 4 , polyimide compound) or other suitable materials.

在一些實施例中，第一磁性層214設置在鈍化層212上方。第一磁性層214使用合適的製程形成在鈍化層212上，例如化學氣相沉積(chemical vapor deposition，CVD)、物理氣相沉積(physical vapor deposition，PVD)、原子層沉積(atomic layer deposition，ALD)、濺射(sputtering)，電化學電鍍(electrochemical plating)、無電電鍍(electroless plating)或一些其他沉積(deposition)或生長(growth)製程。第一磁性層214包括諸如碲化鎘鋅(cadmium zinc telluride，CZT)、鐵-鎳(NiFe)化合物或其他合適的磁性材料。在一些實施例中，第一磁性層214可以包括複數堆疊層。在其他實施例中，第一磁性層214可以包括磁性塊材(bulk magnetic material)，其從第一磁性層214的底表面延伸到第一磁性層214的頂表面。In some embodiments, the first magnetic layer 214 is disposed above the passivation layer 212. The first magnetic layer 214 is formed on the passivation layer 212 using a suitable process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) ), sputtering, electrochemical plating, electroless plating or some other deposition or growth processes. The first magnetic layer 214 includes materials such as cadmium zinc telluride (CZT), iron-nickel (NiFe) compounds, or other suitable magnetic materials. In some embodiments, the first magnetic layer 214 may include a plurality of stacked layers. In other embodiments, the first magnetic layer 214 may include a bulk magnetic material that extends from the bottom surface of the first magnetic layer 214 to the top surface of the first magnetic layer 214.

在一些實施例中，第一磁性層214可以包括矩形佈局(layout)。在一些實施例中，第一磁性層214可以包括複數離散部分(discrete portion)，使得每個電感器單元204/206包括第一磁性層214之一離散部分。在其他實施例中，第一磁性層214可以包括連續部分(continuous portion)，使得第一磁性層214的一部分在複數電感器單元204/206下連續地延伸。此外，第一磁性層214的厚度可以在範圍從約0.1微米(μm)至約15μm。更具體地，第一磁性層214可以範圍從0.1μm至0.5μm、0.5μm至2.5μm、2.5μm至4.5μm、4.5μm至7.5μm、7.5μm至10μm、10μm至12.5μm或12.5μm至15μm的厚度。另外，第一磁性層214具有從約10μm到約500μm範圍內的寬度。更具體地，第一磁性層214可以範圍從0μm至50μm、50μm至100μm、100μm至150μm、150μm至200μm、200μm至250μm、250μm至300μm、300μm至350μm、350μm至400μm、400μm至450μm或450μm至500μm的寬度。In some embodiments, the first magnetic layer 214 may include a rectangular layout. In some embodiments, the first magnetic layer 214 may include a discrete portion such that each inductor unit 204/206 includes one of the discrete portions of the first magnetic layer 214. In other embodiments, the first magnetic layer 214 may include a continuous portion such that a portion of the first magnetic layer 214 extends continuously under the complex inductor units 204/206. In addition, the thickness of the first magnetic layer 214 may range from about 0.1 micrometer (μm) to about 15 μm. More specifically, the first magnetic layer 214 may range from 0.1 μm to 0.5 μm, 0.5 μm to 2.5 μm, 2.5 μm to 4.5 μm, 4.5 μm to 7.5 μm, 7.5 μm to 10 μm, 10 μm to 12.5 μm, or 12.5 μm to 15 μm thickness of. In addition, the first magnetic layer 214 has a width ranging from about 10 μm to about 500 μm. More specifically, the first magnetic layer 214 may range from 0 μm to 50 μm, 50 μm to 100 μm, 100 μm to 150 μm, 150 μm to 200 μm, 200 μm to 250 μm, 250 μm to 300 μm, 300 μm to 350 μm, 350 μm to 400 μm, 400 μm to 450 μm or 450 μm to 500μm width.

導線216/218設置在第一磁性層214上方。在一些實施例中，每個電感器單元204/206包括設置在第一磁性層214上方的第一導線216和第二導線218。導線216/218可以藉由，例如CVD、PVD、ALD、濺射、電化學電鍍、無電電鍍或一些其他沉積或生長製程等，來沉積或生長。導線216/218包括諸如銅(Cu)、鋁(Al)、金(Au)、銀(Ag)、Al-Cu化合物或任何其它合適的導電材料。在一些實施例中，導線216/218可以是後鈍化銅互連(post-passivation copper interconnect)。在一些實施例中，導線216/218具有在約0.5μm至約50μm範圍內的厚度及/或在約0.5μm至約50μm範圍內的寬度。更具體地，導線216/218可以範圍從0.5μm至5μm、5μm至10μm、15μm至20μm、20μm至25μm、25μm至30μm、30μm至40μm或40μm至50μm的厚度。The wires 216/218 are disposed above the first magnetic layer 214. In some embodiments, each inductor unit 204/206 includes a first wire 216 and a second wire 218 disposed above the first magnetic layer 214. The wires 216/218 can be deposited or grown by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, or some other deposition or growth process. The wires 216/218 include materials such as copper (Cu), aluminum (Al), gold (Au), silver (Ag), Al-Cu compound, or any other suitable conductive material. In some embodiments, the wires 216/218 may be post-passivation copper interconnects. In some embodiments, the wires 216/218 have a thickness in the range of about 0.5 μm to about 50 μm and/or a width in the range of about 0.5 μm to about 50 μm. More specifically, the wires 216/218 may range in thickness from 0.5 μm to 5 μm, 5 μm to 10 μm, 15 μm to 20 μm, 20 μm to 25 μm, 25 μm to 30 μm, 30 μm to 40 μm, or 40 μm to 50 μm.

在一些實施例中，阻擋層(barrier layer)222設置在第一隔離層220上方，使得阻擋層222與第一隔離層220物理分離，並且將導線216/218與第一磁性層214電性隔離。在一些實施例中，阻擋層222包括鉭(Ta)、氮化鉭(TaN)、鈦(Ti)、氮化鈦(TiN)及/或鎢(W)等。導線216/218從其生長的晶種層(seed layer)直接設置在阻擋層222上。晶種層包括Cu、Cu合金、Al、Al合金、Au、Ag、Al-Cu化合物或其他合適的材料，並且當導線216/218從晶種層生長時可以合併到導線216/218中，此部分在第2B圖中沒有明確地指出。第一隔離層220包括介電材料，例如SiO 2、Si 3N 4、低k介電質或一些其他合適的介電材料。舉例而言，第一隔離層220及阻擋層222可以藉由CVD、PVD、ALD、濺射、電化學電鍍、無電電鍍或其他沉積或生長製程等來沉積或生長。 In some embodiments, a barrier layer 222 is disposed above the first isolation layer 220 so that the barrier layer 222 is physically separated from the first isolation layer 220 and electrically isolates the wires 216/218 from the first magnetic layer 214 . In some embodiments, the barrier layer 222 includes tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), and/or tungsten (W), and the like. A seed layer from which the wires 216/218 are grown is directly disposed on the barrier layer 222. The seed layer includes Cu, Cu alloy, Al, Al alloy, Au, Ag, Al-Cu compound or other suitable materials, and can be incorporated into the wire 216/218 when the wire 216/218 grows from the seed layer, this Parts are not clearly indicated in Figure 2B. The first isolation layer 220 includes a dielectric material, such as SiO 2 , Si 3 N 4 , low-k dielectric, or some other suitable dielectric material. For example, the first isolation layer 220 and the barrier layer 222 can be deposited or grown by CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, or other deposition or growth processes.

第一導線216從電感器單元204/206的第一輸入/輸出(I/O)接合結構224延伸到電感器單元204/206的第二I/O接合結構226。在一些實施例中，第一導線216以實質上一直線從第一I/O接合結構224連續地延伸到第二I/O接合結構226。此外，第一導線216可順應性地形成在第一磁性層214之上並延伸超過第一磁性層214的最外側壁(outermost sidewall)，使得第一導線216具有在第一磁性層214之上的第一上表面，該第一上表面位於第一導線216的第二上表面上方，其超過第一磁性層214的最外側壁。在其他實施例中，第一導線216以圍繞第一磁性層214的一螺旋圖案，從第一I/O接合結構224連續地延伸到第二I/O接合結構226。在一些實施例中，第二導線218從電感器單元204/206的第三I/O接合結構228延伸到電感器單元的第四I/O接合結構230，並且具有與第一導線216實質上相同的佈局。據此，因為每個電感器單元204/206具有各自的I/O接合結構224/226/228/230，所以PCB可以將電感器單元204/206以各種組合方式來連接以使多端點電感器202輸出各種電感，而不需要特定應用的電感器設計，後者可能導致製造成本的增加或低效的運作條件。The first wire 216 extends from the first input/output (I/O) junction structure 224 of the inductor unit 204/206 to the second I/O junction structure 226 of the inductor unit 204/206. In some embodiments, the first wire 216 continuously extends from the first I/O bonding structure 224 to the second I/O bonding structure 226 in a substantially straight line. In addition, the first wire 216 may be compliantly formed on the first magnetic layer 214 and extend beyond the outermost sidewalls of the first magnetic layer 214 so that the first wire 216 has the first magnetic layer 214 The first upper surface is located above the second upper surface of the first wire 216, which exceeds the outermost sidewall of the first magnetic layer 214. In other embodiments, the first conductive wire 216 continuously extends from the first I/O bonding structure 224 to the second I/O bonding structure 226 in a spiral pattern surrounding the first magnetic layer 214. In some embodiments, the second wire 218 extends from the third I/O junction structure 228 of the inductor unit 204/206 to the fourth I/O junction structure 230 of the inductor unit, and has substantially the same as the first wire 216 Same layout. Accordingly, because each inductor unit 204/206 has its own I/O junction structure 224/226/228/230, the PCB can connect the inductor units 204/206 in various combinations to make the multi-terminal inductor 202 outputs various inductances without the need for inductor design for specific applications, which may result in increased manufacturing costs or inefficient operating conditions.

第二隔離層232設置在導線216/218上方。在一些實施例中，第二隔離層232可以順應性地形成在鈍化層212、第一磁性層214及導線216/218的表面上，使得第二隔離層232直接接觸鈍化層212、第一磁性層214及導線216/218。第二隔離層232包括介電材料，例如SiO 2、Si 3N 4、低k介電質或一些其他合適的介電材料。第二隔離層232可以藉由，例如CVD、PVD、ALD、濺射或一些其他沉積或生長製程等，來沉積或生長。 The second isolation layer 232 is disposed above the wires 216/218. In some embodiments, the second isolation layer 232 may be compliantly formed on the surfaces of the passivation layer 212, the first magnetic layer 214, and the wires 216/218, so that the second isolation layer 232 directly contacts the passivation layer 212, the first magnetic Layer 214 and wires 216/218. The second isolation layer 232 includes a dielectric material, such as SiO 2 , Si 3 N 4 , low-k dielectric, or some other suitable dielectric material. The second isolation layer 232 can be deposited or grown by, for example, CVD, PVD, ALD, sputtering, or some other deposition or growth process.

第一介電層234設置在第二隔離層232上方。第一介電層234可以是例如：聚醯亞胺化合物、聚苯并噁唑化合物(polybenzoxazole compound)及/或任何其他合適的介電材料。第一介電層234可以藉由，例如CVD、PVD、ALD、濺射、旋塗製程(spin-on process)或一些其他沉積或生長製程等，來沉積或生長。在一些實施例中，第一介電層234可具有實質上平坦的上表面。在一些實施例中，在第一磁性層214上，第一介電層234可具有從約0.5μm至約70μm的範圍內的厚度。更具體地，厚度的範圍可以從0.5μm至5μm、5μm至10μm、10μm至15μm、15μm至20μm、20μm至25μm、25μm至30μm、30μm至40μm、40μm至50μm、50μm至60μm或60μm至70μm。此外，在第一磁性層214上，介電質可以具有從約10μm至約450μm範圍內的寬度。更具體地，寬度的範圍可以從10μm至50μm、50μm至100μm、100μm至150μm、150μm至200μm、200μm至250μm、250μm至300μm、300μm至350μm、350μm至400μm或400μm至450μm。The first dielectric layer 234 is disposed above the second isolation layer 232. The first dielectric layer 234 may be, for example, a polyimide compound, a polybenzoxazole compound, and/or any other suitable dielectric material. The first dielectric layer 234 may be deposited or grown by, for example, CVD, PVD, ALD, sputtering, spin-on process, or some other deposition or growth process. In some embodiments, the first dielectric layer 234 may have a substantially flat upper surface. In some embodiments, on the first magnetic layer 214, the first dielectric layer 234 may have a thickness ranging from about 0.5 μm to about 70 μm. More specifically, the thickness may range from 0.5 μm to 5 μm, 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, 20 μm to 25 μm, 25 μm to 30 μm, 30 μm to 40 μm, 40 μm to 50 μm, 50 μm to 60 μm, or 60 μm to 70 μm. In addition, on the first magnetic layer 214, the dielectric may have a width ranging from about 10 μm to about 450 μm. More specifically, the width may range from 10 μm to 50 μm, 50 μm to 100 μm, 100 μm to 150 μm, 150 μm to 200 μm, 200 μm to 250 μm, 250 μm to 300 μm, 300 μm to 350 μm, 350 μm to 400 μm, or 400 μm to 450 μm.

在一些實施例中，第二磁性層236設置在第一介電層234上。第二磁性層236可使用合適的製程，例如CVD、PVD、ALD、濺射、電化學電鍍、無電電鍍或其他沉積或生長製程等，形成在第一介電層234上方。第二磁性層236包括諸如碲化鎘鋅(CZT)、鐵-鎳(NiFe)化合物或其他合適的磁性材料。在一些實施例中，第二磁性層236可以包括複數堆疊層。在其他實施例中，第二磁性層236可以包括從第二磁性層236的底表面延伸到第二磁性層236的頂表面的磁性塊材。In some embodiments, the second magnetic layer 236 is disposed on the first dielectric layer 234. The second magnetic layer 236 may be formed on the first dielectric layer 234 using a suitable process, such as CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, or other deposition or growth processes. The second magnetic layer 236 includes materials such as cadmium zinc telluride (CZT), iron-nickel (NiFe) compounds, or other suitable magnetic materials. In some embodiments, the second magnetic layer 236 may include a plurality of stacked layers. In other embodiments, the second magnetic layer 236 may include a magnetic bulk material extending from the bottom surface of the second magnetic layer 236 to the top surface of the second magnetic layer 236.

第二介電層238設置在第二磁性層236上方。第二介電層238位在第二磁性層236的上表面和第一介電層234的上表面上在一些實施例中，第二介電層238可以是，例如聚醯亞胺化合物、聚苯并噁唑化合物及/或任何其他合適的介電材料。第二介電層238可以藉由，例如CVD、PVD、ALD、濺射、旋塗製程或其他沉積或生長製程等，來沉積或生長。在進一步的實施例中，第一介電層234可具有實質上平坦的上表面。The second dielectric layer 238 is disposed above the second magnetic layer 236. The second dielectric layer 238 is located on the upper surface of the second magnetic layer 236 and the upper surface of the first dielectric layer 234. In some embodiments, the second dielectric layer 238 may be, for example, a polyimide compound, poly Benzoxazole compound and/or any other suitable dielectric material. The second dielectric layer 238 can be deposited or grown by, for example, CVD, PVD, ALD, sputtering, spin coating process, or other deposition or growth processes. In further embodiments, the first dielectric layer 234 may have a substantially flat upper surface.

I/O接合結構224/226/228/230從它們各自的導線216/218分岔/分枝出來(branch off)。在一些實施例中，每個I/O接合結構224/226/228/230穿過第二隔離層232、第一介電層234及第二介電層238，從它們各自的導線216/218分岔，以從第二介電層238的最上表面突出(protrude)。在一些實施例中，每個I/O接合結構224/226/228/230從它們各自的導線216/218向半導體基底208分岔，以連接到互連結構210的導電特徵部件。此外，每個I/O接合結構224/226/228/230可以以非零角度從其各自的導線216/218分岔，以在I/O接合結構224/226/228/230之間提供足夠的間隔，使得I/O接合結構224/226/228/230從它們各自的導線216/218偏移一段距離。在一些實施例中，I/O接合結構224/226/228/230包括Cu、Cu合金、Al、Al合金、Au、Ag、Al-Cu化合物或其他合適的材料。I/O接合結構224/226/228/230可以藉由例如CVD、PVD、ALD、濺射、電化學電鍍、無電電鍍或其他沉積或生長製程等來形成。據此，客戶(或製造商)可以使用外部連接(例如，PCB)來以各種組合連接I/O接合結構224/226/228/230，以使多端點電感器202輸出各種電感。由於多端點電感器單元202包括複數電感器單元204/206，所以多端電感器單元202向客戶(或製造商)提供更多的電感選項，而不需要特定應用的電感器設計，後者可能導致製造成本的增加或低效的運作條件。The I/O bonding structures 224/226/228/230 branch/branch off from their respective wires 216/218. In some embodiments, each I/O junction structure 224/226/228/230 passes through the second isolation layer 232, the first dielectric layer 234, and the second dielectric layer 238 from their respective wires 216/218 Bifurcation to protrude from the uppermost surface of the second dielectric layer 238. In some embodiments, each I/O bonding structure 224/226/228/230 branches from their respective wires 216/218 to the semiconductor substrate 208 to connect to the conductive features of the interconnect structure 210. In addition, each I/O junction structure 224/226/228/230 can branch from its respective wire 216/218 at a non-zero angle to provide sufficient between the I/O junction structures 224/226/228/230 , The I/O bonding structures 224/226/228/230 are offset from their respective wires 216/218 by a distance. In some embodiments, the I/O bonding structure 224/226/228/230 includes Cu, Cu alloy, Al, Al alloy, Au, Ag, Al-Cu compound, or other suitable materials. The I/O bonding structure 224/226/228/230 can be formed by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, or other deposition or growth processes. Accordingly, customers (or manufacturers) can use external connections (eg, PCBs) to connect the I/O junction structures 224/226/228/230 in various combinations so that the multi-terminal inductor 202 outputs various inductances. Since the multi-terminal inductor unit 202 includes a plurality of inductor units 204/206, the multi-terminal inductor unit 202 provides customers (or manufacturers) with more inductance options without requiring application-specific inductor design, which may result in manufacturing Increased costs or inefficient operating conditions.

參考第3A-3C圖，提供了第2A-2C圖的多端點電感器202的一些實施例的各種視圖300A-300C。第3A圖示出了第2A-2C圖的多端點電感器202的電感器單元204的一些實施例的簡化俯視圖300A。第3B圖示出了第2A-2C圖的多端點電感器202的一些實施例的簡化俯視圖300B，其以雙電流配置(dual-current configuration)連接。第3C圖示出了第2A-2C圖的多端點電感器202一些實施例的簡化俯視圖300C，其以單電流配置(single -current configuration)連接。第3A-3C圖是“簡化”的，因為第3A-3C圖僅示出了每個電感器單元的導線、第一磁性層及第二磁性層。With reference to FIGS. 3A-3C, various views 300A-300C of some embodiments of the multi-terminal inductor 202 of FIGS. 2A-2C are provided. FIG. 3A shows a simplified top view 300A of some embodiments of the inductor unit 204 of the multi-terminal inductor 202 of FIGS. 2A-2C. FIG. 3B shows a simplified top view 300B of some embodiments of the multi-terminal inductor 202 of FIGS. 2A-2C, which are connected in a dual-current configuration. FIG. 3C shows a simplified top view 300C of some embodiments of the multi-terminal inductor 202 of FIGS. 2A-2C, which are connected in a single-current configuration. Figures 3A-3C are "simplified" because they only show the wires, first magnetic layer, and second magnetic layer of each inductor unit.

如第3A-3C圖的視圖300A-300C所示，當電流I1/I2通過導線216/218時，每根導線216/218感應出磁場。根據電流I1/I2流動的方向，基於“右手定則(right-hand rule)”，磁場將被感應出來。舉例而言，在一些實施例中，電路被配置為通過第一導線216提供第一電流I1，使得第一電流I1從頁面的左側流到頁面的右側，以及通過第二導線218提供第二電流I2，使得第二電流I2從頁面的右側流到頁面的左側。因此，第一磁場在第一導線216周圍被感應出來，而第二磁場在第二導線218周圍被感應出來。因此，電感器單元204/206具有可測量的電感。As shown in views 300A-300C of FIGS. 3A-3C, when the current I1/I2 passes through the wires 216/218, each wire 216/218 induces a magnetic field. According to the direction in which the current I1/I2 flows, based on the "right-hand rule", the magnetic field will be induced. For example, in some embodiments, the circuit is configured to provide the first current I1 through the first wire 216 so that the first current I1 flows from the left side of the page to the right side of the page, and the second current is provided through the second wire 218 I2, so that the second current I2 flows from the right side of the page to the left side of the page. Therefore, the first magnetic field is induced around the first wire 216 and the second magnetic field is induced around the second wire 218. Therefore, the inductor unit 204/206 has a measurable inductance.

如第3B圖的視圖300B所示，第一電感器單元204與第二電感器單元206串聯並且以雙電流配置連接。第一電感器單元204與第二電感器單元206以雙電流配置連接，因為PCB(圖未繪示)的導電佈線118允許電流在每個電感器單元204/206中以相反的方向流動。例如，第一電流I1從第一電感單元204的第一I/O接合結構224，經由第一電感單元204的第一導線216流至第一電感單元204的第二I/O接合結構226。導電佈線118將第一電感器單元204的第二I/O接合結構226耦合到第二電感器單元206的第一I/O接合結構308，以允許第一電流I1流入第二電感器單元206的第一導線316，並從第二電感器單元206的第二I/O接合結構310流出。As shown in view 300B of FIG. 3B, the first inductor unit 204 and the second inductor unit 206 are connected in series and connected in a dual current configuration. The first inductor unit 204 and the second inductor unit 206 are connected in a dual current configuration because the conductive wiring 118 of the PCB (not shown) allows current to flow in the opposite direction in each inductor unit 204/206. For example, the first current I1 flows from the first I/O junction structure 224 of the first inductor unit 204 to the second I/O junction structure 226 of the first inductor unit 204 via the first wire 216 of the first inductor unit 204. The conductive wiring 118 couples the second I/O junction structure 226 of the first inductor unit 204 to the first I/O junction structure 308 of the second inductor unit 206 to allow the first current I1 to flow into the second inductor unit 206 The first conductive wire 316 and flow out from the second I/O junction structure 310 of the second inductor unit 206.

第二電流I2從第二電感器單元206的第四I/O接合結構314，通過第二電感器單元206的第二導線320流到第二電感器單元206的第三I/O接合結構312。導電佈線118將第二電感器204的第三I/O接合結構312耦合到第一電感器單元204的第四I/O接合結構230，以允許第二電流I2流入第一電感器單元204的第二導線218，並從第一電感器單元204的第三I/O接合結構228流出。在一些實施例中，第二電感器單元206可以包括第五I/O接合結構318，其經由導電佈線118連接，而不是將導電佈線118連接到第三I/O接合結構312。第五I/O接合結構318設置在第三I/O接合結構312與第四I/O接合結構314之間。因此，如果電流從第四I/O接合結構314流向第五I/O接合結構318，那麼第二電感器單元206將具有小於當電流從第四I/O接結構314流向第三I/O接合結構312時之可測量的電感。據此，因為多端點電感器202具有複數電感器單元204/206，多端點電感器單元202向客戶(或製造商)提供更多的電感選項，而不需要特定應用的電感器設計，後者可能導致製造成本的增加或低效的運作條件。The second current I2 flows from the fourth I/O junction structure 314 of the second inductor unit 206 through the second wire 320 of the second inductor unit 206 to the third I/O junction structure 312 of the second inductor unit 206 . The conductive wiring 118 couples the third I/O junction structure 312 of the second inductor 204 to the fourth I/O junction structure 230 of the first inductor unit 204 to allow the second current I2 to flow into the first inductor unit 204 The second wire 218 flows out from the third I/O junction structure 228 of the first inductor unit 204. In some embodiments, the second inductor unit 206 may include a fifth I/O bonding structure 318 that is connected via the conductive wiring 118 instead of connecting the conductive wiring 118 to the third I/O bonding structure 312. The fifth I/O junction structure 318 is disposed between the third I/O junction structure 312 and the fourth I/O junction structure 314. Therefore, if current flows from the fourth I/O junction structure 314 to the fifth I/O junction structure 318, then the second inductor unit 206 will have a smaller current than when the current flows from the fourth I/O junction structure 314 to the third I/O Measurable inductance when the structure 312 is joined. Accordingly, because the multi-terminal inductor 202 has a plurality of inductor units 204/206, the multi-terminal inductor unit 202 provides customers (or manufacturers) with more inductance options without requiring application-specific inductor design, which may Lead to increased manufacturing costs or inefficient operating conditions.

再者，如第3C圖的視圖300C所示，第一電感器單元204與第二電感器單元206以單電流配置連接。第一電感器單元204與第二電感器單元206以單電流配置連接，是因為PCB(圖未繪示)的導電佈線118允許電流僅以單一方向流過每個電感器單元204/206。此外，在第3C圖中，第一磁性層214連續延伸於第一電感單元204及第二電感單元206的下方。因此，因為多端點電感器202也可以以單電流配置或雙電流配置連接，所以多端點電感器單元202向客戶(或製造商)提供額外的電感選項，而不需要特定應用的電感器設計，後者可能導致製造成本的增加或低效的運作條件。Furthermore, as shown in view 300C of FIG. 3C, the first inductor unit 204 and the second inductor unit 206 are connected in a single current configuration. The first inductor unit 204 and the second inductor unit 206 are connected in a single current configuration because the conductive wiring 118 of the PCB (not shown) allows current to flow through each inductor unit 204/206 in only a single direction. In addition, in FIG. 3C, the first magnetic layer 214 continuously extends below the first inductance unit 204 and the second inductance unit 206. Therefore, because the multi-terminal inductor 202 can also be connected in a single-current configuration or a dual-current configuration, the multi-terminal inductor unit 202 provides additional inductance options to customers (or manufacturers) without requiring an application-specific inductor design, The latter may result in increased manufacturing costs or inefficient operating conditions.

參考第4A-4C圖，提供了第2A-2C圖的多端點電感器202的一些實施例的各種視圖400A-400C。第4A圖示出了第2A-2C圖的多端點電感器202的第一電感器單元204的一些實施例的簡化俯視圖400A。第4B圖示出了第2A-2C圖的多端點電感器202的一些實施例的簡化俯視圖400B，其中每個電感器單元204/206設置在第一磁性層214的分離部分(discrete portion)上方。第4C圖示出了第2A-2C圖的多端點電感器202的一些實施例的簡化俯視圖400C，其中第一磁性層214在第一電感器單元204及第二電感器單元206之間連續地延伸。第4A-4C圖是“簡化”的，因為第4A-4C圖僅示出了每個電感器單元204/206的導線216/218、第一磁性層214及第二磁性層236。With reference to FIGS. 4A-4C, various views 400A-400C of some embodiments of the multi-terminal inductor 202 of FIGS. 2A-2C are provided. FIG. 4A shows a simplified top view 400A of some embodiments of the first inductor unit 204 of the multi-terminal inductor 202 of FIGS. 2A-2C. FIG. 4B shows a simplified top view 400B of some embodiments of the multi-terminal inductor 202 of FIGS. 2A-2C, where each inductor cell 204/206 is disposed above a discrete portion of the first magnetic layer 214 . FIG. 4C shows a simplified top view 400C of some embodiments of the multi-terminal inductor 202 of FIGS. 2A-2C, where the first magnetic layer 214 is continuously between the first inductor unit 204 and the second inductor unit 206 extend. FIGS. 4A-4C are “simplified” because FIGS. 4A-4C only show the wires 216/218, the first magnetic layer 214, and the second magnetic layer 236 of each inductor unit 204/206.

如第4A-4C圖的視圖400A-400C所示，電感器單元204/206僅包括單一導線216/316，導線216/316從第一I/O接合結構224/308連續延伸到第二I/O接合結構226/310。在一些實施例中，每個電感器單元204/206可以設置在第一磁性層214的一分離部分之上，如第4B圖所示。在其它實施例中，第一磁性層214在第一電感器單元204及第二電感器單元206下方連續地延伸，如第4C圖的視圖400C所示。As shown in views 400A-400C of FIGS. 4A-4C, the inductor unit 204/206 includes only a single wire 216/316, and the wire 216/316 continuously extends from the first I/O bonding structure 224/308 to the second I/O O接结构226/310. In some embodiments, each inductor unit 204/206 may be disposed on a separate portion of the first magnetic layer 214, as shown in FIG. 4B. In other embodiments, the first magnetic layer 214 extends continuously under the first inductor unit 204 and the second inductor unit 206, as shown in view 400C of FIG. 4C.

參考第5A-5C圖至第6A-6C圖，提供了第2A-2C圖中不具有第一磁性層214或第二磁性層236的多端點電感器202的各種實施例的各種視圖。帶有標記“A”(例如，第5A圖)的圖，是指沿著第2A圖的線A-A'截取的第一電感器單元204的一些實施例的截面圖，第一電感器單元204不具有第一磁性層214或第二磁性層214。帶有標記“B”(例如，第5B圖)的圖，是指不具有第一磁性層214或第二磁性層236的多端點電感器202的第一電感器單元204的俯視圖。帶有標記“C”的圖(例如，第5C圖)，是指不具有第一磁性層214或第二磁性層236的第2A-2C圖的多端點電感器202的一些實施例的俯視圖。With reference to FIGS. 5A-5C through 6A-6C, various views of various embodiments of the multi-terminal inductor 202 without the first magnetic layer 214 or the second magnetic layer 236 in FIGS. 2A-2C are provided. The figure marked with "A" (for example, FIG. 5A) refers to a cross-sectional view of some embodiments of the first inductor unit 204 taken along the line AA' of FIG. 2A, the first inductor unit 204 does not have the first magnetic layer 214 or the second magnetic layer 214. The diagram marked with “B” (for example, FIG. 5B) refers to a top view of the first inductor unit 204 of the multi-terminal inductor 202 without the first magnetic layer 214 or the second magnetic layer 236. The diagram marked with “C” (for example, FIG. 5C) refers to a top view of some embodiments of the multi-terminal inductor 202 of FIGS. 2A-2C without the first magnetic layer 214 or the second magnetic layer 236.

如第5A-5C圖的視圖500A-500C所示，第一電感單元204不包括第一磁性層214或第二磁性層236。相反地，第一導線216與第二導線218僅藉由阻擋層222與鈍化層212分離。雖然電感器單元204不包括第一磁性層214或第二磁性層236，但是當電流流過它們各自的導線216/218/316/320時，每個電感器單元204/206具有可測量的電感。因為每個電感器單元204/206包括第一導線216/316及第二導線218/320，所以第一電感器單元204與第二電感器單元206可以透過PCB(圖未繪示)的導電佈線118，以雙電流配置或單電流配置連接。在其他實施例中，如第6A-6C圖的視圖600A-600C所示，電感器單元204/206可以僅包括單一導線216/316，導線216/316從第一I/O接合結構224/308連續延伸到第二I/O接合結構226/310。As shown in views 500A-500C of FIGS. 5A-5C, the first inductance unit 204 does not include the first magnetic layer 214 or the second magnetic layer 236. On the contrary, the first wire 216 and the second wire 218 are separated from the passivation layer 212 only by the barrier layer 222. Although the inductor unit 204 does not include the first magnetic layer 214 or the second magnetic layer 236, each inductor unit 204/206 has a measurable inductance when current flows through their respective wires 216/218/316/320 . Since each inductor unit 204/206 includes a first wire 216/316 and a second wire 218/320, the first inductor unit 204 and the second inductor unit 206 can pass through the conductive wiring of the PCB (not shown) 118, connected in dual current configuration or single current configuration. In other embodiments, as shown in views 600A-600C of FIGS. 6A-6C, the inductor unit 204/206 may include only a single wire 216/316, the wire 216/316 from the first I/O bonding structure 224/308 Continuously extends to the second I/O junction structure 226/310.

參考第7A-7E圖，提供了多端點電感器202的一些實施例的各種視圖700A-700E。第7A圖示出了多端點電感器202的一些實施例的簡化俯視圖700A。第7B圖示出了第7A圖的多端點電感器202的第一電感器單元204一些實施例的透視圖700B，其從第7A圖的線A-A'投影到第一電感器單元204的一側。第7C圖示出了第2A圖的多端點電感器202的第一電感器單元204的一些實施例的橫截面圖700C，其沿著第7A圖的線C-C'截取。第7D圖示出了第7A圖的多端點電感器202的第一電感器單元204一些實施例的橫截面圖700D，其沿著圖7B的線A-A'截取。第7E圖示出了第7A-7D圖的多端點電感器202的第一電感器單元204的一些實施例的簡化俯視圖700E。第7A及7E圖是“簡化的”，因為第7B-7D圖中所描繪的幾個層及特徵沒有被示出，例如，未示出第二介電層238。Referring to FIGS. 7A-7E, various views 700A-700E of some embodiments of the multi-terminal inductor 202 are provided. FIG. 7A shows a simplified top view 700A of some embodiments of multi-terminal inductor 202. FIG. 7B shows a perspective view 700B of some embodiments of the first inductor unit 204 of the multi-terminal inductor 202 of FIG. 7A, which is projected from the line AA′ of FIG. 7A to the first inductor unit 204. Side. FIG. 7C shows a cross-sectional view 700C of some embodiments of the first inductor unit 204 of the multi-terminal inductor 202 of FIG. 2A, which is taken along the line CC′ of FIG. 7A. FIG. 7D shows a cross-sectional view 700D of some embodiments of the first inductor unit 204 of the multi-terminal inductor 202 of FIG. 7A, which is taken along line AA′ of FIG. 7B. FIG. 7E shows a simplified top view 700E of some embodiments of the first inductor unit 204 of the multi-terminal inductor 202 of FIGS. 7A-7D. FIGS. 7A and 7E are “simplified” because several layers and features depicted in FIGS. 7B-7D are not shown, for example, the second dielectric layer 238 is not shown.

如第7A-7E圖的視圖700A-700E所示，第一電感器單元204包括設置在第一導線216上方的第二導線702。在一些實施例中，通孔704將第二導線702連接到第一導線216，使得第一導線216及第二導線702以圍繞第一磁性層214的一螺旋圖案，從第一I/O接合結構224連續地延伸到第二I/O接合結構226。第二導線702及通孔704可以藉由例如CVD、PVD、ALD、濺射、電化學電鍍、無電電鍍或其他沉積或生長製程等，來沉積或生長。通孔704可以藉由例如單金屬鑲嵌類製程(single damascene like process)或雙金屬鑲嵌製程(dual damascene process)來形成。As shown in views 700A-700E of FIGS. 7A-7E, the first inductor unit 204 includes a second wire 702 disposed above the first wire 216. In some embodiments, the via 704 connects the second wire 702 to the first wire 216 so that the first wire 216 and the second wire 702 are bonded from the first I/O in a spiral pattern surrounding the first magnetic layer 214 The structure 224 continuously extends to the second I/O junction structure 226. The second wire 702 and the through hole 704 can be deposited or grown by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, or other deposition or growth processes. The through hole 704 may be formed by, for example, a single damascene like process or a dual damascene process.

第二導線702及通孔704包括導電材料，例如銅(Cu)、鋁(Al)、金(Au)、銀(Ag)、Al-Cu化合物或其他合適的導電材料。在一些實施例中，第二導線702可以是後鈍化銅互連。在一些實施例中，第二導線702具有範圍從約0.5μm至約50μm的厚度，及/或範圍從約0.5μm至約50μm的寬度。 更具體地，第二導線702可以具有範圍從0.5μm至5μm、5μm至10μm、10μm至15μm、15μm至20μm、20μm至25μm、25μm至30μm、30μm至40μm或40μm至50μm的厚度/寬度。The second wire 702 and the through hole 704 include conductive materials, such as copper (Cu), aluminum (Al), gold (Au), silver (Ag), Al-Cu compound, or other suitable conductive materials. In some embodiments, the second wire 702 may be a post-passivated copper interconnect. In some embodiments, the second wire 702 has a thickness ranging from about 0.5 μm to about 50 μm, and/or a width ranging from about 0.5 μm to about 50 μm. More specifically, the second wire 702 may have a thickness/width ranging from 0.5 μm to 5 μm, 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, 20 μm to 25 μm, 25 μm to 30 μm, 30 μm to 40 μm, or 40 μm to 50 μm.

第三隔離層706將第一磁性層214與第一介電層234分隔開。在一些實施例中，通孔704延伸穿過第三隔離層706，以將第二導線702連接至第一導線216。第三隔離層706包括介電材料，例如SiO 2、Si 3N 4、低k介電質或其他合適的介電質材料。第三隔離層706可以藉由例如CVD、PVD、ALD、濺射或其他沉積或生長製程等來沉積或生長。 The third isolation layer 706 separates the first magnetic layer 214 from the first dielectric layer 234. In some embodiments, the via 704 extends through the third isolation layer 706 to connect the second wire 702 to the first wire 216. The third isolation layer 706 includes a dielectric material, such as SiO 2 , Si 3 N 4 , low-k dielectric or other suitable dielectric materials. The third isolation layer 706 can be deposited or grown by, for example, CVD, PVD, ALD, sputtering, or other deposition or growth processes.

第三介電層708設置在第二介電層238上。在一些實施例中，第三介電層708在第二導線702的側壁之間延伸並接觸第二介電層238的上表面。更進一步地，第三介電層708可以具有實質上平坦的上表面。在一些實施例中，第三介電層708可以是，例如聚醯亞胺化合物、聚苯并噁唑化合物及/或任何其他合適的介電材料。第三介電層708可以藉由例如CVD、PVD、ALD、濺射、旋塗工藝或其他沉積或生長製程等來沉積或生長。The third dielectric layer 708 is disposed on the second dielectric layer 238. In some embodiments, the third dielectric layer 708 extends between the sidewalls of the second wire 702 and contacts the upper surface of the second dielectric layer 238. Still further, the third dielectric layer 708 may have a substantially flat upper surface. In some embodiments, the third dielectric layer 708 may be, for example, a polyimide compound, a polybenzoxazole compound, and/or any other suitable dielectric material. The third dielectric layer 708 can be deposited or grown by, for example, CVD, PVD, ALD, sputtering, spin coating process, or other deposition or growth processes.

參考第8圖，提供了第7A-7E圖的多端點電感器202的第一電感器單元204之一些實施例的簡化俯視圖800。第8圖是“簡化的”，因為第8圖僅示出了第二導線702，以圍繞第一磁性層214的一螺旋圖案連續地延伸。Referring to FIG. 8, a simplified top view 800 of some embodiments of the first inductor unit 204 of the multi-terminal inductor 202 of FIGS. 7A-7E is provided. FIG. 8 is “simplified” because FIG. 8 shows only the second conductive wire 702 continuously extending in a spiral pattern around the first magnetic layer 214.

如第8圖的視圖800所示，在一些實施例中，第一電感器單元204可以包括第三I/O接合結構802及第四I/O接合結構804，其設置在第一I/O接合結構224以及第二I/O接合結構226之間。因此，I/O接合結構224/226/802/804可以以各種組合連接，使得第一電感器單元204可以被配置為具有各種電感。據此，因為多端點電感器202具有多個電感器單元204/206，所以多端點電感器單元202向客戶(或製造商)提供了更多的電感選項，而不需要特定應用的電感器設計，後者可能導致製造成本的增加或低效的運作條件。As shown in view 800 of FIG. 8, in some embodiments, the first inductor unit 204 may include a third I/O junction structure 802 and a fourth I/O junction structure 804, which are disposed at the first I/O Between the junction structure 224 and the second I/O junction structure 226. Therefore, the I/O junction structures 224/226/802/804 may be connected in various combinations, so that the first inductor unit 204 may be configured to have various inductances. Accordingly, because the multi-terminal inductor 202 has multiple inductor units 204/206, the multi-terminal inductor unit 202 provides customers (or manufacturers) with more inductance options without requiring application-specific inductor design The latter may lead to increased manufacturing costs or inefficient operating conditions.

參考第9圖，提供了第7A-7E圖的多端點電感器202的第一電感器單元204一些實施例的簡化俯視圖900。第9圖是“簡化的”，因為第9圖僅示出了第一導線216、圍繞第一磁性層214以螺旋圖案連續延伸的第二導線702，以及圍繞第一磁性層214以螺旋圖案連續延伸的第三導線902。Referring to FIG. 9, a simplified top view 900 of some embodiments of the first inductor unit 204 of the multi-terminal inductor 202 of FIGS. 7A-7E is provided. FIG. 9 is “simplified” because FIG. 9 shows only the first conductive wire 216, the second conductive wire 702 continuously extending in a spiral pattern around the first magnetic layer 214, and continuous in a spiral pattern around the first magnetic layer 214 Extended third wire 902.

如第9圖的視圖900所示，在一些實施例中，第一電感器單元204可以包括第三導線902。第三導線902從第三導線902的第一I/O接合結構904連接到第三導線902的第二I/O接合結構906。在一些實施例中，第三導線902的第三I/O接合結構908設置在第三導線902的第一I/O接合結構904與第三導線902的第二I/O接合結構906之間。在一些實施例中，通孔(圖未繪示)將第三導線902連接到第四導線(圖未繪示)，使得第三導線902及第四導線(圖未繪示)，以螺旋狀從第三導線902的第一I/O接合結構904，連續延伸至第三導線902的第二I/O接合結構906。第一導線216及第二導線702的螺旋圖案與第三導線902及第四導線(圖未繪示)的螺旋圖案相交，但每個螺旋圖案被配置為沿著它們各自的導線216/702/902傳送一離散(discrete)的信號。As shown in view 900 of FIG. 9, in some embodiments, the first inductor unit 204 may include a third wire 902. The third wire 902 is connected from the first I/O bonding structure 904 of the third wire 902 to the second I/O bonding structure 906 of the third wire 902. In some embodiments, the third I/O bonding structure 908 of the third wire 902 is disposed between the first I/O bonding structure 904 of the third wire 902 and the second I/O bonding structure 906 of the third wire 902 . In some embodiments, the through hole (not shown) connects the third wire 902 to the fourth wire (not shown), so that the third wire 902 and the fourth wire (not shown) are spiral From the first I/O bonding structure 904 of the third wire 902, it continuously extends to the second I/O bonding structure 906 of the third wire 902. The spiral patterns of the first wire 216 and the second wire 702 intersect the spiral patterns of the third wire 902 and the fourth wire (not shown), but each spiral pattern is configured to be along their respective wires 216/702/ 902 transmits a discrete signal.

參考第10A-10C圖，提供了第7A-7E圖的多端點電感器202的實施例的各種視圖1000A-1000C，多端點電感器202不具有第一磁性層214。第10A圖是第一電感器單元204之一些實施例沿著第7A圖線A-A'所截取的截面圖1000A，第一電感器單元204不具有第一磁性層214。第10B圖是第7A-7E圖的多端點電感器202的第一電感器單元204之一些實施例的簡化俯視圖1000B，第一電感器單元204不具有第一磁性層214。第10C圖是第7A-7E圖的多端點電感器202的第一電感器單元204之一些其他實施例的簡化俯視圖1000C，第一電感器單元204不具有第一磁性層214。第10B-10C圖是“簡化的”，因為第10B-10C圖僅示出了以螺旋圖案連續延伸的第一導線216及第二導線702。10A-10C, various views 1000A-1000C of the embodiment of the multi-terminal inductor 202 of FIGS. 7A-7E are provided, and the multi-terminal inductor 202 does not have the first magnetic layer 214. FIG. 10A is a cross-sectional view 1000A of some embodiments of the first inductor unit 204 taken along line AA′ of FIG. 7A. The first inductor unit 204 does not have the first magnetic layer 214. FIG. 10B is a simplified top view 1000B of some embodiments of the first inductor unit 204 of the multi-terminal inductor 202 of FIGS. 7A-7E. The first inductor unit 204 does not have the first magnetic layer 214. FIG. 10C is a simplified top view 1000C of some other embodiments of the first inductor unit 204 of the multi-terminal inductor 202 of FIGS. 7A-7E. The first inductor unit 204 does not have the first magnetic layer 214. FIGS. 10B-10C are “simplified” because FIGS. 10B-10C only show the first conductive wire 216 and the second conductive wire 702 that continuously extend in a spiral pattern.

如第10A-10C圖的視圖1000A-1000C所示，第一電感單元204不包括第一磁性層214。相反地，第一導線216及第二導線702透過通孔(圖未繪示)連接，使得第一導線216及第二導線702以螺旋圖案連續地延伸。在一些實施例中，第一導線216及第二導線702圍繞介電材料(圖未繪示)以螺旋圖案連續地延伸。在一些實施例中，介電層可以包括多個層，或者可以是單塊(single bulk)的介電材料，例如聚醯亞胺化合物、聚苯并噁唑化合物及/或任何其他合適的介電材料。As shown in views 1000A-1000C of FIGS. 10A-10C, the first inductance unit 204 does not include the first magnetic layer 214. On the contrary, the first wire 216 and the second wire 702 are connected through a through hole (not shown), so that the first wire 216 and the second wire 702 continuously extend in a spiral pattern. In some embodiments, the first wire 216 and the second wire 702 continuously extend in a spiral pattern around the dielectric material (not shown). In some embodiments, the dielectric layer may include multiple layers, or may be a single bulk dielectric material, such as polyimide compound, polybenzoxazole compound, and/or any other suitable dielectric Electrical materials.

參考第11-17圖，提供了本發明實施例中用於形成多端點電感器單元202的電感器單元204/206的方法的一系列視圖1100-1700。Referring to FIGS. 11-17, a series of views 1100-1700 of a method for forming the inductor unit 204/206 of the multi-terminal inductor unit 202 in an embodiment of the present invention is provided.

如第11圖的視圖1100所示，提供一半導體基底208。半導體基底208可以包括任何類型的半導體本體(例如，單晶矽/CMOS基體、矽鍺(SiGe)、絕緣體上的矽(SOI)等)。在一些實施例中，半導體裝置形成在半導體基底208內/上方。舉例而言，半導體裝置可以是電晶體，電晶體包括設置在半導體基底208上方以及源極與汲極之間的閘極堆疊(例如，佈置在高k介電質上方的金屬閘極)，而源極及汲極設置在半導體基底208內。As shown in view 1100 of FIG. 11, a semiconductor substrate 208 is provided. The semiconductor substrate 208 may include any type of semiconductor body (eg, single crystal silicon/CMOS substrate, silicon germanium (SiGe), silicon on insulator (SOI), etc.). In some embodiments, the semiconductor device is formed in/over the semiconductor substrate 208. For example, the semiconductor device may be a transistor, which includes a gate stack disposed above the semiconductor substrate 208 and between the source and the drain (eg, a metal gate disposed above a high-k dielectric), and The source electrode and the drain electrode are disposed in the semiconductor substrate 208.

在一些實施例中，用於形成半導體裝置的製程包括，在半導體基底208上形成圖案化的光阻層(photoresist layer)(圖未繪示)，圖案化的光阻層可以透過例如旋塗製程來形成。圖案化的光阻層可以圖案化成具有複數源極/汲極的佈局，也可以使用例如光微影(photolithography)來圖案化。在一些實施例中，用於形成半導體裝置的源極/汲極的製程包括使用圖案化的光阻定位來執行離子佈植(ion implantation)，隨後剝離圖案化的光阻。此外，在一些實施例中，閘極可以透過例如使用圖案化的光阻(圖未繪示)定位的CVD、PVD、ALD、濺射、旋塗製程或其他沉積或生長製程來形成，並且隨後剝離圖案化的光阻。In some embodiments, the process for forming a semiconductor device includes forming a patterned photoresist layer (not shown) on the semiconductor substrate 208. The patterned photoresist layer may pass through a spin coating process, for example To form. The patterned photoresist layer may be patterned into a layout having a plurality of source/drain electrodes, or may be patterned using, for example, photolithography. In some embodiments, the process for forming the source/drain of the semiconductor device includes using patterned photoresist positioning to perform ion implantation, and then stripping the patterned photoresist. In addition, in some embodiments, the gate may be formed by, for example, CVD, PVD, ALD, sputtering, spin coating, or other deposition or growth processes positioned using a patterned photoresist (not shown), and then Strip the patterned photoresist.

如第12圖的視圖1200所示，互連結構210形成在半導體基底208之上並與其直接接觸。互連結構210包括多個導電特徵部件，例如金屬互連線、通孔、及/或互連半導體裝置的接觸墊。在一些實施例中，複數導電特徵部件形成在複數金屬層中，該等金屬層形成在彼此之上。在一些實施例中，導電特徵部件可以透過光微影製程及可應用的沉積或生長製程的組合來形成，例如電化學電鍍、無電電鍍、化學或物理氣相沉積、濺射或一些其他沉積或生長製程等。該製程可以是，例如類單鑲嵌製程或類雙鑲嵌製程的一部分。在一些實施例中，化學機械拋光(chemical mechanical polishing，CMP)製程可以在形成每個金屬層之後執行，以形成實質上平坦的上表面。As shown in view 1200 of FIG. 12, the interconnect structure 210 is formed on and directly in contact with the semiconductor substrate 208. The interconnect structure 210 includes a plurality of conductive features, such as metal interconnect lines, vias, and/or contact pads that interconnect semiconductor devices. In some embodiments, a plurality of conductive features are formed in a plurality of metal layers, the metal layers are formed on each other. In some embodiments, the conductive features can be formed by a combination of photolithography processes and applicable deposition or growth processes, such as electrochemical plating, electroless plating, chemical or physical vapor deposition, sputtering, or some other deposition or Growth process, etc. The process may be, for example, part of a single-mosaic-like process or a double-mosaic-like process. In some embodiments, a chemical mechanical polishing (CMP) process may be performed after forming each metal layer to form a substantially flat upper surface.

如第13圖的視圖1300所示，鈍化層212形成在互連結構210上並與之直接接觸。鈍化層212可以包括介電材料，例如SiO 2、氮化矽Si 3N 4)、聚酰亞胺化合物或其他合適的材料。鈍化層212可以藉由，例如光微影及可應用的沉積或生長製程的組合來形成，例如CVD、PVD、濺射、旋塗製程或一些其他沉積或生長製程。在一些實施例中，CMP製程可以在鈍化層212被沉積之後執行，以形成實質上平坦的上表面。 As shown in view 1300 of FIG. 13, a passivation layer 212 is formed on and directly in contact with the interconnect structure 210. The passivation layer 212 may include a dielectric material, such as SiO 2 , silicon nitride (Si 3 N 4 ), polyimide compound, or other suitable materials. The passivation layer 212 may be formed by, for example, a combination of photolithography and applicable deposition or growth processes, such as CVD, PVD, sputtering, spin coating processes, or some other deposition or growth processes. In some embodiments, the CMP process may be performed after the passivation layer 212 is deposited to form a substantially flat upper surface.

如第14圖的視圖1400所示，阻擋層222形成在鈍化層212之上並與其直接接觸。在一些實施例中，阻擋層222包括鉭(Ta)、氮化鉭(TaN)、鈦(Ti)、氮化鈦(TiN)及/或鎢(W)等。阻擋層222可以藉由CVD、PVD、ALD、濺射、電化學電鍍、無電電鍍或其他沉積或生長製程等來沉積或生長。在一些實施例中，阻擋層222地順應性形成於鈍化層212之上。儘管未在第14圖的視圖1600中示出，但是應該理解，導線216/218從其生長的晶種層形成在阻擋層222上。晶種層包括Cu、Cu合金、Al、Al合金、Au、Ag、Al-Cu化合物或其他合適的材料，並且當導線216/218從晶種層生長時可以合併到導線216/218中。晶種層可以藉由CVD、PVD、ALD、濺射、電化學電鍍、無電電鍍或其他沉積或生長製程等來沉積或生長。As shown in view 1400 of FIG. 14, the barrier layer 222 is formed on and directly in contact with the passivation layer 212. In some embodiments, the barrier layer 222 includes tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), and/or tungsten (W), and the like. The barrier layer 222 may be deposited or grown by CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, or other deposition or growth processes. In some embodiments, the compliance of the barrier layer 222 is formed on the passivation layer 212. Although not shown in view 1600 of FIG. 14, it should be understood that a seed layer from which the wires 216/218 are grown is formed on the barrier layer 222. The seed layer includes Cu, Cu alloy, Al, Al alloy, Au, Ag, Al-Cu compound, or other suitable materials, and may be incorporated into the wire 216/218 when the wire 216/218 grows from the seed layer. The seed layer can be deposited or grown by CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, or other deposition or growth processes.

如第15圖的視圖1500所示，使用圖案化的光阻層1502來形成第一導線216及第二導線218，第一導線216及第二導線218形成在阻擋層222之上並與阻擋層222直接接觸。圖案化的光阻層1502藉由例如旋塗製程結合隨後的光微影製程，形成在阻擋層222上方，以在圖案化的光阻層1502中定義出開口(openings)。第一導線216和第二導線218可以藉由例如CVD、PVD、ALD、濺射、電化學電鍍、無電電鍍或一些其他沉積或生長製程來沉積或生長。在進一步的實施例中，第一導線216和第二導線218可以包括Cu、Al、Au、Ag、Al-Cu化合物或任何其它合適的導電材料。As shown in view 1500 of FIG. 15, the patterned photoresist layer 1502 is used to form the first conductive line 216 and the second conductive line 218, the first conductive line 216 and the second conductive line 218 are formed on the barrier layer 222 and are 222 direct contact. The patterned photoresist layer 1502 is formed above the barrier layer 222 by, for example, a spin coating process in combination with a subsequent photolithography process to define openings in the patterned photoresist layer 1502. The first wire 216 and the second wire 218 may be deposited or grown by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, or some other deposition or growth process. In further embodiments, the first wire 216 and the second wire 218 may include Cu, Al, Au, Ag, Al-Cu compound, or any other suitable conductive material.

隨後，藉由例如濕蝕刻或乾蝕刻製程，從阻擋層222剝離圖案化的光阻層1502。在一些實施例中，剝離圖案化的光阻層1502的步驟還去除了未被導線216/218覆蓋的一部分阻擋層222。在其他實施例中，可以執行後續的蝕刻和光微影製程，以去除未被導線216/218覆蓋的一部分阻擋層222分。Subsequently, the patterned photoresist layer 1502 is stripped from the barrier layer 222 by, for example, a wet etching or dry etching process. In some embodiments, the step of stripping the patterned photoresist layer 1502 also removes a portion of the barrier layer 222 that is not covered by the wires 216/218. In other embodiments, subsequent etching and photolithography processes may be performed to remove a portion of the barrier layer 222 that is not covered by the wires 216/218.

如第16圖的視圖1600所示，第二隔離層232形成在第一導線216及第二導線218上方。在一些實施例中，第二隔離層順應性地形成於鈍化層212、第一磁性層214、第一導線216以及第二導線218上，並且與鈍化層212、第一導線216以及第二導線218直接接觸。第二隔離層232包括介電材料，例如SiO 2、Si 3N 4、低k介電質或一些其他合適的介電材料。第二隔離層232可以藉由，例如CVD、PVD、ALD、濺射或一些其他沉積或生長製程來沉積或生長。 As shown in view 1600 of FIG. 16, the second isolation layer 232 is formed above the first conductive line 216 and the second conductive line 218. In some embodiments, the second isolation layer is compliantly formed on the passivation layer 212, the first magnetic layer 214, the first wire 216, and the second wire 218, and is in contact with the passivation layer 212, the first wire 216, and the second wire 218 direct contact. The second isolation layer 232 includes a dielectric material, such as SiO 2 , Si 3 N 4 , low-k dielectric, or some other suitable dielectric material. The second isolation layer 232 may be deposited or grown by, for example, CVD, PVD, ALD, sputtering, or some other deposition or growth process.

如第17圖的視圖1700所示，第一介電層234形成在第二隔離層232之上並與其直接接觸。第一介電層234可以例如是聚醯亞胺化合物、聚苯并噁唑化合物或任何其他合適的介電材料。第一介電層234可以藉由例如，CVD、PVD、ALD、濺射、旋塗製程或一些其他沉積或生長製程來沉積或生長。在一些實施例中，CMP製程可以在第一介電層234被沉積之後執行，以形成實質上平坦的上表面。As shown in view 1700 of FIG. 17, the first dielectric layer 234 is formed on and directly in contact with the second isolation layer 232. The first dielectric layer 234 may be, for example, a polyimide compound, a polybenzoxazole compound, or any other suitable dielectric material. The first dielectric layer 234 may be deposited or grown by, for example, CVD, PVD, ALD, sputtering, spin coating process, or some other deposition or growth process. In some embodiments, the CMP process may be performed after the first dielectric layer 234 is deposited to form a substantially flat upper surface.

儘管在沿A-A'截取的橫截面圖1100至1700中示出，但應可理解的是，形成延伸穿過第一介電層234及第二介電層238的I/O接合結構224/226/228/230，以提供至導線216/218的連接。舉例而言，I/O接合結構224/226/228/230可以包括設置在第二介電層238上的接合墊(bond pad)。I/O接合結構從接合墊延伸穿過第二介電層238及第一介電層234至它們各自的導線216/218。在一些實施例中，I/O接合結構224/226/228/230包括Cu、Cu合金、Al、Al合金、Au、Ag、Al-Cu化合物或其他合適的材料。I/O接合結構224/226/228/230可以藉由，例如CVD、PVD、ALD、濺射、電化學電鍍、無電電鍍或其他一些沉積或生長製程來形成。Although shown in the cross-sectional views 1100 to 1700 taken along AA′, it should be understood that the I/O bonding structure 224 extending through the first dielectric layer 234 and the second dielectric layer 238 is formed /226/228/230 to provide connection to wires 216/218. For example, the I/O bonding structure 224/226/228/230 may include a bond pad disposed on the second dielectric layer 238. The I/O bonding structure extends from the bonding pad through the second dielectric layer 238 and the first dielectric layer 234 to their respective wires 216/218. In some embodiments, the I/O bonding structure 224/226/228/230 includes Cu, Cu alloy, Al, Al alloy, Au, Ag, Al-Cu compound, or other suitable materials. The I/O bonding structure 224/226/228/230 can be formed by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, or some other deposition or growth process.

此外，雖然第11-17圖示出了用於形成第5A-5C圖中描繪實施例的製程，但是應該理解，普通技術人員可以實現上述步驟(或基本上類似的步驟)，以形成在第2A-2C圖、第3A-3C圖、第4A-4C圖、第6A-6C圖、第7A-7E圖、第8圖、第9圖及第10A-10C圖中描繪的實施例。In addition, although FIGS. 11-17 illustrate the process for forming the embodiment depicted in FIGS. 5A-5C, it should be understood that a person of ordinary skill can implement the above steps (or substantially similar steps) to form The embodiments depicted in Figures 2A-2C, 3A-3C, 4A-4C, 6A-6C, 7A-7E, 8th, 9th, and 10A-10C.

參考第18圖，提供了用於形成多端點電感器一些實施例的方法流程圖1800，並選擇性地設置多端點電感器的電感。儘管本文示出及/或描述的揭露的方法和其他方法，可以在本文中被圖式及/或描述為一系列操作或事件，但是應該理解，這些示出的這種操作或事件的排序不應被解釋為限定作用。舉例而言，一些操作可以以不同的順序發生及/或與除本文所示及/或描述的那些以外的其他操作或事件同時發生。此外，並非所有示出的操作都可能需要被實現本文描述的一或多個態樣或實施例，並且本文所描繪的一或多個操作可以在一或多個單獨的操作及/或階段中執行。Referring to FIG. 18, a method flowchart 1800 of some embodiments for forming a multi-terminal inductor is provided, and the inductance of the multi-terminal inductor is selectively set. Although the disclosed methods and other methods shown and/or described herein may be illustrated and/or described herein as a series of operations or events, it should be understood that the order of such operations or events shown is not Should be interpreted as limiting. For example, some operations may occur in a different order and/or simultaneously with other operations or events other than those shown and/or described herein. In addition, not all operations shown may need to be implemented in one or more aspects or embodiments described herein, and one or more operations described herein may be in one or more separate operations and/or stages carried out.

在步驟1802，在半導體基底上形成互連結構，其中互連結構具有複數金屬層。關於操作1802的示例可以如先前的第12圖所示。In step 1802, an interconnect structure is formed on the semiconductor substrate, wherein the interconnect structure has a plurality of metal layers. An example of operation 1802 may be as shown in the previous FIG. 12.

在步驟1804，在互連結構上形成鈍化層。關於操作1804的示例可以如先前的第13圖所示。In step 1804, a passivation layer is formed on the interconnect structure. An example of operation 1804 may be as shown in the previous FIG. 13.

在步驟1806，在鈍化層上形成阻擋層。關於操作1806的示例可以如先前的第14圖所示。At step 1806, a barrier layer is formed on the passivation layer. An example of operation 1806 may be as shown in the previous FIG. 14.

在步驟1808，在阻擋層上形成第一導線和第二導線。關於操作1808的示例可以如先前的第15圖所示。At step 1808, a first wire and a second wire are formed on the barrier layer. An example of operation 1808 may be as shown in the previous FIG. 15.

在步驟1810，在第一導線和第二導線上形成隔離層。關於操作1810的示例可以如先前的第16圖所示。In step 1810, an isolation layer is formed on the first wire and the second wire. An example of operation 1810 may be as shown in the previous FIG. 16.

在步驟1812，在隔離層上形成介電層。關於操作1812的示例可以如先前的第17圖所示。At step 1812, a dielectric layer is formed on the isolation layer. An example of operation 1812 may be as shown in the previous FIG. 17.

在步驟1814，在第一位置及第二位置分別形成第一輸入/輸出(I/O)接合結構及第二I/O接合結構。第一位置及第二位置是分開的。第一I/O接合結構延伸介電層，以在第一位置接觸第一導線。第二I/O接合結構延伸穿過介電層，以在第二位置接觸第一導線。在一些實施例中，第一I/O接合結構及第二I/O接合結構包括Cu、Cu合金、Al、Al合金、Au、Ag、Al-Cu化合物或其他合適的材料。第一I/O接合結構及第二I/O接合結構可以藉由，例如CVD、PVD、ALD、濺射、電化學電鍍、無電電鍍或一些其他沉積或生長製程來形成。關於第一I/O接合結構及第二I/O接合結構接觸第一導線的示例，可以如先前的第4A-4C圖所示。At step 1814, a first input/output (I/O) junction structure and a second I/O junction structure are formed at the first position and the second position, respectively. The first position and the second position are separated. The first I/O bonding structure extends the dielectric layer to contact the first wire at the first location. The second I/O bonding structure extends through the dielectric layer to contact the first wire at the second location. In some embodiments, the first I/O junction structure and the second I/O junction structure include Cu, Cu alloy, Al, Al alloy, Au, Ag, Al-Cu compound, or other suitable materials. The first I/O junction structure and the second I/O junction structure may be formed by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, or some other deposition or growth process. The example in which the first I/O bonding structure and the second I/O bonding structure contact the first wire may be as shown in the previous FIGS. 4A-4C.

在步驟1816，在第三位置及第四位置分別形成第三I/O接合結構及第四I/O接合結構。第三位置及第四位置是分開的。第三I/O接合結構延伸穿過介電層，以在第三位置接觸第二導線。第四I/O接合結構延伸穿過介電層，以在第四位置接觸第二導線。在一些實施例中，第三I/O接合結構及第四I/O接合結構包括Cu、Cu合金、Al、Al合金、Au、Ag、Al-Cu化合物或其他合適的材料。第三I/O接合結構及第四I/O接合結構可以藉由，例如CVD、PVD、ALD、濺射、電化學電鍍、無電電鍍或一些其他沉積或生長製程來形成。關於第三I/O接合結構及第四I/O接合結構接觸第二導線的示例，可以如先前的第4A-4C圖所示。At step 1816, a third I/O junction structure and a fourth I/O junction structure are formed at the third position and the fourth position, respectively. The third position and the fourth position are separated. The third I/O bonding structure extends through the dielectric layer to contact the second wire at the third position. The fourth I/O bonding structure extends through the dielectric layer to contact the second wire at the fourth position. In some embodiments, the third I/O junction structure and the fourth I/O junction structure include Cu, Cu alloy, Al, Al alloy, Au, Ag, Al-Cu compound, or other suitable materials. The third I/O junction structure and the fourth I/O junction structure may be formed by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, or some other deposition or growth process. The example in which the third I/O bonding structure and the fourth I/O bonding structure contact the second wire may be as shown in the previous FIGS. 4A-4C.

在步驟1818，具有導電佈線的印刷電路板(PCB)選擇性地連接到I/O接合結構。連接PCB以允許電流流過第一I/O接合結構並從第二I/O接合結構流出到外部裝置，從而將多端點電感器設置為具有第一電感。替代地，連接PCB以允許電流流過第一I/O接合結構、第二I/O接合結構、第三I/O接合結構，並且從第四I/O接合結構流出到外部裝置，從而將多端點電感設置為具有與第一電感不同的第二電感。在一些實施例中，第二電感大於第一電感。關於I/O接合結構之間的替代連接的例子的示例，可以如先前的第1A-1B圖所示。At step 1818, a printed circuit board (PCB) with conductive wiring is selectively connected to the I/O junction structure. The PCB is connected to allow current to flow through the first I/O junction structure and out of the second I/O junction structure to an external device, thereby setting the multi-terminal inductor to have the first inductance. Alternatively, connect the PCB to allow current to flow through the first I/O junction structure, the second I/O junction structure, and the third I/O junction structure, and flow out from the fourth I/O junction structure to an external device, so that The multi-terminal inductance is set to have a second inductance different from the first inductance. In some embodiments, the second inductance is greater than the first inductance. An example of an alternative connection between I/O junction structures may be as shown in the previous FIGS. 1A-1B.

因此，如上所述，本發明實施例涉及一種多端點電感器，其向客戶(或製造商)提供增加電感的選項，而不需要特定應用的電感器設計。因此，多端點電感器可以改善IC的功能及IC的製造成本。Therefore, as described above, embodiments of the present invention relate to a multi-terminal inductor that provides customers (or manufacturers) with an option to increase inductance without requiring a specific application of inductor design. Therefore, the multi-terminal inductor can improve the function of the IC and the manufacturing cost of the IC.

本發明根據一些實施例提供一種多端點電感器，包括：一半導體基底；一互連結構，設置在半導體基底上，互連結構具有複數金屬層；一第一磁性層，設置在互連結構的一最上表面上；一導線，設置在第一磁性層上；一第一輸入/輸出(I/O)接合(bond)結構，在一第一位置從導線分岔(branch off)；一第二I/O接合結構，在一第二位置從導線分岔，第二位置與第一位置間隔開；以及一第三I/O接合結構，第三I/O接合結構在第一位置與第二位置之間的一第三位置從導電線分岔，其中第三I/O接合結構與第一I/O接合結構之間的一連接具有一第一電感，以及第一I/O接合結構與第二I/O接合結構之間的一替代連接具有一第二電感，第二電感大於第一電感。The present invention provides a multi-terminal inductor according to some embodiments, including: a semiconductor substrate; an interconnect structure provided on the semiconductor substrate, the interconnect structure having a plurality of metal layers; and a first magnetic layer provided on the interconnect structure A top surface; a wire, disposed on the first magnetic layer; a first input/output (I/O) bond structure, branching off the wire at a first position; a second I/O junction structure, bifurcating from the wire at a second position, the second position is spaced from the first position; and a third I/O junction structure, the third I/O junction structure at the first position and the second A third position between the positions diverges from the conductive line, wherein a connection between the third I/O junction structure and the first I/O junction structure has a first inductance, and the first I/O junction structure and An alternative connection between the second I/O junction structures has a second inductance, which is greater than the first inductance.

在一些實施例中，多端點電感器，更包括：一第一介電層，設置在導線上；一第二磁性層，設置在第一介電層上；一第二介電層，設置在第二磁性層上；以及導線沿著一第一方向以實質上一直線從第一I/O接合結構橫向延伸到第二I/O接合結構。In some embodiments, the multi-terminal inductor further includes: a first dielectric layer disposed on the wire; a second magnetic layer disposed on the first dielectric layer; and a second dielectric layer disposed on the On the second magnetic layer; and the wires extend laterally from a first I/O junction structure to a second I/O junction structure in a substantially straight line along a first direction.

在一些實施例中，第二位置在第一方向上與第一磁性層的最外側壁橫向間隔開。In some embodiments, the second position is laterally spaced from the outermost sidewall of the first magnetic layer in the first direction.

在一些實施例中，第一I/O接合結構、第二I/O接合結構及第三I/O接合結構皆從導線延伸穿過第二介電層的一最上表面。In some embodiments, the first I/O bonding structure, the second I/O bonding structure, and the third I/O bonding structure all extend from the wire through an uppermost surface of the second dielectric layer.

在一些實施例中，導線具有在第一磁性層上的一第一上表面，第一上表面位於導線的一第二上表面上。In some embodiments, the wire has a first upper surface on the first magnetic layer, and the first upper surface is located on a second upper surface of the wire.

在一些實施例中，導線以圍繞第一磁性層的一螺旋圖案從第一I/O接合結構連續地延伸到第二I/O接合結構。In some embodiments, the wires continuously extend from the first I/O junction structure to the second I/O junction structure in a spiral pattern surrounding the first magnetic layer.

在一些實施例中，多端點電感器是排列成陣列的複數多端點電感器中的一個，每個多端點電感器彼此間隔開，每個多端點電感器被設置在相同的橫向方向上，並且每個多端點電感器彼此實質上相同。In some embodiments, the multi-terminal inductor is one of a plurality of multi-terminal inductors arranged in an array, each multi-terminal inductor is spaced apart from each other, each multi-terminal inductor is arranged in the same lateral direction, and Each multi-terminal inductor is substantially the same as each other.

本發明亦根據一些其他實施例提供一種多端點電感器，包括：一半導體基底；一互連結構，設置在半導體基底上，互連結構具有複數金屬層；一鈍化層，設置在互連結構的一最上表面上；一磁性層，設置在鈍化層上；複數電感器單元分別包括複數導線，該等電感器單元彼此間隔開並設置在磁性層上，該等電感器單元之一第一電感器單元包括一介電層，介電層在第一電感器單元的一第一導線上延伸，並且第一電感器單元包括一第一端點及一第二端點，其延伸穿過介電層以電性連接到第一電感器單元的第一導線；以及一連接結構，設置在介電層上並具有電性耦接到第一端點及第二端點的導電佈線，連接結構將該等電感器單元中的部分電感器單元彼此電串聯但不是全部的電感器單元。The present invention also provides a multi-terminal inductor according to some other embodiments, including: a semiconductor substrate; an interconnect structure provided on the semiconductor substrate, the interconnect structure having a plurality of metal layers; and a passivation layer provided on the interconnect structure A top surface; a magnetic layer disposed on the passivation layer; the plurality of inductor units includes a plurality of wires, the inductor units are spaced apart from each other and disposed on the magnetic layer, one of the inductor units is a first inductor The unit includes a dielectric layer that extends on a first wire of the first inductor unit, and the first inductor unit includes a first terminal and a second terminal that extend through the dielectric layer A first wire electrically connected to the first inductor unit; and a connection structure provided on the dielectric layer and having conductive wiring electrically coupled to the first terminal and the second terminal Some of the inductor units in the equal inductor units are electrically connected in series with each other but not all of the inductor units.

在一些實施例中，第一端點包括一第一焊料凸塊(solder bump)，第二端點包括一第二焊料凸塊，並且其中連接結構是具有多個導電佈線的印刷電路板(PCB)，導電佈線將該等電感器單元中的兩個或更多個彼此串聯。In some embodiments, the first terminal includes a first solder bump, the second terminal includes a second solder bump, and the connection structure is a printed circuit board (PCB) with a plurality of conductive wiring ), the conductive wiring connects two or more of the inductor units in series with each other.

在一些實施例中，該等電感器單元彼此實質上相同。In some embodiments, the inductor units are substantially the same as each other.

在一些實施例中，第一電感單元更包括：一第三端點，延伸穿過介電層並且電性耦接到第一電感器單元，在第一端點及第二端點之間測量的一第一電感大於在第一端點及第三端點之間測量的一第二電感。In some embodiments, the first inductance unit further includes: a third end point extending through the dielectric layer and electrically coupled to the first inductor unit, measured between the first end point and the second end point A first inductance is greater than a second inductance measured between the first end and the third end.

在一些實施例中，第一導線以實質上一直線從第一端點連續地延伸到第二端點。In some embodiments, the first wire continuously extends from the first end point to the second end point in a substantially straight line.

在一些實施例中，第一電感單元包括與第一導線平行延伸的一第二導線，並且其中一第三端點及一第四端點延伸穿過介電層並且電性耦接到第一電感單元的第二導線。In some embodiments, the first inductance unit includes a second wire extending parallel to the first wire, and a third terminal and a fourth terminal extend through the dielectric layer and are electrically coupled to the first The second wire of the inductance unit.

在一些實施例中，多端點電感器更包括一電路，電路被配置成使一第一電流在一第一方向上通過第一導線，以及在與第一方向相反的一第二方向上使一第二電流通過第二導線。In some embodiments, the multi-terminal inductor further includes a circuit configured to cause a first current to pass through the first wire in a first direction, and to cause a in a second direction opposite to the first direction The second current passes through the second wire.

在一些實施例中，在第一端點及第二端點之間測量的一第一電感實質上等於在第三端點及第四端點之間測量的一第二電感。In some embodiments, a first inductance measured between the first endpoint and the second endpoint is substantially equal to a second inductance measured between the third endpoint and the fourth endpoint.

在一些實施例中，第一導線以圍繞磁性層的一螺旋結構從第一端點連續地延伸到第二端點。In some embodiments, the first wire continuously extends from the first end point to the second end point in a spiral structure surrounding the magnetic layer.

在一些實施例中，第一電感單元更包括：一第三端點，延伸穿過介電層並且電性耦接到第一電感器單元，第一端點位於第一導線的一第一端點，第二端點位於第一導線的一第二端點，以及第三端點位於第一端點與第二端點之間的螺旋結構上的一第一中間位置。In some embodiments, the first inductance unit further includes: a third end point extending through the dielectric layer and electrically coupled to the first inductor unit, the first end point being located at a first end of the first wire Point, the second end point is located at a second end point of the first wire, and the third end point is located at a first intermediate position on the spiral structure between the first end point and the second end point.

在一些實施例中，第一電感單元更包括：一第四端點，延伸穿過介電層並且電性耦接到第一電感器單元，第四端點位於第一端點與第一中間位置之間的螺旋結構上的一第二中間位置。In some embodiments, the first inductance unit further includes: a fourth terminal extending through the dielectric layer and electrically coupled to the first inductor unit, the fourth terminal being located between the first terminal and the first A second intermediate position on the spiral structure between the positions.

在一些實施例中，該等電感器單元包括一第二電感器單元，第二電感器單元與第一電感器單元間隔開，並且設置在磁性層上，第二電感器單元包括與第一導線共線(co-linear)的一第二導線。In some embodiments, the inductor units include a second inductor unit, the second inductor unit is spaced apart from the first inductor unit and is disposed on the magnetic layer, and the second inductor unit includes the first conductor A second wire co-linear.

本發明亦根據一些實施例提供一種多端點電感器形成方法，包括：在一半導體基底上形成具有複數金屬層的一互連結構；在互連結構的一最上表面上形成一鈍化層；在鈍化層上形成一第一磁性層；在第一磁性層上形成彼此間隔開的複數導線；在該等導線上形成一介電層；在介電層上形成複數焊料凸塊，該等焊料凸塊中的不同焊料凸塊電性耦接到不同的導線；以及選擇性地將具有導電佈線的印刷電路板(PCB)連接到等焊料凸塊中的部分焊料凸塊但不是全部。The invention also provides a method for forming a multi-terminal inductor according to some embodiments, including: forming an interconnect structure having a plurality of metal layers on a semiconductor substrate; forming a passivation layer on an uppermost surface of the interconnect structure; Forming a first magnetic layer on the layer; forming a plurality of conductive wires spaced apart from each other on the first magnetic layer; forming a dielectric layer on the wires; forming a plurality of solder bumps on the dielectric layer, the solder bumps The different solder bumps in are electrically coupled to different wires; and selectively connect a printed circuit board (PCB) with conductive wiring to some but not all of the solder bumps in the equal solder bumps.

上述內容概述許多實施例的特徵，因此任何所屬技術領域中具有通常知識者，可更加理解本發明實施例之各面向。任何所屬技術領域中具有通常知識者，可能無困難地以本發明實施例為基礎，設計或修改其他製程及結構，以達到與本發明實施例實施例相同的目的及/或得到相同的優點。任何所屬技術領域中具有通常知識者也應了解，在不脫離本發明實施例之精神和範圍內做不同改變、代替及修改，如此等效的創造並沒有超出本發明實施例的精神及範圍。The above description summarizes the features of many embodiments, so anyone with ordinary knowledge in the technical field can more fully understand the aspects of the embodiments of the present invention. Any person with ordinary knowledge in the technical field may design or modify other processes and structures based on the embodiments of the present invention without difficulty, so as to achieve the same purposes and/or obtain the same advantages as the embodiments of the present invention. Any person with ordinary knowledge in the technical field should also understand that different changes, substitutions, and modifications can be made without departing from the spirit and scope of the embodiments of the present invention. Such an equivalent creation does not exceed the spirit and scope of the embodiments of the present invention.

100A、100B~視圖； 102a、102b~PCB； 104a、104b~多端點電感器； 106a、106b~電感器單元； 108~第一I/O接合結構； 110~第二I/O接合結構； 112~第三I/O接合結構； 114~第四I/O接合結構； 116~導線； 118~導電佈線； 200A、200B、200C~視圖； 202~多端點電感器； 204~第一電感器單元； 206~第二電感器單元； 208~半導體基底； 210~互連結構； 212~鈍化層； 214~第一磁性層； 216~導線； 220~第一隔離層； 222~阻擋層； 224~第一I/O接合結構； 226~第二I/O接合結構； 228~第三I/O接合結構； 230~第四I/O接合結構； 232~第二隔離層； 234~第一介電層； 236~第二磁性層； 238~第二介電層； 300A、300B、300C~視圖； 308~第一I/O接合結構； 310~第二I/O接合結構； 312~第三I/O接合結構； 314~第四I/O接合結構； 316~第一導線； 318~第五I/O接合結構； 320~第二導線； 400A、400B、400C~視圖； 500A、500B、500C~視圖； 600A、600B、600C~視圖； 700A、700B、700C、700D、700E~視圖； 702~第二導線； 704~通孔； 706~第三隔離層； 708~第三介電層； 800~視圖； 802~第三I/O接合結構； 804~第四I/O接合結構； 900~視圖； 902~第三導線； 904~第一I/O接合結構； 906~第二I/O接合結構； 908~第三I/O接合結構； 1000A、1000B、1000C~視圖； 1100、1200、1300、1400、1500、1600、1700~視圖； 1502~圖案化的光阻層； 1800~方法流程圖； 1802、1804、1806、1808、1810、1812、1814、1816、1818~步驟。 100A, 100B~view; 102a, 102b~PCB; 104a, 104b~multi-terminal inductors; 106a, 106b~inductor unit; 108~The first I/O junction structure; 110~Second I/O junction structure; 112~The third I/O junction structure; 114~Fourth I/O junction structure; 116~wire; 118~ conductive wiring; 200A, 200B, 200C~ view; 202~Multi-end inductor; 204~first inductor unit; 206~second inductor unit; 208~Semiconductor substrate; 210~Interconnect structure; 212~passivation layer; 214~ the first magnetic layer; 216~conductor; 220~The first isolation layer; 222~ barrier layer; 224~The first I/O junction structure; 226~Second I/O junction structure; 228~The third I/O junction structure; 230~Fourth I/O junction structure; 232~second isolation layer; 234~ the first dielectric layer; 236~second magnetic layer; 238~second dielectric layer; 300A, 300B, 300C~ view; 308~The first I/O junction structure; 310~Second I/O junction structure; 312~The third I/O junction structure; 314~Fourth I/O junction structure; 316~ the first wire; 318~Fifth I/O junction structure; 320~second wire; 400A, 400B, 400C~ view; 500A, 500B, 500C~view; 600A, 600B, 600C~view; 700A, 700B, 700C, 700D, 700E~view; 702~second wire; 704~through hole; 706~The third isolation layer; 708~ the third dielectric layer; 800~view; 802~The third I/O junction structure; 804~Fourth I/O junction structure; 900~view; 902~ the third wire; 904~ The first I/O junction structure; 906~Second I/O junction structure; 908~ The third I/O junction structure; 1000A, 1000B, 1000C~view; 1100, 1200, 1300, 1400, 1500, 1600, 1700~view; 1502~patterned photoresist layer; 1800~ Flow chart of the method; 1802, 1804, 1806, 1808, 1810, 1812, 1814, 1816, 1818 ~ steps.

以下將配合所附圖式詳述本發明實施例之各面向。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製且僅用以說明例示。事實上，可能任意地放大或縮小元件的尺寸，以清楚地表現出本發明實施例的特徵。 第1A-1B圖示出了多端點電感器的一些實施例的各種俯視圖，多端點電感器具有由印刷電路板以各種不同組合連接的複數電感器單元。 第2A-2C圖示出了多端點電感器的一些實施例的各種視圖。 第3A-3C圖示出了第2A-2C圖的多端點電感器的一些實施例的各種視圖。 第4A-4C圖示出了第2A-2C圖的多端點電感器的一些實施例的各種視圖。 第5A-5C圖及第6A-6C圖示出了第2A-2C圖中，不具有第一磁性層或第二磁性層的多端點電感器的各種實施例的各種視圖。 第7A-7E圖示出了多端點電感器的實施例的各種視圖。 第8圖示出了第7A-7E圖的多端點電感器的第一電感器單元的一些更多實施例的簡化頂視圖。 第9圖示出了第7A-7E圖的多端點電感器的第一電感器單元的一些更多實施例的簡化頂視圖。 第10A-10C圖示出了第7A-7E圖中，不具有第一磁性層的多端點電感器的各種實施例。 第11-17圖示出了形成多端點電感器的方法的一些實施例的一系列視圖。 第18圖示出了形成多端點電感器的方法的一些實施例的流程圖。 The aspects of the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that according to standard practices in the industry, various features are not drawn to scale and are used for illustration only. In fact, the size of the element may be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention. Figures 1A-1B show various top views of some embodiments of multi-terminal inductors having multiple inductor units connected by a printed circuit board in various combinations. Figures 2A-2C show various views of some embodiments of multi-terminal inductors. Figures 3A-3C show various views of some embodiments of the multi-terminal inductor of Figures 2A-2C. Figures 4A-4C show various views of some embodiments of the multi-terminal inductor of Figures 2A-2C. FIGS. 5A-5C and FIGS. 6A-6C show various views of various embodiments of the multi-terminal inductor without the first magnetic layer or the second magnetic layer in FIGS. 2A-2C. Figures 7A-7E show various views of an embodiment of a multi-terminal inductor. Figure 8 shows a simplified top view of some more embodiments of the first inductor unit of the multi-terminal inductor of Figures 7A-7E. Figure 9 shows a simplified top view of some more embodiments of the first inductor unit of the multi-terminal inductor of Figures 7A-7E. FIGS. 10A-10C show various embodiments of the multi-terminal inductor without the first magnetic layer in FIGS. 7A-7E. Figures 11-17 show a series of views of some embodiments of a method of forming a multi-terminal inductor. Figure 18 shows a flowchart of some embodiments of a method of forming a multi-terminal inductor.

100A~視圖； 102a~PCB； 104a~多端點電感器； 106a~電感器單元； 108~第一I/O接合結構； 110~第二I/O接合結構； 116~導線； 118~導電佈線。 100A~view; 102a~PCB; 104a~multi-terminal inductor; 106a~inductor unit; 108~The first I/O junction structure; 110~Second I/O junction structure; 116~wire; 118~ Conductive wiring.

Claims (10)

一種多端點電感器，包括：一半導體基底；一互連結構，設置在該半導體基底上，該互連結構具有複數金屬層；一第一磁性層，設置在該互連結構的一最上表面上；一導線，設置在該第一磁性層上；一第一輸入/輸出(I/O)接合結構，在一第一位置從該導線分岔；一第二I/O接合結構，在一第二位置從該導線分岔，該第二位置與該第一位置間隔開；以及一第三I/O接合結構，該第三I/O接合結構在該第一位置與該第二位置之間的一第三位置從該導電線分岔，其中該第三I/O接合結構與該第一I/O接合結構之間的一連接具有一第一電感，以及該第一I/O接合結構與該第二I/O接合結構之間的一替代連接具有一第二電感，該第二電感大於該第一電感。 A multi-terminal inductor includes: a semiconductor substrate; an interconnection structure provided on the semiconductor substrate, the interconnection structure having a plurality of metal layers; and a first magnetic layer provided on an uppermost surface of the interconnection structure A wire is provided on the first magnetic layer; a first input/output (I/O) junction structure branches from the wire at a first position; a second I/O junction structure, a first Two locations diverge from the wire, the second location is spaced from the first location; and a third I/O junction structure, the third I/O junction structure is between the first position and the second position A third position of is branched from the conductive line, wherein a connection between the third I/O junction structure and the first I/O junction structure has a first inductance, and the first I/O junction structure An alternative connection with the second I/O junction structure has a second inductance that is greater than the first inductance. 如申請專利範圍第1項所述的多端點電感器，更包括：一第一介電層，設置在該導線上；一第二磁性層，設置在該第一介電層上；以及一第二介電層，設置在該第二磁性層上；其中該導線沿著一第一方向以實質上一直線從該第一I/O接合結構橫向延伸到該第二I/O接合結構；其中該第一I/O接合結構、該第二I/O接合結構及該第三I/O接合結構皆從該導線延伸穿過該第二介電層的一最上表面，並且該導線具有在該第一磁性層上的一第一上表面，該第一上表面位於該導線的一第二上表面上。 The multi-terminal inductor as described in item 1 of the patent application scope further includes: a first dielectric layer disposed on the wire; a second magnetic layer disposed on the first dielectric layer; and a first Two dielectric layers disposed on the second magnetic layer; wherein the wire extends laterally from the first I/O bonding structure to the second I/O bonding structure in a substantially straight line along a first direction; wherein the The first I/O junction structure, the second I/O junction structure and the third I/O junction structure all extend from the wire through an uppermost surface of the second dielectric layer, and the wire has a A first upper surface on a magnetic layer, the first upper surface is located on a second upper surface of the wire. 如申請專利範圍第1項所述的多端點電感器，其中該導線以圍繞該第一磁性層的一螺旋圖案從該第一I/O接合結構連續地延伸到該第二I/O接合 結構。 The multi-terminal inductor as described in item 1 of the patent application range, wherein the wire continuously extends from the first I/O junction structure to the second I/O junction in a spiral pattern surrounding the first magnetic layer structure. 如申請專利範圍第1項所述的多端點電感器，其中該多端點電感器是排列成陣列的複數多端點電感器中之一者，其中每個多端點電感器彼此間隔開，每個多端點電感器被設置在相同的橫向方向上，並且每個多端點電感器彼此實質上相同。 The multi-terminal inductor as described in item 1 of the patent application scope, wherein the multi-terminal inductor is one of a plurality of multi-terminal inductors arranged in an array, wherein each multi-terminal inductor is spaced apart from each other, each multi-terminal inductor The point inductors are arranged in the same lateral direction, and each multi-terminal inductor is substantially the same as each other. 一種多端點電感器，包括：一半導體基底；一互連結構，設置在該半導體基底上，該互連結構具有複數金屬層；一鈍化層，設置在該互連結構的一最上表面上；一磁性層，設置在該鈍化層上；複數電感器單元，分別包括複數導線，該等電感器單元彼此間隔開並設置在該磁性層上，其中該等電感器單元之一第一電感器單元包括一介電層，該介電層在該第一電感器單元的一第一導線上延伸，並且包括一第一端點及一第二端點，第一端點及該第二端點延伸穿過該介電層以電性連接到該第一電感器單元的該第一導線；以及一連接結構，設置在該介電層上並具有電性耦接到該第一端點及該第二端點的導電佈線，其中該連接結構將該等電感器單元中的部分電感器單元彼此電串聯，但不是全部的電感器單元。 A multi-terminal inductor includes: a semiconductor substrate; an interconnection structure provided on the semiconductor substrate, the interconnection structure having a plurality of metal layers; a passivation layer provided on an uppermost surface of the interconnection structure; A magnetic layer is provided on the passivation layer; a plurality of inductor units, each including a plurality of wires, the inductor units are spaced apart from each other and disposed on the magnetic layer, wherein one of the inductor units, the first inductor unit includes A dielectric layer extending on a first wire of the first inductor unit, and including a first terminal and a second terminal, the first terminal and the second terminal extending through The first wire electrically connected to the first inductor unit through the dielectric layer; and a connection structure disposed on the dielectric layer and electrically coupled to the first terminal and the second Conductive wiring at the end point, where the connection structure electrically connects some of the inductor units in the same inductor unit to each other in series, but not all of the inductor units. 如申請專利範圍第5項所述的多端點電感器，其中該第一端點包括一第一焊料凸塊，該第二端點包括一第二焊料凸塊，並且其中該連接結構是具有複數導電佈線的印刷電路板，該等導電佈線將該等電感器單元中的兩個或更多個彼此串聯。 The multi-terminal inductor according to item 5 of the patent application scope, wherein the first terminal includes a first solder bump, the second terminal includes a second solder bump, and wherein the connection structure has a plural number A printed circuit board of conductive wiring that connects two or more of these inductor units in series with each other. 如申請專利範圍第5項所述的多端點電感器，其中該第一電感單元更包括： 一第三端點，延伸穿過該介電層並且電性耦接到該第一電感器單元，其中在該第一端點及該第二端點之間測量的一第一電感大於在該第一端點及該第三端點之間測量的一第二電感。 The multi-terminal inductor as described in item 5 of the patent application scope, wherein the first inductance unit further includes: A third terminal extending through the dielectric layer and electrically coupled to the first inductor unit, wherein a first inductance measured between the first terminal and the second terminal is greater than the A second inductance measured between the first endpoint and the third endpoint. 如申請專利範圍第5項所述的多端點電感器，其中該第一導線以實質上一直線從該第一端點連續地延伸到該第二端點，該第一電感單元包括與該第一導線平行延伸的一第二導線，並且其中一第三端點及一第四端點延伸穿過該介電層並且電性耦接到該第一電感單元的該第二導線，其中在該第一端點及該第二端點之間測量的一第一電感實質上等於在該第三端點及該第四端點之間測量的一第二電感。 The multi-terminal inductor according to item 5 of the patent application scope, wherein the first wire continuously extends from the first terminal to the second terminal in a substantially straight line, and the first inductance unit includes A second wire extending parallel to the wire, and a third terminal and a fourth terminal extending through the dielectric layer and electrically coupled to the second wire of the first inductance unit, wherein A first inductance measured between an end point and the second end point is substantially equal to a second inductance measured between the third end point and the fourth end point. 如申請專利範圍第5項所述的多端點電感器，其中該第一導線以圍繞該磁性層的一螺旋結構從該第一端點連續地延伸到該第二端點，其中該第一電感單元更包括：一第三端點，延伸穿過該介電層並且電性耦接到該第一電感器單元，其中該第一端點位於該第一導線的一第一端點，該第二端點位於該第一導線的一第二端點，以及該第三端點位於該第一端點與該第二端點之間的該螺旋結構上的一第一中間位置；以及一第四端點，延伸穿過該介電層並且電性耦接到該第一電感器單元，其中該第四端點位於該第一端點與該第一中間位置之間的該螺旋結構上的一第二中間位置。 The multi-terminal inductor according to item 5 of the patent application scope, wherein the first wire continuously extends from the first terminal to the second terminal in a spiral structure surrounding the magnetic layer, wherein the first inductor The unit further includes: a third terminal extending through the dielectric layer and electrically coupled to the first inductor unit, wherein the first terminal is located at a first terminal of the first wire, the first The two end points are located at a second end point of the first wire, and the third end point is located at a first intermediate position on the spiral structure between the first end point and the second end point; and a first Four terminals, extending through the dielectric layer and electrically coupled to the first inductor unit, wherein the fourth terminal is located on the spiral structure between the first terminal and the first intermediate position A second intermediate position. 一種多端點電感器形成方法，包括：在一半導體基底上形成具有複數金屬層的一互連結構；在該互連結構的一最上表面上形成一鈍化層；在該鈍化層上形成一第一磁性層；在該第一磁性層上形成彼此間隔開的複數導線； 在該等導線上形成一介電層；在該介電層上形成複數焊料凸塊，其中該等焊料凸塊中的不同焊料凸塊電性耦接到不同的導線；以及選擇性地將具有複數導電佈線的印刷電路板連接到該等焊料凸塊中的部分焊料凸塊但不是全部的焊料凸塊。 A method for forming a multi-terminal inductor includes: forming an interconnect structure having a plurality of metal layers on a semiconductor substrate; forming a passivation layer on an uppermost surface of the interconnect structure; forming a first on the passivation layer A magnetic layer; a plurality of wires spaced apart from each other are formed on the first magnetic layer; Forming a dielectric layer on the wires; forming a plurality of solder bumps on the dielectric layer, wherein different solder bumps in the solder bumps are electrically coupled to different wires; and selectively having The printed circuit board of a plurality of conductive wirings is connected to some of the solder bumps but not all of the solder bumps.
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