TWI690817B - Integrated circuit and method of designing layout of integrated circuit, standard cell stored in a standard cell library, and method of manufacturing a semiconductor device - Google Patents

Abstract

An integrated circuit and a method of designing a layout of the integrated circuit are disclosed. The method of designing a layout of an integrated circuit (IC) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary.

Description

Integrated circuit and method for designing layout of the integrated circuit, Standard cell stored in standard cell library and method of manufacturing semiconductor device [Cross-reference to related applications]

This application claims the priority and rights of Provisional Application No. 62/058,432 filed on October 1, 2014 and Korean Patent Application No. 10-2015-0085145 filed on June 16, 2015. The full disclosure contents of the provisional application and the Korean patent application are incorporated in this case for reference.

Exemplary embodiments of the inventive concept relate to an integrated circuit (IC), and more specifically to an integrated circuit including at least one standard cell and a layout for designing the integrated circuit Methods.

The design of a semiconductor integrated circuit includes the operation of converting a behavioral model for the wafer and explaining the operation to be derived from the semiconductor system into a specific structural model for explaining the connection between the required components. Referring to the process of designing a semiconductor integrated circuit, when a cell library included in the semiconductor integrated circuit can be generated and the generated library can be used When the semiconductor integrated circuit is implemented, the time and cost required to design and implement the semiconductor integrated circuit can be reduced.

According to an exemplary embodiment of the inventive concept, a method of designing an integrated circuit (IC) layout includes placing a first cell in the layout; placing a second cell in the first cell and the A first boundary between second cells is placed in the layout adjacent to the first cell; and a plurality of commands executable by the processor are generated to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first pattern and the second pattern are adjacent to the first boundary, the first pattern and the second pattern have different colors, and the first pattern between the first pattern and the first boundary A boundary space is different from the second boundary space between the second pattern and the first boundary.

According to an exemplary embodiment of the inventive concept, a method of designing a layout of an integrated circuit includes placing a first cell in the layout. The first cell includes a plurality of first colorless patterns, and the plurality of first colorless patterns respectively satisfy a first spatial condition. The first spatial condition corresponds to the value of the smallest space between the patterns assigned the same color in the first area adjacent to the first boundary. The method further includes placing a second cell adjacent to the first cell at the first boundary between the first cell and the second cell in the layout. The first zone extends substantially parallel to the first boundary. The method further includes generating a plurality of commands executable by the processor to form a semiconductor device based on the layout.

According to an exemplary embodiment of the inventive concept, an integrated circuit (IC) Including: a plurality of cells; and a plurality of patterns disposed in each of the plurality of cells and adjacent to the boundary of each of the plurality of cells. The plurality of patterns have different colors respectively corresponding to different masks, and the boundary spaces between the pattern and the boundary are different from each other.

According to an exemplary embodiment of the present inventive concept, a standard cell stored in a standard cell library includes a plurality of first colorless patterns, the plurality of first colorless patterns disposed on the standard cells adjacent to the first boundary In the first district. Each of the first colorless patterns meets the first spatial condition. The standard cell further includes a plurality of second colorless patterns, and the plurality of second colorless patterns are disposed in the second region of the standard cell adjacent to the second boundary opposite to the first boundary. Each of the second colorless patterns satisfies the first spatial condition, and the first spatial condition corresponds to the value of the smallest space between the patterns assigned the same color in the first area.

According to an exemplary embodiment of the inventive concept, a method of manufacturing a semiconductor device includes placing a first cell in a layout. The first cell includes at least two patterns disposed adjacent to the first boundary between the first cell and the second cell. The method further includes placing the second cell adjacent to the first cell at the first boundary in the layout. The first cell and the second cell are from a plurality of cells that define an integrated circuit. The at least two patterns have different colors, and the boundary spaces between the at least two patterns and the first boundary are different from each other. The method further includes forming the semiconductor device based on the layout. The semiconductor device is formed using a multiple patterning operation, which is performed on the at least two patterns using different masks respectively corresponding to the different colors.

According to an exemplary embodiment of the present inventive concept, a method of manufacturing a semiconductor device includes placing a first cell in a layout adjacent to a first boundary. The first cell includes a first area, and a plurality of first colorless patterns are disposed in the first area. The method further includes placing a second cell adjacent to the first boundary in the layout. The second cell includes a first pattern having a first color, and the first cell and the second cell are from a plurality of cells that define an integrated circuit. The first colorless pattern satisfies a first spatial condition, which corresponds to the value of the smallest space between the patterns adjacent to the first boundary and assigned the same color. The method further includes assigning a second color to the first colorless pattern, and forming the semiconductor device based on the layout. The semiconductor device is formed using a multiple patterning operation that uses the first mask and the second mask pair corresponding to the first color and the second color, respectively, to have the first The first pattern of one color and the first colorless pattern assigned to the second color are fulfilled.

According to an exemplary embodiment of the inventive concept, a method of manufacturing a semiconductor device includes placing a first cell in a layout of an integrated circuit. The first cell includes a first pattern and a second pattern. The method further includes placing a second cell adjacent to the first cell at the boundary between the first cell and the second cell in the layout. The first pattern and the second pattern are adjacent to the boundary, the first pattern and the second pattern have different colors, and the first boundary space between the first pattern and the boundary is different A second boundary space between the second pattern and the boundary. The method further includes forming the semiconductor device based on the layout Set. The semiconductor device is formed using a multiple patterning operation, which is performed on the first pattern and the second pattern using different masks respectively corresponding to the different colors.

30: Integrated circuit

31: The first pattern

32: The first pattern

33: Second pattern

41: Integrated circuit

42: Integrated circuit

43: Integrated circuit

61: Integrated circuit

62: Integrated circuit

71: Integrated circuit

72: Integrated circuit

73: Integrated circuit

74: Integrated circuit

75: Integrated circuit

76: Integrated circuit

90: Cell

91: first right pattern

92: second right pattern

93: Left pattern

100a: semiconductor device

100b: semiconductor device

101: Integrated circuit

102: Integrated circuit

120: Cell

121: First right pattern

122: second right pattern

123, 124: left pattern

131: Integrated circuit

132: Integrated circuit

150: Integrated circuit

160: Cell

161: First right pattern

162: Second right pattern

163: third right pattern

164: Left pattern

171: Integrated circuit

172: Integrated circuit

180: Cell

181: First right pattern

182: Second right pattern

183: third right pattern

184: first left pattern

185: Second left pattern

191: Integrated circuit

192: Integrated circuit

210: Integrated circuit

221: Integrated circuit

222: Integrated circuit

240: Integrated circuit

251: Integrated circuit

252: Integrated circuit

260: Integrated circuit

261: The first standard cell

262: Second standard cell

280A: Integrated circuit

280B: Integrated circuit

281: The first standard cell

281': the first standard cell

281a, 281b, 281c: no color pattern

281a': the first pattern

281b': second pattern

281c': third pattern

282: second standard cell

282': second standard cell

282a, 282c: No color pattern

282a': the first pattern

282c': third pattern

290: Integrated circuit

291: The first standard cell

291a, 291b: pattern

292: second standard cell

292a, 292b: pattern

300: Integrated circuit

301: the first standard cell

301a: the first pattern

301b: Second pattern

302: second standard cell

302a: the first pattern

302b: Second pattern

320: Integrated circuit

321: the first standard cell

321a: No color pattern

322: second standard cell

322a: No color pattern

322b: the first pattern

322c: Second pattern

322d: third pattern

322e, 322f: no color pattern

323: Third standard cell

323a, 323b: no color pattern

331: Integrated circuit

332: Integrated circuit

411: the first pattern

412: Second pattern

413: The first pattern

414: Second pattern

415: Second pattern

415': Second pattern

416: The first pattern

416': the first pattern

500: storage media

510: Placement and routing program

520: library

530: Analysis program

540: Data structure

601: the first standard cell

601a, 601b: the first pattern

602: second standard cell

602a: the first pattern

602b: Second pattern

611: The first standard cell

611a, 611b: the first pattern

612: Second standard cell

612a: the first pattern

612b: Second pattern

711: the first standard cell

711a: the first pattern

711b: Second pattern

712: Second standard cell

712a: the first pattern

721: The first standard cell

721a: the first pattern

731: The first standard cell

731b: Second pattern

741: The first standard cell

752: Second standard cell

752a: the first pattern

752a': the first pattern

762: Second standard cell

1000: memory card

1001: the first standard cell

1001a: first left pattern

1001b: second left pattern

1001c: right pattern

1002: second standard cell

1002a: first left pattern

1002b: second left pattern

1002c: right pattern

1003: third standard cell

1003a: first right pattern

1003a': the first right pattern

1003b: second right pattern

1003b': second right pattern

1003c: Left pattern

1003c': left pattern

1004: fourth standard cell

1004a: first left pattern

1004b: second left pattern

1004c: right pattern

1100: controller

1200: memory

1301: the first standard cell

1301a: first left pattern

1301b: Second left pattern

1301c: first right pattern

1301d: Second right pattern

1302: second standard cell

1302a: first left pattern

1302b: Second left pattern

1302c: first right pattern

1302d: second right pattern

1303: third standard cell

1303a: first left pattern

1303a': the first left pattern

1303b: Second left pattern

1303b': second left picture

1303c: First right pattern

1303c': the first right pattern

1303d: second right pattern

1303d': second right pattern

1304: fourth standard cell

1304a: the first left pattern

1304b: Second left pattern

1304c: the first right pattern

1304d: Second right pattern

1501: the first standard cell

1501a, 1501b: the first pattern

1502: second standard cell

1502a: the first pattern

1502b: second pattern

1502c: third pattern

1701: the first standard cell

1701a: first left pattern

1701b: second left pattern

1701c: third left pattern

1701d: right pattern

1702: second standard cell

1702a: the first left pattern

1702b: Second left pattern

1702c: Third left pattern

1702d: Right pattern

1703: Third standard cell

1703a: the first right pattern

1703a': the first right pattern

1703b: Second right pattern

1703b': second right pattern

1703c: Third right pattern

1703d: Left pattern

1703d': left pattern

1704: fourth standard cell

1704a: the first left pattern

1704b: Second left pattern

1704c: third left pattern

1704d: right pattern

1901: the first standard cell

1901a: the first right pattern

1901b: second right pattern

1901c: third right pattern

1901d: the first left pattern

1901e: second left pattern

1902: second standard cell

1902a: the first right pattern

1902b: second right pattern

1902c: third right pattern

1902d: the first left pattern

1902e: second left pattern

1903: third standard cell

1903a: the first left pattern

1903a': the first left pattern

1903b: Second left pattern

1903b': second left pattern

1903c: third left pattern

1903c': third left pattern

1903d: the first right pattern

1903d': the first right pattern

1903e: second right pattern

1903e': second right pattern

1904: fourth standard cell

1904a: the first right pattern

1904b: second right pattern

1904c: third right pattern

1904d: the first left pattern

1904e: second left pattern

2000: computing system

2100: processor

2101: The first standard cell

2101a, 2101b: the first pattern

2102: second standard cell

2102a: the first pattern

2102b: Second pattern

2102c: third pattern

2102d: Fourth pattern

2200: Memory device

2201: the first standard cell

2201a: first left pattern

2201b: Second left pattern

2201c: third left pattern

2201d: Fourth left pattern

2201e: right pattern

2202: second standard cell

2202a: first left pattern

2202b: Second left pattern

2202c: third left pattern

2202d: Fourth left pattern

2202e: right pattern

2203: third standard cell

2203a: the first right pattern

2203a': first right pattern

2203b: Second right pattern

2203b': second right pattern

2203c: Third right pattern

2203d: Fourth right pattern

2203e: Left pattern

2203e': left pattern

2204: fourth standard cell

2204a: First left pattern

2204b: Second left pattern

2204c: Third left pattern

2204d: Fourth left pattern

2204e: Right pattern

2300: storage device

2400: Power supply

2401: the first standard cell

2401a, 2401b: the first pattern

2402: second standard cell

2402a: the first pattern

2402b: Second pattern

2402c: third pattern

2402d: Fourth pattern

2500: input/output device

2501: the first standard cell

2501a: first left pattern

2501b: second left pattern

2501c: third left pattern

2501d: fourth left pattern

2501e: right pattern

2502: second standard cell

2502a: first left pattern

2502b: second left pattern

2502c: third left pattern

2502d: fourth left pattern

2502e: right pattern

2503: third standard cell

2503a: first right pattern

2503a': first right pattern

2503b: second right pattern

2503b': second right pattern

2503c: third right pattern

2503c': third right pattern

2503d: Fourth right pattern

2503d': fourth right pattern

2503e: Left pattern

2503e': left pattern

2504: fourth standard cell

2504a: first left pattern

2504b: second left pattern

2504c: third left pattern

2504d: fourth left pattern

2504e: right pattern

2600: bus

2611: The first pattern

2612a: the first pattern

2612b: Second pattern

2622: contact surface

3311: The first standard cell

3311a: Pattern

3312: Second standard cell

3312a: The first pattern

3312b: Second pattern

A-A': line

AR1: the first active area

AR2: second active area

B1: first boundary space/boundary space/left boundary space/right boundary space

B1': the first boundary space

B2: second boundary space/boundary space/left boundary space/right boundary space

B2': second boundary space

B3: Third boundary space/boundary space/left boundary space/right boundary space

B4: Fourth boundary space/boundary space/left boundary space/right boundary space

BD1: the first boundary

BD2: Second border

BD_L: lower boundary

BD_U: upper boundary

bf: distance

Bf: distance/space/left boundary space/boundary space/first left boundary space/second left boundary space

Bf': space

bs: distance

CA: contact surface

CB: Cell boundary

CL: conductive wire/gate electrode

CL': conductive wire/gate electrode

CL_PT: No color pattern

D0: distance

D1: distance

D1': distance

d: predetermined distance

DR1: First direction

FN: First fin to third fin

FN': First to third fins

FZ: District 1

FZ1: Zone 1

FZ2: Zone 2

FZ3: Zone 3

FZ4: Zone 4

IL1: the first insulating layer

IL1': the first insulating layer

IL2: second insulating layer

IL2': Second insulating layer

PT1: The first pattern assigned the first color

PT2: second pattern assigned a second color

PT3: The third pattern assigned the third color

PT4: The fourth pattern assigned the fourth color

RS: Space

RS': space/extra space

S1: First space

S1': the first space

s1: space

S2: Second space

S2': Second space

s2: space

S10, S11, S13, S20: operation

S200, S220, S240, S260: Operation

S200A: Method

S200B: Method

S200C: Method

S200D: Method

S500, S520, S540: Operation

S800, S820: operation

S1100, S1120: operation

S1400, S1420, S1440, S1460: Operation

S2000, S2020, S2040, S2060: Operation

S2300, S2320, S2340, S2360, S2380: Operation

S2700, S2720, S2740: Operation

S3100, S3120, S3140: Operation

SC: standard cell

SC1: the first standard cell

SC2: second standard cell

SC3: third standard cell

SUB: substrate/semiconductor substrate

SUB': substrate

X: direction

Y: direction

V1: the first path

V2: Second channel

V2': the second channel

V3: The third channel

V3': the third channel

V4: the fourth path

VDD: first power line/first power line

VSS: second power line/second power line

The above and other features of the inventive concept will become more apparent by explaining exemplary embodiments of the inventive concept in detail with reference to the drawings. In the drawings:

FIG. 1 is a flowchart of a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.

2 is a flowchart of a method of designing a layout of an integrated circuit according to an exemplary embodiment of the inventive concept.

FIG. 3 illustrates a part of an integrated circuit including a pattern satisfying a first spatial condition and a second spatial condition according to an exemplary embodiment of the inventive concept.

FIG. 4 illustrates an example of a method for resolving color conflicts according to an exemplary embodiment of the inventive concept.

FIG. 5 is a flowchart of a method for designing a cell according to an exemplary embodiment of the inventive concept.

6A is a diagram of an example of an integrated circuit including cells designed according to a comparative example.

6B is a diagram of an example of an integrated circuit including cells designed according to an exemplary embodiment of the inventive concept.

7A to 7F are diagrams of examples of integrated circuits including cells designed according to an exemplary embodiment of the inventive concept.

8 is a flowchart of a modified example of a method of designing a cell according to an exemplary embodiment of the inventive concept.

9 illustrates an example of a cell designed using the method shown in FIG. 8 according to an exemplary embodiment of the inventive concept.

FIG. 10 is a diagram of an example of applying a color inversion operation to an integrated circuit according to an exemplary embodiment of the inventive concept.

FIG. 11 is a flowchart of a modified example of a method of designing a cell according to an exemplary embodiment of the inventive concept.

FIG. 12 illustrates an example of a cell designed using the method shown in FIG. 11 according to an exemplary embodiment of the inventive concept.

13 illustrates an example of applying a color inversion operation to an integrated circuit according to an exemplary embodiment of the inventive concept.

14 is a flowchart of a method of designing a cell according to an exemplary embodiment of the inventive concept.

15 illustrates an example embodiment of an integrated circuit including cells designed using the method shown in FIG. 14 according to an exemplary embodiment of the inventive concept.

16 illustrates an example of a cell designed using the method shown in FIG. 14 according to an exemplary embodiment of the inventive concept.

FIG. 17 illustrates an example of applying a color inversion operation to an integrated circuit including the cell shown in FIG. 16 according to an exemplary embodiment of the inventive concept.

18 illustrates an example of a cell designed using the method shown in FIG. 14 according to an exemplary embodiment of the inventive concept.

FIG. 19 illustrates an example of applying a color inversion operation to an integrated circuit including the cell shown in FIG. 18 according to an exemplary embodiment of the inventive concept.

20 is a flowchart of a method of designing a cell according to an exemplary embodiment of the inventive concept.

FIG. 21 illustrates an example embodiment of an integrated circuit including cells designed using the method shown in FIG. 20 according to an exemplary embodiment of the inventive concept.

FIG. 22 illustrates an example of applying a color inversion operation to an integrated circuit including cells designed using the method shown in FIG. 20 according to an exemplary embodiment of the inventive concept.

23 is a flowchart of a method of designing a cell according to an exemplary embodiment of the inventive concept.

24 illustrates an example embodiment of an integrated circuit including cells designed using the method shown in FIG. 23 according to an exemplary embodiment of the inventive concept.

FIG. 25 illustrates an example of applying a color inversion operation to an integrated circuit including cells designed using the method shown in FIG. 23 according to an exemplary embodiment of the inventive concept.

26 illustrates an example of a layout of an integrated circuit including a cell designed using a method according to an exemplary embodiment of the present inventive concept.

FIG. 27 is a flowchart of a method of designing an integrated circuit according to an exemplary embodiment of the inventive concept.

FIG. 28 illustrates a method of assigning colors to achromatic patterns according to an exemplary embodiment of the inventive concept.

FIG. 29 illustrates an exemplary embodiment according to the inventive concept in which three colors are assigned to four colorless patterns.

30 illustrates an example embodiment of an integrated circuit including cells designed using the method shown in FIG. 27 according to an exemplary embodiment of the inventive concept.

FIG. 31 is a flowchart of a method of designing an integrated circuit according to an exemplary embodiment of the inventive concept.

32 illustrates an example embodiment of an integrated circuit including cells designed using the method shown in FIG. 31 according to an exemplary embodiment of the inventive concept.

33 illustrates an example of a layout of an integrated circuit including a cell designed using a method according to an exemplary embodiment of the present inventive concept.

FIG. 34 illustrates an example of a standard cell including a cell designed according to an exemplary embodiment of the inventive concept.

35 is a perspective view of an example of a semiconductor device having the layout shown in FIG. 34 according to an exemplary embodiment of the inventive concept.

36 is a cross-sectional view taken along line AA' shown in FIG. 34 according to an exemplary embodiment of the present inventive concept.

37 is a perspective view of an example of a semiconductor device having the layout shown in FIG. 34 according to an exemplary embodiment of the inventive concept.

FIG. 38 is a cross-sectional view taken along line AA′ shown in FIG. 37 according to an exemplary embodiment of the inventive concept.

39 is a block diagram of a storage medium according to an exemplary embodiment of the inventive concept.

40 is a block diagram of a memory card including an integrated circuit according to an exemplary embodiment of the inventive concept.

41 is a block diagram of a computing system including an integrated circuit according to an exemplary embodiment of the inventive concept.

Exemplary embodiments of the inventive concept will now be explained more fully hereinafter with reference to the drawings. Throughout the drawings, the same reference number may refer to the same element. In the drawings, the thickness of layers and regions may be exaggerated for clarity.

The terminology used herein is only for explaining specific exemplary embodiments and is not intended to limit the inventive concept. Unless the context clearly indicates otherwise, the singular forms "a" and "the" as used herein are intended to include the plural forms as well.

It will be understood that although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions, layers, and/or sections do not Should be limited to these terms. Therefore, without departing from the teachings of the inventive concept, the first element, component, region, layer, or section described below may be referred to as the second element, component, region, layer, or section.

It will be understood that when a component (eg, a film, region, layer, or element) is referred to as being "on", "connected to", "coupled to", or "adjacent" to another component, the component (eg For example, a film, region, layer, or element) may be directly on, connected to, coupled to, or adjacent to the other component, or there may be an intermediate component. It will also be understood that when a component is referred to as being "between" two components, it can be the only component between the two components, or one or more intervening components may also be present.

In this article, for ease of explanation, spatial relativity can be used, for example "Beneath", "below", "lower", "under", "above ( above), ``upper'', ``to the left of'', ``to the right of'' etc. to illustrate an element or feature shown in the figure Relationship with another (other) element or feature. It will be understood that the term spatial relativity is intended to include different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if the device shown in the figure is turned over, elements described as "below", "below", or "below" other elements or features would then be oriented "above" the other elements or features ". Thus, the exemplary terms "below" and "below" can encompass both an orientation of above and below.

The term "and/or" as used herein includes any and all combinations of one or more of the listed items. In addition, when two or more elements or values are stated to be substantially the same or approximately equal to each other, it will be understood that the elements or values are the same as each other and cannot be distinguished from each other, as those of ordinary skill in the art understand. Or they can be distinguished from each other but functionally the same. In addition, when the processes are described as being performed substantially simultaneously, it will be understood that, as those of ordinary skill in such technology understand, the processes can be performed completely simultaneously or approximately simultaneously.

An integrated circuit (IC) can be defined by multiple cells. For example, an integrated circuit can be designed using a cell library including characteristic information about the plurality of cells. Here, the cell name, size, gate width, pin, delay characteristic, leakage current, critical voltage, and function can be defined in the cell library. A general cell library set may include basic cells (e.g., and, or, inverse or, or inverters), complex cells (e.g., or /And/inverter (OR/AND/INVERTER, OAI) and/or/inverter (AND/OR/INVERTER, AOI)), and storage elements (for example, master-slaver flip -flop) and latch).

In the following exemplary embodiments, the cell library may be a standard cell library. The standard cell method can be a pre-prepared logic circuit block (or cell) with several functions and a dedicated large-scale integrated circuit (large -scale integrated circuit (LSI) method. Cells can be designed and verified in advance and registered in the computer, and the logic design, placement, and routing process can be performed by combining the cells using computer-aided design (CAD).

For example, when designing and manufacturing a large-scale integrated circuit, if the standardized logic circuit block has been maintained at a certain scale, the logic circuit block suitable for the current design purpose can be selected from the standardized logic circuit block and placed in Multiple rows of cells on the wafer. In addition, the entire circuit can be manufactured by optimally routing the line with the shortest route length in the routing space between the cells. As the types of cells maintained in the library become more diverse, design flexibility can increase, and the optical design possibilities of wafers can increase.

It is possible to pre-design and implement an integrated body using standard cells as a semi-custom integrated circuit by placing cells to use the standard cells stored in the standard cell library and minimize the routing between the standard cells Circuit. Therefore, the integrated circuit can be developed at a low cost in a short duration compared to a fully customized integrated circuit.

FIG. 1 is an exemplary embodiment of a concept of the present invention, a manufacturing semiconductor Flow chart of the method of the body device.

Referring to FIG. 1, a method of manufacturing a semiconductor device according to an exemplary embodiment may be divided into an operation of designing an integrated circuit (S10) and an operation of manufacturing an integrated circuit (S20). The operation (S10) of designing the integrated circuit including operations S11 and S13 corresponds to the layout of the design integrated circuit, and can be performed using the tool for designing the integrated circuit. A tool for designing an integrated circuit may be, for example, a program including multiple commands executed by a processor. The operation of manufacturing an integrated circuit (S20) corresponds to manufacturing a semiconductor device based on the integrated circuit based on the designed layout, and can be performed by the semiconductor processing module. For example, according to an exemplary embodiment, when the operation of designing an integrated circuit (S10) has been completed, a plurality of commands executable by the processor to manufacture the integrated circuit may be generated based on the layout designed in operation S10.

In operation S11, a standard cell library may be provided. The standard cell library may include information about multiple standard cells, and may be stored in a computer-readable storage medium. The standard cell library may include, for example, layout information and timing information about standard cells.

In an exemplary embodiment, providing a standard cell cell library may include generating a standard cell cell library, and more specifically designing a standard cell cell. Designing standard cells may include designing multiple patterns using multiple colors corresponding to multiple masks due to color decomposition, for example.

In operation S13, the layout of the integrated circuit can be designed by placing and routing the standard cell using the standard cell library. For example, input data for defining integrated circuits may be received. The input data may be data generated by synthesizing an abstract type of behavior of an integrated circuit (for example, data defined by register transfer level (RTL)) using a standard cell library. Examples In other words, the input data can be generated by synthesizing integrated circuits defined by hardware description languages (HDL) (such as high-speed integrated circuit hardware description languages (VHSIC HDL, VHDL) and VERILOG) Bitstream or netlist.

The storage medium used to store the standard cell library can be accessed, and the standard cells selected based on the input data among the plurality of standard cells stored in the standard cell library can be placed and routed. Here, the placing and routing (P&R) operation refers to the operation of placing the selected standard cell and connecting the placed standard cell. The layout of the integrated circuit can be generated by completing the placement and routing (P&R) operation.

The operation S10 of designing the integrated circuit may include the operations S11 and S13 described above. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, the operation S10 of designing the integrated circuit may further include various operations performed when designing the integrated circuit, such as an operation of revising the standard cell library, an operation of verifying the layout, and a post-simulation operation.

In operation S20, a semiconductor device according to the integrated circuit may be formed based on the layout of the integrated circuit. For example, first, the layout of the integrated circuit can be changed by performing optical proximity correction (OPC) operations based on the layout of the integrated circuit. Here, the optical proximity correction operation refers to a process of changing the layout of the integrated circuit based on the error caused by the optical proximity effect (OPE). If the layout of the integrated circuit is used to make the mask as it is (for example, no change is made based on the error) and the mask is used to perform lithography Cheng, a pattern with a shape different from the designed layout may be formed due to the optical proximity effect. Therefore, when the layout of the integrated circuit is changed based on the error caused by the optical proximity effect, a mask is manufactured based on the changed layout, and the mask is used to perform the lithography process, the same layout as that of the layout can be formed Shaped pattern.

Subsequently, the mask may be manufactured according to the layout changed based on the optical proximity correction result, and the manufactured mask may be used to form an integrated circuit. In this case, a layout based on an optical proximity correction operation (for example, a graphic design system (GDS) based on an optical proximity correction operation) may be used to manufacture the mask, and the manufactured mask may be used by using To perform the lithography process and fabricate integrated circuits on the wafer. The number of masks manufactured may correspond to the number of colors assigned to the patterns included in the layout.

2 is a flowchart of a method of designing a layout of an integrated circuit according to an exemplary embodiment of the inventive concept.

Referring to FIG. 2, a method of designing a layout of an integrated circuit according to an exemplary embodiment may correspond to an example of operation S10 shown in FIG. 1. Therefore, for convenience of explanation, further description of the processes and elements previously explained with reference to FIG. 1 may be omitted herein.

In operation S200, the first cell may be designed so that the patterns adjacent to the first boundary have different colors and different boundary spaces. Operation S200 may be an example of operation S11 shown in FIG. 1. According to an exemplary embodiment, the first cell may be designed so that at least two of the patterns adjacent to the first boundary have different colors and different boundary spaces. Therefore, some of the patterns adjacent to the first boundary may have the same color or the same boundary space.

A cell can be defined by a cell boundary including four boundary lines. In this article, the four boundary lines may also be called boundaries. Thus, the cell boundary may be the outline that defines the cell, and the placement and routing tools may use the cell boundary to identify the cell. The first boundary may be one of the four boundaries. In an exemplary embodiment, the first boundary may be one of two boundaries (for example, two boundaries that are not parallel to the power line) of the four boundaries where the power lines are not arranged.

The pattern adjacent to the first boundary may refer to a pattern or feature arranged closer to the first boundary than the second boundary arranged opposite to the first boundary among the plurality of patterns constituting one layer of the first cell. In an exemplary embodiment, the pattern adjacent to the first boundary may be disposed directly adjacent to the first boundary. For example, other patterns may not be disposed between the first boundary and the pattern adjacent to the first boundary.

In consideration of the patterning resolution, a plurality of masks are used to form the plurality of patterns constituting one layer of the first cell. For example, in the operation of designing cells, a plurality of colors respectively corresponding to a plurality of masks may be used to design a plurality of patterns due to color decomposition. For example, patterns formed using different masks can be assigned different colors. In an exemplary embodiment, at least two of the patterns adjacent to the first boundary may be assigned different colors, respectively.

The boundary space may refer to the space between the first boundary and the pattern adjacent to the first boundary. In an exemplary embodiment, the extending direction of the pattern may be substantially parallel to the first boundary. In this case, the boundary space may refer to side-to-side space. In an exemplary embodiment, the extending direction of the pattern may be substantially perpendicular to the first boundary. In this case, the boundary space may refer to the side-to-tip space. in In an exemplary embodiment, the edge-to-top space may be set larger than the edge-to-edge space. Various exemplary embodiments related to the boundary space will be explained in detail with reference to FIGS. 7A to 7F.

In operation S220, the first cell and the second cell may be placed adjacent to each other at the first boundary. For example, the first cell may be placed first, and the second cell may be placed adjacent to the first boundary of the first cell according to the direction in which the first cell is placed. In an exemplary embodiment, the first cell and the second cell may be placed directly adjacent to each other. Operation S220 may be an example of operation S13 shown in FIG. 1. The second cell can be any cell stored in the standard cell library.

In an exemplary embodiment, the second cell may be a cell designed according to operation S200. For example, the patterns adjacent to one boundary of the second cell may have different colors and different boundary spaces, and the patterns adjacent to another boundary arranged opposite to the one boundary of the second cell may have the same Color and the same boundary space. As another option, the patterns adjacent to another boundary of the second cell may have different colors and different boundary spaces.

In an exemplary embodiment, the second cell may be a cell that is not designed according to operation S200. For example, each pattern adjacent to one boundary of the second cell may have the same color and the same boundary space, and each pattern adjacent to another boundary arranged opposite to the one boundary of the second cell may also have the same color And the same boundary space.

In an exemplary embodiment, the first cell and the second cell may be placed directly adjacent to the first boundary. In this case, the first boundary may substantially overlap one boundary of the second cell. In an exemplary embodiment, the second cell may be adjacent to the first boundary and A boundary is placed at a predetermined space.

In operation S240, it may be determined whether the space between the pattern included in the first cell and the pattern included in the second cell satisfies the first spatial condition and the second spatial condition. For example, it can be determined whether the space between the pattern adjacent to the first boundary in the first cell and the pattern adjacent to the first boundary in the second cell meets the first spatial condition and the second spatial condition. If the obtained result is that the space does not satisfy the first space condition and the second space condition, operation S260 may be performed. Otherwise, if the space meets the first space condition and the second space condition, the method of designing the layout of the integrated circuit can be completed. Herein, when the space between the patterns is stated as satisfying the space condition, it will be understood that the value of the space satisfying the space condition is equal to or greater than the value corresponding to the space condition.

The first space that refers to the smallest space between patterns assigned the same color in the layout may be preset in the operation of designing the layout of the integrated circuit. The operation of judging whether the space satisfies the first spatial condition may include judging between the patterns in the first cell adjacent to the first boundary and the patterns in the second cell adjacent to the first boundary that are assigned the same color Is the first space or a larger space.

The second space refers to the smallest space between patterns assigned different colors in the layout. The operation of judging whether the space satisfies the second spatial condition may include judging between a pattern in the first cell adjacent to the first boundary and a pattern in the second cell adjacent to the first boundary that is assigned a different color Is the space a second space or a larger space? In this case, the second space is smaller than the first space.

In operation S260, the pattern contained in the second cell may be subjected to color Reverse operation. The color inversion operation may be an operation of exchanging different colors (for example, the first color and the second color) previously assigned to the pattern with each other. The color inversion operation may be referred to as a color exchange operation. To satisfy the first spatial condition and the second spatial condition, the color of the pattern assigned the first color may be inverted from the first color to the second color, and the color of the pattern assigned the second color may be the second color Invert to the first color. The color inversion operation will be explained in detail with reference to the integrated circuit 43 shown in FIG. 4.

FIG. 3 illustrates a part of an integrated circuit 30 including a pattern satisfying a first spatial condition and a second spatial condition according to an exemplary embodiment of the inventive concept.

Referring to FIG. 3, the integrated circuit 30 may include first patterns 31 and 32 (as represented by PT1 shown in FIG. 3) assigned a first color and second patterns 33 (as shown by FIG. 3) assigned a second color PT2 shown means). In this case, the first color and the second color may be different colors. Therefore, the first patterns 31 and 32 and the second pattern 33 can be formed using different masks. Here, in each figure, PT1 indicates that the corresponding pattern has been assigned a first color, and PT2 indicates that the corresponding pattern has been assigned a second color.

For example, the first patterns 31 and 32 having the first color may be transmitted to the first mask, and the second pattern 33 having the second color may be transmitted to the second mask. The first mask and the second mask may be, for example, a lithography mask having a transparent pattern to allow light transmission and an opaque pattern to block light. The first mask and the second mask can be combined with each other to form a double-patterned mask set. The first mask and the second mask may be used to expose the photoresist of the same type of pattern arranged at the same level.

The space between the two patterns 31 and 32 assigned the first color may be It is the first space S1. The first patterns 31 and 32 can satisfy the first spatial condition. As explained above with reference to FIG. 2, the first space (for example, S1) may be the smallest space between the patterns assigned the same color. For example, the first space S1 may be 100. Herein, the first space S1 may be expressed in arbitrary units (a.u.) (for example, nanometer, millimeter, micrometer, etc.). Hereinafter, the case where the first space S1 is 100 will be explained in detail.

The space between the first pattern 31 assigned the first color and the second pattern 33 assigned the second color may be a second space S2 or a larger space. The first pattern 31 and the second pattern 33 can satisfy the second spatial condition. In addition, the space between the first pattern 32 assigned the first color and the second pattern 33 assigned the second color may be the second space S2 or a larger space. The first pattern 32 and the second pattern 33 can satisfy the second spatial condition. As explained above with reference to FIG. 2, the second space (for example, S2) may be the smallest space between the patterns assigned different colors. For example, the second space S2 may be 50. Here, the second space S2 may be expressed in arbitrary units (a.u.) (for example, nanometer, millimeter, micrometer, etc.). Hereinafter, the case where the second space S2 is 50 will be explained in detail.

In an exemplary embodiment, the first patterns 31 and 32 and the second pattern 33 may be included in one cell. In an exemplary embodiment, the first pattern 31 may be included in the first cell, and the first pattern 32 and the second pattern 33 may be included in the second cell. Therefore, in the integrated circuit 30, the first patterns 31 and 32 and the second pattern 33 may be arranged in the same cell and adjacent cells to satisfy the first spatial condition and the second spatial condition.

FIG. 4 illustrates an example of a method for resolving color conflicts according to an exemplary embodiment of the inventive concept.

4, the integrated circuit 41 may include a first standard cell SC1, a second standard cell SC2, and a third standard cell SC3 placed adjacent to each other. The first standard cell SC1 may include a first pattern 411 having a first color and a second pattern 412 having a second color. The second standard cell SC2 may include a first pattern 413 having a first color and a second pattern 414 having a second color. The third standard cell SC3 may include a second pattern 415 having a second color and a first pattern 416 having a first color.

The first standard cell SC1 and the second standard cell SC2 may be adjacent to the first boundary BD1. The second pattern 412 included in the first standard cell SC1 adjacent to the first boundary BD1 and the first pattern 413 included in the second standard cell SC2 adjacent to the first boundary BD1 may have different colors. Therefore, it can be determined whether the second pattern 412 and the first pattern 413 satisfy the second spatial condition. For example, it can be determined whether the distance D0 between the second pattern 412 and the first pattern 413 is more than 50. Herein, the distance D0 can be expressed in arbitrary units (a.u.) (for example, nanometer, millimeter, micrometer, etc.).

The second standard cell SC2 and the third standard cell SC3 may be adjacent to the second boundary BD2. The second pattern 414 included in the second standard cell SC2 adjacent to the second boundary BD2 may have the same color as the second pattern 415 included in the third standard cell SC3 adjacent to the second boundary BD2. Therefore, it can be determined whether the second pattern 414 and the second pattern 415 satisfy the first spatial condition. For example, it can be determined whether the distance D1 between the second pattern 414 and the second pattern 415 is 100 or more. Here, the distance D1 can be expressed in arbitrary units (a.u.) (for example, nanometer, millimeter, micrometer, etc.).

In this example, the distance between the second pattern 414 and the second pattern 415 is smaller than the first space S1. Therefore, the second pattern 414 and the second pattern 415 do not satisfy the first spatial condition. As described above, when the distance between two patterns assigned the same color does not satisfy the first spatial condition, a color violation occurs between the two patterns. In the operation of placing and routing the standard cells defining the integrated circuit, color conflicts may occur due to color violations.

In the integrated circuit 42, the third standard cell SC3 may be placed apart from the second standard cell SC2 by a predetermined distance d to resolve color conflicts. Therefore, the distance D1' between the second pattern 414 and the second pattern 415 may be the first space S1 or a larger space. Therefore, the second pattern 414 and the second pattern 415 can satisfy the first spatial condition. According to the cell spacing method described above, the area of the integrated circuit 42 can be increased.

In the integrated circuit 43, the second pattern 415 and the first pattern 416 included in the third standard cell SC3 may perform a color inversion operation to resolve color conflicts. As a result of the color inversion operation, the second pattern 415' may have a first color, and the first pattern 416' may have a second color. Therefore, since the second pattern 414 and the second pattern 415' have different colors, the second pattern 414 and the second pattern 415' can satisfy the second spatial condition. In this example, the distance D1 between the second pattern 414 and the second pattern 415' may be the second space S2 or a larger space. Therefore, the second pattern 414 and the second pattern 415' can satisfy the second spatial condition.

5 is a flowchart of a method S200A for designing a cell according to an exemplary embodiment of the inventive concept.

Referring to FIG. 5, a method S200A for designing a cell according to an exemplary embodiment It may correspond to an example of operation S200 shown in FIG. 2. Therefore, for convenience of explanation, further description of the processes and elements previously described with reference to FIG. 2 may be omitted herein.

In operation S500, a first color and a second color may be assigned to the first pattern and the second pattern, respectively. The first color and the second color may be different colors and may correspond to the first mask and the second mask, respectively. The first pattern and the second pattern may be different patterns contained in the same layer. Hereinafter, the pattern assigned the first color will be referred to as the first pattern, and the pattern assigned the second color will be referred to as the second pattern.

In an exemplary embodiment, since the color decomposition is performed using two colors (for example, the first color and the second color), two masks may be used to form the first pattern and the second pattern. Therefore, the first pattern and the second pattern according to the exemplary embodiment may be formed using double patterning technology (DPT).

In operation S520, the first boundary space may be determined based on the first space. The first space may be the smallest space between the patterns assigned the same color. The first boundary space may be a space between the first pattern adjacent to the first boundary and the first boundary. In this article, when the boundary space is stated to be determined based on certain factors, it should be understood that the value of the boundary space is set based on the certain factors.

In operation S540, the second boundary space may be determined to be different from the first boundary space based on the second space. The second space may be the smallest space between patterns assigned different colors. The second boundary space may be a space between the second pattern adjacent to the first boundary and the first boundary. In an exemplary embodiment, the second boundary space may be determined to be smaller than the first boundary space.

With reference to the general operation of designing cells, it is often impossible to predict cells to be placed adjacent to each other. According to an exemplary embodiment of the present inventive concept, the first boundary space and the second boundary space may be determined in two cells placed adjacent to each other at the first boundary such that the patterns arranged on both sides of the first boundary satisfy The first space condition and the second space condition. The first boundary space and the second boundary space that satisfy the first space condition and the second space condition may be referred to herein as boundary criteria.

6A illustrates an example of an integrated circuit including cells designed according to a comparative example.

6A, the integrated circuit 61 may include a first standard cell 601 and a second standard cell 602 placed adjacent to the first boundary BD1. The first standard cell 601 may include first patterns 601a and 601b assigned a first color. The distance bf between the first pattern 601a and the first boundary BD1 may be equal to the distance bf between the first pattern 601b and the first boundary BD1. For example, the distance bf may be 25. Herein, the distance bf can be expressed in arbitrary units (a.u.) (for example, nanometer, millimeter, micrometer, etc.). The second standard cell 602 may include a first pattern 602a assigned a first color and a second pattern 602b assigned a second color. The distance bs between the first pattern 602a and the first boundary BD1 may be equal to the distance bs between the second pattern 602b and the first boundary BD1. For example, the distance bs may be 75. Here, the distance bs can be expressed in arbitrary units (a.u.) (eg, nanometer, millimeter, micrometer, etc.).

Since the first pattern 601a and the first pattern 602a arranged on both sides of the first boundary BD1 have the same color, the first patterns 601a and 602a should satisfy the first spatial condition. In this example, since the first pattern 601a and the first pattern 602a The distance between them is 100, so the first patterns 601a and 602a satisfy the first spatial condition. Since the first pattern 601b and the second pattern 602b arranged on both sides of the first boundary BD1 have different colors, the first pattern 601b and the second pattern 602b should satisfy the second spatial condition. In this example, since the distance between the first pattern 601b and the second pattern 602b is 100, the first pattern 601b and the second pattern 602b satisfy the second spatial condition. However, since the distance (for example, 100) between the first pattern 601b and the second pattern 602b is much larger than the second space S2 (for example, 50), space efficiency may be reduced.

6B illustrates an example of an integrated circuit including cells designed according to an exemplary embodiment of the inventive concept.

Referring to FIG. 6B, the integrated circuit 62 may include a first standard cell 611 and a second standard cell 612 placed adjacent to each other at the first boundary BD1. The first standard cell 611 may include first patterns 611a and 611b assigned a first color. The distance Bf between the first pattern 611a and the first boundary BD1 may be equal to the distance Bf between the first pattern 611b and the first boundary BD1. For example, the distance Bf may be 25. The second standard cell 612 may include a first pattern 612a assigned a first color and a second pattern 612b assigned a second color. The first boundary space B1 between the first pattern 612a and the first boundary BD1 may be different from the second boundary space B2 between the second pattern 612b and the first boundary BD1.

The second boundary space B2 may be determined to be smaller than the first boundary space B1. For example, the first boundary space B1 may be 75, and the second boundary space B2 may be 25. Therefore, since the first colors arranged on both sides of the first boundary BD1 and having different colors The space between the pattern 611b and the second pattern 612b is 50, so the first pattern 611b and the second pattern 612b satisfy the second spatial condition, and the space efficiency can be improved.

The space RS′ between the second boundary BD2 arranged opposite to the first boundary BD1 and the second pattern 612b included in the second standard cell 612 in the integrated circuit 62 may be larger than the first row arranged opposite to the first boundary BD1 The space RS between the second boundary BD2 and the second pattern 602b included in the second standard cell 602 in the integrated circuit 61. Therefore, in an exemplary embodiment, other patterns may be arranged in the space RS′ in the second standard cell 612. That is, in the exemplary embodiment, the extra space RS′ in the second standard cell 612 can be used for other patterns. In an exemplary embodiment, the longitudinal dimension of the second standard cell 612 may be reduced. Therefore, according to an exemplary embodiment, the area utilized in the standard cell can be optimized as the space RS′ increases.

7A to 7F illustrate examples of integrated circuits including cells designed according to exemplary embodiments of the inventive concept.

Referring to FIG. 7A, the integrated circuit 71 may include a first standard cell 711 and a second standard cell 712 placed adjacent to each other at the first boundary BD1. The first standard cell 711 may include a first pattern 711a assigned a first color and a second pattern 711b assigned a second color. The second standard cell 712 may include a first pattern 712a assigned a first color.

The direction in which the first pattern 711a and the second pattern 711b extend in the first standard cell 711 may be substantially parallel to the first boundary BD1. In this case, the first pattern 711a and the second pattern 711b may be referred to as vertical patterns. The first boundary space B1 may be different from the second boundary space B2. The first boundary space B1 is the first pattern 711a and the first A space between a boundary BD1, and a second boundary space B2 is a space between the first boundary BD1 and the second pattern 711b. The first boundary space B1 may be larger than the second boundary space B2.

Since the first patterns 711a and 712a arranged on both sides of the first boundary BD1 are assigned a first color, the first patterns 711a and 712a should satisfy the first spatial condition. In this case, the space between the first patterns 711a and 712a (for example, the sum of the space Bf between the first pattern 712a and the first boundary BD1 and the first boundary space B1) may be an edge-to-edge space, and It may be equal to or greater than the first space S1.

Since the first pattern 712a and the second pattern 711b arranged on both sides of the first boundary BD1 are assigned the first color and the second color, respectively, the first pattern 712a and the second pattern 711b should satisfy the second spatial condition. In this case, the space between the first pattern 712a and the second pattern 711b (for example, the sum of the space Bf between the first pattern 712a and the first boundary BD1 and the second boundary space B2) may be edge-to-edge Space, and may be equal to or greater than the second space S2.

Referring to FIG. 7B, the integrated circuit 72 may include a first standard cell 721 and a second standard cell 712 placed adjacent to each other at the first boundary BD1. The first standard cell 721 may include a first pattern 721a assigned a first color and a second pattern 711b assigned a second color. The second standard cell 712 may include a first pattern 712a assigned a first color. The integrated circuit 72 may have substantially the same configuration as the integrated circuit 71 shown in FIG. 7A except for the first pattern 721a included in the first standard cell 721.

The extending direction of the first pattern 721a included in the first standard cell 721 may be substantially perpendicular to the first boundary BD1, and the extending direction of the second pattern 711b may be implemented Qualitatively parallel to the first boundary BD1. In this case, the first pattern 721a may be referred to as a horizontal pattern, and the second pattern 711b may be referred to as a vertical pattern. The first boundary space B1' may be larger than the first boundary space B1 shown in FIG. 7A.

Since the first patterns 721a and 712a arranged on both sides of the first boundary BD1 are assigned a first color, the first patterns 721a and 712a should satisfy the first spatial condition. In this case, the space between the first patterns 721a and 712a (for example, the sum of the space Bf between the first pattern 712a and the first boundary BD1 and the first boundary space B1′) may be an edge-to-top space, And may be larger than the first space S1'. In this case, the first space S1' may be larger than the first space S1 shown in FIG. 7A.

Referring to FIG. 7C, the integrated circuit 73 may include a first standard cell 731 and a second standard cell 712 placed adjacent to each other at the first boundary BD1. The first standard cell 731 may include a first pattern 711a assigned a first color and a second pattern 731b assigned a second color. The second standard cell 712 may include a first pattern 712a assigned a first color. Except for the second pattern 731b included in the first standard cell 731, the integrated circuit 73 may accordingly have substantially the same configuration as the integrated circuit 71 shown in FIG. 7A.

The extending direction of the first pattern 711a included in the first standard cell 731 may be substantially parallel to the first boundary BD1, and the extending direction of the second pattern 731b may be substantially perpendicular to the first boundary BD1. The second boundary space B2' may be larger than the second boundary space B2 shown in FIG. 7A.

Since the first pattern 712a and the second pattern 731b arranged on both sides of the first boundary BD1 are assigned the first color and the second color, respectively, the first pattern 712a and the second pattern 731b should satisfy the second spatial condition. In this case, the space between the first pattern 712a and the second pattern 731b (for example, the sum of the space Bf between the first pattern 712a and the first boundary BD1 and the second boundary space B2') may be the edge to The head space can be larger than the second space S2'. In this case, the second space S2' may be equal to or larger than the second space S2 shown in FIG. 7A.

Referring to FIG. 7D, the integrated circuit 74 may include a first standard cell 741 and a second standard cell 712 placed adjacent to each other at the first boundary BD1. The first standard cell 741 may include a first pattern 721a assigned a first color and a second pattern 731b assigned a second color. The second standard cell 712 may include a first pattern 712a assigned a first color. Except for the first pattern 721a and the second pattern 731b included in the first standard cell 741, the integrated circuit 74 may have substantially the same configuration as the integrated circuit 71 shown in FIG. 7A.

The extending directions of the first pattern 721a and the second pattern 731b included in the first standard cell 741 may be substantially perpendicular to the first boundary BD1. The first boundary space B1′ may be larger than the first boundary space B1 shown in FIG. 7A, and the second boundary space B2′ may be larger than the second boundary space B2 shown in FIG. 7A.

Since the first patterns 721a and 712a arranged on both sides of the first boundary BD1 are assigned a first color, the first patterns 721a and 712a should satisfy the first spatial condition. In this case, the space between the first patterns 721a and 712a (for example, the sum of the space Bf between the first pattern 712a and the first boundary BD1 and the first boundary space B1′) may be an edge-to-top space, And may be equal to or greater than the first space S1'. As for the first pattern 712a and the second pattern arranged on both sides of the first boundary BD1 The first color and the second color are assigned to 731b, respectively, so the first pattern 712a and the second pattern 731b should satisfy the second spatial condition. In this case, the space between the first pattern 712a and the second pattern 731b (for example, the sum of the space Bf between the first pattern 712a and the first boundary BD1 and the second boundary space B2') may be the edge to The head space, and may be equal to or greater than the second space S2'.

7E, the integrated circuit 75 may include a first standard cell 711 and a second standard cell 752 placed adjacent to each other at the first boundary BD1. The first standard cell 711 may include a first pattern 711a assigned a first color and a second pattern 711b assigned a second color. The second standard cell 752 may include a first pattern 752a assigned a first color. The integrated circuit 75 may have substantially the same configuration as the integrated circuit 71 shown in FIG. 7A except for the first pattern 752a included in the second standard cell 752.

The extending direction of the first pattern 752a included in the second standard cell 752 may be substantially perpendicular to the first boundary BD1, and the first pattern 752a may be arranged adjacent to the first pattern 711a included in the first standard cell 711. The space Bf′ between the first pattern 752a and the first boundary BD1 may be larger than the space Bf shown in FIG. 7A.

Since the first patterns 711a and 752a arranged on both sides of the first boundary BD1 are assigned a first color, the first patterns 711a and 752a should satisfy the first spatial condition. In this case, the space between the first patterns 711a and 752a (for example, the sum of the space Bf′ between the first pattern 752a and the first boundary BD1 and the first boundary space B1) may be a top-to-side space, And may be equal to or greater than the first space S1'.

Referring to FIG. 7F, the integrated circuit 76 may include a first standard cell 711 and a second standard cell 762 placed adjacent to each other at the first boundary BD1. First standard cell 711 may include a first pattern 711a assigned a first color and a second pattern 711b assigned a second color. The second standard cell 762 may include a first pattern 752a' assigned a first color. Except for the first pattern 752a' included in the second standard cell 762, the integrated circuit 76 may have a configuration substantially the same as the integrated circuit 71 shown in FIG. 7A.

The extending direction of the first pattern 752a' included in the second standard cell 762 may be substantially perpendicular to the first boundary BD1, and the first pattern 752a' may be adjacent to the second pattern 711b included in the first standard cell 711 arrangement. The space Bf' between the first pattern 752a' and the first boundary BD1 may be larger than the space Bf shown in FIG. 7A.

Since the first pattern 752a' and the second pattern 711b arranged on both sides of the first boundary BD1 are assigned the first color and the second color, respectively, the first pattern 752a' and the second pattern 711b should satisfy the second space condition. In this case, the space between the first pattern 752a' and the second pattern 711b (eg, the sum of the space Bf' between the first pattern 752a' and the first boundary BD1 and the second boundary space B2) may be Top-to-side space, and may be equal to or greater than the second space S2'.

8 is a flowchart of a modified example of a method of designing a cell according to an exemplary embodiment of the inventive concept.

The method of designing a cell according to the exemplary embodiment shown in FIG. 8 may be performed after operation S540 shown in FIG. 5. Therefore, for convenience of explanation, further description of the processes and elements previously described with reference to FIG. 5 may be omitted herein.

In operation S800, one of the first color and the second color may be assigned to the pattern arranged adjacent to the second boundary. The second boundary may be a boundary arranged opposite to the first boundary in the same cell. In an exemplary embodiment, operation S800 may be substantially the same The operation S500 is shown in FIG. 5. For example, the first boundary shown in FIG. 5 may be called a right boundary, and the first pattern and the second pattern adjacent to the first boundary may be called right patterns. In this case, the second boundary may be referred to as a left boundary, and the pattern adjacent to the second boundary may be referred to as a left pattern. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in an exemplary embodiment, the first boundary may be a left boundary, and the second boundary may be a right boundary.

In operation S820, the boundary space between the pattern adjacent to the second boundary and the second boundary may be determined to be equal to or greater than the minimum value of the first boundary space and the second boundary space. In this case, the first boundary space may be the space between the first right pattern adjacent to the first boundary and the first boundary, and the second boundary space may be the second right pattern adjacent to the first boundary and the first boundary The space between.

9 illustrates an example of a cell designed using the method shown in FIG. 8 according to an exemplary embodiment of the inventive concept.

Referring to FIG. 9, the cell 90 may be defined by the cell boundary CB including the first boundary BD1 and the second boundary BD2. The first boundary BD1 may be called a right boundary, and the second boundary BD2 may be called a left boundary. The cell 90 may include a first right pattern 91 having a first color, a second right pattern 92 having a second color, and a left pattern 93 having a first color.

The first boundary space B1 between the first right pattern 91 and the first boundary BD1 may be larger than the second boundary space B2 between the second right pattern 92 and the first boundary BD1. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in the exemplary embodiment, the first boundary between the first right pattern 91 and the first boundary BD1 The space B1 may be smaller than the second boundary space B2 between the second right pattern 92 and the first boundary BD1.

The left boundary space Bf between the left pattern 93 and the second boundary BD2 may be determined to be equal to or greater than the minimum value of the first boundary space B1 and the second boundary space B2. Therefore, in the operation of placing the cell, between each pattern included in the cell to be placed adjacent to the cell 90 on the left side of the cell 90 and the left pattern 93 included in the cell 90, the first One space condition and the second space condition.

FIG. 10 illustrates an example of applying a color inversion operation to an integrated circuit according to an exemplary embodiment of the inventive concept.

Referring to FIG. 10, the integrated circuit 101 may include a first standard cell 1001 to a fourth standard cell 1004 placed along the first direction DR1. The first standard cell 1001 may include a first left pattern 1001a, a second left pattern 1001b, and a right pattern 1001c. The boundary space B2 (for example, 25) of the first left pattern 1001a may be smaller than the boundary space B1 (for example, 75) of the second left pattern 1001b. The boundary space Bf of the right pattern 1001c may be equal to or greater than the minimum value of the left boundary spaces B1 and B2. For example, the boundary space Bf may be 25.

The second standard cell 1002 may include a first left pattern 1002a, a second left pattern 1002b, and a right pattern 1002c. The boundary space B1 (for example, 75) of the first left pattern 1002a may be larger than the boundary space B2 (for example, 25) of the second left pattern 1002b. The boundary space Bf of the right pattern 1002c may be equal to or greater than the minimum value of the left boundary spaces B1 and B2. For example, the boundary space Bf may be 25.

In this case, since the right pattern 1001c and the first left pattern 1002a With the same color, the space between the right pattern 1001c and the first left pattern 1002a should satisfy the first space condition. In this example, since the space between the right pattern 1001c and the first left pattern 1002a is 100, the space between the right pattern 1001c and the first left pattern 1002a satisfies the first spatial condition. In addition, since the right pattern 1001c and the second left pattern 1002b have different colors, the space between the right pattern 1001c and the second left pattern 1002b should satisfy the second spatial condition. In this example, since the space between the right pattern 1001c and the second left pattern 1002b is 50, the space between the right pattern 1001c and the second left pattern 1002b satisfies the second spatial condition.

The third standard cell 1003 may include a first right pattern 1003a, a second right pattern 1003b, and a left pattern 1003c, and the boundary space B1 (eg, 75) of the first right pattern 1003a may be larger than the boundary space B2 of the second right pattern 1003b (For example, 25). The boundary space Bf of the left pattern 1003c may be equal to or greater than the minimum value of the right boundary spaces B1 and B2. For example, the boundary space Bf may be 25.

In this case, since the right pattern 1002c and the left pattern 1003c have the same color, the space between the right pattern 1002c and the left pattern 1003c should satisfy the first spatial condition. In this example, since the space between the right pattern 1002c and the left pattern 1003c is 50, the space between the right pattern 1002c and the left pattern 1003c does not satisfy the first spatial condition. Therefore, a color conflict occurs between the right pattern 1002c and the left pattern 1003c.

The fourth standard cell 1004 may include a first left pattern 1004a, a second left pattern 1004b, and a right pattern 1004c, and the boundary space B1 (eg, 75) of the first left pattern 1004a may be larger than the boundary space B2 of the second left pattern 1004b (For example, 25). The boundary space Bf of the right pattern 1004c may be equal to or greater than the minimum value of the left boundary spaces B1 and B2. For example, the boundary space Bf may be 25.

In this case, since the second right pattern 1003b and the second left pattern 1004b have the same color, the space between the second right pattern 1003b and the second left pattern 1004b should satisfy the first spatial condition. In this example, since the space between the second right pattern 1003b and the second left pattern 1004b is 50, the space between them does not satisfy the first space condition. Therefore, a color conflict occurs between the second right pattern 1003b and the second left pattern 1004b.

The integrated circuit 102 can perform a color inversion operation on the third standard cell 1003 to solve the color conflict between the second standard cell 1002 and the third standard cell 1003 and the third standard cell 1003 and the fourth standard cell The color conflict between yuan 1004. Therefore, the left pattern 1003c' and the second right pattern 1003b' may change from the second color to the first color, and the first right pattern 1003a' may change from the first color to the second color.

Therefore, the right pattern 1002c and the left pattern 1003c' may have different colors, and the space between the right pattern 1002c and the left pattern 1003c' may satisfy the second spatial condition, thereby solving the color conflict. In addition, the second right pattern 1003b' and the second left pattern 1004b may have different colors, and the space between the second right pattern 1003b' and the second left pattern 1004b may satisfy the second spatial condition, thereby solving the color conflict.

FIG. 11 is a flowchart of a modified example of a method of designing a cell according to an exemplary embodiment of the inventive concept.

Referring to FIG. 11, the method of designing a cell according to the present exemplary embodiment may be performed after operation S540 shown in FIG. 5. Therefore, for ease of explanation, we can save A brief explanation of the previously described process is provided.

In operation S1100, one of the first color and the second color may be assigned to the pattern adjacent to the second boundary. In an exemplary embodiment, the second boundary may be a boundary arranged opposite to the first boundary in the same cell. In an exemplary embodiment, operation S1100 may be substantially the same as operation S800 shown in FIG. 8. For example, the first boundary shown in FIG. 5 may be a right boundary, and the first pattern and the second pattern adjacent to the first boundary may be referred to as right patterns. In this case, the second boundary may be the left boundary, and the pattern adjacent to the second boundary may be referred to as the left pattern. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in an exemplary embodiment, the first boundary may be a left boundary, and the second boundary may be a right boundary.

In operation S1120, the boundary space between each pattern adjacent to the second boundary and the second boundary may be determined to be the same value, which is equal to or greater than the minimum value of the first boundary space and the second boundary space. In this case, the first boundary space may be the space between the first right pattern adjacent to the first boundary and the first boundary, and the second boundary space may be the second right pattern adjacent to the first boundary and the first boundary The space between.

FIG. 12 illustrates an example of a cell designed using the method shown in FIG. 11 according to an exemplary embodiment of the inventive concept.

Referring to FIG. 12, the cell 120 may be defined by a cell boundary CB including a first boundary BD1 and a second boundary BD2. The first boundary BD1 may be called a right boundary, and the second boundary BD2 may be called a left boundary. The cell 120 may include a first right pattern 121 having a first color, a second right pattern 122 having a second color, and left patterns 123 and 124 having a first color. However, the exemplary embodiments of the inventive concept are not Only this. For example, in an exemplary embodiment, the left patterns 123 and 124 may have a second color.

In an exemplary embodiment, the first boundary space B1 between the first right pattern 121 and the first boundary BD1 may be larger than the second boundary space B2 between the second right pattern 122 and the first boundary BD1. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in an exemplary embodiment, the first boundary space B1 between the first right pattern 121 and the first boundary BD1 may be smaller than the second boundary space B2 between the second right pattern 122 and the first boundary BD1.

In an exemplary embodiment, the first left boundary space Bf between the left pattern 123 and the second boundary BD2 may be equal to the second left boundary space Bf between the left pattern 124 and the second boundary BD2. In this case, the first left boundary space Bf and the second left boundary space Bf may be determined to be equal to or greater than the minimum values of the first boundary space B1 and the second boundary space B2. Therefore, in the operation of placing the cell, between the patterns included in the cell to be placed on the left side of the cell 120 and the left patterns 123 and 124 included in the cell 120, the first spatial condition can be satisfied And the second space condition.

FIG. 13 illustrates an example of applying a color inversion operation to the integrated circuit 132 according to an exemplary embodiment of the inventive concept.

Referring to FIG. 13, the integrated circuit 131 may include first standard cells 1301 to fourth standard cells 1304 arranged along the first direction DR1. The first standard cell 1301 may include a first left pattern 1301a and a second left pattern 1301b and a first right pattern 1301c and a second right pattern 1301d. The boundary space B1 (for example, 75) of the first right pattern 1301c may be larger than the boundary space B2 (for example, 25) of the second right pattern 1301d. the first The boundary space Bf of the left pattern 1301a and the second left pattern 1301b may be equal to or greater than the minimum value of the right boundary spaces B1 and B2. For example, the boundary space Bf may be 25.

The second standard cell 1302 may include a first left pattern 1302a and a second left pattern 1302b and a first right pattern 1302c and a second right pattern 1302d. The boundary space B1 (for example, 75) of the first right pattern 1302c may be larger than the boundary space B2 (for example, 25) of the second right pattern 1302d. The boundary space Bf of the first left pattern 1302a and the second left pattern 1302b may be equal to or greater than the minimum value of the right boundary spaces B1 and B2. For example, the boundary space Bf may be 25.

In this case, since the first right pattern 1301c and the first left pattern 1302a have the same color, the space between the first right pattern 1301c and the first left pattern 1302a should satisfy the first spatial condition. In this example, since the space between the first right pattern 1301c and the first left pattern 1302a is 100, the space between them satisfies the first space condition. In addition, since the second right pattern 1301d and the second left pattern 1302b have different colors, the space between the second right pattern 1301d and the second left pattern 1302b should satisfy the second spatial condition. In this example, since the space between the second right pattern 1301d and the second left pattern 1302b is 50, the space between them satisfies the second space condition.

The third standard cell 1303 may include a first left pattern 1303a and a second left pattern 1303b and a first right pattern 1303c and a second right pattern 1303d. The boundary space B1 (for example, 75) of the first left pattern 1303a may be larger than the boundary space B2 (for example, 25) of the second left pattern 1303b. The boundary space Bf of the first right pattern 1303c and the second right pattern 1303d may be equal to or greater than the minimum value of the left boundary spaces B1 and B2. Examples In other words, the boundary space Bf may be 25.

In this case, since the first right pattern 1302c and the first left pattern 1303a have the same color, the space between the first right pattern 1302c and the first left pattern 1303a should satisfy the first spatial condition. In this example, since the space between the first right pattern 1302c and the first left pattern 1303a is 150, the space between them satisfies the first space condition.

Since the second right pattern 1302d and the second left pattern 1303b have the same color, the space between the second right pattern 1302d and the second left pattern 1303b should satisfy the first spatial condition. In this example, since the space between the second right pattern 1302d and the second left pattern 1303b is 50, the space between them does not satisfy the first space condition. Therefore, a color conflict occurs between the second right pattern 1302d and the second left pattern 1303b.

The fourth standard cell 1304 may include a first left pattern 1304a and a second left pattern 1304b and a first right pattern 1304c and a second right pattern 1304d. The boundary space B1 (for example, 75) of the first right pattern 1304c may be larger than the boundary space B2 (for example, 25) of the second right pattern 1304d. The boundary space Bf of the first left pattern 1304a and the second left pattern 1304b may be equal to or greater than the minimum value of the right boundary spaces B1 and B2. For example, the boundary space Bf may be 25.

The integrated circuit 132 can perform a color inversion operation on the third standard cell 1303 to solve the color conflict between the second standard cell 1302 and the third standard cell 1303 and the third standard cell 1303 and the fourth standard cell The color conflict between yuan 1304. Therefore, the first left pattern 1303a' and the first right pattern 1303c' and the second right pattern 1303d' may change from the first color to the second color, and the second left pattern 1303b' may change from the second color to the first color.

Therefore, the second right pattern 1302d and the second left pattern 1303b' may have different colors, and the space between the second right pattern 1302d and the second left pattern 1303b' may satisfy the second space condition, thereby solving the color conflict. In addition, the first right pattern 1303c' and the first left pattern 1304a may have different colors, and the space between the first right pattern 1303c' and the first left pattern 1304a may satisfy the second spatial condition, thereby solving the color conflict. In addition, the second right pattern 1303d' and the second left pattern 1304b may have different colors, and the space between the second right pattern 1303d' and the second left pattern 1304b may satisfy the second spatial condition, thereby solving the color conflict.

FIG. 14 is a flowchart of a method S200B for designing cells according to an exemplary embodiment of the inventive concept.

Referring to FIG. 14, the method S200B of designing a cell according to the present exemplary embodiment may correspond to an example of operation S200 shown in FIG. 2. Therefore, for convenience of explanation, further description of the processes and elements previously described with reference to FIG. 2 may be omitted herein.

In operation S1400, the first to third patterns may be assigned to the first to third colors, respectively. The first to third colors may be different from each other and correspond to the first to third masks, respectively. The first pattern to the third pattern may be different patterns included in the same layer. Hereinafter, the pattern assigned the first color will be referred to as the first pattern (for example, PT1), the pattern assigned the second color will be referred to as the second pattern (for example, PT2), and assigned the third The pattern of colors will be referred to as a third pattern (for example, PT3).

In the exemplary embodiment, since the color decomposition process is performed using three colors (for example, the first color to the third color), the first pattern to the third pattern may be formed using three masks. Therefore, the first to third patterns according to the exemplary embodiment may be formed using triple patterning technology (TPT).

In operation S1420, the first boundary space may be determined based on the first space. The first space may be the smallest space between the patterns assigned the same color. The first boundary space may be a space between the first pattern adjacent to the first boundary and the first boundary.

In operation S1440, the second boundary space may be determined to be different from the first boundary space based on the second space. The second space may be the smallest space between patterns assigned different colors. The second boundary space may be a space between the second pattern adjacent to the first boundary and the first boundary. In an exemplary embodiment, the second boundary space may be determined to be smaller than the first boundary space.

With reference to the general operation of designing cells, it is often impossible to predict cells to be placed adjacent to each other. According to an exemplary embodiment of the inventive concept, when two cells are placed adjacent to each other at the first boundary, the first boundary space and the second boundary space may be determined such that the patterns arranged on both sides of the first boundary Satisfy the first space condition and the second space condition.

In operation S1460, a third boundary space may be determined based on the first space. In an exemplary embodiment, the third boundary space may be equal to or larger than the second boundary space, and equal to or smaller than the first boundary space.

FIG. 15 illustrates a product including cells designed by the method shown in FIG. 14 Examples of circuits.

Referring to FIG. 15, the integrated circuit 150 may include a first standard cell 1501 and a second standard cell 1502 placed adjacent to each other at the first boundary BD1. The first standard cell 1501 may include first patterns 1501a and 1501b assigned a first color. The space Bf between the first pattern 1501a and the first boundary BD1 may be equal to the space Bf between the first pattern 1501b and the first boundary BD1. For example, the space Bf may be 25.

The second standard cell 1502 may include a first pattern 1502a assigned a first color, a second pattern 1502b assigned a second color, and a third pattern 1502c assigned a third color. The space between the first pattern 1502a and the first boundary BD1 may be the first boundary space B1, the space between the second pattern 1502b and the first boundary BD1 may be the second boundary space B2, and the third pattern 1502c and the first The space between the boundary BD1 may be the third boundary space B3. At least two of the first boundary space B1, the second boundary space B2, and the third boundary space B3 may be different from each other.

According to an exemplary embodiment, the second boundary space B2 may be determined to be smaller than the first boundary space B1. For example, the first boundary space B1 may be 75, and the second boundary space B2 may be 25. In addition, the third boundary space B3 may be determined to be equal to or larger than the second boundary space B2 and equal to or smaller than the first boundary space B1. For example, the third boundary space B3 may be 50.

According to the present exemplary embodiment, since the space between the first patterns 1501a and 1502a arranged on both sides of the first boundary BD1 and having the same color is 100, the space between them satisfies the first space condition. In addition, since the first pattern 1501b and the second pattern having different colors are arranged on both sides of the first boundary BD1 The space between 1502b is 50, so the space between them meets the second space condition.

16 illustrates an example of a cell designed using the method shown in FIG. 14 according to an exemplary embodiment of the inventive concept.

16, the cell 160 may be defined by the cell boundary CB including the first boundary BD1 and the second boundary BD2. The first boundary BD1 may be called a right boundary, and the second boundary BD2 may be called a left boundary. The cell 160 may include a first right pattern 161 having a first color, a second right pattern 162 having a second color, a third right pattern 163 having a third color, and a left pattern 164 having a first color. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in an exemplary embodiment, the left pattern 164 may have a second color or a third color.

The first right pattern 161, the second right pattern 162, and the third right pattern 163 can be generated using the method shown in FIG. In an exemplary embodiment, the first boundary space B1 between the first right pattern 161 and the first boundary BD1 may be larger than the second boundary space B2 between the second right pattern 162 and the first boundary BD1. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in an exemplary embodiment, the first boundary space B1 between the first right pattern 161 and the first boundary BD1 may be smaller than the second boundary space B2 between the second right pattern 162 and the first boundary BD1.

In an exemplary embodiment, the third boundary space B3 between the third right pattern 163 and the first boundary BD1 may be equal to or larger than the second boundary space B2 and equal to or smaller than the first boundary space B1. In an exemplary embodiment, when the second boundary space B2 is larger than the first boundary space B1, the third boundary space B3 may be equal to or larger than the first boundary space B1 and equal to or smaller than the second boundary space B2.

The left pattern 164 may be generated using a method substantially similar to the method shown in FIG. 8. For example, first, one of the first color to the third color may be assigned to the left pattern 164 adjacent to the second boundary BD2. Subsequently, the boundary space Bf between the left pattern 164 adjacent to the second boundary BD2 and the second boundary BD2 may be determined to be equal to or greater than the minimum value of the first boundary space B1, the second boundary space B2, and the third boundary space B3 . Therefore, in the operation of placing the cell, between each pattern included in the cell to be placed on the left side of the cell 160 and the left pattern 164 included in the cell 160, the first spatial condition and the first Two space conditions.

FIG. 17 illustrates an example of applying a color inversion operation to an integrated circuit including the cell shown in FIG. 16 according to an exemplary embodiment of the inventive concept.

Referring to FIG. 17, the integrated circuit 171 may include first to fourth standard cells 1701 to 1704 arranged in the first direction DR1. The first standard cell 1701 may include a first left pattern 1701a to a third left pattern 1701c and a right pattern 1701d. The boundary space B3 (for example, 50) of the third left pattern 1701c may be larger than the boundary space B2 (for example, 25) of the first left pattern 1701a and smaller than the boundary space B1 (for example, 75) of the second left pattern 1701b. The boundary space Bf of the right pattern 1701d may be equal to or greater than the minimum value of the left boundary spaces B1, B2, and B3. For example, the boundary space Bf may be 25.

The second standard cell 1702 may include a first left pattern 1702a to a third left pattern 1702c and a right pattern 1702d. The boundary space B3 (for example, 50) of the third left pattern 1702c may be larger than the boundary space B2 (for example, 25) of the second left pattern 1702b and smaller than the boundary space B1 (for example, 75) of the first left pattern 1702a. Right pattern 1702d The boundary space Bf may be the minimum value of the left boundary spaces B1, B2, and B3. For example, the boundary space Bf may be 25.

In this case, since the right pattern 1701d and the first left pattern 1702a have the same color, the space between the right pattern 1701d and the first left pattern 1702a should satisfy the first spatial condition. In this example, since the space between the right pattern 1701d and the first left pattern 1702a is 100, the space between them satisfies the first space condition. In addition, since the right pattern 1701d and the second left pattern 1702b have different colors, the space between the right pattern 1701d and the second left pattern 1702b should satisfy the second spatial condition. In this example, since the space between the right pattern 1701d and the second left pattern 1702b is 50, the space between them satisfies the second space condition.

The third standard cell 1703 may include a first right pattern 1703a to a third right pattern 1703c and a left pattern 1703d. The boundary space B3 (for example, 50) of the third right pattern 1703c may be larger than the boundary space B2 (for example, 25) of the second right pattern 1703b and smaller than the boundary space B1 (for example, 75) of the first right pattern 1703a. The boundary space Bf of the left pattern 1703d may be equal to or greater than the minimum value of the right boundary spaces B1, B2, and B3. For example, the boundary space Bf may be 25.

In this case, since the right pattern 1702d and the left pattern 1703d have the same color, the space between the right pattern 1702d and the left pattern 1703d should satisfy the first spatial condition. In this example, since the space between the right pattern 1702d and the left pattern 1703d is 50, the space between them does not satisfy the first spatial condition. Therefore, a color conflict occurs between the right pattern 1702d and the left pattern 1703d.

The fourth standard cell 1704 may include a first left pattern 1704a to a third left image Case 1704c and right pattern 1704d. The boundary space B3 (for example, 50) of the third left pattern 1704c may be larger than the boundary space B2 (for example, 25) of the second left pattern 1704b and smaller than the boundary space B1 (for example, 75) of the first left pattern 1704a. The boundary space Bf of the right pattern 1704d may be equal to or greater than the minimum value of the left boundary spaces B1, B2, and B3. For example, the boundary space Bf may be 25.

In this case, since the second right pattern 1703b and the second left pattern 1704b have the same color, the space between the second right pattern 1703b and the second left pattern 1704b should satisfy the first spatial condition. In this example, since the space between the second right pattern 1703b and the second left pattern 1704b is 50, the space between them does not satisfy the first space condition. Therefore, a color conflict occurs between the second right pattern 1703b and the second left pattern 1704b.

Since the third right pattern 1703c and the third left pattern 1704c have the same color, the space between the third right pattern 1703c and the third left pattern 1704c should satisfy the first spatial condition. In this example, since the space between the third right pattern 1703c and the third left pattern 1704c is 100, the space between them satisfies the first spatial condition. Similarly, since the space between the first right pattern 1703a and the first left pattern 1704a is 150, the space between them satisfies the first spatial condition.

The integrated circuit 172 can perform a color inversion operation on the third standard cell 1703 to solve the color conflict between the second standard cell 1702 and the third standard cell 1703 and the third standard cell 1703 and the fourth standard cell The color conflict between yuan 1704. In the present exemplary embodiment, the color inversion operation may be performed between the first color and the second color, and the color inversion operation may not be performed on the third color. Therefore, the left picture Case 1703d' and the second right pattern 1703b' can be changed from the second color to the first color, and the first right pattern 1703a' can be changed from the first color to the second color.

Therefore, the right pattern 1702d and the left pattern 1703d' may have different colors, and the space between the right pattern 1702d and the left pattern 1703d' may satisfy the second spatial condition. Therefore, color conflicts can be resolved. In addition, the second right pattern 1703b' and the second left pattern 1704b may have different colors, and the space between the second right pattern 1703b' and the second left pattern 1704b may satisfy the second spatial condition. Therefore, color conflicts can be resolved.

18 illustrates an example of a cell designed using the method shown in FIG. 14 according to an exemplary embodiment of the inventive concept.

Referring to FIG. 18, the cell 180 may be defined by a cell boundary CB including a first boundary BD1 and a second boundary BD2. The first boundary BD1 may be called a right boundary, and the second boundary BD2 may be called a left boundary. The cell 180 may include a first right pattern 181 having a first color, a second right pattern 182 having a second color, a third right pattern 183 having a third color, and a first left pattern 184 having a first color and Second left pattern 185. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in an exemplary embodiment, the first left pattern 184 and the second left pattern 185 may have a second color or a third color.

The first right pattern 181, the second right pattern 182, and the third right pattern 183 can be generated using the method shown in FIG. In an exemplary embodiment, the first boundary space B1 between the first right pattern 181 and the first boundary BD1 may be larger than the second boundary space B2 between the second right pattern 182 and the first boundary BD1. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in the exemplary embodiment, the first The first boundary space B1 between the right pattern 181 and the first boundary BD1 may be smaller than the second boundary space B2 between the second right pattern 182 and the first boundary BD1.

In an exemplary embodiment, the third boundary space B3 between the third right pattern 183 and the first boundary BD1 may be equal to or larger than the second boundary space B2 and equal to or smaller than the first boundary space B1. In an exemplary embodiment, when the second boundary space B2 is larger than the first boundary space B1, the third boundary space B3 may be equal to or larger than the first boundary space B1 and equal to or smaller than the second boundary space B2.

The first left pattern 184 and the second left pattern 185 may be generated using a method substantially similar to the method described with reference to FIG. 11. For example, first, one of the first color to the third color may be assigned to the first left pattern 184 and the second left pattern 185 adjacent to the second boundary BD2. Subsequently, the boundary spaces Bf between the first left pattern 184 and the second left pattern 185 adjacent to the second boundary BD2 and the second boundary BD2 may be determined to be equal to each other and equal to or greater than the first boundary space B1 and the second boundary space The minimum value of B2 and the third boundary space B3. Therefore, in the operation of placing the cell, between each pattern included in the cell to be placed on the left side of the cell 180 and the first left pattern 184 and the second left pattern 185 included in the cell 180, The first space condition and the second space condition can be satisfied.

FIG. 19 illustrates an example of applying a color inversion operation to an integrated circuit including the cell shown in FIG. 18 according to an exemplary embodiment of the inventive concept.

Referring to FIG. 19, the integrated circuit 191 may include first standard cells 1901 to fourth standard cells 1904 arranged in the first direction DR1. The first standard cell 1901 may include a first right pattern 1901a to a third right pattern 1901c and a first left pattern 1901d And the second left pattern 1901e. The boundary space B3 (for example, 50) of the third right pattern 1901c may be larger than the boundary space B2 (for example, 25) of the second right pattern 1901b and smaller than the boundary space B1 (for example, 75) of the first right pattern 1901a. The boundary space Bf of the first left pattern 1901d and the second left pattern 1901e may be equal to or greater than the minimum value of the right boundary spaces B1, B2, and B3. For example, the boundary space Bf may be 25.

The second standard cell 1902 may include a first right pattern 1902a to a third right pattern 1902c and a first left pattern 1902d and a second left pattern 1902e. The boundary space B3 (for example, 50) of the third right pattern 1902c may be larger than the boundary space B2 (for example, 25) of the second right pattern 1902b and smaller than the boundary space B1 (for example, 75) of the first right pattern 1902a. The boundary space Bf of the first left pattern 1902d and the second left pattern 1902e may be equal to or greater than the minimum value of the right boundary spaces B1, B2, and B3. For example, the boundary space Bf may be 25.

In this case, since the first right pattern 1901a and the first left pattern 1902d have the same color, the space between the first right pattern 1901a and the first left pattern 1902d should satisfy the first spatial condition. In this example, since the space between the first right pattern 1901a and the first left pattern 1902d is 100, the space between them satisfies the first space condition. In addition, since the second right pattern 1901b and the second left pattern 1902e have different colors, the space between the second right pattern 1901b and the second left pattern 1902e should satisfy the second spatial condition. In this example, since the space between the second right pattern 1901b and the second left pattern 1902e is 50, the space between them satisfies the second space condition.

The third standard cell 1903 may include a first left pattern 1903a to a third left image Case 1903c and the first right pattern 1903d and the second right pattern 1903e. The boundary space B3 (for example, 50) of the third left pattern 1903c may be larger than the boundary space B2 (for example, 25) of the second left pattern 1903b and smaller than the boundary space B1 (for example, 75) of the first left pattern 1903a. The boundary space Bf of the first right pattern 1903d and the second right pattern 1903e may be equal to or greater than the minimum value of the left boundary spaces B1, B2, and B3. For example, the boundary space Bf may be 25.

In this case, since the second right pattern 1902b and the second left pattern 1903b have the same color, the space between the second right pattern 1902b and the second left pattern 1903b should satisfy the first spatial condition. In this example, since the space between the second right pattern 1902b and the second left pattern 1903b is 50, the space between them does not satisfy the first space condition. Therefore, a color conflict occurs between the second right pattern 1902b and the second left pattern 1903b.

Since the third right pattern 1902c and the third left pattern 1903c have the same color, the space between the third right pattern 1902c and the third left pattern 1903c should satisfy the first spatial condition. In this example, since the space between the third right pattern 1902c and the third left pattern 1903c is 100, the space between them satisfies the first spatial condition. Similarly, since the space between the first right pattern 1902a and the first left pattern 1903a is 150, the space between them satisfies the first space condition.

The fourth standard cell 1904 may include a first right pattern 1904a to a third right pattern 1904c and a first left pattern 1904d and a second left pattern 1904e. The boundary space B3 (for example, 50) of the third right pattern 1904c may be larger than the boundary space B2 (for example, 25) of the second right pattern 1904b and smaller than the boundary space B1 of the first right pattern 1904a (For example, 75). The boundary space Bf of the first left pattern 1904d and the second left pattern 1904e may be equal to or greater than the minimum value of the right boundary spaces B1, B2, and B3. For example, the boundary space Bf may be 25.

In this case, since the first right pattern 1903d and the first left pattern 1904d have the same color, the space between the first right pattern 1903d and the first left pattern 1904d should satisfy the first spatial condition. In this example, since the space between the first right pattern 1903d and the first left pattern 1904d is 50, the space between them does not satisfy the first space condition. Therefore, a color conflict occurs between the first right pattern 1903d and the first left pattern 1904d.

Similarly, since the second right pattern 1903e and the second left pattern 1904e have the same color, the space between the second right pattern 1903e and the second left pattern 1904e should satisfy the first spatial condition. In this example, since the space between the second right pattern 1903e and the second left pattern 1904e is 50, the space between them does not satisfy the first space condition. Therefore, a color conflict occurs between the second right pattern 1903e and the second left pattern 1904e.

The integrated circuit 192 can perform a color inversion operation on the third standard cell 1903 to solve the color conflict between the second standard cell 1902 and the third standard cell 1903 and the third standard cell 1903 and the fourth standard cell Color conflict between yuan 1904. In this example, the color inversion operation is performed between the first color and the second color, and the color inversion operation is not performed on the third color. Therefore, the first left pattern 1903a' and the first right pattern 1903d' and the second right pattern 1903e' may change from the first color to the second color, and the second left pattern 1903b' may change from the second color to the first color.

Therefore, the second right pattern 1902b and the second left pattern 1903b' may have different colors, and the space between the second right pattern 1902b and the second left pattern 1903b' may satisfy the second space condition, thereby solving the color conflict. In addition, the first right pattern 1903d' and the first left pattern 1904d may have different colors, and the space between the first right pattern 1903d' and the first left pattern 1904d may satisfy the second spatial condition, thereby solving the color conflict. In addition, the second right pattern 1903e' and the second left pattern 1904e may have different colors, and the space between the second right pattern 1903e' and the second left pattern 1904e may satisfy the second space condition, thereby solving the color conflict.

20 is a flowchart of a method of designing a cell according to an exemplary embodiment of the inventive concept.

Referring to FIG. 20, a method S200C for designing a cell according to the present exemplary embodiment may correspond to an example of operation S200 shown in FIG. Therefore, for convenience of explanation, further description of the processes and elements previously described with reference to FIG. 2 may be omitted herein.

In operation S2000, the first to fourth patterns may be assigned to the first to fourth colors, respectively. The first to fourth colors may be different from each other and correspond to the first to fourth masks, respectively. The first to fourth patterns may be different patterns contained in the same layer. Hereinafter, the pattern assigned the first color will be referred to as the first pattern (for example, PT1), and the pattern assigned the second color will be referred to as the second pattern (for example, PT2), assigned the third color The pattern of will be called a third pattern (for example, PT3), and the pattern assigned the fourth color will be called a fourth pattern (for example, PT4).

In the exemplary embodiment, since the color decomposition is performed using four colors (for example, the first color to the fourth color), the first pattern to the fourth pattern It can be formed using four masks. Therefore, the first to fourth patterns according to the exemplary embodiment may be formed using quadruple patterning technology (QPT).

In operation S2020, the first boundary space may be determined based on the first space. The first space may be the smallest space between the patterns assigned the same color. The first boundary space may be a space between the first pattern adjacent to the first boundary and the first boundary.

In operation S2040, the second boundary space may be determined to be different from the first boundary space based on the second space. The second space may be the smallest space between patterns assigned different colors. The second boundary space may be a space between the second pattern adjacent to the first boundary and the first boundary. In the present exemplary embodiment, the second boundary space may be determined to be smaller than the first boundary space.

With reference to the general operation of designing cells, it is often impossible to predict cells to be placed adjacent to each other. According to an exemplary embodiment of the inventive concept, when two cells are placed adjacent to each other at the first boundary, the first boundary space and the second boundary space may be determined such that the patterns arranged on both sides of the first boundary Satisfy the first space condition and the second space condition.

In operation S2060, it may be determined that the third boundary space and the fourth boundary space are the same space based on the first space. In the present exemplary embodiment, the third boundary space and the fourth boundary space may be equal to or larger than the second boundary space and equal to or smaller than the first boundary space.

FIG. 21 illustrates an example embodiment of an integrated circuit including cells designed using the method shown in FIG. 20 according to an exemplary embodiment of the inventive concept.

Referring to FIG. 21, the integrated circuit 210 may include a first standard cell 2101 and a second standard cell 2102 placed adjacent to each other at the first boundary BD1. The first standard cell 2101 may include first patterns 2101a and 2101b assigned a first color. The space Bf between the first pattern 2101a and the first boundary BD1 may be equal to the space Bf between the first pattern 2101b and the first boundary BD1. For example, the space Bf may be 25.

The second standard cell 2102 may include a first pattern 2102a assigned a first color, a second pattern 2102b assigned a second color, a third pattern 2102c assigned a third color, and a fourth assigned The fourth pattern of colors 2102d. The space between the first pattern 2102a and the first boundary BD1 may be the first boundary space B1, the space between the second pattern 2102b and the first boundary BD1 may be the second boundary space B2, and the third pattern 2102c and the first boundary The space between BD1 may be the third boundary space B3, and the space between the fourth pattern 2102d and the first boundary BD1 may be the fourth boundary space B4. At least two of the first boundary space B1, the second boundary space B2, the third boundary space B3, and the fourth boundary space B4 may be different from each other.

According to the present exemplary embodiment, the second boundary space B2 may be determined to be smaller than the first boundary space B1. For example, the first boundary space B1 may be 75 and the second boundary space B2 may be 25. According to the present exemplary embodiment, the third boundary space B3 may be determined to be equal to the fourth boundary space B4. Each of the third boundary space B3 and the fourth boundary space B4 may be determined to be equal to or larger than the second boundary space B2 and equal to or smaller than the first boundary space B1. For example, each of the third boundary space B3 and the fourth boundary space B4 may be 50.

According to the present exemplary embodiment, since it is arranged on both sides of the first boundary BD1 The space between the first patterns 2101a and 2102a having the same color on the top is 100, so the space between them meets the first space condition. In addition, since the space between the first pattern 2101b and the second pattern 2102b that are arranged on both sides of the first boundary BD1 and have different colors is 50, the space therebetween satisfies the second space condition.

FIG. 22 illustrates an example of applying a color inversion operation to an integrated circuit including cells designed using the method shown in FIG. 20 according to an exemplary embodiment of the inventive concept.

Referring to FIG. 22, the integrated circuit 221 may include first standard cells 2201 to fourth standard cells 2204 arranged in the first direction DR1. The first standard cell 2201 may include a first left pattern 2201a to a fourth left pattern 2201d and a right pattern 2201e. Each of the boundary spaces B3 and B4 (for example, 50) of the third left pattern 2201c and the fourth left pattern 2201d may be larger than the boundary space B2 (for example, 25) of the first left pattern 2201a and smaller than the second left pattern 2201b Boundary space B1 (for example, 75). The boundary space Bf of the right pattern 2201e may be equal to or greater than the minimum value of the left boundary spaces B1, B2, B3, and B4. For example, the boundary space Bf may be 25.

The second standard cell 2202 may include a first left pattern 2202a to a fourth left pattern 2202d and a right pattern 2202e. Each of the boundary spaces B3 and B4 (eg, 50) of the third left pattern 2202c and the fourth left pattern 2202d may be larger than the boundary space B2 (eg, 25) of the second left pattern 2202b and smaller than the first left pattern 2202a Boundary space B1 (for example, 75). The boundary space Bf of the right pattern 2202e may be equal to or greater than the minimum value of the left boundary spaces B1, B2, B3, and B4. For example, the boundary space Bf may be 25.

In this case, since the right pattern 2201e and the second left pattern 2202b have different colors, the space between the right pattern 2201e and the second left pattern 2202b should satisfy the second space condition. In this example, since the space between the right pattern 2201e and the second left pattern 2202b is 50, the space between them satisfies the second space condition. In addition, since the right pattern 2201e and the first left pattern 2202a have the same color, the space between the right pattern 2201e and the first left pattern 2202a should satisfy the first space condition. In this example, since the space between the right pattern 2201e and the first left pattern 2202a is 100, the space between them satisfies the first space condition.

The third standard cell 2203 may include a first right pattern 2203a to a fourth right pattern 2203d and a left pattern 2203e. Each of the boundary spaces B3 and B4 (for example, 50) of the third right pattern 2203c and the fourth right pattern 2203d may be larger than the boundary space B2 (for example, 25) of the second right pattern 2203b and smaller than the first right pattern 2203a Boundary space B1 (for example, 75). The boundary space Bf of the left pattern 2203e may be equal to or greater than the minimum value of the right boundary spaces B1, B2, B3, and B4. For example, the boundary space Bf may be 25.

In this case, since the right pattern 2202e and the left pattern 2203e have the same color, the space between the right pattern 2202e and the left pattern 2203e should satisfy the first space condition. In this example, since the space between the right pattern 2202e and the left pattern 2203e is 50, the space between them does not satisfy the first space condition. Therefore, a color conflict occurs between the right pattern 2202e and the left pattern 2203e.

The fourth standard cell 2204 may include a first left pattern 2204a to a fourth left pattern 2204d and a right pattern 2204e. The third left pattern 2204c and the fourth left pattern 2204d Each of the boundary spaces B3 and B4 (eg, 50) may be larger than the boundary space B2 (eg, 25) of the second left pattern 2204b and smaller than the boundary space B1 (eg, 75) of the first left pattern 2204a. The boundary space Bf of the right pattern 2204e may be equal to or greater than the minimum value of the left boundary spaces B1, B2, B3, and B4. For example, the boundary space Bf may be 25.

In this case, since the second right pattern 2203b and the second left pattern 2204b have the same color, the space between the second right pattern 2203b and the second left pattern 2204b should satisfy the first spatial condition. In this example, since the space between the second right pattern 2203b and the second left pattern 2204b is 50, the space between them does not satisfy the first space condition. Therefore, a color conflict occurs between the second right pattern 2203b and the second left pattern 2204b.

Since the third right pattern 2203c and the third left pattern 2204c have the same color, the space between the third right pattern 2203c and the third left pattern 2204c should satisfy the first spatial condition. In this example, since the space between the third right pattern 2203c and the third left pattern 2204c is 100, the space between them satisfies the first spatial condition. Similarly, since the space between the first right pattern 2203a and the first left pattern 2204a is 150, the space between them satisfies the first spatial condition.

The integrated circuit 222 can perform a color inversion operation on the third standard cell 2203 to solve the color conflict between the second standard cell 2202 and the third standard cell 2203 and the third standard cell 2203 and the fourth standard cell The color conflict between yuan 2204. In the present exemplary embodiment, the color inversion operation may be performed between the first color and the second color, and the color inversion operation may not be performed for the third color and the fourth color. Therefore, the left pattern 2203e' and the second right pattern 2203b' may change from the second color to the first color, and the first right pattern 2203a' may change from the first color to the second color.

Therefore, the right pattern 2202e and the left pattern 2203e' may have different colors, and the space between the right pattern 2202e and the left pattern 2203e' may satisfy the second space condition, thereby solving the color conflict. In addition, the second right pattern 2203b' and the second left pattern 2204b may have different colors, and the space between the second right pattern 2203b' and the second left pattern 2204b may satisfy the second space condition, thereby solving the color conflict.

23 is a flowchart of a method of designing a cell according to an exemplary embodiment of the inventive concept.

Referring to FIG. 23, the method S200D of designing a cell according to an exemplary embodiment may correspond to an example of operation S200 shown in FIG. Therefore, for convenience of explanation, further description of the processes and elements described with reference to FIG. 2 may be omitted herein.

In operation S2300, the first to fourth patterns may be assigned to the first to fourth colors, respectively. The first to fourth colors may be different from each other and correspond to the first to fourth masks, respectively. The first to fourth patterns may be different patterns contained in the same layer. Hereinafter, the pattern assigned the first color will be referred to as the first pattern (for example, PT1), and the pattern assigned the second color will be referred to as the second pattern (for example, PT2), assigned the third color The pattern of will be called a third pattern (for example, PT3), and the pattern assigned the fourth color will be called a fourth pattern (for example, PT4).

In the exemplary embodiment, since the color decomposition is performed using four colors (first color to fourth color), the first to fourth patterns may be formed using four masks. Therefore, the first to fourth figures according to the exemplary embodiment Cases can be formed using quadruple patterning technology.

In operation S2320, the first boundary space may be determined based on the first space. The first space may be the smallest space between the patterns assigned the same color. The first boundary space may be a space between the first pattern adjacent to the first boundary and the first boundary.

In operation S2340, the second boundary space may be determined to be different from the first boundary space based on the second space. The second space may be the smallest space between patterns assigned different colors. The second boundary space may be a space between the second pattern adjacent to the first boundary and the first boundary. In an exemplary embodiment, the second boundary space may be determined to be smaller than the first boundary space.

With reference to the general operation of designing cells, it is often impossible to predict cells to be placed adjacent to each other. According to an exemplary embodiment of the inventive concept, when two cells are placed adjacent to each other at the first boundary, the first boundary space and the second boundary space may be determined such that the patterns arranged on both sides of the first boundary Satisfy the first space condition and the second space condition.

In operation S2360, a third boundary space may be determined based on the first space. In an exemplary embodiment, the third boundary space may be equal to or larger than the second boundary space and equal to or smaller than the first boundary space. In operation S2380, the fourth boundary space may be determined to be different from the third boundary space based on the second space.

24 illustrates an example embodiment of an integrated circuit including cells designed using the method shown in FIG. 23 according to an exemplary embodiment of the inventive concept.

Referring to FIG. 24, the integrated circuit 240 may include a first standard cell 2401 and a second standard cell 2402 placed adjacent to each other at the first boundary BD1. First standard cell The cell 2401 may include first patterns 2401a and 2401b assigned a first color, and the space Bf between the first pattern 2401a and the first boundary BD1 may be equal to the space Bf between the first pattern 2401b and the first boundary BD1. For example, the space Bf may be 25. The second standard cell 2402 may include a first pattern 2402a assigned a first color, a second pattern 2402b assigned a second color, a third pattern 2402c assigned a third color, and a fourth assigned The fourth pattern of colors 2402d. The space between the first pattern 2402a and the first boundary BD1 may be the first boundary space B1, the space between the second pattern 2402b and the first boundary BD1 may be the second boundary space B2, and the third pattern 2402c and the first boundary The space between BD1 may be the third boundary space B3, and the space between the fourth pattern 2402d and the first boundary BD1 may be the fourth boundary space B4. At least two of the first boundary space B1, the second boundary space B2, the third boundary space B3, and the fourth boundary space B4 may be different from each other.

According to this example, the second boundary space B2 may be determined to be smaller than the first boundary space B1. For example, the first boundary space B1 may be 75, and the second boundary space B2 may be 25. According to the present example, the third boundary space B3 may be determined to be different from the fourth boundary space B4. Each of the third boundary space B3 and the fourth boundary space B4 may be determined to be equal to or larger than the second boundary space B2 and equal to or smaller than the first boundary space B1. According to the present example, the fourth boundary space B4 may be determined to be larger than the third boundary space B3. For example, the third boundary space B3 may be 25, and the fourth boundary space B4 may be 75.

According to this example, since the space between the first patterns 2401a and 2402a that are arranged on both sides of the first boundary BD1 and have the same color is 100, they are The space between meets the first space condition. In addition, since the space between the first pattern 2401b and the second pattern 2402b, which are arranged on both sides of the first boundary BD1 and have different colors, is 50, the space therebetween satisfies the second space condition.

FIG. 25 illustrates an example of applying a color inversion operation to an integrated circuit including cells designed using the method shown in FIG. 23 according to an exemplary embodiment of the inventive concept.

Referring to FIG. 25, the integrated circuit 251 may include first standard cells 2501 to fourth standard cells 2504 arranged in the first direction DR1. The first standard cell 2501 may include a first left pattern 2501a to a fourth left pattern 2501d and a right pattern 2501e. The boundary spaces B2 and B3 of the first left pattern 2501a and the third left pattern 2501c may be the same (for example, 25). The boundary spaces B1 and B4 of the second left pattern 2501b and the fourth left pattern 2501d may be the same (eg, 75) and larger than the boundary spaces B2 and B3 of the first left pattern 2501a and the third left pattern 2501c. The boundary space Bf of the right pattern 2501e may be equal to or greater than the minimum value of the left boundary spaces B1 to B4. For example, the boundary space Bf may be 25.

The second standard cell 2502 may include a first left pattern 2502a to a fourth left pattern 2502d and a right pattern 2502e. The boundary spaces B2 and B3 of the second left pattern 2502b and the fourth left pattern 2502d may be the same (for example, 25). The boundary spaces B1 and B4 of the first left pattern 2502a and the third left pattern 2502c may be the same (eg, 75), and may be larger than the boundary spaces B2 and B3 of the second left pattern 2502b and the fourth left pattern 2502d. The boundary space Bf of the right pattern 2502e may be equal to or greater than the minimum value of the left boundary spaces B1 to B4. For example, the boundary space Bf may be 25.

In this case, since the right pattern 2501e and the second left pattern 2502b have different colors, the space between the right pattern 2501e and the second left pattern 2502b should satisfy the second space condition. In this example, since the space between the right pattern 2501e and the second left pattern 2502b is 50, the space between them satisfies the second space condition. In addition, since the right pattern 2501e and the first left pattern 2502a have the same color, the space between the right pattern 2501e and the first left pattern 2502a should satisfy the first space condition. In this example, since the space between the right pattern 2501e and the first left pattern 2502a is 100, the space between them satisfies the first space condition.

The third standard cell 2503 may include a first right pattern 2503a to a fourth right pattern 2503d and a left pattern 2503e. The boundary spaces B2 and B3 of the second right pattern 2503b and the third right pattern 2503c may be the same space (for example, 25). The boundary spaces B1 and B4 of the first and fourth right patterns 2503a and 2503d may be the same (for example, 75), and may be larger than the boundary spaces B2 and B3 of the second and third right patterns 2503b and 2503c. The boundary space Bf of the left pattern 2503e may be equal to or greater than the minimum value of the right boundary spaces B1 to B4. For example, the boundary space Bf may be 25.

In this case, since the right pattern 2502e and the left pattern 2503e have the same color, the space between the right pattern 2502e and the left pattern 2503e should satisfy the first space condition. In this example, since the space between the right pattern 2502e and the left pattern 2503e is 50, the space between them does not satisfy the first space condition. Therefore, a color conflict occurs between the right pattern 2502e and the left pattern 2503e.

The fourth standard cell 2504 may include a first left pattern 2504a to a fourth left pattern 2504d and a right pattern 2504e. The second left pattern 2504b and the third left pattern 2504c The boundary spaces B2 and B3 may be the same (for example, 25). The boundary spaces B1 and B4 of the first left pattern 2504a and the fourth left pattern 2504d may be the same (eg, 75), and may be larger than the boundary spaces B2 and B3 of the second left pattern 2504b and the third left pattern 2504c. The boundary space Bf of the right pattern 2504e may be equal to or greater than the minimum value of the left boundary spaces B1 to B4. For example, the boundary space Bf may be 25.

In this case, since the second right pattern 2503b and the second left pattern 2504b have the same color, the space between the second right pattern 2503b and the second left pattern 2504b should satisfy the first spatial condition. In this example, since the space between the second right pattern 2503b and the second left pattern 2504b is 50, the space between them does not satisfy the first space condition. Therefore, a color conflict occurs between the second right pattern 2503b and the second left pattern 2504b.

In addition, since the fourth right pattern 2503d and the fourth left pattern 2504d have the same color, the space between the fourth right pattern 2503d and the fourth left pattern 2504d should satisfy the first spatial condition. In this example, since the space between the fourth right pattern 2503d and the fourth left pattern 2504d is 150, the space between them satisfies the first spatial condition.

Since the third right pattern 2503c and the third left pattern 2504c have the same color, the space between the third right pattern 2503c and the third left pattern 2504c should satisfy the first spatial condition. In this example, since the space between the third right pattern 2503c and the third left pattern 2504c is 50, the space between them does not satisfy the first space condition. In addition, since the space between the first right pattern 2503a and the first left pattern 2504a is 150, the space between them satisfies the first space condition.

The integrated circuit 252 can perform a color inversion operation on the third standard cell 2503 to solve the color conflict between the second standard cell 2502 and the third standard cell 2503 and the third standard cell 2503 and the fourth standard cell The color conflict between yuan 2504. In this example, the color inversion operation can be performed between the first color and the second color, while the color inversion operation can be performed between the third color and the fourth color.

Therefore, the left pattern 2503e' and the second right pattern 2503b' may change from the second color to the first color, and the first right pattern 2503a' may change from the first color to the second color. In addition, the third right pattern 2503c' may be changed from the third color to the fourth color, and the fourth right pattern 2503d' may be changed from the fourth color to the third color.

Therefore, the right pattern 2502e and the left pattern 2503e' may have different colors, and the space between the right pattern 2502e and the left pattern 2503e' may satisfy the second space condition, thereby solving the color conflict. In addition, the second right pattern 2503b' and the second left pattern 2504b may have different colors, and the space between the second right pattern 2503b' and the second left pattern 2504b may satisfy the second space condition, thereby solving the color conflict. In addition, the fourth right pattern 2503d' and the fourth left pattern 2504d may have different colors, and the space between the fourth right pattern 2503d' and the fourth left pattern 2504d may satisfy the second spatial condition, thus solving the color conflict.

26 illustrates an example of the layout of an integrated circuit including cells designed according to an exemplary embodiment of the inventive concept.

Referring to FIG. 26, the integrated circuit 260 may include a first standard cell 261 and a second standard cell 262 disposed adjacent to each other at the first boundary BD1. The first standard cell 261 may include a first pattern 2611 assigned a first color, and the second standard cell 262 A first pattern 2612a assigned a first color and a second pattern 2612b assigned a second color may be included. In this case, the first patterns 2611 and 2612a and the second pattern 2612b may be patterns that constitute the same layer. In the present exemplary embodiment, the space between the first patterns 2611 and 2612a assigned the first color may be equal to or larger than the first space S1.

In addition, the second standard cell 262 may further include a contact surface 2622 electrically connected to the active area. In an example, the first patterns 2611 and 2612a and the second pattern 2612b may be formed in a layer different from the contact surface 2622. For example, the first patterns 2611 and 2612a and the second pattern 2612b may be formed above the contact surface 2622. The second standard cell 262 may further include a first power line VDD and a second power line VSS, and the extending direction of the first power line VDD and the second power line VSS may be substantially perpendicular to the first boundary BD1.

FIG. 27 is a flowchart of a method of designing an integrated circuit according to an exemplary embodiment of the inventive concept.

Referring to FIG. 27, a method of designing a layout of an integrated circuit according to an exemplary embodiment may correspond to an example of operation S10 shown in FIG. Therefore, for convenience of explanation, further description of the processes and elements previously described with reference to FIG. 1 may be omitted herein.

In operation S2700, in the first region adjacent to the first boundary, the first cell including the first colorless pattern that satisfies the first spatial condition may be designed. The first area may be a virtual space generated in the operation of designing the cell. According to an exemplary embodiment, patterns having different colors may be forced not to be formed in the first area.

In operation S2720, the first may be placed adjacent to each other at the first boundary Cell and second cell. For example, the first cell can be placed first, and the second cell can be placed adjacent to the first boundary of the first cell in the direction in which the first cell and the second cell are placed. Operation S2720 may be an example of operation S13 shown in FIG. 1. The second cell can be any cell stored in the standard cell library.

In an exemplary embodiment, the second cell may be a cell designed according to operation S2700. For example, the colorless pattern satisfying the first spatial condition may be arranged in a region adjacent to a boundary of the second cell. In an exemplary embodiment, the second cell may be a cell not designed according to operation S2700. For example, the colorless pattern that does not satisfy the first spatial condition may be arranged in the region adjacent to the one boundary of the second cell.

In an exemplary embodiment, the first cell and the second cell may be placed directly adjacent to the first boundary. In this case, the first boundary may substantially overlap one boundary of the second cell. In an exemplary embodiment, the second cell may be placed adjacent to the first boundary and spaced apart from the first boundary by a predetermined space.

In operation S2740, the first colorless pattern may be assigned the same color. According to an exemplary embodiment, after the operation of placing the cell, the first colorless pattern generated in the first area may be assigned the same color in the operation of designing the cell. Since the first colorless pattern can then be assigned the same color, the space between any two first colorless patterns in the first zone can be equal to or greater than the first space. In an exemplary embodiment, in the operation of designing the first cell, the first cell may be designed not to include patterns having different colors and arranged at the same level as the first colorless pattern in the first region.

FIG. 28 illustrates a method of assigning colors to achromatic patterns according to an exemplary embodiment of the inventive concept.

Referring to FIG. 28, the integrated circuit 280A may include a first standard cell 281 and a second standard cell 282 placed adjacent to the first boundary BD1. In the integrated circuit 280A, the first standard cell 281 may include colorless patterns 281a to 281c of unassigned colors, and the second standard cell 282 may include colorless patterns 282a and 282c of unassigned colors. In this article, CL_PT can be used in the figure to indicate a colorless pattern.

In an exemplary embodiment, the colorless patterns 281a to 281c, 282a, and 282c may correspond to via plugs. For example, the colorless patterns 281a to 281c, 282a, and 282c may be via plugs for connecting the contact surface with the first metal layer. In an example, the colorless patterns 281a to 281c, 282a, and 282c may be via plugs for connecting the first metal layer and the second metal layer.

In the operation performed after placing the first standard cell 281 and the second standard cell 282, a coloring operation for assigning colors to the colorless patterns 281a to 281c, 282a, and 282c may be performed. For example, the coloring operation may be performed in a design rule check (DRC) operation. The integrated circuit 280B may include a first standard cell 281' and a second standard cell 282' that can be generated by a coloring operation for assigning colors to the colorless patterns 281a to 281c, 282a, and 282c.

For example, the colorless patterns 281a and 282a may be assigned a first color through a coloring operation, so that the colorless patterns 281a and 282a may be referred to as first patterns 281a' and 282a'. In addition, the colorless pattern 281b may be assigned a second color through a coloring operation, so that the colorless pattern 281b may be referred to as a second pattern 281b'. In addition, The colorless patterns 281c and 282c may be assigned a third color through a coloring operation, so that the colorless patterns 281c and 282c may be referred to as third patterns 281c' and 282c'.

FIG. 29 illustrates an example of assigning three colors to four colorless patterns according to an exemplary embodiment of the inventive concept.

Referring to FIG. 29, the integrated circuit 290 may include a first standard cell 291 and a second standard cell 292 placed adjacent to each other at the first boundary BD1. The first power line VDD may be arranged parallel to the upper boundary BD_U substantially perpendicular to the first boundary BD1, and the second power line VSS may be arranged substantially parallel to the lower boundary BD_L substantially perpendicular to the first boundary BD1.

The first standard cell 291 may include patterns 291a and 291b arranged adjacent to the first boundary BD1. In the first standard cell 291 stored in the standard cell library, the patterns 291a and 291b may be colorless patterns before the cell placement operation or immediately after the cell placement operation. The second standard cell 292 may include patterns 292a and 292b arranged adjacent to the first boundary BD1. Before the operation of placing the cell or immediately after the operation of placing the cell, in the second standard cell 292 stored in the standard cell library, the patterns 292a and 292b may be colorless patterns.

To form four patterns 291a, 291b, 292a, and 292b adjacent to the first boundary BD1, when three masks are used, the four patterns 291a, 291b, 292a, and 292b must be assigned three colors. Therefore, two of the four patterns 291a, 291b, 292a, and 292b can be assigned the same color. In this case, since any two patterns assigned the same color must satisfy the first spatial condition, a color conflict that does not occur at the cell level may occur at the wafer level.

For example, if the first color is assigned to the pattern 291a, the second color is assigned to the pattern 292a, and the third color is assigned to the pattern 291b, then one of the first color to the third color must be assigned to the pattern 292b By. In this case, the pattern 292b and the pattern assigned the same color as the color assigned to the pattern 292b must satisfy the first spatial condition. Therefore, to ensure a predetermined space between the first standard cell 291 and the second standard cell 292, the second standard cell 292 may be placed apart from the first standard cell 291 by a predetermined space. Therefore, since the area of the integrated circuit 290 increases, space efficiency can be reduced.

30 illustrates an example embodiment of an integrated circuit including cells designed using the method shown in FIG. 27 according to an exemplary embodiment of the inventive concept.

Referring to FIG. 30, the integrated circuit 300 may include a first standard cell 301 and a second standard cell 302 placed adjacent to each other at the first boundary BD1. The first power line VDD may be arranged substantially parallel to the upper boundary BD_U substantially perpendicular to the first boundary BD1. The second power line VSS may be arranged substantially parallel to the lower boundary BD_L substantially perpendicular to the first boundary BD1.

According to an exemplary embodiment, the first standard cell 301 may have a first zone FZ adjacent to the first boundary BD1, and the first pattern 301a and the second pattern 301b may be arranged in the first zone FZ. In this case, the space between the first pattern 301a and the second pattern 301b may be equal to or larger than the first space S1. Therefore, after performing the coloring operation, even if the same color is assigned to the first pattern 301a and the second pattern 301b, no color conflict will occur between the first pattern 301a and the second pattern 301b.

The second standard cell 302 may include a first arranged adjacent to the first boundary BD1 The pattern 302a and the second pattern 302b, and the space between the first pattern 302a and the second pattern 302b may be determined to be equal to or larger than the second space. Therefore, even if three colors are assigned to the four patterns 301a, 301b, 302a, and 302b, no color conflict occurs between the four patterns 301a, 301b, 302a, and 302b.

FIG. 31 is a flowchart of a method of designing an integrated circuit according to an exemplary embodiment of the inventive concept.

Referring to FIG. 31, a method of designing a layout of an integrated circuit according to the present exemplary embodiment may correspond to an example of operation S10 shown in FIG. Therefore, for convenience of explanation, further description of the processes and elements previously described with reference to FIG. 1 may be omitted herein. In addition, the method of designing the layout of the integrated circuit according to the present exemplary embodiment may correspond to a modified example of the exemplary embodiment shown in FIG. 27. Therefore, for convenience of explanation, further description of the processes and elements previously described with reference to FIG. 27 may be omitted herein.

In operation S3100, a first cell including a first colorless pattern and a second colorless pattern may be designed. The first colorless pattern may be arranged in the first area adjacent to the first boundary and may satisfy the first spatial condition. The second colorless pattern may be arranged in the second area adjacent to the second boundary and may satisfy the first spatial condition. The first area and the second area may be virtual spaces generated in the operation of generating cells. According to an exemplary embodiment, it may be prohibited to generate patterns having different colors in the first area. Similarly, the generation of patterns with different colors in the second area can be prohibited.

In operation S3120, the first cell and the second cell may be placed adjacent to each other at the first boundary. For example, the first cell can be placed first, and the second The cell is placed adjacent to the first boundary of the first cell in the direction in which the first cell and the second cell are placed. Operation S3120 may be an example of operation S13 shown in FIG. 1. The second cell can be any cell stored in the standard cell library.

In operation S3140, the first color and the second colorless pattern may be assigned to the first color and the second color, respectively. In an exemplary embodiment, the first color may be the same as the second color. In an exemplary embodiment, the first color may be different from the second color.

Therefore, according to an exemplary embodiment, after the operation of placing the cell, the first colorless pattern generated in the first area may be assigned the same color in the operation of designing the cell. Since the first colorless pattern can then be assigned the same color, the space between any two first colorless patterns in the first zone can be equal to or greater than the first space.

In addition, after the operation of placing the cell, the second colorless pattern generated in the second area may be assigned the same color in the operation of designing the cell. Since the second colorless pattern can then be assigned the same color, the space between any two colorless patterns in the second zone can be equal to or greater than the first space.

FIG. 32 illustrates an exemplary embodiment of the inventive concept including an example of an integrated circuit of cells designed using the method shown in FIG. 31.

Referring to FIG. 32, the integrated circuit 320 may include a first standard cell 321, a second standard cell 322, and a third standard cell 323 arranged along the first direction. The first power line VDD may be arranged substantially parallel to the upper boundary BD_U substantially perpendicular to the first boundary BD1 and the second boundary BD2. The second power line VSS may be substantially parallel to the The first boundary BD1 and the second boundary BD2 are arranged with substantially vertical lower boundaries BD_L.

The first standard cell 321 may have a first zone FZ1 adjacent to the first boundary BD1. The first zone FZ1 may be a virtual space that may prohibit the generation of patterns assigned different colors. In the first zone FZ1, only patterns assigned the same color or uncolored patterns to be assigned the same color can be generated. In an exemplary embodiment, the first standard cell 321 may include a colorless pattern 321a disposed in the first zone FZ1.

The second standard cell 322 may have a second zone FZ2 adjacent to the first boundary BD1. The second zone FZ2 may be a virtual space that may prohibit the generation of patterns assigned different colors. In the second zone FZ2, only patterns assigned the same color or uncolored patterns to be assigned the same color can be generated. In an exemplary embodiment, the second standard cell 322 may include a colorless pattern 322a disposed in the second zone FZ2.

In an exemplary embodiment, the second standard cell 322 may further include the first pattern 322b disposed in the second zone FZ2. In this case, the space s1 between the colorless pattern 322a and the first pattern 322b may be equal to or greater than the first space S1. The colorless pattern 322a and the first pattern 322b may have the same color.

In an exemplary embodiment, the second standard cell 322 may further include a second pattern 322c arranged outside the second zone FZ2. In this case, the space s2 between the colorless pattern 322a and the second pattern 322c may be smaller than the first space S1. Therefore, the second pattern 322c may have a color different from the colorless pattern 322a. Therefore, only the patterns having the same color may be arranged in the second zone FZ2.

Even if the third pattern 322d has a color different from the colorless pattern 322a, the third pattern 322d cannot be arranged at the boundary of the second zone FZ2 or the second zone FZ2. Since the space between the colorless pattern 321a and the third pattern 322d arranged in the first zone FZ1 of the first standard cell 321 is equal to or smaller than the first space S1, when the colorless pattern 322a and the third pattern 322d are When matching the same color, a color conflict may occur between the colorless pattern 322a and the third pattern 322d.

The second standard cell 322 may further include a third zone FZ3 disposed adjacent to the second boundary BD2. The third zone FZ3 may be a virtual space that may prohibit the generation of patterns assigned different colors. In the third zone FZ3, only patterns assigned the same color or uncolored patterns to be assigned the same color can be generated. In an exemplary embodiment, the second standard cell 322 may include colorless patterns 322e and 322f disposed in the third zone FZ3. In this case, the space between the colorless patterns 322e and 322f may be equal to or larger than the first space S1.

The third standard cell 323 may have a fourth zone FZ4 disposed adjacent to the second boundary SD2. The fourth zone FZ4 may be a virtual space that may prohibit the generation of patterns assigned different colors. In the fourth zone FZ4, only patterns assigned the same color or uncolored patterns to be assigned the same color can be generated. In an exemplary embodiment, the third standard cell 323 may include colorless patterns 323a and 323b disposed in the fourth zone FZ4. In this case, the space between the colorless patterns 323a and 323b may be equal to or larger than the first space S1. In an exemplary embodiment, the colorless patterns 322e and 322f disposed in the third zone FZ3 and the colorless patterns 323a and 323b disposed in the fourth zone FZ4 may be assigned different colors.

In an exemplary embodiment, the first zone FZ1 may be generated to be spaced apart from the first boundary BD1 by a predetermined space. In an exemplary embodiment, the first zone FZ1 may be generated It is in contact with the first boundary BD1. In an exemplary embodiment, the second zone FZ2 may be generated to be spaced apart from the first boundary BD1 by a predetermined space. In an exemplary embodiment, the second zone FZ2 may be generated to be in contact with the first boundary BD1. In an exemplary embodiment, the third zone FZ3 may be generated to be spaced apart from the second boundary BD2 by a predetermined space. In an exemplary embodiment, the third zone FZ3 may be generated to be in contact with the second boundary BD2. In an exemplary embodiment, the fourth zone FZ4 may be generated to be spaced apart from the second boundary BD2 by a predetermined space. In an exemplary embodiment, the fourth zone FZ4 may be generated to be in contact with the second boundary.

33 illustrates an example of the layout of an integrated circuit including cells designed according to an exemplary embodiment of the inventive concept.

Referring to FIG. 33, the integrated circuit 331 may include a first standard cell 3311 and a second standard cell 3312 adjacent to the first boundary BD1. The first standard cell 3311 may include a pattern 3311a adjacent to the first boundary BBD1, and the first via V1 may be formed on the pattern 3311a. The second standard cell 3312 may include a first pattern 3312a and a second pattern 3312b, and the first pattern 3312a is located in the first zone FZ. In this case, the second via V2 and the third via V3 may be located on the first pattern 3312a, and the fourth via V4 may be located on the second pattern 3312b.

To form the first to third passages V1 to V3, when two masks are used, the first to third passages V1 to V3 are decomposed into two colors. Since the first zone FZ is a space that does not allow patterns with different colors, the second channel V2 and the third channel V3 can be assigned the same color. In this case, when the space between the second passage V2 and the third passage V3 is smaller than the first space S1, the second passage V2 and the third Color conflicts may occur between channels V3.

In the integrated circuit 332, in order to solve the color conflict between the second path V2 and the third path V3, the space between the second path V2' and the third path V3' may be determined to be equal to or greater than the first space S1 , So that the second path V2' and the third path V3' can satisfy the first space condition.

FIG. 34 illustrates an example of a standard cell including a cell designed according to an exemplary embodiment of the inventive concept.

Referring to FIG. 34, the standard cell SC may be defined by a cell boundary CB, and may include a plurality of fins FN, a plurality of active regions (for example, a first active region AR1 and a second active region AR2), and a plurality of conductive lines CL , And multiple contact surfaces CA. The cell boundary CB may be the outline defining the standard cell SC, and the placement and routing tool may use the cell boundary CB to identify the standard cell SC. The cell boundary CB may include four boundary lines.

The plurality of fins FN may extend in a first direction (for example, X direction), and are arranged substantially parallel to each other in a second direction (for example, Y direction) that is substantially perpendicular to the first direction. The first active area AR1 and the second active area AR2 may be arranged substantially parallel to each other and may have different conductivity types. In an exemplary embodiment, three fins FN may be arranged in each of the first active area AR1 and the second active area AR2. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in the exemplary embodiment, the number of fins FN arranged in each of the first active area AR1 and the second active area AR2 may be changed in various ways.

In this case, the plurality of fins FN arranged in the first active area AR1 and the second active area AR2 may be referred to as active fins. Although Figure 34 only says Active fins are shown, but exemplary embodiments of the inventive concept are not limited to this. The standard cell SC may further include, for example, a cell boundary CB, a first active region AR1, a region between the first active region AR1 and the second active region AR2, and/or arranged between the second active region AR2 and the cell boundary CB Dummy fins in the area between.

The plurality of conductive lines CL may extend in the second direction (for example, Y direction), and may be arranged substantially parallel to each other in the first direction (for example, X direction). In this case, the conductive line CL may be formed of a material having conductivity. For example, the conductive line CL may include polysilicon (poly-Si), metal, or metal alloy.

In an exemplary embodiment, the conductive line CL may correspond to the gate electrode. However, the exemplary embodiments of the inventive concept are not limited thereto. In an exemplary embodiment, the conductive line CL may have traces with arbitrary conductivity. In addition, although FIG. 34 illustrates an exemplary embodiment in which the standard cell SC includes three conductive lines CL, the exemplary embodiment of the inventive concept is not limited thereto. For example, in an exemplary embodiment, the standard cell SC may include at least four conductive lines, which may extend along the second direction and be arranged substantially parallel to each other along the first direction.

The plurality of contact surfaces CA may be arranged on the first active area AR1 and the second active area AR2 and electrically connected to the first active area AR1 and the second active area AR2. In an exemplary embodiment, the plurality of contact surfaces CA may be source/drain contact surfaces. In an exemplary embodiment, the plurality of contact surfaces CA may be electrical contact surfaces. The standard cell SC may further include a contact surface that can be arranged on the plurality of conductive lines CL and electrically connected to the plurality of conductive lines CL.

FIG. 35 is an exemplary embodiment according to the inventive concept, having FIG. 34 A perspective view showing an example of a layout semiconductor device. 36 is a cross-sectional view taken along line AA' shown in FIG. 34 according to an exemplary embodiment of the present inventive concept.

Referring to FIGS. 35 and 36, the semiconductor device 100a may be a block-type fin field-effect transistor (FinFET). The semiconductor device 100a may include, for example, a substrate SUB, a first insulating layer IL1, a second insulating layer IL2, first to third fins FN, and conductive lines CL. The conductive line CL may also be referred to herein as the gate electrode CL.

The substrate SUB may be a semiconductor substrate. For example, the semiconductor substrate SUB may include silicon, silicon-on-insulator (SOI), silicon sapphire, germanium (Ge), silicon germanium (SiGe), and gallium arsenic (GaAs) Any of them. The substrate SUB may be, for example, a P-type substrate and used as the first active area AR1.

The first to third fins FN may be connected to the substrate SUB. In an exemplary embodiment, the first to third fins FN may be active regions formed by doping n+-type dopants or p+-type dopants into portions vertically protruding from the substrate SUB.

The first insulating layer IL1 and the second insulating layer IL2 may include insulating materials. For example, the insulating material may include any one of an oxide layer, a nitride layer, or an oxynitride layer. The first insulating layer IL1 may be arranged on the first fin to the third fin FN. The first insulating layer IL1 may be arranged between the first to third fins FN and the gate electrode CL, and serve as a gate insulating layer. The second insulating layer IL2 may be disposed at a predetermined height in the space between the first fin to the third fin FN. The second insulating layer IL2 may be arranged in The first to third fins FN are used as device isolation layers.

The gate electrode CL may be arranged on the first insulating layer IL1 and the second insulating layer IL2. Therefore, the gate electrode CL may be configured to surround the upper portions of the first to third fins FN, the first insulating layer IL1, and the second insulating layer IL2 as shown in FIG. 36. That is, in an exemplary embodiment, the first to third fins FN may be arranged inside the gate electrode CL (for example, the gate electrode CL may be disposed at the first to third fins FN, the first insulation On the upper part of the layer IL1 and the second insulating layer IL2). The gate electrode CL may include a metal material (for example, tungsten (W) and tantalum (Ta)), its nitride, its silicon, or doped polysilicon, and may be formed using a deposition process.

37 is a perspective view of an example of a semiconductor device having the layout shown in FIG. 34 according to an exemplary embodiment of the inventive concept. FIG. 38 is a cross-sectional view taken along line AA′ shown in FIG. 37 according to an exemplary embodiment of the inventive concept.

Referring to FIGS. 37 and 38, the semiconductor device 100b may be a silicon insulator type fin field effect transistor. The semiconductor device 100b may include a substrate SUB', a first insulating layer IL1', a second insulating layer IL2', first to third fins FN', and a conductive line CL'. The conductive line CL' may also be referred to herein as the gate electrode CL'. The semiconductor device 100b according to the present exemplary embodiment is a modified example of the semiconductor device 100a shown in FIGS. 35 and 36. Therefore, for convenience of explanation, only the difference between the semiconductor device 100b and the semiconductor device 100a may be explained, and the processes and elements previously described may be omitted herein.

The first insulating layer IL1' may be arranged on the substrate SUB'. The second insulating layer IL2' may be arranged between the first to third fins FN' and the gate electrode CL', and serve as a gate Insulation. The first to third fins FN' may include semiconductor materials, such as silicon or doped silicon.

The gate electrode CL' may be arranged on the second insulating layer IL2'. Therefore, the gate electrode CL′ may be configured to surround the upper portions of the first to third fins FN′ and the second insulating layer IL2′. That is, in an exemplary embodiment, the first and second fins FN' may be arranged inside the gate electrode CL' (for example, the gate electrode CL' may be disposed at the first to third fins FN' And on the upper part of the second insulating layer IL2').

39 is a block diagram of a storage medium according to an exemplary embodiment of the inventive concept.

Referring to FIG. 39, the storage medium 500 may be a computer-readable storage medium, and the computer-readable storage medium may include any computer-readable storage medium and is used to provide commands and/or data to the computer. For example, the storage medium 500 may include magnetic or optical media (eg, magnetic disks, magnetic tapes, CD-ROM), digital versatile CD-ROM (DVD-ROM), and recordable discs (CD-R), rewritable disc (CD-RW), readable digital versatile disc (DVD-R), and rewritable digital versatile disc (DVD-RW)), volatile or non-volatile Memory (eg, random access memory (RAM), read-only memory (ROM), or flash memory) can be accessed via a universal serial bus (universal serial bus, USB) interface access to non-volatile memory, and/or micro electro mechanical system (MEMS). The storage medium 500 can be inserted into the computer, integrated into the computer, or combined with the computer via a network and/or communication medium (such as a wireless link).

Exemplary embodiments of the inventive concept can be directly implemented in hardware, in a software module executed by a processor, or in a combination of the two. Software modules can be tangibly implemented on the following non-transitory program storage devices: such as RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard drives, removable magnetic Disk, CD-ROM, or any other form of storage media known in the art. An exemplary storage medium may be coupled to the processor so that the processor can read information from and write information to the storage medium. In the alternative, storage media may be an integral part of the processor. In addition, in some aspects, the processor and the storage medium may reside in an application specific integrated circuit (ASIC). In addition, application-specific integrated circuits can reside in user terminals. As another option, the processor and the storage medium may reside as discrete components in the user terminal.

It should be understood that the inventive concept can be implemented in various forms of hardware, software, firmware, dedicated processors, or combinations thereof. In one embodiment, the inventive concept can be implemented in software as an application program that can be tangibly implemented on a program storage device. The application can be uploaded to and executed by a machine including any suitable architecture.

As shown in FIG. 39, the storage medium 500 may include a P&R program 510, a library 520, an analysis program 530, and a data structure 540. The P&R program 510 may include multiple commands to perform the method of designing an integrated circuit using a standard cell library according to an exemplary embodiment of the inventive concept described herein. For example, the storage medium 500 may store the P&R program 510. The P&R program 510 includes any of the At least one of the standard cell libraries shown in the standard cell is used to design the integrated circuit commands. The library 520 may include information about standard cells, which are units of integrated circuits.

The analysis program 530 may include multiple commands to perform a method of analyzing the integrated circuit based on the data defining the integrated circuit. The data structure 540 may include a storage space for managing data generated during the following processes: a process of using a standard cell library included in the library 520, a process of extracting specific information from a general standard cell library included in the library 520 Or the process of analyzing the characteristics of the integrated circuit using the analysis program 530.

40 is a block diagram of a memory card including an integrated circuit according to an exemplary embodiment of the inventive concept.

Referring to FIG. 40, the memory card 1000 may be configured to allow the controller 1100 and the memory 1200 to exchange electrical signals. For example, when the controller 1100 issues a command, the memory 1200 can transmit data.

Each of the controller 1100 and the memory 1200 may include an integrated circuit according to an exemplary embodiment of the inventive concept described herein. In an exemplary embodiment, at least one of the plurality of semiconductor devices included in the controller 1100 and the memory 1200 may be based on a product including cells in which at least two patterns of adjacent borders have different colors and different boundary spaces Body circuit. In an exemplary embodiment, at least one of the plurality of semiconductor devices included in the controller 1100 and the memory 1200 may include a colorless pattern that satisfies the first spatial condition in a region adjacent to the boundary The integrated circuit of the cell is implemented.

The memory card 1000 may constitute various memory cards, such as an extended memory card (memory stick card), a smart media (SM) card, a secure digital (SD) card, a mini secure digital card, and a multimedia card (multimedia card, MMC).

41 is a block diagram of a computing system including an integrated circuit according to an exemplary embodiment of the inventive concept.

Referring to FIG. 41, the computing system 2000 may include a processor 2100, a memory device 2200, a storage device 2300, a power supply 2400, and an input/output (I/O) device 2500. The computing system 2000 may communicate with a video card, sound card, memory card, or universal serial bus device, or may further include a port capable of communicating with other electronic devices.

Each of the processor 2100, the memory device 2200, the storage device 2300, the power supply 2400, and the input/output device 2500 included in the computing system 2000 may include an exemplary implementation according to the inventive concept described herein The integrated circuit of one of the examples. In an exemplary embodiment, at least one of the plurality of semiconductor devices included in the processor 2100, the memory device 2200, the storage device 2300, the power supply 2400, and the input/output device 2500 may be based on including adjacent boundaries The two patterns have integrated circuits of cells with different colors and different boundary spaces. In an exemplary embodiment, at least one of the plurality of semiconductor devices included in the processor 2100, the memory device 2200, the storage device 2300, the power supply 2400, and the input/output device 2500 may be included in the vicinity of the boundary An integrated circuit of cells with a colorless pattern that satisfies the first spatial condition is implemented in a zone of.

The processor 2100 may perform specific calculations or tasks. In an exemplary embodiment, the processor 2100 may be a microprocessor (MP) or a central processing unit (CPU). The processor 2100 may communicate with the memory device 2200, the storage device 2300, and the input/output device 2500 via a bus 2600 (eg, an address bus, a control bus, or a data bus). In an exemplary embodiment, the processor 2100 may be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

The memory device 2200 can store data required for the operation of the computing system 2000. For example, the memory device 2200 may be composed of dynamic random access memory (dynamic RAM, DRAM), mobile dynamic random access memory (mobile DRAM, MDRAM), static random access memory (static RAM, SRAM), Phase-change RAM (PRAM), ferroelectric RAM (FRAM), resistive RAM (resistive RAM, RRAM), and/or magnetic random access memory Implementation (magnetic RAM, MRAM). The storage device 2300 may include a solid-state drive (SSD), a hard disk drive, or a CD-ROM.

The input/output device 2500 may include an input unit such as a keyboard, a keypad, or a mouse, and an output unit such as a printer or a display. The power supply 2400 may supply the operating voltage required for the operation of the computing system 2000.

The integrated circuit according to one of the above-described exemplary embodiments of the inventive concept may be implemented using packets having various shapes. For example, at least some elements of an integrated circuit according to one of the above exemplary embodiments can utilize the following techniques to Installation: Package on Package (PoP) technology, ball grid array (BGA) technology, chip-scale package (CSP) technology, plastic-leaded chip carrier , PLCC) technology, plastic dual in-line package (PDIP) technology, die-in-waffle-pack technology, die-in-waffle-pack technology in-wafer-form technology, chip-on-board (COB) technology, ceramic dual in-line package (CERDIP) technology, plastic metric quad flat package (metric quad flat) -pack, MQFP) technology, thin quad flat-pack (TQFP) technology, small outline IC (SOIC) technology, shrink small outline package (SSOP) technology , Thin small outline package (thin small outline package, TSOP) technology, system-in-package (SIP) technology, multi-chip package (multi-chip package, MCP) technology, wafer-level manufacturing package (wafer- Level fabricated package (WFP) technology, or wafer-level processed stack package (WSP) technology.

Although the inventive concept has been specifically shown and explained with reference to exemplary embodiments of the inventive concept, those of ordinary skill in the art will understand that without departing from the spirit and scope of the inventive concept defined by the following patent applications Under the conditions, various forms and details of the concept of the present invention can be changed.

S200, S220, S240, S260: Operation

Claims (25)

A method for designing a layout of an integrated circuit, including: presetting a first spatial condition, the first spatial condition being defined between a pattern of the same color assigned to a first cell and a second cell in the layout The smallest acceptable space, wherein the first cell is adjacent to the second cell; a second space condition different from the first space condition is preset, and the second space condition is defined in the layout The smallest acceptable space between the first cell and the second cell that are assigned different color patterns; placing the first cell in the layout, where the first cell Including a first pattern having a first color and a second pattern having a second color different from the first color; placing the second cell between the first cell and the second cell Is placed in the layout adjacent to the first cell at the first boundary, wherein the second cell includes a third pattern having the first color and a fourth pattern having the first color, wherein The first pattern and the second pattern are adjacent to the first boundary, the third pattern and the fourth pattern are adjacent to the first boundary, wherein between the first pattern and the third pattern The first pattern-to-pattern space meets the first space condition, and the second pattern-to-pattern space between the second pattern and the fourth pattern satisfies the second space condition, wherein the first pattern and The first boundary space between the first boundary is different from the second boundary space between the second pattern and the first boundary; and A plurality of commands executable by the processor are generated to form a semiconductor device based on the layout. The method as described in item 1 of the patent application scope further includes: determining a value of the first boundary space and a value of the second boundary space, wherein the first color corresponds to the first mask, the first The two colors correspond to the second mask. The method according to item 2 of the patent application scope, wherein the value of the first boundary space is based on the first spatial condition, and the value of the second boundary space is based on the second spatial condition And the value of the second boundary space is smaller than the value of the first boundary space. The method as described in item 2 of the scope of the patent application, further comprising: assigning the first color to the fifth pattern disposed in the first cell and adjacent to the second boundary opposite to the first boundary One of the second colors; and determining the value of the third boundary space between the fifth pattern and the second boundary to be equal to or greater than the first boundary space and the second boundary space The minimum value. The method as described in item 2 of the patent application scope, further comprising: assigning the first color to a plurality of additional patterns disposed in the first cell and adjacent to a second boundary opposite to the first boundary And one of the second colors; and The value of each boundary space between the additional pattern and the second boundary is determined to be equal to or greater than the minimum value of the first boundary space and the second boundary space. The method according to item 2 of the scope of the patent application further includes: performing a color inversion operation on the second cell, wherein, when performing the color inversion operation, the second cell is adjacent to the The pattern arranged at the first boundary, and the first pattern or the second pattern satisfy the first spatial condition and the second spatial condition. The method according to item 1 of the scope of the patent application, further comprising: assigning a third color to the fifth pattern disposed in the first cell and adjacent to the first boundary, wherein the first color corresponds to A first mask, the second color corresponds to a second mask, and the third color corresponds to a third mask; and determine the value of the first boundary space, the value of the second boundary space, And the value of the third boundary space between the fifth pattern and the first boundary, wherein at least two of the values of the first boundary space to the third boundary space are different from each other. The method according to item 7 of the patent application scope, wherein the value of the first boundary space is determined based on the first space condition, and the value of the second boundary space is based on the second Spatial conditions; and the value of the third boundary space is determined based on the first boundary space set. The method according to item 8 of the patent application scope, wherein the value of the third boundary space is equal to or greater than the value of the second boundary space and equal to or less than the value of the first boundary space . The method according to item 1 of the scope of the patent application, further comprising: assigning a third color to the fifth pattern disposed in the first cell and adjacent to the first boundary, wherein the first color corresponds to A first mask, the second color corresponds to a second mask, and the third color corresponds to a third mask; for a sixth pattern disposed in the first cell and adjacent to the first boundary Assign a fourth color, where the fourth color corresponds to a fourth mask; and determine the value of the first boundary space, the value of the second boundary space, the fifth pattern and the first boundary The value of the third boundary space between and the value of the fourth boundary space between the sixth pattern and the first boundary, wherein the values of the first boundary space to the fourth boundary space At least two of them are different from each other. The method according to item 10 of the patent application scope, wherein the value of the first boundary space is determined based on the first space condition, and the value of the second boundary space is based on the second space condition It is determined that the value of the second boundary space is smaller than the value of the first boundary space, and the value of the third boundary space and the value of the fourth boundary space are based on The first boundary space is determined to have the same value. The method according to item 11 of the patent application scope, wherein each of the values of the third boundary space and the fourth boundary space is equal to or greater than the value of the second boundary space and is equal to Or less than the value of the first boundary space. The method according to item 10 of the patent application scope, wherein the value of the first boundary space is determined based on the first space condition, and the value of the second boundary space is based on the second space condition And determined, and the value of the second boundary space is less than the value of the first boundary space, the value of the third boundary space is determined based on the first boundary space, and the The value of the fourth boundary space is determined to be different from the third boundary space. The method according to item 1 of the patent application scope, wherein the first pattern and the second pattern correspond to conductive lines arranged at the same level in the integrated circuit. The method according to item 1 of the patent application scope, wherein the first pattern is a vertical pattern and the second pattern is a horizontal pattern, the extending direction of the vertical pattern is substantially parallel to the first boundary, and the The extending direction of the horizontal pattern is substantially perpendicular to the first boundary, and the first boundary space between the vertical pattern and the first boundary is smaller than that between the horizontal pattern and the first boundary The second boundary space. A method for designing the layout of integrated circuits, including: Placing the first cell in the layout, wherein the first cell includes a plurality of first colorless patterns, the plurality of first colorless patterns respectively satisfying a first spatial condition, wherein the first space The condition corresponds to the value of the smallest space between the patterns assigned the same color in the first region adjacent to the first boundary; placing the second cell between the first cell and the second cell Is placed in the layout adjacent to the first cell at the first boundary, where the first region extends parallel to the first boundary; and a plurality of commands executable by the processor are generated to be based on the The layout to form a semiconductor device, wherein the second cell includes a plurality of second colorless patterns disposed in a second area adjacent to the second boundary, the second colorless patterns satisfying the first space Conditionally, the second area extends parallel to the second boundary. The method according to item 16 of the patent application range, wherein the first cell does not include a pattern having a different color and having the same level as the first colorless pattern in the first region. The method according to item 16 of the patent application scope further includes: after placing the first cell and the second cell, assigning a first color to the first colorless pattern. The method according to item 16 of the patent application scope, wherein the first colorless pattern corresponds to a via plug. The method according to item 16 of the patent application scope, wherein the first cell further includes a plurality of third colorless patterns disposed in the third area, the third area is adjacent to Near a third boundary opposite to the first boundary, and the third colorless pattern satisfies the first spatial condition. An integrated circuit includes: a first cell, including a first pattern having a first color and a second pattern having a second color different from the first color; and a second cell, and the first Cells are adjacent, and the second cell includes a third pattern having the first color and a fourth pattern having the first color, wherein the first pattern and the second pattern have a first boundary Adjacent, and the third pattern and the fourth pattern are adjacent to the first boundary, wherein the first pattern-to-pattern space between the first pattern and the third pattern satisfies the first spatial condition , The first spatial condition defines a minimum acceptable space between patterns assigned the same color, and the second pattern-to-pattern space between the second pattern and the fourth pattern satisfies the second spatial condition, The second spatial condition defines a minimum acceptable space between patterns assigned different colors, wherein the first boundary space between the first pattern and the first boundary is different from the second pattern and all Said the second boundary space between the first boundary. The integrated circuit according to item 21 of the patent application range, wherein the first pattern, the second pattern, the third pattern, and the fourth pattern correspond to conductive lines arranged at the same level. A standard cell stored in a standard cell library includes: a plurality of first colorless patterns disposed in a first area of the standard cell adjacent to a first boundary, wherein each of the first colorless patterns is Satisfy the first space condition; to And a plurality of second colorless patterns, arranged in the second region of the standard cell adjacent to the second boundary opposite to the first boundary, wherein each of the second colorless patterns satisfies the first A spatial condition, wherein the first spatial condition corresponds to a value of a minimum space between patterns assigned the same color in the first area, wherein the first colorless pattern or the second colorless The pattern corresponds to multiple via plugs. A method of manufacturing a semiconductor device, including: presetting a first spatial condition that defines a minimum acceptable between a pattern arranged in a first cell and a second cell assigned to the same color in a layout Space, wherein the first cell is adjacent to the second cell; a second space condition different from the first space condition is preset, and the second space condition is defined to be assigned to different in the layout The smallest acceptable space between the pattern in the first cell and the second cell of the color; placing the first cell in the layout, wherein the first cell includes A first pattern of one color and a second pattern having a second color different from the first color; placing the second cell between the first cell and the second cell A boundary is placed in the layout adjacent to the first cell, wherein the second cell includes a third pattern with a first color and a fourth pattern with the first color, and the first cell And the second cell are from a plurality of cells that define an integrated circuit In, wherein the first pattern and the second pattern are adjacent to the first boundary, and the third pattern and the fourth pattern are adjacent to the first boundary; wherein the first pattern and the first pattern The first pattern-to-pattern space between the three patterns satisfies the first spatial condition, and the second pattern-to-pattern space between the second pattern and the fourth pattern satisfies the second spatial condition; and The layout forms the semiconductor device, wherein the semiconductor device is formed using a multiple patterning operation that uses different masks respectively corresponding to the different colors for the first pattern, the The second pattern, the third pattern and the fourth pattern fulfill. A method of manufacturing a semiconductor device, comprising: placing a first cell adjacent to a first boundary in a layout, wherein the first cell includes a first region, and a plurality of first colorless patterns are disposed on the first In the area; placing the second cell adjacent to the first boundary in the layout, wherein the second cell includes a first pattern having a first color and a second area, and a plurality of second colorless The pattern is arranged in the second region, and the first cell and the second cell are from a plurality of cells defining an integrated circuit, wherein the first colorless pattern satisfies the first spatial condition, The first spatial condition corresponds to the value of the smallest space between the patterns adjacent to the first boundary and assigned the same color, and the second colorless pattern satisfies the first spatial condition; for the The first colorless pattern is assigned a second color; and the semiconductor device is formed based on the layout, wherein the semiconductor device Is formed by a multiple patterning operation using the first mask and the second mask pair respectively corresponding to the first color and the second color The first pattern and the first colorless pattern assigned to the second color perform, wherein the first colorless pattern corresponds to a plurality of via plugs.

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