TWI685926B - Stacked sensor package structure - Google Patents

Abstract

The disclosure provides a stacked sensor package structure. The stacked sensor package structure includes a substrate, a semiconductor chip mounted on the substrate, a plurality of first metal wires electrically coupling the substrate and the semiconductor chip, a first supporting dam disposed on the substrate and arranged outside of the semiconductor chip, a second supporting dam disposed on the substrate and separately surrounding the first supporting dam, a sensor chip disposed on the first supporting dam and the second supporting dam, and a plurality of second metal wires electrically coupling the sensor chip and the substrate. Each of the first metal wires is at least partially embedded in the first supporting dam, and the sensor chip is spaced apart from the semiconductor chip by a distance.

Description

Stacked sensor packaging structure

The invention relates to a packaging structure, in particular to a stacked sensor packaging structure.

In order to reduce the size of the existing sensor package structure, most of the internal components are arranged in a stacked manner. However, under the structure of the existing sensor packaging structure, it is easy to derive the problem of shedding or thermal interference between internal components, which in turn affects the yield and performance of the existing sensor packaging structure.

Therefore, the inventor believes that the above-mentioned defects can be improved, and Naite devotes himself to research and cooperates with the application of scientific principles, and finally proposes a reasonable design and effectively improves the above-mentioned defects of the present invention.

An embodiment of the present invention is to provide a stacked sensor package structure, which can effectively improve the problems that may be caused by the existing sensor package structure.

An embodiment of the present invention discloses a stacked sensor package structure, including: a substrate on which a plurality of first pads and a plurality of second pads located outside the first pads are formed on the upper surface; a semiconductor A chip and a plurality of first metal wires, the semiconductor chip is mounted on the substrate and located inside the first pads, the semiconductor chip is electrically coupled to the first pads through the first metal wires A first supporting colloid, disposed on the substrate and located outside the semiconductor wafer, at least a portion of each first metal wire is embedded in the first supporting colloid; a second supporting colloid is formed in a ring shape On the substrate, the second supporting colloid is located inside the second bonding pads and surrounds the outer side of the first supporting colloid at intervals; a sensing chip and a plurality of second metal wires, the sensing chip The size is larger than the size of the semiconductor wafer, the sensing wafer is disposed on the first supporting colloid and the second supporting colloid, and is spaced apart from the semiconductor wafer, the sensing wafer passes through the second metal wires and is electrically Coupled to the second pads; a light-transmitting layer and a spacer layer, the light-transmitting layer is disposed on the sensing chip through the spacer layer; and a package body is disposed on the substrate and wraps the The outer edge of the second supporting colloid, the outer edge of the sensing wafer, the outer edge of the light-transmitting layer, and the outer edge of the spacer layer.

An embodiment of the present invention also discloses a stacked sensor package structure, which includes: a substrate on which a plurality of first bonding pads and a plurality of second bonding pads outside the first bonding pads are formed on the upper surface; A semiconductor chip and a plurality of first metal wires, the semiconductor chip is mounted on the substrate and located inside the first pads, the semiconductor chip is electrically coupled to the first solder wires through the first metal wires Pad; a first supporting colloid, disposed on the substrate and located outside the semiconductor wafer, at least a portion of each first metal wire is embedded in the first supporting colloid; a second supporting colloid, which is ring-shaped and Disposed on the substrate, the second support colloid is located inside the second pads, and surrounds the outside of the first support colloid at intervals; and a sensing chip and a plurality of second metal wires, the sensing The size of the wafer is larger than the size of the semiconductor wafer, the sensing wafer is disposed on the first supporting colloid and the second supporting colloid, and is spaced apart from the semiconductor wafer by a distance; the sensing wafer passes through the second metal wires The second pads are electrically coupled.

In summary, the stacked sensor package structure disclosed in the embodiments of the present invention supports the sensing chip by forming the first support colloid and the second support colloid on the substrate at intervals, according to The bonding effect between the elements is strengthened, and the substrate, the sensing chip, and the second supporting colloid can surround to form a small enclosed space, thereby reducing the volume of the stacked sensor packaging structure and simultaneously The thermal interference between the sensing wafer and the semiconductor wafer is reduced. Furthermore, each first metal wire can be embedded in the first support colloid with at least part of it, and then each first metal wire can be protected by the first support colloid.

In order to understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention, but these descriptions and drawings are only used to illustrate the present invention, not to make any protection to the scope of the present invention. limit.

Please refer to FIG. 1 to FIG. 6, which are the embodiments of the present invention. It should be noted that this embodiment corresponds to the relevant quantity and appearance mentioned in the drawings, and is only used to specifically illustrate the implementation of the present invention. In order to facilitate understanding of the content of the present invention, rather than to limit the scope of protection of the present invention.

[Example 1]

Please refer to FIG. 1 and FIG. 2, which is the first embodiment of the present invention. This embodiment discloses a stacked sensor package structure 100, which is preferably suitable for system in package (SIP), but the present invention is not limited thereto. It should be noted that the internal components are not any sensor package structure in a stacked form, and the structural design basis is different from the stacked sensor package structure 100 referred to in this embodiment, so there is no basis for comparison between the two.

The stacked sensor package structure 100 includes a substrate 1, a semiconductor chip 2 mounted on the substrate 1, a plurality of first metal wires 3 electrically coupled to the substrate 1 and the semiconductor chip 2, spaced apart A first supporting colloid 4 and a second supporting colloid 5 on the substrate 1 and located outside the semiconductor wafer 2, a sensing chip 6 disposed on the first supporting colloid 4 and the second supporting colloid 5, A plurality of second metal wires 7 electrically coupled to the substrate 1 and the sensing chip 6, a spacer layer 8 disposed on the sensing chip 6, and disposed on the sensing chip 6 through the spacer layer 8 A light-transmitting layer 9 and a package P provided on the substrate 1 and surrounding the outside of the device.

In this embodiment, although the stacked sensor package structure 100 is described by including the above-mentioned components, it can also be adjusted and changed according to design requirements. For example, in other embodiments not shown in the present invention, the stacked sensor package structure 100 may also include the above-mentioned substrate 1, semiconductor chip 2, multiple first metal wires 3, and first support colloid 4 , The second supporting colloid 5, the sensing chip 6, and the plurality of second metal wires 7; that is to say, the stacked sensor packaging structure 100 can include the above-mentioned spacer layer 8, light-transmitting layer 9, and package P Omit or set in other ways.

It needs to be clarified that, to facilitate the description of the stacked sensor package structure 100 of this embodiment, FIG. 1 is presented in a cross-sectional view, but it can be understood that the stacked sensor package structure 100 not shown in FIG. 1 Corresponding structures will also be formed in the parts. For example, FIG. 1 only shows two first metal wires 3 and two second metal wires 7, but the other parts of the stacked sensor package structure 100 not shown in FIG. 1 include other first metal wires 3 and Other second metal wires 7. The following describes the structure and connection relationship of each element of the stacked sensor package structure 100 of this embodiment.

The substrate 1 is a printed circuit board (PCB) that is square or rectangular in this embodiment, but the invention is not limited thereto. Wherein, the substrate 1 is provided with a wafer fixing area 11 at the approximate center of the upper surface, and the substrate 1 is formed with a plurality of first bonding pads 12 located outside the wafer fixing area 11 on the upper surface and the first pads A plurality of second bonding pads 13 outside one bonding pad 12. The first pads 12 (or the second pads 13) are arranged in a ring shape in this embodiment, but the invention is not limited thereto. For example, in other embodiments not shown in the present invention, the first bonding pads 12 (or the second bonding pads 13) may also be arranged in two on opposite sides of the chip fixing area 11 Column.

In addition, in other embodiments not shown in the present invention, the substrate 1 may also be provided with a plurality of solder balls (not shown) on its lower surface, and the stacked sensor package structure 100 can pass these solders The ball is soldered and fixed on an electronic component, so that the stacked sensor package structure 100 can be electrically connected to the electronic component.

The semiconductor wafer 2 is described in this embodiment as a digital signal processor (DSP), but the invention is not limited to this. The semiconductor wafer 2 is fixed to the wafer fixing area 11 of the substrate 1, that is to say, the semiconductor wafer 2 is located inside the first bonding pads 12.

Furthermore, one end of the first metal wires 3 is connected to the semiconductor chip 2, and the other ends of the first metal wires 3 are respectively connected to the first bonding pads 12 of the substrate 1, so that the semiconductor The chip 2 can be electrically coupled to the first bonding pads 12 through the first metal wires 3. It should be noted that the semiconductor chip 2 of this embodiment is limited to electrically couple the first metal wires 3 to the substrate 1.

In the present embodiment, the first supporting colloid 4 has a ring shape (eg, a square ring shape) and surrounds the outer side of the semiconductor wafer 2 at intervals (and independently). A height of the first supporting colloid 4 relative to the substrate 1 is greater than a height of the semiconductor wafer 2 relative to the substrate 1 and also greater than a height of any first metal wire 3 relative to the substrate 1. In addition, in other embodiments not shown in the present invention, the first support colloid 4 may also be non-ring-shaped (eg, the first support colloid 4 includes a plurality of elongated shapes parallel to the edges of the semiconductor wafer 2 respectively) structure).

Furthermore, the position of the first supporting colloid 4 on the substrate 1 is preferably such that the first bonding pads 12 are buried in it (that is, the width of the first supporting colloid 4 is smaller than Preferably, it is larger than the width of the first bonding pad 12), and a portion of each first metal wire 3 is embedded in the first supporting colloid 4, but the present invention is not limited thereto.

For example, in other embodiments not shown in the present invention, the first supporting colloid 4 may also cover multiple edges of the semiconductor wafer 2, and the first bonding pads 12 and the first metals The wires 3 are completely embedded in the first supporting colloid 4. Accordingly, in the present invention, each of the first metal wires 3 can be at least partially embedded in the first support colloid 4, and then the first support colloid 4 can protect each first metal wire 3.

The second supporting colloid 5 has a ring shape (eg, a square ring shape) and surrounds the outer side of the first supporting colloid 4 at intervals (and independently), and a height of the second supporting colloid 5 relative to the substrate 1 is approximately It is equal to the height of the first supporting colloid 4 relative to the substrate 1. In other words, an annular gap G is formed between the first supporting colloid 4 and the second supporting colloid 5 in this embodiment, so that the first supporting colloid 4 does not contact the second supporting colloid 5. Furthermore, the second support colloid 5 is located inside the second pads 13 of the substrate 1, and the width of the second support colloid 5 is preferably substantially equal to the width of the first support colloid 4.

The sensing chip 6 is described as an image sensing chip in this embodiment, but it is not limited thereto. The size of the sensing wafer 6 is larger than the size of the semiconductor wafer 2. The sensing wafer 6 is disposed on the first support colloid 4 and the second support colloid 5 and is separated from the semiconductor wafer 2 by a distance. In this embodiment, the sensing wafer 6 and the semiconductor wafer 2 are separated by air, and the central axis of the sensing wafer 6 preferably overlaps the central axis of the semiconductor wafer 2, but it is not limited to this .

In more detail, the (outer surface) of the sensing wafer 6 includes a top surface 61 and a bottom surface 62 on opposite sides, and an outer edge 63 connected to the edges of the top surface 61 and the bottom surface 62. Wherein, the sensing chip 6 is provided with a sensing area 611 at the approximate center of the top surface 61, and the bottom surface 62 of the sensing chip 6 is disposed on the first supporting colloid 4 and the second supporting colloid 5, and the The outer edge 63 of the sensing wafer 6 slightly protrudes outward from the outer edge 51 of the second supporting colloid 5 in this embodiment, but the invention is not limited thereto. For example, in other embodiments not shown in the present invention, the outer edge 63 of the sensing wafer 6 may be substantially aligned with the outer edge 51 of the second supporting colloid 5.

Furthermore, one end of the second metal wires 7 is connected to the sensing chip 6, and the other ends of the second metal wires 7 are respectively connected to the second bonding pads 13 of the substrate 1, so that the The sensing chip 6 can be electrically coupled to the second bonding pads 13 through the second metal wires 7. Wherein, each of the second metal wires 7 adjacent to the sensing wafer 6 is preferably located above (or directly above) the second supporting colloid 5, so that the sensing wafer is supported by the second supporting colloid 5 6. When the second metal wires 7 are connected to the sensing wafer 6, the force applied to the sensing wafer 6 can be withstood.

As described above, the stacked sensor package structure 100 of this embodiment supports the sensing chip 6 by forming the first support colloid 4 and the second support colloid 5 spaced apart on the substrate 1, according to The bonding effect between the components is strengthened, and the substrate 1, the sensing wafer 6, and the second supporting colloid 5 can surround to form a small enclosed space, thereby reducing the volume of the stacked sensor packaging structure 100 And can simultaneously reduce the thermal interference between the sensing wafer 6 and the semiconductor wafer 2.

In this embodiment, the material of the spacer layer 8 is the same as the material of the first supporting colloid 4 and the second supporting colloid 5, but the invention is not limited thereto. The spacer layer 8 is disposed on the top surface 61 of the sensing wafer 6 and is located outside the sensing area 611 and inside the second metal wires 7. Furthermore, the spacer layer 8 is preferably located directly above the first support colloid 4, so that the force applied to the sensing wafer 6 via the spacer layer 8 is supported by the first support colloid 4 (eg: The weight of the light-transmitting layer 9).

In this embodiment, the light-transmitting layer 9 is described as a transparent flat glass, but the invention is not limited thereto. The light-transmitting layer 9 is disposed on the spacer layer 8, and thus is disposed on the sensing wafer 6 through the spacer layer 8. Wherein, the light-transmitting layer 9, the spacer layer 8 and the sensing chip 6 together form a closed space E, and the sensing area 611 of the sensor wafer 6 is located in the closed space E and faces the light-transmitting layer 9. Furthermore, the outer edge 91 of the light-transmitting layer 9 is substantially aligned with the outer edge 81 of the spacer layer 8 in this embodiment, but in other embodiments not shown in the present invention, the The outer edge may protrude from the outer edge 81 of the spacer layer 8.

The package P is disposed on the substrate 1 and covers the outer edge 51 of the second support colloid 5, the outer edge 63 of the sensing chip 6, the outer edge 91 of the light-transmitting layer 9, and the spacing layer 8 The outer edge 81. Furthermore, the second bonding pads 13 and the second metal wires 7 are completely embedded in the package P.

More specifically, in this embodiment, the package P includes a first sealant P1 formed on the substrate 1 and a second sealant P2 formed on the first sealant P1. The first sealant P1 is a liquid compound, and the second sealant P2 is a molding compound.

Furthermore, the first sealant P1 covers the outer edge 51 of the second support colloid 5, the outer edge 63 of the sensing wafer 6, the outer edge 91 of the light-transmitting layer 9, and the outer edge of the spacer layer 8 81, and the second bonding pads 13 and the second metal wires 7 are completely embedded in the first sealant P1, and the top edge of the second sealant P2 is substantially coplanar with the light-transmitting layer 9 Top surface, but the invention is not limited to this. For example, in other embodiments not shown in the present invention, the package P may also be only liquid sealant or molded sealant.

[Example 2]

Please refer to FIG. 3 and FIG. 4, which is the second embodiment of the present invention. Since this embodiment is similar to the first embodiment described above, the similarities between the two embodiments will not be repeated, and the differences between the two embodiments are roughly explained as follows: The stacked sensor package structure 100 is in this embodiment It further includes a plurality of inner supporting colloids S arranged at intervals, and each inner supporting colloid S is in a ring shape (such as a square ring shape) and is sandwiched between the semiconductor wafer 2 and the sensing wafer 6, and each The opposite ends of the first metal wire 3 are embedded in the first supporting colloid 4 and the inner supporting colloid S adjacent to the first supporting colloid 4 respectively.

In addition, in other embodiments not shown in the present invention, the number of inner supporting colloids S of the stacked sensor packaging structure 100 may also be at least one, and at least one of the inner supporting colloids S is in a ring shape (eg: square Ring-shaped) and sandwiched between the semiconductor wafer 2 and the sensing wafer 6, and the opposite ends of each first metal wire 3 are embedded in the first support colloid 4 and at least one of the inner supports respectively Colloid S.

According to this, the stacked sensor package structure 100 of the present embodiment sandwiches at least one internal support colloid S between the semiconductor wafer 2 and the sensing wafer 6, so that the sensing wafer 6 can be further The inner support colloid S is supported, and the thermal energy of the semiconductor wafer 2 is prevented from thermally interfering with the sensing wafer 6.

[Embodiment 3]

Please refer to FIG. 5, which is the third embodiment of the present invention. Since this embodiment is similar to the first embodiment described above, the similarities between the two embodiments will not be repeated, and the differences between the two embodiments are roughly explained as follows: The stacked sensor package structure 100 is in this embodiment A cross-shaped inner supporting colloid S is further included, and the inner supporting colloid S is located inside the first supporting colloid 4 in a square ring shape. Wherein, the inner supporting colloid S is partially sandwiched between the semiconductor wafer 2 and the sensing wafer 6, and the four end points of the inner supporting colloid S are respectively connected to the four side lengths of the first supporting colloid 4 center of.

[Embodiment 4]

Please refer to FIG. 6, which is the fourth embodiment of the present invention. Since this embodiment is similar to the third embodiment described above, the similarities between the two embodiments will not be repeated, and the differences between the two embodiments are roughly explained as follows: the four end points of the inner supporting colloid S are as in this embodiment Are connected to the four corners of the first supporting colloid 4 respectively.

[Technical Effects of Embodiments of the Invention]

In summary, the stacked sensor package structure disclosed in the embodiments of the present invention supports the sensing chip by forming the first support colloid and the second support colloid on the substrate at intervals, according to The bonding effect between the elements is strengthened, and the substrate, the sensing chip, and the second supporting colloid can surround to form a small enclosed space, thereby reducing the volume of the stacked sensor packaging structure and simultaneously The thermal interference between the sensing wafer and the semiconductor wafer is reduced. Furthermore, each first metal wire can be embedded in the first support colloid with at least part of it, and then each first metal wire can be protected by the first support colloid.

In addition, the stacked sensor packaging structure disclosed in the embodiments of the present invention can make the overall structure more stable by selecting the positions of the first supporting colloid and the second supporting colloid. For example, each second metal wire portion adjacent to the sensing wafer is located above the second supporting colloid, thereby supporting the sensing wafer through the second supporting colloid, so that the second metal wires are welded to the When sensing a wafer, the force exerted on the sensing wafer can be sustained. Alternatively, the spacer layer is located directly above the first supporting colloid, so that the force applied to the sensing wafer via the spacer layer is supported by the first supporting colloid (eg, the weight of the light-transmitting layer).

The content disclosed above is only a preferred and feasible embodiment of the present invention, and therefore does not limit the patent scope of the present invention. Therefore, any equivalent technical changes made by using the description and drawings of the present invention are included in the patent scope of the present invention. Inside.

100‧‧‧Stacked sensor packaging structure 1‧‧‧ substrate 11‧‧‧chip fixed area 12‧‧‧First pad 13‧‧‧Second pad 2‧‧‧Semiconductor chip 3‧‧‧ First metal wire 4‧‧‧ First support colloid 5‧‧‧second support colloid 51‧‧‧Outer edge 6‧‧‧sensing chip 61‧‧‧Top 611‧‧‧sensing area 62‧‧‧Bottom 63‧‧‧Outer edge 7‧‧‧Second metal wire 8‧‧‧ Spacer 81‧‧‧Outer edge 9‧‧‧Transparent layer 91‧‧‧Outer edge P‧‧‧Package P1‧‧‧The first sealant P2‧‧‧Second sealant E‧‧‧Enclosed space G‧‧‧Annular gap S‧‧‧Inner support colloid

FIG. 1 is a schematic cross-sectional view of a stacked sensor package structure according to Embodiment 1 of the present invention.

FIG. 2 is a schematic top view of the stacked sensor package structure according to Embodiment 1 of the present invention (omitting the spacer layer, the light-transmitting layer, and the package body).

3 is a schematic cross-sectional view of a stacked sensor packaging structure according to Embodiment 2 of the present invention.

4 is a schematic top view of a stacked sensor package structure according to Embodiment 2 of the present invention (omitting the spacer layer, the light-transmitting layer, and the package body).

FIG. 5 is a schematic top view of the stacked sensor package structure according to Embodiment 3 of the present invention (omitting the spacer layer, the light-transmitting layer, and the package).

6 is a schematic top view of a stacked sensor package structure according to Embodiment 4 of the present invention (omitting the spacer layer, the light-transmitting layer, and the package body).

100‧‧‧Stacked sensor packaging structure

1‧‧‧ substrate

11‧‧‧chip fixed area

12‧‧‧First pad

13‧‧‧Second pad

2‧‧‧Semiconductor chip

3‧‧‧ First metal wire

4‧‧‧ First support colloid

5‧‧‧second support colloid

51‧‧‧Outer edge

6‧‧‧sensing chip

61‧‧‧Top

611‧‧‧sensing area

62‧‧‧Bottom

63‧‧‧Outer edge

7‧‧‧Second metal wire

8‧‧‧ Spacer

81‧‧‧Outer edge

9‧‧‧Transparent layer

91‧‧‧Outer edge

P‧‧‧Package

P1‧‧‧The first sealant

P2‧‧‧Second sealant

E‧‧‧Enclosed space

G‧‧‧Annular gap

Claims (10)

A stacked sensor packaging structure includes: a substrate on which a plurality of first bonding pads and a plurality of second bonding pads located outside the first bonding pads are formed on the upper surface; a semiconductor chip and a plurality of first bonding pads A metal wire, the semiconductor chip is mounted on the substrate and is located inside the first pads, the semiconductor chip is electrically coupled to the first pads through the first metal wires; a first support Colloid, which is arranged on the substrate and located outside the semiconductor wafer, at least part of each first metal wire is embedded in the first supporting colloid; a second supporting colloid is in a ring shape and is arranged on the substrate, The second supporting colloid is located inside the second bonding pads and surrounds the outer side of the first supporting colloid at intervals; a sensing chip and a plurality of second metal wires, the sensing chip is larger in size than the semiconductor chip Size, the sensing chip is disposed on the first supporting colloid and the second supporting colloid, and is separated from the semiconductor chip by a distance, the sensing chip is electrically coupled to the plurality of second metal wires A second pad; a light-transmitting layer and a spacer layer, the light-transmitting layer is disposed on the sensing chip through the spacer layer; and a package is disposed on the substrate and covers the second support colloid The outer edge, the outer edge of the sensing wafer, the outer edge of the light-transmitting layer, and the outer edge of the spacer layer. The stacked sensor packaging structure according to claim 1, wherein the first bonding pads are embedded in the first supporting colloid. The stacked sensor package structure according to claim 1, wherein the stacked sensor package structure further includes at least one inner support colloid, and at least one of the inner support colloid is sandwiched between the semiconductor chip and the sensor Between test wafers. The stacked sensor packaging structure according to claim 3, wherein opposite ends of each first metal wire are embedded in the first support colloid and at least one inner support colloid respectively. The stacked sensor packaging structure according to claim 1, wherein the stacked sensor packaging structure further includes an inner supporting colloid in a cross shape, and the inner supporting colloid is located inside the first supporting colloid ; Part of the internal support colloid is clamped between the semiconductor wafer and the sensing wafer. The stacked sensor packaging structure according to claim 5, wherein the first supporting colloid has a square ring shape, and four end points of the inner supporting colloid are respectively connected to four corners of the first supporting colloid. The stacked sensor packaging structure according to claim 1, wherein the spacer layer is located directly above the first supporting colloid. The stacked sensor package structure of claim 1, wherein each of the second metal wire portions adjacent to the sensing chip is located above the second supporting colloid. The stacked sensor package structure according to claim 1, wherein each second metal wire is completely embedded in the package body. A stacked sensor packaging structure includes: a substrate on which a plurality of first bonding pads and a plurality of second bonding pads outside the first bonding pads are formed on the upper surface; a semiconductor chip and a plurality of first bonding pads A metal wire, the semiconductor chip is mounted on the substrate and is located inside the first pads, the semiconductor chip is electrically coupled to the first pads through the first metal wires; a first support Colloid, which is arranged on the substrate and located outside the semiconductor wafer, at least part of each first metal wire is embedded in the first supporting colloid; a second supporting colloid, which is ring-shaped and arranged on the substrate, The second supporting colloid is located inside the second bonding pads and surrounds the outer side of the first supporting colloid at intervals; and a sensing chip and a plurality of second metal wires, the sensing chip is larger than the semiconductor The size of the chip, the sensing chip is disposed on the first supporting colloid and the second supporting colloid, and is separated from the semiconductor wafer by a distance; the sensing chip is electrically coupled to the through the second metal wires Some second pads.

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