TWI685918B - Method of fabricating tapered gate dielectric layer and semiconductor structure comprising the same - Google Patents

Abstract

A method of forming a tapered gate oxide layer and a semiconductor structure comprising the tapered gate dielectric layer is provided. In the method of fabricating the tapered gate dielectric layer, a patterned stack layer having a first oxide layer and a silicon nitride layer disposed thereon is formed on a substrate. Then, an oxide spacer is formed on the sidewall of the patterned stack layer. Next, a third oxide layer is formed on the substrate, and the thickness of the third oxide layer is smaller than the thickness of the first oxide layer. The first oxide layer, the silicon nitride layer, the oxide spacer and the third oxide layer form the tapered gate dielectric layer. A method of forming a semiconductor structure including the tapered gate dielectric is also provided.

Description

Gate dielectric layer with inclined surface and manufacturing method of semiconductor structure

The invention relates to a semiconductor manufacturing process, and in particular to a method for manufacturing a gate dielectric layer with an inclined plane and a semiconductor structure thereof.

Using a planar dual gate device (Layerally Diffused Metal Oxide Semiconductor; LDMOS) at the drain-source breakdown voltage (BV _DSS ), Specific ON-resistance (R _sp ), transconductance, hot carrier lifetimes, safe operating area (SOA) and other evaluation indicators (figure of merit) ; FOM) have excellent performance. The key structure of this type of LDMOS is a gate dielectric layer with different thickness, and there is a portion with a gradually varying thickness between the thick and thin gate dielectric layers to smoothly connect the thin gate dielectric layer and the thick gate dielectric layer, thereby obtaining more Uniform lateral electric field distribution to reduce the surface field (reduced surface field; RESURF) of the polysilicon field plate.

Therefore, the present invention provides a method for manufacturing a gate dielectric layer having an inclined surface and a semiconductor structure thereof.

In the above method for manufacturing a gate dielectric layer with an inclined plane, a patterned stack is first formed on a substrate. The stack includes a first oxide layer below and a silicon nitride layer above. An oxide spacer is then formed on the sidewall of the patterned stack. Next, a third oxide layer is formed on the substrate. The thickness of the third oxide layer is smaller than the thickness of the first oxide layer. The above-mentioned first oxide layer, the silicon nitride layer, the oxide spacer and the third oxide layer constitute a gate dielectric layer having an inclined surface.

According to an embodiment, the method for forming the patterned stack includes first forming a first oxide layer and a silicon nitride layer on the substrate in sequence. A lithography etching process is performed on the first oxide layer and the silicon nitride layer to pattern the above-mentioned stack and expose part of the surface of the substrate. The method for forming the first oxide layer may be a thermal oxidation method, and the method for forming the silicon nitride layer may be a chemical vapor deposition method or a nitrogen-containing plasma treatment method, for example.

According to another embodiment, the method for forming the above-mentioned oxide spacer includes forming a second oxide layer on the substrate to cover the above-mentioned stacked layer and the substrate. The second oxide layer is then anisotropically etched, using the silicon nitride layer as an etch stop layer (etch stop layer) until the surface of the substrate not covered by the stack is exposed. The method for forming the above-mentioned second oxide layer may be, for example, chemical vapor deposition, and the method for anisotropic etching described above The method may be, for example, dry etching, or a mixture of dry etching and wet etching.

According to still another embodiment, the method for forming the third oxide layer may be, for example, a thermal oxidation method or a chemical vapor deposition method.

According to yet another embodiment, the method for manufacturing the gate dielectric layer with an inclined surface further includes removing the silicon nitride layer between the steps of forming the oxide spacer and forming the third oxide layer, for example, using dry etching Method or wet etching method to remove the silicon nitride layer. Moreover, the height of the oxidation spacer is approximately equal to the thickness of the first oxide layer.

In the manufacturing method of the semiconductor structure including the above-mentioned inclined gate dielectric layer, in addition to the above-mentioned manufacturing steps of the above-mentioned inclined gate dielectric layer, it also includes forming a gate electrode on the gate dielectric layer, and then Source and drain are formed in the substrate on both sides of the gate.

Based on the above, the oxide spacer is used to form a slope between the thin gate dielectric layer and the thick oxide layer to smoothly connect the thin gate dielectric layer and the thick gate dielectric layer to make the electric field distribution more uniform. The semiconductor structure with the inclined gate dielectric layer has better device performance.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

100‧‧‧ base

110‧‧‧First oxide layer

120‧‧‧Silicon nitride layer

125‧‧‧Lamination

130‧‧‧ Oxidation gap

140‧‧‧third oxide layer

150‧‧‧Gate

160‧‧‧ Jiji

170‧‧‧Source

180‧‧‧Doped well

1 and 2A-2B are schematic cross-sectional structure diagrams of a manufacturing process of a gate dielectric layer with an inclined plane according to the first embodiment of the present invention.

1 and 3A-3B are schematic cross-sectional structural views of a manufacturing process of a gate dielectric layer with an inclined plane according to a second embodiment of the invention.

1 and 4A-4B are schematic cross-sectional structural views of a manufacturing process of a gate dielectric layer with an inclined plane according to a third embodiment of the invention.

1 and 5A-5B are schematic cross-sectional structural views of a manufacturing process of a gate dielectric layer with an inclined plane according to a fourth embodiment of the invention.

1 and 2A-2B are schematic cross-sectional structure diagrams of a manufacturing process of a gate dielectric layer with an inclined plane according to the first embodiment of the present invention. In FIG. 1, a first oxide layer 110 and a silicon nitride layer 120 are sequentially formed on the substrate 100. The formation method of the first oxide layer 110 may be, for example, thermal oxidation. The thickness of the first oxide layer 110 is, for example, about 130-170Å, such as 130, 140, 150, 160, 170Å. The formation method of the silicon nitride layer 120 may be, for example, a chemical vapor deposition (CVD) method to directly deposit the silicon nitride layer 120, or a nitrogen-containing plasma is used to nitride the surface layer of the first oxide layer 110. The silicon nitride layer 120 is formed. The thickness of the silicon nitride layer 120 is, for example, about 30-70Å, such as 30, 40, 50, 60, 70Å.

Next, the silicon nitride layer 120 and the first oxide layer 110 are patterned to obtain a patterned stack 125, and a portion of the surface of the substrate 100 is exposed. For the above patterning method, for example, a lithography etching process may be performed on the silicon nitride layer 120 to obtain a patterned silicon nitride layer 120. Next, using the patterned silicon nitride layer 120 as a hard mask, the first oxide layer 110 is continuously etched to form a patterned stack 125.

In FIG. 2A, a second oxide layer is formed, and the step covers the exposed substrate 100 and the patterned stack 125. The thickness of the second oxide layer is, for example, about 150-250Å, such as about 180-220Å, such as 180, 190, 200, 210, 220Å. Next, the second oxide layer is anisotropically etched until the silicon nitride layer 120 is exposed to obtain an oxide spacer 130 located on the side wall of the stack 125. The method for forming the second oxide layer may be, for example, chemical vapor deposition, and the method for anisotropic etching may be, for example, dry etching, or a mixture of dry etching and wet etching. Generally speaking, the oxide spacer 130 can be obtained only by dry etching. If you want to adjust the degree of inclination of the surface of the oxide spacer 130, you can adjust various parameters of the dry etching method or add a wet etching method. Since this is a decision made by those with ordinary knowledge in the field of semiconductor manufacturing, all details of this step will not be repeated here.

Then, a third oxide layer 140 is formed to cover the exposed substrate 100, the oxide spacer 130, and the silicon nitride layer 120. The forming method of the third oxide layer 140 may be, for example, chemical vapor deposition, and the thickness of the third oxide layer 140 may be about 25-35Å, such as 25, 27, 29, 30, 31, 33, 35Å. At this step, the first oxide layer 110, the silicon nitride layer 120, the oxide spacer 130, and the third oxide layer 140 constitute a gate dielectric layer having an inclined surface.

In FIG. 2B, the gate electrode 150 may continue to be formed on the gate dielectric layer (the first oxide layer 110, the silicon nitride layer 120, the oxide spacer 130, and the third oxide layer 140), and then the thicker first A drain 160 is formed on the side of the oxide layer 110, and a source 170 is formed in the doped well 180 on the side of the thinner third oxide layer 140 to obtain the basic structure of a laterally diffused metal oxide semi-transistor.

1 and 3A-3B are schematic cross-sectional structural views of a manufacturing process of a gate dielectric layer with an inclined plane according to a second embodiment of the invention. The description of FIG. 1 is as described above and will not be repeated here. Next, in FIG. 3A, an oxide spacer 130 located on the side wall of the stack 125 is formed. The formation method of the oxide spacer 130 has been described in FIG. 2A and will not be repeated here.

Then, thermal oxidation or oxygen-containing plasma treatment is performed to oxidize the surfaces of the substrate 100 and the silicon nitride layer 120 to form a third oxide layer 140. The thickness of the third oxide layer 140 may be, for example, about 25-35Å, such as 25, 27, 29, 30, 31, 33, 35Å. So far, the first oxide layer 110, the silicon nitride layer 120, the oxide spacer 130 and the third oxide layer 140 constitute a gate dielectric layer having an inclined surface.

In FIG. 3B, the gate electrode 150 may continue to be formed on the gate dielectric layer (the first oxide layer 110, the silicon nitride layer 120, the oxide spacer 130, and the third oxide layer 140), and then the thicker first A drain 160 is formed on the side of the oxide layer 110, and a source 170 is formed in the doped well 180 on the side of the thinner third oxide layer 140 to obtain the basic structure of a laterally diffused metal oxide semi-transistor.

1 and 4A-4B are schematic cross-sectional structural views of a manufacturing process of a gate dielectric layer with an inclined plane according to a third embodiment of the invention. The description of FIG. 1 is as described above and will not be repeated here. In FIG. 4A, a second oxide layer is formed, and the steps cover the exposed substrate 100 and the patterned stack 125. The thickness of the second oxide layer is, for example, about 150-250Å, such as about 180-220Å, such as 180, 190, 200, 210, 220Å. Next, the second oxide layer is anisotropically etched until the height of the obtained oxide spacer 130 is approximately equal to the thickness of the first oxide layer 110 to form a bit An oxide spacer 130 is formed on the sidewall of the first oxide layer 110. The above-mentioned etching method of the second oxide layer is as described above in FIG. 2A and will not be repeated here.

Next, the silicon nitride layer 120 is removed, and the removal method may be, for example, a dry etching method or a wet etching method. Then, a third oxide layer 140 is formed to cover the exposed substrate 100, the oxide spacer 130, and the first oxide layer 110. The method for forming the third oxide layer 140 may be, for example, chemical vapor deposition, and the thickness of the third oxide layer 140 may be about 25-35Å, such as 25, 27, 29, 30, 31, 33, 35Å. Up to this step, the first oxide layer 110, the oxide spacer 130 and the third oxide layer 140 constitute a gate dielectric layer having an inclined surface.

In FIG. 4B, the gate electrode 150 may continue to be formed on the gate dielectric layer (the first oxide layer 110, the oxide spacer 130, and the third oxide layer 140), and then the gate electrode 150 may be formed on the thicker first oxide layer 110 side. Electrode 160, and a source electrode 170 is formed in the doped well 180 on the side of the thin third oxide layer 140 to obtain the basic structure of a laterally diffused metal oxide semi-transistor.

1 and 5A-5B are schematic cross-sectional structural views of a manufacturing process of a gate dielectric layer with an inclined plane according to a fourth embodiment of the invention. In FIG. 5A, an oxide spacer 130 located on the side wall of the first oxide layer 110 is formed. The method for forming the oxidized spacer 130 is as described above in FIG. 4A and will not be repeated here.

Next, the silicon nitride layer 120 is removed, and the removal method may be, for example, a dry etching method or a wet etching method. Then, a thermal oxidation method or an oxygen-containing plasma treatment method is performed to oxidize the surface of the substrate 100 to form a third oxide layer 140, and the thickness of the third oxide layer 140 may be about 25-35Å, such as 25, 27, 29, 30, 31, 33, 35Å. So far, the above The first oxide layer 110, the oxide spacer 130, and the third oxide layer 140 constitute a gate dielectric layer having an inclined surface.

Please refer to FIG. 5B, which is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. In FIG. 2B, the gate electrode 150 may continue to be formed on the gate dielectric layer (the first oxide layer 110, the oxide spacer 130, and the third oxide layer 140), and then the drain is formed on the thicker first oxide layer 110 side. Electrode 160, and a source electrode 170 is formed in the doped well 180 on the side of the thin third oxide layer 140 to obtain the basic structure of a laterally diffused metal oxide semi-transistor.

In summary, the present invention uses an oxide spacer to form a slope between the thin layer and the thick layer in the gate dielectric layer to smoothly connect the thin layer and the thick layer in the gate dielectric layer. In this way, the electric field distribution is more uniform, the surface electric field of the polysilicon field plate is reduced, and the semiconductor structure including the gate dielectric layer with the inclined plane has better device performance.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100‧‧‧ base

110‧‧‧First oxide layer

120‧‧‧Silicon nitride layer

125‧‧‧Lamination

130‧‧‧ Oxidation gap

140‧‧‧third oxide layer

Claims (12)

A method for manufacturing a gate dielectric layer with an inclined plane includes: forming a patterned stack on a substrate, the stack including a first oxide layer located below and a silicon nitride layer located above; forming an oxide spacer Forming a third oxide layer on the substrate; wherein the thickness of the third oxide layer is less than the thickness of the first oxide layer, and the first oxide layer, the silicon nitride layer, the The oxide spacer and the third oxide layer constitute a gate dielectric layer having an inclined surface. The method for manufacturing a gate dielectric layer having an inclined surface as described in claim 1, wherein the method of forming the stack includes: forming the first oxide layer on the substrate; forming the silicon nitride layer on the first oxide Above the layer; and patterning the silicon nitride layer and the first oxide layer to expose part of the surface of the substrate. The method for manufacturing a gate dielectric layer having an inclined surface as described in claim 2, wherein the method for forming the first oxide layer includes a thermal oxidation method. The method for manufacturing a gate dielectric layer having an inclined surface as described in claim 2, wherein the method for forming the silicon nitride layer includes a chemical vapor deposition method or a nitrogen-containing plasma treatment method. The method for manufacturing a gate dielectric layer having an inclined surface as described in claim 2, wherein the method of patterning the silicon nitride layer and the first oxide layer includes a lithography etching method. The method for manufacturing a gate dielectric layer having an inclined surface as described in claim 1, wherein the method of forming the oxide spacer includes: forming a second oxide layer on the substrate to cover the stack and the substrate; and non- The second oxide layer is etched isotropically until the surface of the substrate not covered by the stack is exposed. The method for manufacturing a gate dielectric layer having an inclined surface as described in claim 6, wherein the method for forming the second oxide layer includes a chemical vapor deposition method. The method for manufacturing a gate dielectric layer having an inclined surface as described in claim 6, wherein the method of anisotropically etching the second oxide layer includes using a dry etching method, or a mixture of dry etching and wet etching. The method for manufacturing a gate dielectric layer having an inclined surface as described in claim 1, wherein the method for forming the third oxide layer includes a thermal oxidation method or a chemical vapor deposition method. The method for manufacturing a gate dielectric layer having an inclined surface as described in claim 1, further comprising removing the silicon nitride layer and forming the oxide spacer between the steps of forming the oxide spacer and forming the third oxide layer The height of is equal to the thickness of the first oxide layer. The method for manufacturing a gate dielectric layer having an inclined surface as described in claim 10, wherein the method for removing the silicon nitride layer includes a dry etching method or a wet etching method. A manufacturing method of a semiconductor structure, comprising: forming the gate dielectric layer having an inclined plane on the substrate using the manufacturing method described in any one of claims 1-11; forming a gate electrode on the gate dielectric layer; And the source and the drain are formed in the substrate on both sides of the gate.

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