TWI685827B - Shift register circuit and method of driving the same - Google Patents

Abstract

A shift register circuit and a method of driving the same. The shift register circuit includes a first pull-up circuit and a pull-down circuit. The first pull-up circuit is used for receiving a first pull-up signal, according to which the first pull-up circuit receives a first clock signal and outputs the first clock signal to a first node, and connects a first power supply with an output terminal according to the first clock signal. The first discharge unit of the first pull-up circuit connects the first node with a second power supply according to a pull-down signal. The pull-down circuit is used for receiving and outputting the pull-down signal to a second node, and connecting the output terminal with a third power supply according to the pull-down signal. The second discharge circuit of the pull-down circuit connects the second node with a fourth power supply according to the first pull-up signal. The enabling period of the first pull-up signal and that of the pull-down signal do not overlap.

Description

Shift register circuit and its driving method

The invention relates to a driving circuit and a driving method thereof, in particular to a shift register circuit and a driving method thereof.

The shift register is a widely used digital logic circuit. It generally includes multiple stages of flip-flops connected in series. The flip-flops are connected in parallel to the clock signal line. The output of each flip-flop is coupled to the next-level flip-flop. The input terminal of each level, so that the flip-flops at all levels output the stored signals in sequence.

The circuit structure of the traditional shift register cannot output the long pulse drive signal. The reason is that the transistors to which the gate of the control signal is output all form a current path, so that the potential of the node to which the gate is coupled is likely to drop due to leakage current, which causes the transistor to be output from the control signal to fail to conduct. On the other hand, since the transistor outputting the control signal must always be at the high potential of the gate to output the signal to the output terminal, it is easy to aging and cause the drive accuracy to decline or even malfunction.

The technical solution adopted by the embodiment of the present invention is to provide a shift register circuit, which includes a first pull-up circuit and a pull-down circuit. The first pull-up circuit includes a first pull-up control unit, a first current storage unit, a first pull-up unit, and a first discharge circuit. The first pull-up control unit receives a first pull-up signal, and receives and outputs a first clock signal to a first node according to the first pull-up signal. The first current storage unit is coupled to the first node. The first pull-up unit is coupled to the first node and a first voltage The source and an output terminal are used to receive the first clock signal, and electrically connect the first voltage source and the output terminal according to the first clock signal. The first discharge circuit is coupled to the first node, the pull-down circuit and a second voltage source for electrically connecting the first node to the second voltage source according to the pull-down signal received by the pull-down circuit. The pull-down circuit includes a pull-down control unit, a second current storage unit, a pull-down unit, and a second discharge circuit. The pull-down control unit is used to receive the pull-down signal and output the pull-down signal to the second node. The second current storage unit is coupled to the second node. The pull-down unit is coupled to the second node, the output terminal, and the third voltage source, and is used to receive the pull-down signal and electrically connect the third voltage source and the output terminal according to the pull-down signal. The second discharge circuit is coupled to the second node and the fourth voltage source for receiving the first pull-up signal and electrically connecting the second node to the fourth voltage source according to the first pull-up signal. The enable period of the first pull-up signal does not overlap with the enable period of the pull-down signal.

A technical solution provided by another embodiment of the present invention is to provide a method for driving a shift register circuit for driving the shift register circuit, including: during a first output period, outputting to the first pull-up circuit The first clock signal; during the first pull-up period during the first output period, the first pull-up signal is output to the first pull-up circuit; and during the first output period and after the first pull-up period During a pull-down period, a pull-down signal is output to the pull-down circuit.

The shift register circuit provided by an embodiment of the present invention includes a second pull-up circuit. The second pull-up circuit includes a second pull-up control unit, a third current storage unit, a second pull-up unit, and a third discharge circuit. The second pull-up control unit is used to receive the second pull-up signal and receive and output the second clock signal to the third node according to the second pull-up signal. The third current storage unit is coupled to the third node. The second pull-up unit is coupled to the third node, the output terminal, and the first voltage source for receiving the second clock signal and electrically connecting the first voltage source and the output terminal according to the second clock signal. The third discharge circuit is coupled to the third node and the second The node and the seventh voltage source are used to electrically connect the third node to the seventh voltage source according to the potential of the second node. The enabling period of the first clock signal does not overlap with the enabling period of the second clock signal.

A technical solution provided by another embodiment of the present invention is to provide a shift register circuit driving method for driving the above shift register circuit, including: outputting to the first pull-up circuit during the first output period The first clock signal; during the first pull-up period during the first output period, the first pull-up signal is output to the first pull-up circuit; during the first output period and after the first pull-up period During the pull-down period, the pull-down signal is output to the pull-down circuit; during the second output period after the first output period, the second clock signal with the enable potential is output to the second pull-up circuit; the first among the second output periods During the second pull-up period, a second pull-up signal is output to the second pull-up circuit; and during the second pull-down period during and after the second pull-up period, the pull-down signal is output to the pull-down circuit.

Z‧‧‧Shift register circuit

1‧‧‧ First pull-up circuit

1a‧‧‧Second pull-up circuit

11‧‧‧First pull-up control unit

11a‧‧‧Second pull-up control unit

12‧‧‧ First current storage unit

12a‧‧‧third current storage unit

13‧‧‧First pull-up unit

13a‧‧‧Second pull-up unit

14‧‧‧ First discharge circuit

14a‧‧‧The third discharge circuit

T1, T11, T12, T13, T14 ‧‧‧ first transistor

T2, T21, T22 ‧‧‧ second transistor

T31, T32, T33, T34 ‧‧‧ third transistor

C1‧‧‧ First capacitor

C3‧‧‧The third capacitor

2‧‧‧pull-down circuit

21‧‧‧Pull-down control unit

22‧‧‧second current storage unit

23‧‧‧Pull-down unit

24‧‧‧Second discharge circuit

T4‧‧‧ fourth transistor

T5‧‧‧ fifth transistor

T61, T62 ‧‧‧ sixth transistor

VDD, VSS1, VSS2, VSS3, VSS4, VSS5, VSS6, VSS7

G‧‧‧First pull-up signal, second pull-up signal

ECK‧‧‧ First clock signal

EXCK‧‧‧second clock signal

G’‧‧‧ pull down signal

Q‧‧‧The first node

K‧‧‧The second node

P‧‧‧The third node

FIG. 1 is a shift register circuit according to a first embodiment of the invention.

FIG. 2 is an embodiment of the shift register circuit according to the first embodiment of the invention.

FIG. 3 is a signal timing diagram of the shift register circuit according to the first embodiment of the invention.

FIG. 4 is a driving method of the shift register circuit according to the first embodiment of the present invention.

5 is a shift register circuit of a second embodiment of the invention.

6 is a signal timing diagram of a shift register circuit according to a second embodiment of the invention.

7 is a driving method of a shift register circuit according to a second embodiment of the invention.

8 is a shift register circuit of a third embodiment of the invention.

The following describes the implementation of the shift register circuit and its driving method disclosed by the present invention through specific specific examples and FIG. 1 to FIG. 8. Those skilled in the art can use this description The contents disclosed in the book understand the advantages and effects of the present invention. However, the content disclosed below is not intended to limit the protection scope of the present invention. Without departing from the spirit of the inventive concept, those skilled in the art can implement the present invention in other different embodiments based on different viewpoints and applications. In the drawings, for the sake of clarity, all shown are simplified schematic diagrams to illustrate the basic architecture of the present invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and the present invention, and will not be interpreted as idealized or excessive Formal meaning unless explicitly defined as such in this article.

In addition, it should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, And/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, for example, "first element" and "first signal" discussed below may be referred to as "second element" and "second signal" without departing from the teachings herein.

First embodiment

The shift register circuit Z provided by the first embodiment of the present invention and its driving method are described below with reference to FIGS. 1 to 4. First, please refer to FIG. 1, the shift register circuit Z of the first embodiment of the present invention has a first pull-up circuit 1 and a pull-down circuit 2. The first pull-up circuit 1 and the pull-down circuit 2 are both coupled to an output terminal S, wherein the first pull-up circuit 1 has a first pull-up control unit 11, a first current storage unit 12, a first pull-up unit 13 and a first A discharge circuit 14; the pull-down circuit 2 has a pull-down control unit 21, a second current storage unit 22, a pull-down unit 23, and a second discharge circuit 24.

In the shift register circuit Z of FIG. 1, the first pull-up circuit 1 is used to receive the first pull-up signal G, and receives the first clock signal ECK according to the first pull-up signal G and converts the first clock The signal ECK is output to the first node Q. The first current storage unit 12 is coupled to the first node Q to accumulate the charge output to the first node Q, so that the first pull-up unit 13 receives the first clock signal ECK from the first node Q, and according to the first The clock signal ECK electrically connects the first voltage source VDD and the output terminal S. The first discharge circuit 14 is coupled to the second node K to electrically connect the first node Q to the second current source VSS1 according to the potential of the second node K.

Specifically, in this embodiment, the first pull-up control unit 11, the first pull-up unit 13, and the first discharge circuit 14 may be implemented by switching. When the first pull-up signal G is in the enable period, the first pull-up control unit 11 is turned on to receive the first clock signal ECK and output the first clock signal ECK to the first node Q; when the first pull-up signal G does not reach the enabling potential, and the first pull-up control unit 11 does not output the first clock signal ECK. When the first clock signal ECK is at the enable potential, the first pull-up unit 13 is turned on to electrically connect the first voltage source VDD and the output terminal S; when the first clock signal ECK does not reach the enable potential, the first The pull-up unit 13 does not make conduction. Similarly, when the second node K is at an enabling potential, the first discharge circuit 14 is turned on to electrically connect the first node Q to the second voltage source VSS1; when the second node is at a non-enabling potential, the first discharge circuit 14 is not turned on, so that the first node Q and the second voltage source VSS1 are electrically disconnected.

In this embodiment, by coupling the first current storage unit 12 to the first node Q, the first node Q stores the potential of the first clock signal ECK. Thereby, when the first pull-up signal G is in the enable period and the first clock signal ECK is in the enable period, the first pull-up unit 13 can be surely driven by the received first clock signal ECK to drive the first voltage The source VDD is connected to the output terminal S.

On the other hand, please refer to FIG. 1 again. The pull-down control unit 21 is used to receive the pull-down signal G'and output the pull-down signal G'to the second node K. The second current storage unit 22 is coupled to the second node K to accumulate The charge output to the second node K is accumulated. The pull-down unit 23 is coupled to the second node K to receive the pull-down signal G', and electrically connects the output terminal S to the third voltage source VSS2 according to the pull-down signal G'. The second discharge circuit 24 is coupled to the second node K and the fourth voltage source VSS3 for receiving the first pull-up signal G and electrically connecting the second node K and the fourth voltage source VSS3 according to the first pull-up signal G .

In the embodiment of FIG. 1, the structure of the pull-down circuit 2 is similar to that of the first pull-up circuit 1, in which the pull-down control unit 21, the pull-down unit 23, and the second discharge circuit 24 can be implemented by switching elements. When the pull-down signal G′ received by the pull-down control unit 21 is at the enable potential, the pull-down control unit 21 is turned on to output the pull-down signal G′ to the second node K, and the pull-down unit receives the pull-down signal G′ from the second node K 23 is turned on to control the third voltage source VSS2 to be electrically connected to the output terminal S; when the pull-down signal G'does not reach the enable potential, the pull-down control unit 21 does not output the pull-down signal G'to the second node K, and the pull-down unit 23 enables The third voltage source VSS2 is not electrically connected to the output terminal S. When the first pull-up signal G is in the enable period, the second discharge circuit 24 is turned on to electrically connect the second node K and the fourth voltage source VSS3; when the first pull-up signal G is in the disable period, the second The discharge circuit 24 is not conductive, so the second node K and the fourth voltage source VSS3 are not electrically connected.

In this embodiment, the enable period during which the first pull-up signal G is at the enable potential does not overlap with the enable period during which the pull-down signal is at the enable potential. Further, when the output voltage of the output terminal S is to be the voltage provided by the first voltage source VDD, the first pull-up signal G is in the enable period and the pull-down signal G'is in the disable period. As far as the first pull-up circuit 1 is concerned, the first pull-up control unit 11 is turned on to output the first clock signal ECK, and the first node Q stores the first clock signal ECK to turn on the first pull-up unit 13. As far as the pull-down circuit 2 is concerned, the pull-down control unit 21 is not turned on and the second discharge circuit 24 is turned on, so the second node K maintains the low voltage of the fourth voltage source VSS3, so that the first discharge circuit 14 is not turned on, so the first Festival The charge accumulated at the point Q will not leak through the first discharge circuit 14, so that the first pull-up unit 13 can continue to be in the on state.

On the other hand, when the output potential of the output terminal S is to be changed from the voltage provided by the first voltage source VDD to the voltage provided by the third voltage source VSS2, the pull-down signal G′ is in the enable period and the first pull-up signal G is in During disabling. As far as the pull-down circuit 2 is concerned, the pull-down control unit 21 is turned on and the second discharge circuit 24 is not turned on, so that the second node K accumulates the charge output from the pull-down control unit 21, and the pull-down unit 23 is continuously turned on. As for the first pull-up circuit 1, the first discharge circuit 14 is turned on due to the enable potential of the second node K, and the charge accumulated in the first node Q is discharged through the first discharge circuit 14 to cause the first The pull-up unit 13 is not conductive. In this way, the first voltage source VDD will not affect the output terminal S to output the voltage signal of the third voltage source VSS2.

In this embodiment, the first voltage source VDD provides a higher potential than the third voltage source VSS2. More specifically, the third voltage source VSS2 is a ground terminal. However, the present invention is not limited to this. In other embodiments, the third voltage source VSS2 may provide the same potential as the first voltage source VDD to extend the signal output time. Further, in this embodiment, the second voltage source VSS1, the third voltage source VSS2, and the fourth voltage source VSS3 are commonly coupled to a ground. However, the present invention is not limited to this. For example, in other embodiments, the second voltage source VSS1 and the fourth voltage source VSS3 may each provide low voltages with different potential values, as long as the first node Q and the second node K can be discharged.

Please refer to FIG. 2. In this embodiment, the first pull-up control unit 11 includes at least one first transistor T1 whose gate is used to receive the first pull-up signal G, and the drain and source of the first transistor T1 One of them receives the first clock signal ECK, and the other of the drain and source of the first transistor T1 is coupled to the first node Q. In this embodiment, the first pull-up control unit 11 includes one first transistor T1 as an example. However, the present invention is not limited to this. The first current storage unit includes a first capacitor C1 coupled to the first node Q and the fifth voltage Source VSS4. In this embodiment, the fifth voltage source VSS4 is the ground terminal VSS, so that the first node Q stores the potential of the first clock signal ECK, however, the present invention is not limited to this. The first pull-up unit 13 includes a second transistor T2, the gate of the second transistor T2 is coupled to the first node Q for receiving the first clock signal ECK, and the drain or source of the second transistor T2 is coupled Connected to the first voltage source VDD, the other one of the drain or the source of the second transistor T2 is coupled to the output terminal S to electrically connect the first voltage source VDD to the output when the second transistor T2 is turned on端S。 End S. The first discharge circuit 14 includes at least one third transistor (T31, T32), the gate of the third transistor (T31, T32) is coupled to the second node K, and the drain of the third transistor (T31, T32) One of the sources is coupled to the first node Q, and the other of the drain and source of the third transistor (T31, T32) is coupled to the second current source VSS1. This embodiment takes two third transistors (T31, T32) as an example, however, the present invention is not limited to this.

Please refer to FIG. 2 again. In the pull-down circuit 2 of this embodiment, the pull-down control unit 21 has a fourth transistor T4. The gate and the drain or the source of the fourth transistor T4 are used to receive the pull-down signal. G', the other one of the drain or the source of the fourth transistor T4 is coupled to the second node K. The second current storage unit 22 includes a second capacitor C2 coupled between the second node K and the sixth voltage source VSS5. The pull-down unit 23 includes a fifth transistor T5. The gate of the fifth transistor T5 is coupled to the second node K. One of the drain or the source of the fifth transistor T5 is coupled to the output terminal S. The fifth The other of the drain or the source of the transistor T5 is coupled to the third voltage source VSS2. The second discharge circuit 24 has at least one sixth transistor (T61, T62), the gate of the sixth transistor (T61, T62) is used to receive the first pull-up signal G, the sixth transistor (T61, T62) One of the drain and the source is coupled to the second node K, and the other of the drain and the source of the sixth transistor (T61, T62) is coupled to the fourth voltage source VSS3. This embodiment takes two sixth transistors (T61, T62) as an example, however, the present invention is not limited to this. FIG. 2 illustrates an embodiment of the shift register circuit Z of FIG. 1. However, it should be emphasized that the present invention is not limited to the circuit shown in FIG. For example, in In other embodiments, the first pull-up control unit 11, the first current storage unit 12, and the like may be replaced by other circuit elements.

Please refer to FIG. 2, FIG. 3 and FIG. 4, an embodiment of the present invention provides a driving method for the shift register circuit Z of FIG. 2 and a schematic diagram of a pulse wave implemented according to the driving method. The driving method provided in this embodiment includes at least the following steps. Step S100: during the first output period T1, output the first clock signal ECK to the first pull-up circuit 1; Step S102: during the first pull-up period t1 among the first output period T1, to the first pull-up circuit The first pull-up signal G is output; and step S104: during the first pull-down period t2 during the first output period T1 and after the first pull-up period t1, the pull-down signal G′ is output to the pull-down circuit 2.

Specifically, referring to FIG. 3, in step S100, the first clock signal ECK having the gate high potential V _GH is input to the source or the drain of the first transistor T1. In step S102, the first pull-up signal G of the gate high potential V _GH is input to the gate of the first transistor T1, so that the first transistor T1 is turned on to output the first clock signal ECK to the first node Q. In step S104, the pull-down signal _G'of the gate high potential V _GH is input to the gate of the fourth transistor T4, so that the fourth transistor T4 is turned on and the pull-down signal G'is output to the second node K.

As shown in FIG. 3, after the first transistor T1 receives the first pull-up signal G, the first node Q stores the charge of the first clock signal, where V _GH - V _TH represents the potential of the first clock signal minus the The crystal reaches the voltage at the first node Q after the threshold voltage. At the time t3 after receiving the first pull-up signal G and before the first pull-down period t2, since the first discharge circuit 14 is not turned on, the charge accumulated in the first node Q is difficult to leak through the first discharge circuit 14, so the first The node Q can maintain the potential of V _GH - V _TH during this period, so that the second transistor T2 is kept on for a predetermined output period t5, and the voltage supplied by the first voltage source VDD is output to the output terminal S.

After the output of the pull-down signal G', the second discharge circuit 24 is not conductive, so the second node K maintains the potential of V _GH - V _{TH for} the time t4, so that the fifth transistor T5 remains conductive, and the output terminal S continues Receive the supply voltage of the third voltage source VSS2 (the third voltage source VSS2 is the ground terminal VSS in this embodiment). At the same time, since the potential of the second node K turns on the third transistor (T31, T32) of the first discharge circuit, the first node Q is discharged to the second voltage source VSS1 through the third transistor (T31, T32) (Ground terminal VSS).

Through the above-mentioned technical means, this embodiment can effectively prevent the first node Q and the second node K from leaking when outputting signals. Therefore, on the one hand, the pulse width of the output signal can be extended, and on the other hand, the distortion of the output signal can be avoided. In addition, since the first pull-up circuit 1 and the pull-down circuit 2 alternately output signals to the output terminal S, the drive transistors (second transistor T2, fifth transistor T5) can be prevented from aging or even malfunctioning due to receiving a positive voltage for a long time .

Second embodiment

The shift register circuit Z and the driving method thereof according to the second embodiment of the present invention will be described below with reference to FIGS. 5 to 7. Please refer to FIG. 5. The main difference between this embodiment and the embodiment of FIG. 2 is that the shift register circuit Z of this embodiment further includes a second pull-up circuit 1 a. The second pull-up circuit 1a basically has the same structure as the first pull-up circuit 1. Specifically, the second pull-up circuit 1a includes a second pull-up control unit 11a, a third current storage unit 12a, a second pull-up unit 13a, and a third discharge circuit 14a. Similar to the first pull-up circuit, the second pull-up control unit 11a has a first transistor T12 for receiving the second clock signal EXCK; the third current storage unit 12a has a third capacitor C3 coupled to a third node Between P and the eighth voltage source VSS7; the second pull-up unit 13a has a second transistor T22; the third discharge circuit 14a has a third transistor (T33, T34), coupled to the third node P and the seventh voltage Source VSS6. The second pull-up control unit 11a, The functions of the third current storage unit 12a, the second pull-up unit 13a, and the third discharge circuit 14a are substantially the same as those of the first pull-up control unit 11, the first current storage unit 12, the first pull-up unit 13, and the first discharge circuit , So I won’t repeat them here. In this embodiment, the seventh voltage source VSS6 and the eighth voltage source VSS7 are coupled to the ground VSS, however, the invention is not limited thereto. In addition, the circuit structure of the second pull-up circuit 1a in FIG. 5 is only an example, and the present invention is not limited thereto. For example, in other embodiments, the second pull-up control unit 11a may be replaced with other switching elements, which is not limited to that shown in FIG. 5.

In this embodiment, the enable period of the first clock signal ECK and the enable period of the second clock signal do not overlap. In this way, the burden of driving transistors (T21, T22) can be further reduced, and the life of the circuit and the accuracy of the output signal can be improved.

Specifically, please refer to FIGS. 6 and 7. The driving method provided in this embodiment includes at least the following steps. Step S200: output the first clock signal ECK to the first pull-up circuit during the first output period T1; Step S202: output to the first pull-up circuit during the first pull-up period t1 among the first output period T1 First pull-up signal G; Step S204: During the first output period T1 and in the first pull-down period t2 after the first pull-up period t1, the pull-down signal G'is output to the pull-down circuit; Step S206: At the first output During the second output period T2 after the period T1, the second clock signal T is output to the second pull-up circuit; Step S208: During the second pull-up period t1' in the second output period T2, the second pull-up circuit Output the second pull-up signal G; and Step S210: output the pull-down signal G'to the pull-down circuit during the second output period T2 and in the second pull-down period t2' after the second pull-up period t1'.

As shown in FIG. 6, the waveform corresponding to the first output period T1 is the same as FIG. 3, and corresponds to step S200, step S202, and step S204, and details are not described herein again. The difference between the driving method of this embodiment and the previous embodiment is that in step S206, the second clock signal EXCK is output to the second pull-up circuit 1a during the second output period T2. In detail, the second pull-up circuit The first transistor T12 of the second pull-up control unit 11a of 1a outputs the second clock signal EXCK of the gate high potential V _GH . Next, in step S208, during the second pull-up period t1' in the second output period T2, the second pull-up of the gate high potential V _GH is output to the gate of the first transistor T12 of the second pull-up circuit 1a The signal G makes the first transistor T12 conduct, and then receives and outputs the second clock signal EXCK to the third node P. Here, the third node P corresponds to the first node Q during the first output period T1, stores the second clock signal EXCK output by the first transistor T12 through the third capacitor C3, and reaches the potential V _GH - V _TH and The second transistor T22 is turned on to output the voltage signal of the first voltage source VDD. Since the third discharge circuit 14a does not conduct during the period t6 when the third node P maintains a high potential (the second node K remains at a low potential VSS during this period), the charge accumulated in the third node P is prevented from leaking through the third discharge circuit 14a. Therefore, the third node P can be maintained at the V _GH - V _TH potential during the period t6 to keep the second transistor T22 on, so that the output time t7 of the output terminal S of the second output period T2 is equal to t6.

It should be noted that, in this embodiment, the first transistor T11 of the first pull-up circuit 1 and the first transistor T12 of the second pull-up circuit 1a actually receive the first pull-up signal G and the second pull-up at the same time The signal G, however, the clock signals ECK and EXCK received by the first transistor T11 and the first transistor T12, respectively, do not overlap during the enabling period. That is, in this embodiment, when the first transistor T11 and the first transistor When T12 receives the first pull-up signal G and the second pull-up signal G during the first output period T1, the first clock signal ECK received by the first transistor T11 is the gate high potential V _GH and the first transistor T12 The received second clock signal EXCK is the gate collector low potential V _GL , so the first transistor T12 will not be driven during the first output period T1. Conversely, when the first transistor T11 and the first transistor T12 receive the first pull-up signal G and the second pull-up signal G during the second output period T2, the first clock signal ECK received by the first transistor T11 The second clock signal EXCK received by the first transistor T12 for the gate collection low potential V _GL is the gate high potential V _GH , so the first transistor T11 will not be driven during the second output period T2.

In addition, in this embodiment, the first pull-up signal G received by the first pull-up control unit 11 and the second pull-up signal G received by the second pull-up control unit 11a have the same potential, and may come from the same voltage generator. However, the present invention is not limited to this. For example, in other embodiments, the first pull-up signal may be different from the second pull-up signal, as long as the first transistors T11 and T12 can be turned on.

Please refer to Figure 6. Next, in step S210, in the second pull-down period t2' after the second pull-up period t1', a pull-down signal G'is output to the pull-down circuit, the second node K starts to store charge, and the fifth transistor T5 is turned on to output The output potential of the terminal S drops to VSS, and the third discharge circuit 14a is turned on to discharge the third node P.

In this embodiment, the shift register circuit Z further includes a second pull-up circuit 1a to receive the alternately enabled clock signals ECK and EXCK with the first pull-up circuit 1. In this way, the aging of the driving transistors T11 and T12 can be delayed to improve the reliability of the output signal.

Third embodiment

Referring to FIG. 8, the shift register circuit Z provided in this embodiment is compared with the embodiment in FIG. 5. The main difference is that the shift register circuit Z in this embodiment further includes a seventh transistor (T71, T72). Specifically, in the third embodiment, the first pull-up control unit 11 includes a plurality of first transistors connected in series (T11, T12), and the second pull-up control unit 11a includes a plurality of first transistors connected in series (T13, T14). There is a fourth node (A, C) between every two adjacent serially connected first transistors (T11, T12), (T13, T14), and every two adjacent serially connected third transistors (T31, T32) , (T33, T34) With a fifth node (B, D). In this embodiment, one of the gate and the drain or the source of the seventh transistor (T71, T72) is coupled to the output terminal S, and the other of the drain or the source of the seventh transistor (T71, T72) One is coupled to the fourth node (A, C) and the fifth node (B, D). Thereby, when the output terminal S outputs the voltage signal VDD, the seventh transistor (T71, T72) will be turned on, so that the voltage signal VDD is output to each fourth node (A, C) and fifth node (B, D) . In this way, by making the fourth node (A, C) and the fifth node (B, D) maintain a high potential when the signal output of the output terminal S is performed, the first node Q and the third node P can be further prevented from maintaining the second When the transistors (T21, T22) are turned on, leakage occurs through the first transistor (T11, T12, T13, T14) or the third transistor (T31, T32, T33, T34).

In summary, the shift register circuit and the driving method thereof provided by the embodiments of the present invention are coupled to the first node, the second node, and the second voltage source through The potential of the node electrically connects the first node to the second voltage source", "the second discharge circuit is coupled to the second node and the fourth voltage source, the second discharge circuit is used to receive the first pull-up signal and according to the first The pull-up signal electrically connects the second node to the fourth voltage source" and the "non-overlap of the enable period of the first pull-up signal and the pull-down signal" to extend the pulse width of the output signal, And reduce the probability of failure of the first pull-up unit and the second pull-up unit.

The content disclosed above is only a preferred and feasible embodiment of the present invention, and therefore does not limit the scope of the patent application of the present invention, so any technical changes made by using the description and drawings of the present invention fall into the application of the present invention. Within the scope of the patent.

Z‧‧‧Shift register circuit

1‧‧‧ First pull-up circuit

11‧‧‧First pull-up control unit

12‧‧‧ First current storage unit

13‧‧‧First pull-up unit

14‧‧‧ First discharge circuit

T1‧‧‧ First transistor

T2‧‧‧second transistor

T31, T32 ‧‧‧ third transistor

C1‧‧‧ First capacitor

2‧‧‧pull-down circuit

21‧‧‧Pull-down control unit

22‧‧‧second current storage unit

23‧‧‧Pull-down unit

24‧‧‧Second discharge circuit

T4‧‧‧ fourth transistor

T5‧‧‧ fifth transistor

T61, T62 ‧‧‧ sixth transistor

VDD, VSS1, VSS2, VSS3, VSS4, VSS5 ‧‧‧ voltage source

G‧‧‧First pull-up signal

ECK‧‧‧ First clock signal

G’‧‧‧ pull down signal

Q‧‧‧The first node

K‧‧‧The second node

Claims (14)

A shift register circuit, including: A first pull-up circuit, including: A first pull-up control unit for receiving a first pull-up signal, and receiving and outputting a first clock signal to a first node according to the pull-up signal; A first current storage unit coupled to the first node; A first pull-up unit, coupled to the first node, a first voltage source, and an output terminal, is used to receive the first clock signal, and according to the first clock signal, the first voltage source and The output is electrically connected; and A first discharge circuit, coupled to the first node, a second node, and a second voltage source, for electrically connecting the first node and the second voltage source according to the potential of the second node; and A pull-down circuit, including: A pull-down control unit for receiving the pull-down signal and outputting the pull-down signal to the second node; A second current storage unit coupled to the second node; A pull-down unit, coupled to the second node, the output terminal, and a third voltage source, for receiving the pull-down signal, and electrically connecting the third voltage source and the output terminal according to the pull-down signal; and A second discharge circuit is coupled to the second node and a fourth voltage source. The second discharge circuit is used to receive the first pull-up signal and enable the second node and the first node according to the first pull-up signal Four voltage sources are electrically connected, Wherein, the coincidence energy period of the first pull-up signal and the coincidence energy period of the pull-down signal do not overlap. The shift register circuit according to claim 1, wherein the potential provided by the first voltage source is higher than the potential provided by the third voltage source. The shift register circuit of claim 1, wherein the first pull-up control unit includes at least one first transistor, and a gate of the at least one first transistor is used to receive the first pull-up signal , One of the drain and source of the at least one first transistor is used to receive the first clock signal, and the other of the drain and source of the at least one first transistor is coupled to the first A node. The shift register circuit according to claim 1, wherein the first current storage unit includes a first capacitor, and the first capacitor is coupled between the first node and a fifth voltage source. The shift register circuit according to claim 1, wherein the first pull-up unit includes a second transistor, the gate of the second transistor is coupled to the first node, and the second transistor The drain or source of is coupled to the first voltage source, and the other one of the drain or source of the second transistor is coupled to the output. The shift register circuit of claim 1, wherein the first discharge circuit has at least one third transistor, the gate of the at least one third transistor is coupled to the second node and the at least one first transistor One of the drain and source of the three transistors is coupled to the first node, and the other of the drain and source of the at least one third transistor is coupled to the second current source. The shift register circuit according to claim 1, wherein the pull-down control unit has a fourth transistor, a gate of the fourth transistor, and one of a drain or a source of the fourth transistor One is for receiving the pull-down signal, and the other one of the drain or the source of the fourth transistor is coupled to the second node. The shift register circuit according to claim 1, wherein the second current storage unit includes a second capacitor, and the second capacitor is coupled between the second node and a sixth voltage source. The shift register circuit according to claim 1, wherein the pull-down unit has a fifth transistor, a gate of the fifth transistor is coupled to the second node, and a drain of the fifth transistor One of the sources is coupled to the output, and the other of the drain or source of the fifth transistor is coupled to the third voltage source. The shift register circuit according to claim 1, wherein the second discharge circuit has at least one sixth transistor, the gate of the at least one sixth transistor is used to receive the first pull-up signal, the One of the drain and source of at least one sixth transistor is coupled to the second node, and the other of the drain and source of the at least one sixth transistor is coupled to the fourth current source. The shift register circuit according to claim 1, wherein the first pull-up control unit has a plurality of first transistors connected in series, and gates of the plurality of first transistors are used to receive the first Pull signal, one of the drain and source of the at least one first transistor is used to receive the first clock signal, and the other of the drain and the source of the at least one first transistor is coupled to The first node, and there is a fourth node between every two adjacent serially connected first transistors; the first discharge circuit has a plurality of third transistors, the gate coupling of the plurality of third transistors Connected to the second node, one of the drains and sources of the plurality of third transistors is coupled to the first node, and the drains of the plurality of third transistors are coupled to the other one of the sources It is connected to the second current source, and there is a fifth node between every two adjacent third transistors connected in series. The shift register circuit further includes: A seventh transistor, one of the gate of the seventh transistor and the drain or source of the seventh transistor is coupled to the output terminal, and the other of the drain or source of the seventh transistor One is coupled to each of the fourth node and each of the fifth node. The shift register circuit as described in claim 1 includes: A second pull-up circuit, including: A second pull-up control unit for receiving a second pull-up signal, and receiving and outputting a second clock signal to a third node according to the second pull-up signal; A third current storage unit, coupled to the third node; A second pull-up unit, coupled to the third node, the output terminal, and the first voltage source, is used to receive the second clock signal, and according to the second clock signal, the first voltage source and The output is electrically connected, and A third discharge circuit, coupled to the third node, the second node and a seventh voltage source, for electrically connecting the third node and the seventh voltage source according to the potential of the second node, Wherein, the coincidence energy period of the first clock signal and the coincidence energy period of the second clock signal do not overlap. A method for driving a shift register circuit for driving the shift register circuit according to any one of claims 1 to 11, the driving method includes: During a first output period, output the first clock signal to the first pull-up circuit; During a first pull-up period among the first output periods, output the first pull-up signal to the first pull-up circuit; and The pull-down signal is output to the pull-down circuit during the first output period and a first pull-down period after the first pull-up period. A driving method of a shift register circuit for driving the shift register circuit according to claim 12, the driving method includes: During a first output period, output the first clock signal to the first pull-up circuit; During a first pull-up period among the first output periods, output the first pull-up signal to the first pull-up circuit; Output the pull-down signal to the pull-down circuit during the first output period and a first pull-down period after the first pull-up period; Outputting the second clock signal to the second pull-up circuit in a second output period after the first output period; During a second pull-up period among the second output periods, output the second pull-up signal to the second pull-up circuit; and During the second output period and a second pull-down period after the second pull-up period, the pull-down signal is output to the pull-down circuit.

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