TWI777777B - Shift register and display device - Google Patents

Abstract

A shift register and a display device are provided. The shift register includes a pull-up control circuit, a pull-up circuit, a pull-down control circuit, a pull-down circuit, and a fast pull-down circuit. The pull-up control circuit is used to set an internal drive voltage. The pull-up circuit provides a gate signal and a driving signal based on a first clock signal and the internal driving voltage. The pull-down control circuit and the pull-down circuit pull down the gate signal, the internal drive voltage, and the drive signal based on the internal drive voltage. The fast pull-down circuit selects one of a first drive signal and a second drive signal based on a first timing control signal and a second timing control signal, and pulls down the gate signal based on the selected first drive signal or the selected second drive signal.

Description

Shift register and display device

The present invention relates to a shifter circuit, and more particularly, to a shift register and a display device.

In an active display panel, a gate driver provides a gate signal to a pixel to control the opening and closing of the pixel, wherein the gate driver has a plurality of displacement registers. At present, although the shift register of the gate driver can support the clock-aligned design at the same time and has a pre-charge function, the current gate driver meets the customer's demand for switching the resolution of the display panel. Therefore, The circuit design of the gate driver and even the displacement register needs to be updated.

The invention provides a displacement register and a display device, which can adapt to the change of the operation frequency of the display device.

The shift register of the present invention includes a pull-up control circuit, a pull-up circuit, a pull-down control circuit, a pull-down circuit and a fast pull-down circuit. The pull-up control circuit receives the first scanning direction voltage, the second scanning direction voltage, the first driving signal and the second driving signal, and is based on the first scanning direction voltage, the second scanning direction voltage, the first driving signal and the second driving signal Set the internal drive voltage. The pull-up circuit receives the first clock signal and the internal driving voltage, and provides a gate signal and a third driving signal based on the first clock signal and the internal driving voltage. The pull-down control circuit receives the internal driving voltage, pulls down the gate signal and the internal driving voltage based on the internal driving voltage, and provides the internal control signal. The pull-down circuit receives the internal control signal to pull down the gate signal and the third driving signal based on the internal control signal. The fast pull-down circuit receives the first timing control signal, the second timing control signal, the fourth driving signal and the fifth driving signal to select the fourth driving signal and the fifth driving signal based on the first timing control signal and the second timing control signal one of the signals, and the gate signal is pulled low based on the selected fourth and fifth drive signals.

The display device of the present invention includes a display panel, a source driver and a gate driver. The source driver receives at least one first control signal to provide a plurality of pixel voltages to the display panel. The gate driver has a plurality of displacement registers as described above, so as to provide a plurality of gate signals and a plurality of driving signals to the display panel.

Based on the above, in the shift register and the display device according to the embodiments of the present invention, the fast pull-down circuit can select driving signals with different timings in response to the first timing control signal and the second timing control signal, so as to avoid the output gate signal And the driving signal is pulled down early, thereby adapting to the change of the operating frequency of the display device.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed as having meanings consistent with their meanings in the context of the related art and the present invention, and are not to be construed as idealized or excessive Formal meaning, unless expressly defined as such herein.

It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or or parts shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, "a first element," "component," "region," "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms including "at least one" unless the content clearly dictates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms "comprising" and/or "comprising" designate the stated feature, region, integer, step, operation, presence of an element and/or part, but do not exclude one or more The presence or addition of other features, entireties of regions, steps, operations, elements, components, and/or combinations thereof.

FIG. 1 is a schematic circuit diagram of a shift register according to a first embodiment of the present invention. Referring to FIG. 1 , in this embodiment, the shift register 100 includes a pull-up control circuit 110 , a pull-up circuit 120 , a pull-down control circuit 130 , a pull-down circuit 140 , and a fast pull-down circuit 150 .

The pull-up control circuit 110 receives the first scanning direction voltage U2D, the second scanning direction voltage D2U, the driving signal ST(n-4) (corresponding to the first driving signal) and the driving signal ST(n+8) (corresponding to the second driving signal) ) to set the internal driving voltage Q based on the first scanning direction voltage U2D, the second scanning direction voltage D2U, the driving signal ST(n-4) and the driving signal ST(n+8). Among them, n is an index and is a positive integer.

In the embodiment of the present invention, the voltage levels of the first scanning direction voltage U2D and the second scanning direction voltage D2U are opposite to each other, that is, when the first scanning direction voltage U2D is one of a high voltage level and a low voltage level , the second scanning direction voltage D2U is the other of the high voltage level and the low voltage level. For forward scanning, under different operating frequencies, the driving signal ST(n-4) can be a driving signal that leads the driving signal ST(n) by 4/2 time units (for example, the time of one horizontal scanning line). , the driving signal ST(n+8) is a driving driving signal that lags behind the driving signal ST(n) by 8/4 time units; for reverse scanning, the above relationship is reversed.

The pull-up circuit 120 is coupled to the pull-up control circuit 110 and receives the clock signal HC1 (corresponding to the first clock signal) and the internal driving voltage Q, so as to provide the corresponding gate signal G based on the clock signal HC1 and the internal driving voltage Q (n) and the corresponding drive signal ST(n) (corresponding to the third drive signal). The pull-down control circuit 130 is coupled to the pull-up control circuit 110 to pull down the gate signal G(n) and the internal driving voltage Q based on the internal driving voltage Q, and provide the internal control signal P.

The pull-down circuit 140 is coupled to the pull-up circuit 120 and the pull-down control circuit 130 , and receives the internal control signal P to pull down the gate signal G(n) and the driving signal ST(n) based on the internal control signal P. The fast pull-down circuit 150 is coupled to the pull-up circuit 120 and receives the first timing control signal MD1, the second timing control signal MD2, the driving signal ST(n+4) (corresponding to the fourth driving signal) and the fifth driving signal ST ( n+2) (corresponding to the fifth driving signal) to select one of the driving signal ST(n+4) and the driving signal ST(n+2) based on the first timing control signal MD1 and the second timing control signal MD2 , and pull down the gate signal G(n) based on the selected drive signal ST(n+4) and drive signal ST(n+2).

In terms of forward scanning, under different operating frequencies, the driving signal ST(n+4) can be a driving signal that lags behind the driving signal ST(n) by 4/2 time units, and the driving signal ST(n+2) It is a driving driving signal that lags behind the driving signal ST(n) by 2/1 time unit. In the embodiment of the present invention, it is assumed that the gate signal G(n) and the driving signal ST(n) enable two time units to provide sufficient response time (ie, charging time) for the pixels. At this time, the fast pull-down circuit 150 can In response to the first timing control signal MD1 and the second timing control signal MD2, the driving signal ST(n+4) and the driving signal ST(n+2) are selected to avoid the gate signal G(n) and the driving signal ST(n ) is pulled down early, thereby adapting to changes in the operating frequency of the display device (the display device 10 shown in FIG. 4 ).

In the embodiment of the present invention, the pull-up control circuit 110 selects one of the first scanning direction voltage U2D and the second scanning direction voltage D2U based on the driving signal ST(n-4) and the driving signal ST(n+8), and The internal driving voltage Q is set based on the selected first scan direction voltage U2D or second scan direction voltage D2U. For example, when performing forward scanning, the first scanning direction voltage U2D is at a high voltage level, and the second scanning direction voltage D2U is at a low voltage level. Therefore, during forward scanning, the internal driving voltage Q is set to a high voltage level by the first scan direction voltage U2D, and the internal driving voltage Q is set to a low voltage level by the second scan direction voltage D2U. During reverse scanning, the first scanning direction voltage U2D is at a low voltage level, and the second scanning direction voltage D2U is at a high voltage level. Therefore, during reverse scanning, the internal driving voltage Q is set to a high voltage level by the second scanning direction voltage D2U, and the internal driving voltage Q is set to a low voltage level by the first scanning direction voltage U2D.

In the embodiment of the present invention, the pull-up control circuit 110 includes a first transistor M1, a second transistor M2 and a third transistor M3. The first transistor M1 has a first terminal receiving the first scanning direction voltage U2D, a control terminal receiving the driving signal ST(n-4), and a second terminal coupled to the internal driving voltage Q. The second transistor M2 has a first terminal receiving the second scanning direction voltage D2U, a control terminal receiving the driving signal ST(n+8), and a second terminal coupled to the internal driving voltage Q. The third transistor M3 has a first terminal coupled to the internal driving voltage Q, a control terminal receiving the gate high voltage VGH, and a second terminal coupled to the second terminal of the first transistor M1. Before the node of the internal driving voltage Q is coupled to a higher voltage by the clock signal HC1, the third transistors M3 are all turned on, but when the node of the internal driving voltage Q is coupled to a higher voltage by the clock signal HC1, the third transistor M3 is turned on. The transistor M3 is turned off (that is, in an off state. When the third transistor M3 is turned on, the second terminals of the first transistor M1 and the second transistor M2 can instantly set the internal driving voltage Q. Further, , because when the node of the internal driving voltage Q is pumped to a higher voltage of the third transistor M3, the voltage level of the second end of the third transistor M3 is charged to the gate high voltage VGH and the third transistor M3 is turned off , so the third transistor M3 can reach the node that reduces the internal driving voltage Q and is affected by the leakage of the ninth transistor M9/second transistor M2 when it is pumped. In other words, the third transistor M3 has considerable technical effects, including There is a need, and therefore, cannot be ignored in some embodiments.

In the embodiment of the present invention, the pull-up circuit 120 includes a fourth transistor M4, a fifth transistor M5 and a sixth transistor M6. The fourth transistor M4 has a first terminal for receiving the clock signal HC1, a control terminal coupled to the internal driving voltage Q, and a second terminal for providing the gate signal G(n). The fifth transistor M5 has a first terminal for receiving the clock signal HC1, a control terminal coupled to the internal driving voltage Q, and a second terminal for providing the driving signal ST(n). The sixth transistor M6 is coupled to form a capacitor between the internal driving voltage Q and the gate signal G(n).

In the embodiment of the present invention, the pull-down control circuit 130 includes a seventh transistor M7 , an eighth transistor M8 , a ninth transistor M9 , a tenth transistor M10 , an eleventh transistor M11 and a resistor R. The seventh transistor M7 has a first terminal receiving the gate high voltage VGH, a control terminal receiving a clock signal HC9 (corresponding to the second clock signal), and a second terminal, wherein the phase of the clock signal HC9 is different from the clock Signal HC1. The eighth transistor M8 has a first terminal for providing the internal control signal P, a control terminal for coupling with the internal driving voltage Q, and a second terminal for receiving the power low voltage XDONB.

The resistor R is coupled between the second end of the seventh transistor M7 and the first end of the eighth transistor M8. The ninth transistor M9 has a first terminal coupled to the internal driving voltage Q, a control terminal receiving the internal control signal P, and a second terminal receiving the power low voltage XDONB. The tenth transistor M10 has a first terminal for receiving the reset signal RST, a control terminal for receiving the reset signal RST, and a second terminal coupled to the first terminal of the eighth transistor M8. The eleventh transistor M11 has a first terminal receiving the gate signal G(n), a control terminal receiving the gate signal G(n), and a second terminal coupled to the first terminal of the ninth transistor M9.

Moreover, according to different circuit designs, the tenth transistor M10 and the eleventh transistor M11 may be ignored, but the embodiment of the present invention is not limited thereto.

In the embodiment of the present invention, the pull-down circuit 140 includes a twelfth transistor M12 and a thirteenth transistor M13. The twelfth transistor M12 has a first terminal for receiving the gate signal G(n), a control terminal for receiving the internal control signal P, and a second terminal for receiving the power supply low voltage XDONB. The thirteenth transistor M13 has a first terminal receiving the third driving signal ST(n), a control terminal receiving the internal control signal P, and a second terminal receiving the power supply low voltage XDONB.

In the embodiment of the present invention, the fast pull-down circuit 150 includes a fourteenth transistor M14, a fifteenth transistor M15 and a sixteenth transistor M16. The fourteenth transistor M14 has a first terminal for receiving the gate signal G(n), a control terminal, and a second terminal for receiving the power supply low voltage XDONB. The fifteenth transistor M15 has a first terminal receiving the driving signal ST(n+4), a control terminal receiving the first timing control signal MD1, and a second terminal coupled to the control terminal of the fourteenth transistor M14. The sixteenth transistor M16 has a first terminal receiving the driving signal ST(n+2), a control terminal receiving the second timing control signal MD2, and a second terminal coupled to the control terminal of the fourteenth transistor M14.

2 is a schematic diagram of a high-frequency operation waveform of the displacement register performing forward scanning according to the first embodiment of the present invention. Please refer to FIG. 1 and FIG. 2 , during high-frequency operation, the width of the enable level (ie, the high voltage level) of the clock signal (here, 12 clock signals HC1-HC12 are taken as an example) is 2 The time unit (that is, the time of 2 horizontal scanning lines), the period is 12 time units (that is, the time of 12 horizontal scanning lines), and each clock signal (such as the clock signal HC1-HC12) and the next clock signal (For example, the time difference of the clock signals HC1-HC12) is 1 time unit (that is, the time of 1 horizontal scanning line). At this time, the signal width of the output gate signal G(n) and the driving signal ST(n) is 2 time units (that is, the time of 2 horizontal scanning lines), and the gate signal G(n)/driving signal ST( The time difference between n) and the next gate signal G(n+1)/next driving signal ST(n+1) is 1 time unit (ie, the time of 1 horizontal scanning line).

During high frequency operation, the second timing control signal MD2 turns on the sixteenth transistor M16, and the first timing control signal MD1 turns off the fifteenth transistor M15. At this time, the pull-down function of the fourteenth transistor M14 is controlled by the driving signal ST(n+2), so that the gate signal G(n)/driving signal ST(n) and the next gate signal G(n+1) /The time difference of the next driving signal ST(n+1) is 1 time unit (ie, the time of 1 horizontal scanning line).

3 is a schematic diagram of a low frequency operation waveform of the displacement register performing forward scanning according to the first embodiment of the present invention. Please refer to FIG. 1 and FIG. 3 , in the low frequency operation, the width of the enable level (ie the high voltage level) of the clock signal (here, the 12 clock signals HC1-HC12 are taken as an example) is 2 times Unit (that is, 2 horizontal scanning lines), the period is 6 time units (that is, 6 horizontal scanning lines), and the clock signals (such as clock signals HC1-HC12) have the same phase in pairs. (ie no time difference). At this time, the signal width of the output gate signal G(n) and the driving signal ST(n) is 2 time units (that is, the time of 2 horizontal scanning lines), and the gate signal G(n)/driving signal ST( n) and the next gate signal G(n+1)/next driving signal ST(n+1) have no time difference.

During low frequency operation, the second timing control signal MD2 turns off the sixteenth transistor M16, and the first timing control signal MD1 turns on the fifteenth transistor M15. At this time, the pull-down function of the fourteenth transistor M14 is controlled by the driving signal ST(n+4), so that the gate signal G(n)/driving signal ST(n) and the next gate signal G(n+1) /The next drive signal ST(n+1) has no time difference.

FIG. 4 is a system schematic diagram of a display device according to an embodiment of the present invention. Referring to FIG. 1 and FIG. 4 , in this embodiment, the display device 10 includes a timing controller 11 , a source driver 12 , a gate driver 13 and a display panel 14 . The timing controller 11 is coupled to the source driver 12 to provide a plurality of first control signals SC1, and is coupled to the gate driver 13 to provide a plurality of second control signals SC2 (as shown in FIG. 1 , the first scanning direction voltage U2D, the second scanning direction voltage, reset signal RST, first timing control signal MD1, second timing control signal MD2, etc.).

The source driver 12 is coupled to the display panel 14 to provide a plurality of pixel voltages Vpx to the display panel 14 based on the first control signal SC1. The gate driver 13 is coupled to the display panel 14 to provide a plurality of gate signals (such as G_D1-G_D4, G[1]-G[12] and/or a plurality of driving signals (as shown in FIG. 1 ) based on the second control signal SC2 drive signal ST(n)), and the gate driver 13 includes a plurality of shift registers (eg, SR[D1]-SR[D4], SR[1]-SR[12]), wherein each shift register (For example, SR[D1]-SR[D4], SR[1]-SR[12]) can be described with reference to the embodiment of the shift register 100, and details are not repeated here.

5 is a schematic circuit diagram of a shift register according to a second embodiment of the present invention. Please refer to FIG. 1 and FIG. 5 , in this embodiment, the shift register 200 is substantially the same as the shift register 100 , and the difference is that the fast pull-down circuit 250 further includes a seventeenth transistor M17 and an eighteenth transistor Crystal M18. The seventeenth transistor M17 has a first terminal receiving the driving signal ST(n-4) (corresponding to the sixth driving signal), a control terminal receiving the third timing control signal MD3, and a control terminal coupled to the fourteenth transistor M14 the second end of the end. The eighteenth transistor M18 has a first terminal receiving the driving signal ST(n-2) (corresponding to the seventh driving signal), a control terminal receiving the fourth timing control signal MD4, and a control terminal coupled to the fourteenth transistor M14 the second end of the end.

6 is a schematic diagram of a high-frequency operation waveform of the displacement register performing reverse scanning according to the second embodiment of the present invention. 5 and FIG. 6 , during high frequency operation, the second timing control signal MD2 turns off the sixteenth transistor M16, the first timing control signal MD1 turns off the fifteenth transistor M15, and the third timing control signal turns off the fifteenth transistor M15. MD3 turns off the seventeenth transistor M17, and the fourth timing control signal MD4 turns on the eighteenth transistor M18. At this time, the pull-down function of the fourteenth transistor M14 is controlled by the driving signal ST(n-2), so that the gate signal G(n)/driving signal ST(n) and the next gate signal G(n-1) /The time difference of the next driving signal ST(n-1) is 1 time unit (ie, the time of 1 horizontal scanning line).

FIG. 7 is a schematic diagram of a low frequency operation waveform of the displacement register performing reverse scanning according to the second embodiment of the present invention. Please refer to FIG. 5 and FIG. 7 , during low frequency operation, the second timing control signal MD2 turns off the sixteenth transistor M16, the first timing control signal MD1 turns off the fifteenth transistor M15, and the third timing control signal MD3 turns off the fifteenth transistor M15. The seventeenth transistor M17 is turned on, and the fourth timing control signal MD4 turns off the eighteenth transistor M18. At this time, the pull-down function of the fourteenth transistor M14 is controlled by the driving signal ST(n-4), so that the gate signal G(n)/driving signal ST(n) and the next gate signal G(n-1) /The next drive signal ST(n-1) has no time difference.

To sum up, in the shift register and the display device according to the embodiments of the present invention, the fast pull-down circuit can select driving signals with different timings in response to the first timing control signal and the second timing control signal, so as to avoid the output gate The pole signal and the drive signal are pulled down early, thereby adapting to changes in the operating frequency of the display device.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

10: Display device

11: Timing Controller

12: Source driver

13: Gate driver

14: Display panel

100, 200, SR[D1]-SR[D4], SR[1]-SR[12]: Shift register

110: Pull-up control circuit

120: Pull-up circuit

130: Pull-down control circuit

140: pull-down circuit

150, 250: Fast pull-down circuit

D2U: Voltage in the second scanning direction

G(n), G_D1-G_D4, G[1]-G[12]: gate signal

HC1-HC12: Clock signal

M1: first transistor

M10: Tenth transistor

M11: Eleventh transistor

M12: The twelfth transistor

M13: Thirteenth transistor

M14: The fourteenth transistor

M15: The fifteenth transistor

M16: Sixteenth transistor

M17: The seventeenth transistor

M18: Eighteenth transistor

M2: second transistor

M3: The third transistor

M4: Fourth transistor

M5: Fifth transistor

M6: sixth transistor

M7: seventh transistor

M8: Eighth transistor

M9: ninth transistor

MD1: The first timing control signal

MD2: The second timing control signal

MD3: The third timing control signal

MD4: Fourth timing control signal

P: Internal control signal

Q: Internal drive voltage

R: resistance

RST: reset signal

SC1: the first control signal

SC2: The second control signal

ST(n-1)-ST(n-4), ST(n+8), ST(n), ST(n+1)-ST(n+4): drive signal

U2D: Voltage in the first scan direction

VGH: Gate High Voltage

Vpx: pixel voltage

XDONB: Power supply low voltage

FIG. 1 is a schematic circuit diagram of a shift register according to a first embodiment of the present invention. 2 is a schematic diagram of a high-frequency operation waveform of the displacement register performing forward scanning according to the first embodiment of the present invention. 3 is a schematic diagram of a low frequency operation waveform of the displacement register performing forward scanning according to the first embodiment of the present invention. FIG. 4 is a system schematic diagram of a display device according to an embodiment of the present invention. 5 is a schematic circuit diagram of a shift register according to a second embodiment of the present invention. 6 is a schematic diagram of a high-frequency operation waveform of the displacement register performing reverse scanning according to the second embodiment of the present invention. FIG. 7 is a schematic diagram of a low frequency operation waveform of the displacement register performing reverse scanning according to the second embodiment of the present invention.

100: Displacement register

110: Pull-up control circuit

120: Pull-up circuit

130: Pull-down control circuit

140: pull-down circuit

150: Fast pull-down circuit

D2U: Voltage in the second scanning direction

G(n): gate signal

HC1, HC9: clock signal

M1: first transistor

M10: Tenth transistor

M11: Eleventh transistor

M12: The twelfth transistor

M13: Thirteenth transistor

M14: The fourteenth transistor

M15: The fifteenth transistor

M16: Sixteenth transistor

M2: second transistor

M3: The third transistor

M4: Fourth transistor

M5: Fifth transistor

M6: sixth transistor

M7: seventh transistor

M8: Eighth transistor

M9: ninth transistor

MD1: The first timing control signal

MD2: The second timing control signal

P: Internal control signal

Q: Internal drive voltage

R: resistance

RST: reset signal

ST(n-4), ST(n+8), ST(n), ST(n+2), ST(n+4): drive signal

U2D: Voltage in the first scan direction

VGH: Gate High Voltage

XDONB: Power supply low voltage

Claims (13)

A displacement register, comprising: a pull-up control circuit, receiving a first scanning direction voltage, a second scanning direction voltage, a first driving signal and a second driving signal, so as to be based on the first scanning direction voltage, The second scanning direction voltage, the first driving signal and the second driving signal set an internal driving voltage; a pull-up circuit receives a first clock signal and the internal driving voltage based on the first clock signal and the internal driving voltage to provide a gate signal and a third driving signal; a pull-down control circuit, based on the internal driving voltage, pulls down the gate signal and the internal driving voltage, and provides an internal control signal; a pull-down circuit, receiving the internal control signal to pull down the gate signal and the third driving signal based on the internal control signal; and a fast pull-down circuit for receiving a first timing control signal, a second timing control signal, a fourth timing control signal driving signal and a fifth driving signal to select one of the fourth driving signal and the fifth driving signal based on the first timing control signal and the second timing control signal, and based on the selected fourth driving signal The gate signal is pulled down by the driving signal or the fifth driving signal. The shift register of claim 1, wherein the pull-up control circuit selects one of the first scanning direction voltage and the second scanning direction voltage based on the first driving signal and the second driving signal, and The internal driving voltage is set based on the selected first scan direction voltage or the second scan direction voltage. The shift register of claim 2, wherein the pull-up control circuit comprises: a first transistor having a first terminal for receiving the voltage in the first scanning direction, and a control terminal for receiving the first driving signal , and a second terminal coupled to the internal driving voltage; and a second transistor having a first terminal receiving the second scanning direction voltage, a control terminal receiving the second driving signal, and coupled to to a second terminal of the internal driving voltage. The displacement register of claim 3, wherein the pull-up control circuit further comprises: a third transistor having a first end coupled to the internal driving voltage, a control receiving a gate high voltage terminal, and a second terminal coupled to the second terminal of the first transistor. The shift register of claim 1, wherein the pull-up circuit comprises: a fourth transistor having a first terminal for receiving the first clock signal and a control terminal coupled to the internal driving voltage , and a second terminal for providing the gate signal; a fifth transistor having a first terminal for receiving the first clock signal, a control terminal coupled to the internal driving voltage, and providing the third a second end of the driving signal; A sixth transistor is coupled to form a capacitor between the internal driving voltage and the gate signal. The shift register according to claim 1, wherein the pull-down control circuit comprises: a seventh transistor having a first terminal receiving a gate high voltage, a control terminal receiving a second clock signal, and a second end; an eighth transistor having a first end for providing the internal control signal, a control end for coupling with the internal driving voltage, and a second end for receiving a low voltage of a power supply; a resistor, coupled between the second end of the seventh transistor and the first end of the eighth transistor; and a ninth transistor having a first end coupled to the internal driving voltage, receiving the internal a control terminal of the control signal, and a second terminal for receiving the low voltage of the power supply. The shift register of claim 6, wherein the pull-down control circuit further comprises: a tenth transistor having a first terminal for receiving a reset signal, a control terminal for receiving the reset signal, and a coupling A second end connected to the first end of the eighth transistor. The shift register of claim 6, wherein the pull-down control circuit further comprises: An eleventh transistor has a first end receiving the gate signal, a control end receiving the gate signal, and a second end coupled to the first end of the ninth transistor. The shift register of claim 1, wherein the pull-down circuit comprises: a twelfth transistor having a first terminal for receiving the gate signal, a control terminal for receiving the internal control signal, and a a second terminal of the power supply low voltage; and a thirteenth transistor having a first terminal for receiving the third driving signal, a control terminal for receiving the internal control signal, and a second terminal for receiving the power supply low voltage end. The shift register of claim 1, wherein the fast pull-down circuit comprises: a fourteenth transistor having a first terminal receiving the gate signal, a control terminal, and a power supply low voltage receiving a second terminal; a fifteenth transistor having a first terminal receiving the fourth driving signal, a control terminal receiving the first timing control signal, and a terminal coupled to the control terminal of the fourteenth transistor a second terminal; and a sixteenth transistor having a first terminal receiving the fifth driving signal, a control terminal receiving the second timing control signal, and the control terminal coupled to the fourteenth transistor a second end of the end. The shift register of claim 10, wherein the fast pull-down circuit further comprises: a seventeenth transistor having a first end receiving a sixth driving signal and a control receiving a third timing control signal terminal, and a second terminal coupled to the control terminal of the fourteenth transistor; and an eighteenth transistor having a first terminal for receiving a seventh driving signal, and a terminal for receiving a fourth timing control signal a control end, and a second end coupled to the control end of the fourteenth transistor. The displacement register of claim 1, wherein the voltage levels of the first scanning direction voltage and the second scanning direction voltage are opposite to each other. A display device, comprising: a display panel; a source driver receiving at least a first control signal to provide a plurality of pixel voltages to the display panel; a gate driver having a plurality of displacements as described in claim 1 The register is used to provide a plurality of gate signals and a plurality of driving signals to the display panel.

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