TWI684862B - Muti-state memory device and method for adjusting memory state characteristics of the same - Google Patents

Abstract

A multi-state memory device includes a first memory element, a second memory element, a first controlling element and a second controlling element. The second memory element has a memory cell structure identical to that of the first memory element and connects to the first memory element in series. The first controlling element is connected to the first memory element either in series or in parallel. The second controlling element has a characteristic value identical to that of the first controlling element and is electrically connected to the second memory element by a connection structure identical to that of the first controlling element. When the first memory element receives a first signal and a second signal through the first controlling element, a first state value and a second state value are generated correspondingly, and the characteristic value is greater than the first state value and less than the second state value.

Description

Multi-state memory element and method for adjusting memory state value

This disclosure is about a non-volatile memory (NVM). In particular, there is a method for adjusting a multi-state memory device (multi-state memory) and its memory state value (characteristics of memory-state).

Non-volatile memory elements have the property of not losing the information stored in the memory unit when the power is removed. At present, more widely used are charge storage flash (CTF) memory devices that use a charge trap (charge trap). However, as the accumulation density of the memory device increases, the critical size and pitch of the device decrease, and the charge storage type flash memory device faces its physical limit and cannot operate.

The multi-state memory element is to apply a plurality of different pulse voltages to the memory element to generate a plurality of memory state values as the basis for the judgment of the information storage state. Taking a resistive memory device as an example, when applying two different pulses to a resistive random access memory device (Resistive random-access memory, ReRAM) When a voltage is applied, the metal oxide film of the resistive random access memory device generates two different resistance values, which are used as the basis for judging the data storage status such as "0" and "1". Because multi-state memory devices are superior to flash memory in terms of device density, power consumption, programming/erasing speed, or three-dimensional space stacking characteristics. Therefore, it has become one of the memory devices that has attracted much attention in the industry.

However, for multi-state memory devices, due to process variation or dimensional tolerance of the device, the memory of each memory cell (or memory cell) located in the same memory string The distribution range of state values is different, which leads to the inability to accurately judge the data storage state of the multi-state memory device when reading data from these memory units with the same signal, which seriously affects the operational reliability of the multi-state memory device ( reliability).

Therefore, there is a need to provide an advanced multi-state memory device and its memory state value adjustment method to solve the problems faced by the conventional technology.

An embodiment of the present specification discloses a multi-state memory device. The multi-state memory device includes: a first memory unit, a second memory unit, a first control unit, and a second control unit. The second memory unit has substantially the same memory cell structure as the first memory unit, and is connected in series with the first memory unit. The first control unit and the first memory unit are connected in series or in parallel. The second control unit has the same characteristic values and phases as the first control unit The same connection structure is used to electrically connect with the second memory unit. When the first memory unit receives the first signal and the second signal via the first control unit, the first memory unit generates a first state value and a second state value respectively; wherein the characteristic value is between the first state value and the second state Between values.

Another embodiment of the present specification discloses a method for adjusting the memory state value of a multi-state memory element, including the following steps: providing a first memory unit and a memory cell structure having substantially the same memory cell structure as the first memory unit The second memory unit, and the first memory unit and the second memory unit are connected in series. A first control unit is provided to be connected in series or in parallel with the first memory unit. A second control unit is provided, having the same characteristic value and the same connection structure as the first control unit, for electrically connecting with the second memory unit. When the first memory unit receives the first signal and the second signal via the first control unit, the first memory unit respectively generates a first state value and a second state value; wherein the characteristic value is between the first state value And the second state value.

According to the above embodiment, the present specification discloses a multi-state memory device including at least one memory cell string and a method for adjusting the memory state value. It adopts series or parallel connection, and each memory cell (memory cell) in the same memory cell series is electrically connected to a control unit, which is used to adjust the memory state value of each memory cell and reduce the difference. The degree of distribution variation of the memory state value generated by the memory unit when receiving the same signal, so as to accurately judge the data storage state of the multi-state memory element.

In some embodiments of the present specification, the memory state value may be the resistance value, conductivity value or threshold voltage value of the memory cell voltage, Vth). The type of control unit depends on the selection of the memory state value, and may be a resistor with a stable resistance value or a switch with a stable threshold voltage. The connection mode (serial or parallel) of the control unit and the memory unit can be selected according to the type, application range and operation signal form of the multi-state memory device.

For example, in an embodiment of the present specification, when the multi-state memory device uses the resistance value of each memory cell as the basis for judging the data storage state (such as "0" and "1"), the control unit device It can be a resistor with stable resistance. And when the operation signal is a fixed voltage, each memory cell can be connected in series with a resistor to reduce the degree of variation in the distribution of the conductivity value of the memory cell used as the storage state value in the low resistance range; and When the operation signal is a fixed current, each memory cell can be connected in parallel with a resistor, thereby reducing the degree of variation in the distribution of the resistance value of the memory cell as a storage state value in the high resistance range.

In another embodiment of the present specification, when the multi-state memory device uses the threshold voltage value of each memory cell as the basis for judging the data storage state (such as "0" and "1"), the control unit device It can be a switch with stable threshold voltage. And when each memory cell is connected in series with a switch, the degree of variation in the distribution of the threshold voltage value used by the memory cell as the storage state value in the low threshold voltage range can be reduced; and when each memory cell is connected to When a switch is formed in parallel, the distribution variation of the critical voltage value used by the memory cell as the storage state value in the high critical voltage value range can be reduced.

100, 400, 700, 1000, 1100, 1200, 1300‧‧‧ multi-state memory device

101-104, 1001-1004, 1201-1204 ‧‧‧ memory unit

111-114, 1011-1014, 1211-1214, 1311-1314 ‧‧‧ selector switch

401-404, 701-704, 1005-1008, 1105-1108, 1205-1208, 1305-1308‧‧‧Control unit

101a-104a, 1001a-1004a, upper electrode layer

101b-104b, 1001b-1004b‧Lower electrode layer

101c-104c, 1001c-1004c ‧‧‧ transition metal layer

111a-114a, 1011a-1014a ‧‧‧ gate

111b-114b, 1011b-1014b‧‧‧Source

111c-114c, 1011c-1014c ‧‧‧ Drain

150, 150a-150e, 450, 450a-450e, 750, 750a-750e, 1050, 1150, 1250, 1350

131-134, 431-434, 731-734, 1031-1034, 1131-1134, 1231-1234, 1331-1334‧‧‧ memory cell structure

201, 202, 301-305, 501, 502, 601-605, 801, 802, 901-905

203, 213‧‧‧ critical resistance value

606-609‧‧‧critical conductivity

BL‧‧‧bit line

SL‧‧‧ common source line

LRS‧‧‧Low resistance area

HRS‧‧‧High resistance area

WL1, WL2, WL3, WL4 ‧‧‧ character line

In order to have a better understanding of the above and other aspects of this specification, the following examples are specifically described in conjunction with the drawings as follows: Figure 1 is a multi-state memory device according to an embodiment of this specification Block diagram of the circuit; Figure 2A shows that the first signal with a higher fixed voltage and the second signal with a lower fixed voltage are written separately for the memory cell structure of the multi-state memory device shown in Figure 1 After entering the program, the reading is performed by a read signal with a fixed voltage pulse, and the cumulative distribution function diagram of the resistance value is obtained; FIG. 2B is drawn according to FIG. 2A Cumulative distribution function diagram of conductance value; Figure 3 shows a memory string composed of the memory cells as shown in Figure 1. After applying the same voltage pulse to write to it, another one is used. The reading signal with a fixed voltage pulse is used for reading, and the resulting cumulative distribution function diagram of the sum of conductance values of the memory string; FIG. 4 is a diagram of a multi-state memory device according to another embodiment of the present specification. Schematic diagram of the circuit block; FIG. 5 shows the result of providing the first signal with a lower fixed voltage and the second signal with a higher fixed voltage to the memory cell structure of the multi-state memory device shown in FIG. 4 Cumulative distribution function diagram of the resistance value of a single memory cell; Figure 6 shows a series of memory composed of memory cells as shown in Figure 4, after applying the same voltage pulse to it The cumulative distribution function graph of the sum of conductance values of the obtained memory series; FIG. 7 is a schematic circuit block diagram of a multi-state memory device according to yet another embodiment of this specification; FIG. 8 is a diagram showing the structure of the memory cell of the multi-state memory device shown in FIG. 7; After the first signal with a higher fixed current and the second signal with a lower fixed current, the cumulative distribution function diagram of the resistance value of the single memory cell is obtained; Figure 9 shows The memory string of the memory unit is combined, and after providing the same current signal to it, the cumulative distribution function graph of the sum of conductance values of the obtained memory string; FIG. 10 is drawn according to yet another embodiment of this specification The circuit block diagram of the multi-state memory device shown in FIG. 11 is the circuit block diagram of the multi-state memory device according to yet another embodiment of this specification. The FIG. 12 is still another one according to this specification. The circuit block diagram of the multi-state memory device shown in the embodiment; and FIG. 13 is the circuit block diagram of the multi-state memory device according to yet another embodiment of this specification.

This specification provides a multi-state memory device and a method for adjusting its memory state value, which can accurately interpret the information storage state of the multi-state memory device, thereby improving the operation reliability of the multi-state memory device. In order to make the above embodiments of the specification and other purposes, features and advantages more obvious and understandable, In the following, a memory device and its manufacturing method are specifically cited as preferred embodiments, which will be described in detail in conjunction with the attached drawings.

However, it must be noted that these specific implementation examples and methods are not intended to limit the present invention. The present invention can still be implemented using other features, components, methods, and parameters. The proposed preferred embodiments are only used to illustrate the technical features of the present invention, and are not intended to limit the patent application scope of the present invention. Those with ordinary knowledge in this technical field will be able to make equivalent modifications and changes based on the description of the following description without departing from the spirit of the present invention. In different embodiments and drawings, the same elements will be denoted by the same element symbols.

Please refer to FIG. 1, which is a circuit block diagram of a multi-state memory device 100 according to an embodiment of this specification. The multi-state memory device 100 includes a plurality of memory cells 101-104 with the same structure and a plurality of selection switches 111-114 with the same structure. Each memory cell corresponds to a selection switch and is connected in series with each other to form a memory cell structure (for example, memory cell structures 131-134). The memory cell structures 131-134 can be connected in series to form a memory cell string 150 by a bit line BL. It is worth noting that although the memory string 150 shown in FIG. 1 only includes four memory cell structures 131-134 (memory units 101-104), the memory cell structure (memory) in the memory string 150 The number of memory cells is not limited to this. In other embodiments of the present specification, the memory string 150 may include more or less memory cell structures (memory cells).

For example, in this embodiment, the memory unit 101 and the selection switch 111 are connected in series to form a memory cell structure 131; the memory unit 102 and the selection switch 112 are connected in series to form a memory cell structure 132; the memory unit 103 and the selection The switches 113 are connected in series to form a memory cell structure 133; and the memory cell 104 and the selection switch 114 are connected in series to form a memory cell structure 134.

In some embodiments of the present specification, the memory cells 101-104 may be a memory element that uses the resistance value as the basis for judging the data storage state (for example, "0" and "1"). For example, Resistive Random-Access Memory (ReRAM), Phase Change Memory (PCM), Magnetic Random-Access Memory (MRAM) or Spin-Transfer Torque Random-Access Memory (STT-RAM).

In this embodiment, the memory cells 101-104 may be a resistive random access memory device. The memory cell 101 includes an upper electrode layer 101a, a lower electrode layer 101b, and a transition metal layer 101c. Among them, the upper electrode layer 101a is connected to the selection switch 111; the lower electrode layer 101b is connected to the bit line BL; and the transition metal layer 101c is connected to the upper electrode layer 101a and the lower electrode layer 101b. The memory cell 102 includes an upper electrode layer 102a, a lower electrode layer 102b, and a transition metal layer 102c. The upper electrode layer 102a is connected to the selection switch 112; the lower electrode layer 102b is connected to the bit line BL; and the transition metal layer 102c is connected to the upper electrode layer 102a and the lower electrode layer 102b. The memory unit 103 includes an upper electrode layer 103a, a lower electrode layer 103b and a transition metal layer 103c. Among them, the upper electrode layer 103a is connected to the selection switch 113; the lower electrode layer 103b is connected to the bit line BL; and the transition metal layer 103c is connected to the upper electrode layer 103a and the lower electrode layer 103b. The memory cell 104 includes an upper electrode layer 104a, a lower electrode layer 104b, and a transition metal layer 104c. The upper electrode layer 104a is connected to the selection switch 114; the lower electrode layer 104b is connected to the bit line BL; and the transition metal layer 104c is connected to the upper electrode layer 104a and the lower electrode layer 104b.

In some embodiments of the present specification, the selection switches 111-114 may be a transistor, a diode, or a selector. In this embodiment, the selection switches 111-114 may be a metal oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET). The gate 111a of the selection switch 111 is connected to the word line WL1; the source 111b of the selection switch 111 is connected to the common source line SL; and the drain 111c of the selection switch 111 is connected to the upper electrode layer 101a of the memory cell 101. The gate 112a of the selection switch 112 is connected to the word line WL2; the source 112b of the selection switch 112 is connected to the common source line SL; and the drain 112c of the selection switch 112 is connected to the upper electrode layer 102a of the memory cell 102. The gate 113a of the selection switch 113 is connected to the word line WL3; the source 113b of the selection switch 113 is connected to the common source line SL; and the drain 113c of the selection switch 113 is connected to the upper electrode layer 103a of the memory cell 103. The gate 114a of the selection switch 114 is connected to the word line WL4; the source 114b of the selection switch 114 is connected to the common source Line SL; the drain 114c of the selection switch 114 is connected to the upper electrode layer 104a of the memory cell 104.

Please refer to FIG. 2A and FIG. 2B. FIG. 2A illustrates the first signal of higher voltage and the lower voltage of the memory cell structure 131-134 of the multi-state memory device 100 shown in FIG. After the second signals are written separately, the resistance value cumulative distribution function graph of a single memory cell (for example, the memory cell 101) obtained by reading with a read signal having a fixed voltage pulse respectively. FIG. 2B is a graph plotting the cumulative distribution function of conductance shown in FIG. 2A. The horizontal axis of FIG. 2A represents the resistance value of the memory cell 101; the vertical axis represents the cumulative probability of the memory cell 101. The horizontal axis of FIG. 2B represents the conductivity value of the memory cell 101; the vertical axis represents the cumulative probability of the memory cell 101. Curves 201 and 202 in FIG. 2A respectively represent the cumulative distribution function area line of the measured resistance value when a high voltage pulse and a low voltage pulse are applied to the memory cell 101. Curves 211 and 212 in Fig. 2B represent the cumulative distribution function area lines corresponding to the curves 201 and 202, respectively.

After a high voltage pulse is applied, the cumulative distribution of the resistance value of the memory cell 101 will fall in the region of higher resistance HRS (see curve 201); the cumulative distribution of the conductivity value will fall in the region of lower conductivity value (see curve 211). After a low voltage pulse is applied, the cumulative distribution of the resistance value of the memory cell 101 will fall in the area of lower resistance LRS (see curve 202); the cumulative distribution of the conductivity value will fall in the area of higher conductivity value (see curve 212). Curves 201 and 202 (211 and 212) have a reading interval that does not overlap with each other. When reading, by comparing Whether the resistance value (conductance value) of the memory cell is higher or lower than the critical resistance value 203 (213) located in the reading interval can determine the data storage state stored in the more resistive random access memory cell (for example, Decide whether the storage bit (bit) is "0" or "1").

As can be seen from FIGS. 2A and 2B, the degree of variation of the resistance value distribution of the memory cell 101 in the high resistance value region HRS (the range of which spans between 1.5× ^{10 5} ohms (Ohm, Ω) to 1.4× ^{10 6} ohms ), which is greater than the variation degree of the resistance value distribution in the low resistance value region LRS (the range of which spans between 0 ohms and 5× ^{10 4} ohms). And the conductance value storage unit 101 in a low resistance region LRS distribution degree of variation (which spans the range between 2.5x10 ^-5 Siemens (S) to 7.5x10 ^-5 Siemens) is greater than the conductance value of the high resistance region of the HRS The degree of variation of the value distribution (its range spans from 0 Siemens to 9x10 ^-6 Siemens).

However, due to factors such as process variation or dimensional tolerance of the device, the resistance (conductance) distribution of each memory cell 101-104 constituting the multi-state memory device 100 varies in degree of variation. It may even exhibit the opposite characteristics. This phenomenon will result in the inability to accurately determine the data storage status of each memory unit 101-104 when the memory units 102-104 are read under the same conditions.

This problem will be more prominent in neuromorphic computing applications based on non-volatile memory. For example, when the same voltage pulse is applied to all the memory cells of different memory strings 150a-150b in the multi-state memory device 100, if the same memory string (eg, memory string 150a) is measured The measured resistance value (conductance value) of the memory cell is Take the summation to get the cumulative distribution function graph of the sum conductance value. The resulting cumulative distribution function graph of the total conductance value will have large numerical differences due to the use of memory cells with different degrees of variation in the distribution of resistance values (conductance values) of different memory strings 150a-150b.

Please refer to FIG. 3, which illustrates the writing of the same voltage pulses to the memory strings 150a-150e formed by combining the memory cells 101-104 as shown in FIG. 1. After the input, a read signal with a fixed voltage pulse is used for reading, and the cumulative distribution function graph of the total conductance value of the memory string is obtained. Among them, each of the memory cells 101-104 constituting the memory strings 150a-150e may have the same structure, but when written under the same conditions and then read, they will have different memory state values. Curves 301-305 represent the cumulative distribution function curves of the sum conductance of the memory strings 150a-150e, respectively.

For example, in this embodiment, all the memory cells 101-104 constituting the memory string 150a, the read memory state value (resistance value), and the variation degree of the resistance value distribution in the high resistance value region HRS are all The degree of variation of the resistance value distribution in the LRS greater than the low resistance value area. There are three memory cells (for example, memory cells 101-103) in the memory series 150b, and the read memory state value (resistance value) in the high resistance value area HRS has a greater variation in resistance value distribution than in the The degree of variation of the resistance value distribution in the low resistance value region LRS; the degree of variation in the resistance value distribution of another memory cell (for example, the memory unit 104) in the low resistance value region LRS is greater than the resistance in the high resistance value region HRS The degree of variation of the value distribution. Remember There are two memory cells (for example, memory cells 101-102) in the memory series 150c, and the read memory state value (resistance value) in the high resistance value area HRS has a greater variation in resistance value distribution than in the The degree of variation of the resistance value distribution in the low resistance value region LRS; the memory state values (resistance values) read by the other 2 memory cells (eg, memory cells 103-104), the resistance in the low resistance value region LRS The degree of variation in the value distribution is greater than the degree of variation in the resistance value distribution in the HRS in the high resistance value region. There is only one memory cell (for example, memory cell 101) in the memory series 150d, and the read memory state value (resistance value) in the high resistance value area HRS has a greater variation in resistance value distribution than in the low resistance The degree of variation of the resistance value distribution in the value area LRS; the other three memory cells (such as memory cells 102-104), the read memory state value (resistance value), the resistance value in the low resistance value area LRS The degree of variation in the distribution is greater than the degree of variation in the resistance value distribution in the HRS in the high resistance value region. The memory state values (resistance values) of all the memory cells 101-104 in the memory string 150e have a greater variation in resistance value distribution in the low resistance value region LRS than in the high resistance value region HRS The degree of variation in the value distribution.

It can be observed from FIG. 3 that, in addition to the memory series 150a (see curve 301), the extended range of the total conductance value distribution curves 302-305 of the other memory series 150b-150e (see) is quite large, and There are overlapping areas between each other, and it is impossible to find a non-overlapping critical value between the two fetch lines as a criterion for judging the data storage status.

In order to solve this problem, please refer to FIG. 4, which is a circuit of a multi-state memory device 400 according to another embodiment of this specification. Block diagram. The structure of the multi-state memory device 400 is roughly similar to that of the multi-state memory device 100, except that the multi-state memory device 400 also includes a plurality of control units 401-404, which correspond to the memory units 101-104, and Tandem.

In this embodiment, the memory unit 101 and the selection switch 111 and the control unit 401 are connected in series to form a memory cell structure 431; the memory unit 102 and the selection switch 112 and the control unit 402 are connected in series to form a memory cell structure 432; The memory unit 103 and the selection switch 113 and the control unit 403 are connected in series with each other to form a memory cell structure 433; and the memory unit 104, the selection switch 114 and the control unit 404 are connected in series with each other to form a memory cell structure 434. These memory cell structures 431-434 can be connected in series by a bit line BL to form a memory cell string 450

In some embodiments of this specification, the control units 401-404 may be any electronic circuit elements (such as transistors, resistance elements, memory elements), parasitic elements (such as semiconductor doping) that can provide stable resistance values (characteristic values) Impurity region) or an insulating structure (such as a dielectric isolation structure made of silicon oxide). For example, in this embodiment, the control units 401-404 may be a resistance element composed of doped polysilicon, and the control units 401-404 have substantially the same resistance value (characteristic value).

One end of the control unit 401 is connected to the lower electrode layer 101b of the memory unit 101, the other end is connected to the bit line BL; one end of the control unit 402 is connected to the lower electrode layer 102b of the memory unit 102, and the other end is connected to the bit line BL; One end of the control unit 403 is connected to the lower electrode layer 103b of the memory unit 103, the other end is connected to the bit line BL; one end of the control unit 404 is connected to the lower electrode layer 104b of the memory unit 104, and the other end is connected to the bit line BL.

When the selector switches 111-114 are all turned on, a higher voltage pulse and a lower voltage pulse are applied to the memory cell structures 431-434 in the memory cell string 450 through the bit line BL (ie, a high voltage is provided Signal and a low voltage signal), the cumulative distribution function (not shown) of the resistance value and the cumulative distribution function of the conductivity value of each memory cell 101-104 can be obtained separately.

For example, please refer to Figure 5. FIG. 5 shows that after the low-voltage signal (low-voltage pulse-on) and the high-voltage signal (high-voltage pulse-on) are provided to the memory cell structures 431-434 of the multi-state memory device 400 shown in FIG. 4, A graph of the cumulative distribution function of the resistance values of a single memory cell (eg, memory cell 101). When the memory cell 101 of the memory cell structure 431 receives the low voltage first signal, the measured resistance value forms a low resistance value region LRS (not shown) on the cumulative distribution function; when the memory cell structure 431 When the memory unit 101 receives the high voltage signal, the measured resistance value forms a high resistance value region HRS (not shown) on the cumulative distribution function. After that, the aforementioned cumulative distribution function of resistance value (not shown) is converted into the cumulative distribution function diagram of conductivity value shown in FIG. 5. Among them, the curves 501 and 502 respectively represent the cumulative distribution of conductance values corresponding to the low resistance value region LRS and the high resistance value region HRS. The stable resistance (characteristic value) provided by the control unit 401 is substantially between the high resistance value region HRS and the low resistance value region LRS.

Comparing Figure 5 with Figure 2B, it can be observed that the addition of a series control unit 401 to the memory cell 101 of the memory cell structure 431 can limit the conductivity value of the memory cell 101 in the low resistance value region LRS ( Distribution range in the region of high conductance value). Similarly, the distribution variation of the conductance values of the other memory cells 102-104 in the low resistance value region LRS (high conductance value region) will also decrease.

As described in FIG. 3, the corresponding conductance values of each of the memory cells 101-104 located in the low resistance value region LRS measured in the same memory string (for example, the memory string 450a) are added up. A cumulative distribution function of the sum conductance of the memory cell string 450a can be obtained. Please refer to FIG. 6. FIG. 6 shows the memory strings 431-434 formed by combining the memory cells 101-104 as shown in FIG. 4, after applying the same voltage pulse to them. The obtained cumulative distribution function graph of the sum of conductance values of the memory series. Among them, the curves 601-605 represent cumulative distribution functions of the sum conductance of the memory strings 450a-450e, respectively.

It can be observed from Figure 6 that the distribution range of the conductivity values of the curves 601-605 is quite narrow, and there is a non-overlapping area between each other. Multiple critical conductivity values 606-609 can be found between the curves 601-605 for As a criterion for reading the data storage status. This shows that after the control units 401-404 connected in series with the memory units 101-104 are added, the accuracy of the interpretation of the data storage state of the memory units 101-104 in the multi-state memory device 400 can be improved, and the multi-state can be improved The purpose of the operational reliability of the memory device 400.

Please refer to FIG. 7, which is a circuit block diagram of a multi-state memory device 700 according to yet another embodiment of this specification. Polymorphism The structure of the multi-state memory device 700 is similar to that of the multi-state memory device 400 except that the control units 701-704 of the multi-state memory device 700 are connected in parallel with the corresponding memory units 101-104, not in series.

In this embodiment, the memory unit 101 and the control unit 701 are connected in parallel with each other, and then connected in series with the selection switch 111 to form a memory cell structure 731; the memory unit 102 and the control unit 702 are connected in parallel with each other, and then connected in series with the selection switch 112, To form a memory cell structure 732; the memory unit 103 and the control unit 703 are connected in parallel with each other, and then connected in series with the selection switch 113 to form a memory cell structure 733; the memory unit 104 and the control unit 704 are connected in parallel with each other, and then the selection switch 114 Connected in series to form a memory cell structure 734. The memory cell structures 731-734 are connected in series through the bit line BL to form a memory cell string 750.

In this embodiment, the control units 701-704 may be a resistance element composed of doped polysilicon, and the control units 701-704 have substantially the same resistance value. One end of the control unit 701 is connected to the upper electrode layer 101 a of the memory unit 101 and the drain 111 c of the selection switch 111, and the other end is connected to the lower electrode layer 101 b of the memory unit 101 and the bit line BL. One end of the control unit 702 is connected to the upper electrode layer 102a of the memory unit 102 and the drain 112c of the selection switch 112, and the other end is connected to the lower electrode layer 102b of the memory unit 102 and the bit line BL. One end of the control unit 703 is connected to the upper electrode layer 103a of the memory unit 103 and the drain 113c of the selection switch 113, and the other end is connected to the lower electrode layer 103b of the memory unit 103 and the bit line BL; one end of the control unit 704 is connected To memory The upper electrode layer 104 a of the body cell 104 and the drain 114 c of the selection switch 114 have the other ends connected to the lower electrode layer 103 b of the memory cell 103 and the bit line BL.

When the selector switches 111-114 are all turned on, and the bit lines BL respectively provide a first signal with a higher fixed current and a lower fixed current to the memory cell structures 731-734 in the memory cell string 750 In the second signal, the cumulative distribution function of the resistance value of each memory cell 101-104 can be obtained separately.

Taking the memory unit 101 as an example, please refer to FIG. 8. FIG. 8 shows that after providing the first signal with a higher fixed current and the second signal with a lower fixed current to the memory cell structures 731-734 of the multi-state memory device 700 shown in FIG. 7, A graph of the cumulative distribution function of the resistance values of a single memory cell (eg, memory cell 101). When the memory cell 101 of the memory cell structure 731 receives the first signal with a higher fixed current, the measured resistance value will form a low resistance value region LRS on the cumulative distribution function (as shown by curve 801 ); When the memory cell 101 of the memory cell structure 731 receives the first signal with a lower fixed current, the measured resistance value will form a high resistance value region HRS (as shown by curve 802) on the cumulative distribution function (Shown). The stable resistance value (characteristic value) provided by the control unit 701 is substantially between the high resistance value region HRS (as shown by curve 802) and the low resistance value region LRS (as shown by curve 801).

Comparing Figure 8 with Figure 2A, it can be observed that adding a parallel control unit 701 to the memory cell 101 of the memory cell structure 731 can limit the resistance value of the memory cell 101 in the high resistance value region HRS Distribution of The degree of variation of the resistance value distribution of the memory lowering unit 101 in the high resistance value region HRS. Similarly, the degree of variation in the distribution of the resistance values of the other memory cells 102-104 in the HRS region will also decrease.

Summing up the corresponding conductance values of each memory cell 101-104 located in the high resistance value region HRS measured in the same memory string (eg, memory string 750a) to obtain the memory cell string Cumulative conductance cumulative distribution function of 750a. Please refer to FIG. 9, which shows the memory obtained after providing the same current signal to the memory strings 731-734 assembled from the memory units 101-104 shown in FIG. 7. Cumulative distribution function graph of the total conductance value of the volume series. Among them, curves 901-905 represent the cumulative distribution function of the total conductance of the memory strings 750a-750e, respectively.

It can be observed from Figure 9 that the distribution of the conductivity values of curves 901-905 is quite tight, and there is a non-overlapping area between each other. Multiple critical values 906-909 can be found between the two curves for data storage Interpretation criteria of status. This shows that after the control units 701-704 connected in series with the memory units 101-104 are added, the accuracy of the interpretation of the data storage state of the memory units 101-104 in the multi-state memory device 700 can be improved, and the multi-state can be improved The purpose of the operational reliability of the memory element 700.

It is worth noting that although in Figures 1, 4, and 7, the memory cell strings 150, 170, and 750 constituting the multi-state memory devices 100, 400, and 700 are all AND-type memory cell strings, However, the form of the memory cell string constituting the multi-state memory device described in this specification is not limited thereto. In this note In some embodiments of the book, the memory cell string constituting the multi-state memory device may be a NAND type memory cell string.

For example, referring to FIG. 10, FIG. 10 is a circuit block diagram of a multi-state memory device 1000 according to yet another embodiment of the present specification. The multi-state memory device 1000 includes a plurality of memory units 1001-1004 with the same structure, a plurality of selection switches 1011-1014 with the same structure, and a plurality of control units 1005-1008 with the same structure.

In some embodiments of the present specification, the memory cells 1001-1004 may be a resistive random access memory element, a phase change memory, a magnetoresistive random access memory or a spin-transfer torque random access memory . In this embodiment, the memory cells 1001-1004 can be a resistive random access memory device.

The selection switches 1011-1014 can be a transistor, a diode, or a selector. In this embodiment, the selection switches 1011-1014 may be a metal oxide semiconductor field effect transistor. The control unit 1005-1008 may be any electronic circuit element (such as a transistor, a resistive element, a memory element), a parasitic element (such as a semiconductor doped region), or an insulating structure (such as a material) that can provide a stable resistance value (characteristic value) (Silicon oxide dielectric isolation structure). In this embodiment, the control unit 1005-1008 is a resistance element composed of doped polysilicon, and the control unit 1005-1008 has substantially the same resistance value.

The memory unit 1001, the selection switch 1011 and the control unit 1005 are connected in parallel with each other to form a memory cell structure 1031; the memory unit 1002 The selection switch 1012 and the control unit 1006 are connected in parallel to each other to form a memory cell structure 1032; the memory unit 1003 and the selection switch 1013 and the control unit 1007 are connected in parallel to each other to form a memory cell structure 1033; and the memory unit 1004 and the selection switch 1014 and The control units 1008 are connected in parallel to each other to form a memory cell structure 1034. These memory cell structures 1031-1034 can be connected in series by a bit line BL to form a memory cell string 1050

The gate 1011a of the selection switch 1011 is connected to the word line WL1; the source 1011b of the selection switch 1011 is connected to the upper electrode layer 1001a of the memory cell 1001 and one end of the control unit 1005; the drain 1011c of the selection switch 1011 is connected to The lower electrode layer 1001b of the memory unit 1001 and the other end of the control unit 1005. The gate 1012a of the selection switch 1012 is connected to the word line WL2; the source 1012b of the selection switch 1012 is connected to the upper electrode layer 1002a of the memory cell 1002 and one end of the control unit 1006; the drain 1012c of the selection switch 1012 is connected to the memory The lower electrode layer 1002b of the unit 1002 and the other end of the control unit 1006. The gate 1013a of the selection switch 1013 is connected to the word line WL3; the source 1013b of the selection switch 1013 is connected to the upper electrode layer 1003a of the memory unit 1003 and one end of the control unit 1007; the drain 1013c of the selection switch 1013 is connected to the memory The lower electrode layer 1003b of the unit 1003 and the other end of the control unit 1007. The gate 1014a of the selection switch 1014 is connected to the word line WL4; the source 1014b of the selection switch 1014 is connected to the upper electrode layer 1004a of the memory cell 1004 and one end of the control unit 1008; the drain 1014c of the selection switch 1014 is connected to the memory The lower electrode layer 1004b of the unit 1004 and the other end of the control unit 1008.

As described above, when the selection switches 1011-1014 are all turned on, and a bit line BL is provided to the memory cell structure 1031-1034 in the memory cell string 1050, a first signal (for example, a lower fixed voltage) and a During the second signal (for example, a higher fixed voltage), the cumulative distribution function (not shown) of the resistance value of each memory cell 1001-1004 can be obtained separately. The cumulative distribution function of the resistance value of each memory cell structure 1031-1034 will have a low resistance value distribution area LRS (not shown) and a high resistance value distribution area HRS (not shown), respectively. The stable resistance value (characteristic value) provided by the control unit 1005-1008 is substantially between the high resistance value distribution area HRS and the low resistance value distribution area LRS.

Compare the cumulative distribution function of the resistance value of each memory cell structure 1031-1034 (not shown) with the cumulative distribution function of the resistance value of the memory cell structure 131 without a serial control unit (as shown in Figure 2B), It can be observed that a corresponding control unit 1005-1008 is connected in parallel with each memory cell 1001-1004 of the memory cell structure 1031-1034, which can limit the resistance value of each memory cell 1001-1004 in the high resistance value region Distribution range of HRS.

Please refer to FIG. 11, which is a circuit block diagram of a multi-state memory device 1100 according to yet another embodiment of this specification. The structure of the multi-state memory device 1100 is roughly the same as that of the multi-state memory device 900. The only difference is that the control units 1105-1108 of the multi-state memory device 1100 are connected in series with the corresponding memory units 1001-1004, not in parallel. . Since the other structures of the multi-state memory device 1100 and the method for adjusting the memory state value are described in detail above, they will not be repeated here.

In addition, in some embodiments of the present specification, the memory cell constituting the multi-state memory device may be a data storage state (such as "0" and "1") with a threshold voltage (threshold voltage, Vth) The memory element on which the interpretation is based. For example, Ferroelectric Random-Access Memory (FeRAM). The control unit constituting the multi-state memory element may be any electronic circuit element (such as a transistor, a diode, or a selector) that can provide a stable threshold voltage value (characteristic value).

Please refer to FIG. 12, which is a circuit block diagram of a multi-state memory device 1200 according to yet another embodiment of this specification. The multi-state memory device 1200 includes a plurality of memory units 1201-1204 with the same structure, a plurality of selection switches 1211-1214 with the same structure, and a plurality of control units 1205-1208 with the same structure. In this embodiment, the memory units 1201-1204 may be a ferroelectric random access memory. The control unit 1205-1208 may be a diode.

The memory unit 1201 and the selection switch 1211 and the control unit 1205 are connected in series to form a memory cell structure 1231; the memory unit 1202 and the selection switch 1212 and the control unit 1206 are connected in series to form a memory cell structure 1232; the memory unit 1203 and the selection The switch 1213 and the control unit 1207 are connected in series with each other to form a memory cell structure 1233; and the memory unit 1204 and the selection switch 1214 and the control unit 1208 are connected in series with each other to form a memory cell structure 1234. The memory cell structures 1231-1234 are connected in series through the bit lines BL to form a memory cell string sequence 1250.

When the selection switches 1211-1214 are all turned on, and a bit line BL is provided to the memory cells 1201-1204 in the memory cell string 1250, a first signal (such as a lower fixed voltage) and a second signal (such as High fixed voltage), the cumulative distribution function (not shown) of the threshold voltage value of each memory cell 1201-1204 can be obtained separately. The cumulative distribution function of the threshold voltage value of each memory cell 1201-1204 has a low threshold voltage value region LVth (not shown) and a high threshold voltage value region HVth (not shown), respectively. The stable threshold voltage value (characteristic value) provided by the control units 1201-1204 is substantially between the high threshold voltage value region HVth and the low threshold voltage value region LVth.

Similarly, compare the cumulative distribution function (not shown) of the critical voltage value of each memory cell 1201-1204 with the cumulative distribution function (not shown) of the critical voltage value of the memory cell without the additional serial control unit, It can be observed that a control unit 1205-1208 is connected in series with each memory unit 1201-1204, which can limit the threshold voltage of the memory unit 1201-1204 to the range of the low critical voltage value region LVth, reducing each memory The distribution variation of the threshold voltage value in the low threshold voltage value region LVth of the body units 1201-1204 achieves the purpose of improving the operation reliability of the multi-state memory device 1200.

Please refer to FIG. 13, which is a circuit block diagram of a multi-state memory device 1300 according to an embodiment of the present specification. The structure of the multi-state memory device 1300 is substantially similar to that of the multi-state memory device 1200 except that the control unit of the multi-state memory device 1300 1301-1304, respectively connected in parallel with the corresponding memory cells 1201-1204, rather than in series.

In this embodiment, the memory unit 1201 and the control unit 1201 are connected in parallel with each other, and then connected in series with the selection switch 1211 to form a memory cell structure 1331; the memory unit 1202 and the control unit 1202 are connected in parallel with each other, and then connected in series with the selection switch 1212, To form a memory cell structure 1332; the memory unit 1201 and the control unit 1303 are connected in parallel with each other, and then connected in series with the selection switch 1213 to form a memory cell structure 1333; the memory unit 1204 and the control unit 1304 are connected in parallel with each other, and then the selection switch 1214 Connected in series to form a memory cell structure 1334. And the memory cell structures 1331-1334 are connected in series through the bit line BL to form a memory cell string sequence 1350.

When the selection switches 1211-1214 are all turned on, and a bit line BL is provided to the memory cells 1201-1204 in the memory cell string 1350, a first signal (e.g., a lower fixed voltage) and a second signal (e.g. High fixed voltage), the cumulative distribution function (not shown) of the threshold voltage value of each memory cell 1201-1204 can be obtained separately. The cumulative distribution function of the threshold voltage value of each memory cell 1201-1204 has a low threshold voltage value region LVth (not shown) and a high threshold voltage value region HVth (not shown), respectively. The stable threshold voltage value (characteristic value) provided by the control units 1301-1304 is substantially between the high threshold voltage value region HVth and the low threshold voltage value region LVth.

Similarly, compare the cumulative distribution function (not shown) of the critical voltage value of each memory cell 1201-1204 with the cumulative distribution function (not shown) of the critical voltage value of the memory cell without the additional serial control unit, Observable: in each A corresponding control unit 1305-1308 is connected in parallel to the memory units 1201-1204, which can limit the distribution range of the critical voltage value of each memory unit 1201-1204 in the region of high critical voltage value HVth and reduce each memory unit 1201-204 1204, the degree of variation in the distribution of the critical voltage value in the high critical voltage value region HVth achieves the purpose of improving the operation reliability of the multi-state memory device 1300.

According to the above embodiment, the present specification discloses a multi-state memory device including at least one memory cell string and a method for adjusting the memory state value. It adopts series or parallel connection, and each memory cell (memory cell) in the same memory cell series is electrically connected to a control unit, which is used to adjust the memory state value of each memory cell and reduce the difference. The degree of distribution variation of the memory state value generated by the memory unit when receiving the same signal, so as to accurately judge the data storage state of the multi-state memory element.

In some embodiments of the present specification, the memory state value may be the resistance value, conductivity value, or threshold voltage value of the memory cell. The type of control unit depends on the selection of the memory state value, and may be a resistor with stable resistance or a switch with a stable threshold voltage. The connection mode (serial or parallel) of the control unit and the memory unit can be selected according to the type, application range and operation signal form of the multi-state memory device.

For example, in an embodiment of the present specification, when the multi-state memory device uses the resistance value of each memory cell as the basis for judging the data storage state (such as "0" and "1"), the control unit device It can be a resistor with stable resistance. And when the operation signal is a fixed voltage, each memory unit can It can be connected in series with a resistor to reduce the degree of variation in the distribution of the conductivity value of the memory cell as the storage state value in the low resistance range; and when the operation signal is a fixed current, each memory cell can Formed in parallel with a resistor to reduce the degree of variation in the distribution of the resistance value used by the memory cell as the storage state value in the high resistance range.

In another embodiment of the present specification, when the multi-state memory device uses the threshold voltage value of each memory cell as the basis for judging the data storage state (such as "0" and "1"), the control unit device It can be a switch with stable threshold voltage. And when each memory cell is connected in series with a switch, the degree of variation in the distribution of the threshold voltage value used by the memory cell as the storage state value in the low threshold voltage range can be reduced; and when each memory cell is connected to When a switch is formed in parallel, the distribution variation of the critical voltage value used by the memory cell as the storage state value in the high critical voltage value range can be reduced.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in this technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be deemed as defined by the appended patent application scope.

400‧‧‧Multi-state memory element

101-104‧‧‧Memory unit

111-114‧‧‧selection switch

401-404‧‧‧Control unit

101a-104a‧‧‧ Upper electrode layer

101b-104b‧‧‧Lower electrode layer

101c-104c‧‧‧Transition metal layer

111a-114a‧‧‧Gate

111b-114b‧‧‧Source

111c-114c‧‧‧ Drain

450‧‧‧ Memory cell series

431-434‧‧‧ memory cell structure

BL‧‧‧bit line

SL‧‧‧ common source line

WL1, WL2, WL3, WL4 ‧‧‧ character line

Claims (10)

A multi-state memory device includes: a first memory unit; a second memory unit, having a memory cell structure substantially the same as the first memory unit, and the first memory Body units are connected in series; a first control unit is connected in series or parallel with the first memory unit; and a second control unit has the same characteristic value and the same connection structure as the first control unit for The second memory unit is electrically connected; when the first memory unit receives a first signal and a second signal through the first control unit, the first memory unit generates a first state value and a A second state value; wherein the characteristic value is between the first state value and the second state value. The multi-state memory device as described in item 1 of the patent scope, wherein the first state value and the second state value are after the first memory unit receives the first signal and the second signal, It is measured by inputting a read signal with a fixed voltage pulse to the first memory unit. The multi-state memory device as described in item 1 of the patent application range, wherein the first control unit includes a first resistor having a first resistor Value; the second control unit includes a second resistor having a second resistance value, the characteristic value is the first resistance value, and is substantially equal to the second resistance value; when both the first signal and the second signal are At a fixed voltage, the first resistor is connected in series with the first memory unit, and the second resistor is connected in series with the second memory unit; when both the first signal and the second signal are a fixed current, the first The resistor is connected in parallel with the first memory unit; and the second resistor is connected in parallel with the second memory unit. The multi-state memory device as described in item 1 of the patent scope, wherein the first control unit includes a first switch with a first threshold voltage value; the second control unit includes a second switch, Has a second threshold voltage value, the characteristic value is the first threshold voltage value, and is substantially equal to the second threshold voltage value; wherein when the first state value is less than the first threshold voltage value, and has a second When the distribution of the state value is large, the first switch is connected in series with the first memory unit; and the second switch is connected in series with the second memory unit; when the first state value is greater than the first threshold voltage value And a distribution variation greater than the second state value, the first switch is connected in parallel with the first memory unit; and the second switch is connected in parallel with the second memory unit. The multi-state memory device as described in item 4 of the patent application scope further includes: a first selection switch and a second selection switch, both of which have There is the same switch structure, which is electrically connected to the first memory unit and the second memory unit respectively; when the first switch is connected in series with the first memory unit, and the second switch and the second memory unit When the cells are connected in series, the first selection switch includes: a first gate connected to a first word line; a first source connected to a common source line; and a first drain through the first memory The body unit and the first control unit are connected to a bit line; the second selection switch includes: a second gate connected to a second word line; a second source connected to the common source line; and A second drain connected to the bit line through the second memory unit and the second control unit; when the first switch is connected in parallel with the first memory unit, and the second switch and the second memory When the body units are connected in parallel, the first selection switch includes: a first gate connected to a first word line; a first source connected to one end of the first memory unit; and a first drain connected to The other end of the first memory unit; the second selector switch includes: a second gate connected to a second word line; a second source connected to one end of the second memory unit; and a first The second drain is connected to the other end of the second memory unit. The multi-state memory device as described in item 1 of the patent application scope further includes a third memory unit having the memory cell structure, and the second memory unit is connected in series to form a memory array. A method for adjusting the characteristics of memory-state of a multi-state memory device includes: providing a first memory unit; providing a second memory unit having substantially the same as the first memory unit A memory cell structure, which is connected in series with the first memory unit; provides a first control unit to be connected in series or parallel with the first memory unit; and provides a second control unit with the first control The unit has a characteristic value and an identical connection structure for electrically connecting with the second memory unit; when the first memory unit receives a first signal and a second signal through the first control unit, The first memory unit respectively generates a first state value and a second state value; wherein the characteristic value is between the first state value and the second state value. The method for adjusting the memory state value of a multi-state memory device as described in item 7 of the patent application scope, wherein the first state value and the second state value are received by the first signal in the first memory unit or The second signal Then, it is measured by inputting a read signal with a fixed voltage pulse to the first memory unit. The method for adjusting the memory state value of a multi-state memory element as described in item 7 of the patent application scope, wherein when both the first signal and the second signal are a fixed voltage, the step of providing the first control unit includes , Providing a first resistor in series with the first memory unit; providing the second control unit includes providing a second resistor in series with the second memory unit; the characteristic value is equal to a first A resistance value and a second resistance value of the second resistance; when the characteristic value is a resistance value, when both the first signal and the second signal are a fixed current, the step of providing the first control unit includes , Providing a first resistor in parallel with the first memory unit; providing the second control unit includes providing a second resistor in parallel with the second memory unit; the characteristic value is equal to a first A resistance value and a second resistance value of the second resistance. The method for adjusting the memory state value of a multi-state memory device as described in item 1 of the patent scope, wherein the characteristic value is a threshold voltage, when the first state value is less than the threshold voltage The step of providing the first control unit includes a first switch connected in series with the first memory unit when a distribution with a large value has a variation degree of distribution; the second control unit is provided The step of the element includes providing a second switch in series with the second memory cell; the characteristic value is equal to a first threshold voltage of the first switch and a second threshold voltage of the second switch; when the first When the state value is greater than the first threshold voltage value and has a distribution variation greater than the second state value, the step of providing the first control unit includes providing a first switch in parallel with the first memory unit; The step of providing the second control unit includes providing a second switch in parallel with the second memory unit; the characteristic value is equal to a first threshold voltage of the first switch and a second threshold voltage value of the second switch .

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